ADA4558 [ADI]
Bridge Sensor Signal Conditioner IC with LIN Interface, Nonlinearity Correction, Temperature Compensation;
| 型号： | ADA4558 |
| 厂家： | 
ADI |
| 描述： | Bridge Sensor Signal Conditioner IC with LIN Interface, Nonlinearity Correction, Temperature Compensation |
| 文件： | 总12页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Bridge Sensor Signal Conditioner IC with LIN Interface,
Nonlinearity Correction, Temperature Compensation
Data Sheet
ADA4558
FEATURES
GENERAL DESCRIPTION
LIN 2.1 compliant interface (bridge sensor signal, temperature)
Digitally programmable gain and offset voltage adjustment
Gain range from 2.94 V/V to 971.10 V/V
Sensor temperature compensation (first- or second-order)
Sensor nonlinearity correction (first- or second-order)
Internal or external temperature sensor compensation
EEPROM nonvolatile memory for calibration data
High system accuracy: 0.1% FSR over temperature
EMC and EMI protection
Fault protection for open circuits and short circuits
4 mm × 4 mm, 20-lead LFCSP
6 V to 18 V supply operation
−40°C to +150°C operating temperature range
AEC-Q100 qualified for automotive applications
The ADA4558 is a fully integrated, sensor signal conditioner
IC for bridge sensors. The device provides digital nonlinearity
correction and temperature compensation via internal or external
sensed temperatures using on-chip correction and calibration
hardware that can be optimized for a specific bridge sensor.
The ADA4558 utilizes a fourth-order digital correction algorithm
and delivers a system accuracy of 0.1% full scale range (FSR) for
bridge sensors with second-order nonlinearity sensitivity. The
ADA4558 includes a local interconnect network (LIN) physical
interface for single-wire, high voltage communications in
automotive environments. LIN 2.1 and earlier versions are
supported. The LIN interface allows access to measurements,
end of line (EOL) calibration, and a wide range of diagnostic
functions.
APPLICATIONS
The analog subsystem consists of an analog-to-digital
Strain gage
converter (ADC) and a programmable gain amplifier (PGA)
with a wide gain range from 2.94 V/V to 971.10 V/V. To minimize
power supply noise, the bridge sensor is biased with an internal
4 V voltage regulator. The ADA4558 is fully specified from −40°C
to +150°C. The device operates from battery supply voltages
of 6 V to 18 V. The ADA4558 is available in a 4 mm × 4 mm,
20-lead lead frame chip scale package (LFCSP).
Pressure signal conditioner for automotive vehicles
FUNCTIONAL BLOCK DIAGRAM
INPUT VOLTAGE = 6V TO 18V
VDD12
DVDD
POWER SECTION
VREG
5V LDO
AFE
1.8V LDO
REFERENCE
VREG
VPOS
VNEG
0.1µF
DIGITAL CORRECTION ENGINE
CORRECTION ALGORITHM
EMI
FILTER
LOW-PASS
FILTER
SENSOR
BRIDGE
VREG
LIN2
PGA
FAULT HANDLING
LIN
LIN
14-BIT
ADC
IIR
FILTER
MUX
TRANSCEIVER
±OFFSET ADJUSTMENT
VREG
+
COMMUNICATION BUS
VREG
RREFN
STATIC
ONE TIME
PROGRAM-
MABLE
EEPROM
TPOS
TNEG
RANDOM
ACCESS
MEMORY
OPTIONAL
EXTERNAL
MEMORY
RESISTIVE
–
TEMPERATURE
DETECTOR
INTERNAL
TEMPERATURE
SENSOR
ISINK
ADA4558
AGND
DGND LINGND
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2019 Analog Devices, Inc. All rights reserved.
www.analog.com
ADA4558
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Theory of Operation .........................................................................9
Applications Information.............................................................. 10
Typical Connection Diagram ................................................... 10
EMC Performance...................................................................... 10
PCB Layout Guidelines.............................................................. 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Automotive Products................................................................. 12
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
6/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
ADA4558
SPECIFICATIONS
Supply voltage (VDD12) = 12 V, common-mode voltage (VCM) = 2 V, and TA = 25°C, unless otherwise specified. Minimum and maximum
values are specified over the full supply voltage and a temperature range of −40°C to +150°C.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY (SYSTEM)
Supply Voltage
VDD12
6
27
26
12
18
V
V
V
Operating Range1
VDD12, LOAD DUMP
VDD12, JUMP START
VUVLO
Load dump for 0.3 sec
Jump start for 60 sec
Undervoltage Lockout (UVLO)
Rising
Hysteresis
5.1
0.2
5.0
V
V
mA
Supply Current
ISY
Normal operation, VREG current (IVREG), LIN
current (ILIN) = 0 mA, TA = −40°C to +85°C
7
Normal operation, IVREG, ILIN = 0 mA, TA =
−40°C to +150°C
8.2
mA
Sleep Mode Current
VREG Output
VREG Temperature Coefficient2
DVDD Regulated Voltage
SYSTEM SPECIFICATIONS
Full-Scale Accuracy with Calibration
Enabled with inactivity on the LIN bus
150
4.0
95
µA
V
ppm/°C
V
VREG
3.8
1.6
4.2
2.0
DVDD
1.8
Sensor characteristic dependent
PGA gain = 2.94 V/V to 162.52 V/V
PGA gain = 224.72 V/V to 971.10 V/V
0.1
0.25
% FSR
% FSR
INPUT STAGE
PGA Gain Setting
Common-Mode Input Voltage Range
Bridge Resistance
2.94
34
2
971.10 V/V
65
20
% VREG
kΩ
RBR
Input Electromagnetic Interference
(EMI) Filter3
Cutoff Frequency (f−3 dB
Differential
f−3 dB Common Mode
)
0.55
0.58
MHz
MHz
Input Offset
Voltage4
Voltage Drift
Maximum Input Capacitance
COARSE OFFSET5
Bridge Offset Cancellation Range
Offset Trim
VOS
TCVOS
5
10
20
15
µV
nV/°C
nF
VPOS/VNEG nodes
At PGA input
60
mV/V
Resolution
PGA gain = 2.94
PGA gain = 971.10
At PGA output
6
14
31
Bits
Bits
mV
Step Size
COARSE GAIN
Gain Setting Accuracy
Gain = 2.94 to 162.52
Gain = 224.72 to 971.10
Gain ≤ 573.0
Gain = 722.3
Gain = 971.10
−1.2
−2.75
0.2
1
+1.2
+2.75
50
64
121
%
%
Gain Error Temperature Coefficient
ppm/°C
ppm/°C
ppm/°C
ADC PERFORMANCE
Main ADC Resolution
14
Bits
ADC Integral Nonlinearity (INL)
ADC Differential Nonlinearity (DNL)
−4
−1
+4
+1
LSB14
LSB14
Rev. 0 | Page 3 of 12
ADA4558
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
EXTERNAL TEMPERATURE SENSOR
Valid Temperature Range
External Temperature Sensor
Accuracy
−50
−0.5
+165
+0.5
°C
°C
Two calibration points using a PT1000
sensor
One calibration point using a PT1000
sensor
−2
−2
+2
+2
°C
%
Gain Setting Accuracy
LIN INPUT AND OUTPUT STAGE
Voltage
0.2
Compliant with LIN Specification 2.1
Voltage range over which LIN is
functional
6
18
V
Baud Rate
Current Limit for Driver (LIN Bus
Dominant State)
1
40
20
200
kbps
mA
ILIN_DOM_MAX Pulled to maximum VDD12
Driver Off
Input Leakage
LIN Pin Current
While Ground Disconnected
ILIN_PASS_REC
ILIN_PAS_DOM
8 V < VDD12 < 18 V, VLIN ≥ VDD12
VLIN = 0 V
20
μA
mA
−1
−1
ILIN_NO_GND
ILIN_NO_BAT
VDD12 = 12 V, control unit
disconnected from ground
VDD12 disconnected, 0 V < VLIN < 18 V
+1
30
mA
μA
While Battery Disconnected
LIN Receiver
Dominant State
Recessive State
Center Voltage
Hysteresis Voltage
VLIN_DOM
VLIN_REC
VLIN_CNT
VHYS
40
%VDD12
% VDD12
% VDD12
% VDD12
kΩ
60
47.5
50
25
52.5
17.5
34
Slave Termination Resistance
LIN RECEIVER TIMING PARAMETERS
Propagation Delay of Receiver
Symmetry of Receiver Propagation
Delay
RSLAVE
21
−2
tRX_PD
tRX_SYM
6
+2
µs
µs
Rising edge with the respect to falling
edge
LIN DRIVER TIMING PARAMETERS
Bus load conditions (CBUS, RBUS): 1 nF and
1 kΩ; 6.8 nF and 660 Ω; 10 nF and 500 Ω
Duty Cycle 1
Duty Cycle 2
Duty Cycle 3
Duty Cycle 4
ADC Measurement Time
LIN SLEEP/WAKE-UP
D1
D2
D3
D4
For proper operation at 20 kbps
For proper operation at 20 kbps
For proper operation at 10.4 kbps
For proper operation at 10.4 kbps
To valid reading
0.396
0.417
0.581
0.590
120
µs
Force sleep mode by sending a
diagnostic master request frame (frame
identifier = 0x3C, with the first data
byte equal to 0x00); sleep mode is also
entered if there is no activity on the LIN
bus for a certain time
Auto Sleep Enable Time
Minimum Dominant Time
Wake-up occurs if a recessive to
dominant transition on the LIN bus is
followed by a dominant level on the LIN
bus maintained for a certain time
(minimum dominant time), followed by
a dominant to recessive transition; the
dominant to recessive transition wakes
up the device
4
sec
150
µs
Rev. 0 | Page 4 of 12
Data Sheet
ADA4558
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Start-Up Time (System)
First readback of valid data, filter
setting = 500 Hz, all faults enabled or
disabled
100
ms
Main Oscillator Frequency
All internal timers are related to
oscillator
9.5
10
10.5
MHz
kHz
Oscillator Frequency (Sleep Mode)
300
ELECTRICALLY ERASABLE
PROGRAMMABLE READ-ONLY
MEMORY (EEPROM)
Programming
Number of Cycles
Time
Temperature
Data Retention
1000
Cycles
ms
°C
Years
Years
Per 32-bit written word
20
40
+150
−40
10
15
1000 write cycles, operation at 150°C
1000 write cycles, 40,000 hour
operation (10,000 hours at 55°C +
27,000 hours at 125°C + 3000 hours at
150°C)
FAULTS
Bridge Sensor Input Bias Current
IB
Detects input open circuit (startup)
5
300
µA
nA
Detects input open circuit,
normal/running mode operation
(EEPROM register
PGA_ADD_PULUP_150 = 0), default
Detects input open circuit,
normal/running mode operation
(EEPROM register
450
nA
PGA_ADD_PULUP_150 = 1)
Input Open Detection Resistance
Startup
320
32
kΩ
MΩ
Normal running mode operation
Open Detection Threshold
Low
High
Input Short Detection Resistance
Oscillator Crosscheck Limit
18.75
81.25
0.5
% VREG
% VREG
kΩ
14
%
External Temperature Sensor Bias
Current
Detects external temperature open
circuit
28
nA
Thermal Shutdown
Hysteresis
TSD
TSD_HY
170
7
°C
°C
1 Guaranteed by absolute maximum ratings (see the Absolute Maximum Ratings section).
2 The VREG voltage is also the reference to the ADC. Therefore, reference temperature drift does not affect system error. This specification can be useful in gain and
offset selection at EOL calibration.
3 Guaranteed by design.
4 Errors in PGA, temperature sensor gain, offset, and temperature drift are eliminated based on the EOL calibration routine.
5 The input offset trim range is −60 mV/V to +60 mV/V. The ADC reference is 4 V. The resulting input offset trim range is 0.48 V. The output preferred offset trim
resolution is 31 mV. For a gain of 2.9, the input referred offset trim resolution is 10.6 mV. Dividing range by resolution gives approximately 50 steps, which is close to a
6-bit resolution. For a gain of 971, the input referred offset trim resolution is 32 μV. Dividing range by resolution equals 16,287 LSBs, which is close to 14-bit resolution.
In all cases, this only provides the coarse offset calibration required to get the PGA output into the valid ADC range of operation. The digital linearization engine
provides fine offset calibration to meet the system accuracy targets.
Rev. 0 | Page 5 of 12
ADA4558
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Close
attention to PCB thermal design is required.
Parameter
Rating
VDD12
LIN
40 V
40 V
Reverse Protection
VDD12
LIN
VREG, VPOS, VNEG, TPOS, TNEG, ISINK,
RREFN
LIN Short-Circuit Duration to LINGND or
VDD12
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
AGND to −0.3 V
−40 V
−0.3 V to +6 V
Table 3. Thermal Resistance
Indefinite
Package Type
θJA
θJC
Unit
CP-20-81
49
1.42
°C/W
ESD
1 Test Condition 1: Thermal impedance simulated values are based on JEDEC
4-layer test board.
Human Body Model (All Pins)
LIN and LIN2 Pins
4000 V
6000 V
Charged Device Model
Machine Model
1000 V
200 V
ESD CAUTION
LIN, LIN2 ESD (IEC 61000-4-2)
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Soldering Profile
>8 kV contact
−65°C to +150°C
−40°C to +150°C
−40°C to +165°C
IPC/JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 6 of 12
Data Sheet
ADA4558
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 ISINK
14 TNEG
13 TPOS
1
2
3
4
5
DVDD
DGND
TESTD
SWDIO
SWCLK
ADA4558
TOP VIEW
(Not to Scale)
12
RREFN
11 VREG
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THIS PIN IS NOT INTERNALLY CONNECTED.
CONNECT NIC TO THE GROUND PLANE.
2. CONNECT THE EXPOSED PAD OF THE LFCSP PACKAGE TO THE ANALOG GROUND PLANE.
ENSURE THAT AGND IS CONNECTED TO DGND AND LINGND AT A SINGLE POINT ON THE PCB.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
DVDD
1.8 V Low Dropout (LDO) Digital Supply. Add a 0.1 μF capacitor placed as close to Pin 1 as possible between DVDD
and the DGND plane.
2
3
4
5
6
7
8
9
DGND
TESTD
SWDIO
SWCLK
NIC
VNEG
TEST1
VPOS
TEST2
VREG
Digital Ground.
Test Pin. Analog Devices, Inc., uses this pin at the production test. Connect TESTD to the DGND plane in the application.
Test Pin. Analog Devices uses this pin at the production test. Connect SWDIO to the DGND plane in the application.
Test Pin. Analog Devices uses this pin at the production test. Connect SWCLK to the DGND plane in the application.
Not Internally Connected. This pin is not internally connected. Connect NIC to the ground plane.
Negative Input. Pin 7 is the negative input to the PGA from the external resistive bridge.
Test Pin. Analog Devices uses this pin at the production test. Connect TEST1 to the AGND plane in the application.
Positive Input. Pin 9 is the positive input to the PGA from an external resistive bridge.
10
11
Test Pin. Analog Devices uses this pin at the production test. Connect TEST2 to the AGND plane in the application.
Regulated 4.0 V Output. Pin 11 drives the top of the external bridge. Add a 0.1 μF capacitor between VREG and the
AGND plane, placed as close to the VREG pin as possible.
12
RREFN
Reference Resistor. Pin 12 is the reference resistor for the external temperature sensor sense connection. Connect
Pin 12 to ground when there is no external temperature sensor.
13
14
15
TPOS
TNEG
ISINK
External Temperature Positive Input. Connect Pin 13 to ground when there is no external temperature sensor.
External Temperature Sensor Negative Input. Connect Pin 14 to ground when there is no external temperature sensor.
Current Sink. Pin 15 drives the external temperature sensor. Connect Pin 15 to ground when there is no external
temperature sensor.
16
17
AGND
VDD12
Analog Ground.
Supply. Connect the 12 V battery supply to this pin. Decouple VDD12 with a 1 µF capacitor. A 100 nF capacitor can
be used only when a 1 µF capacitor to ground is placed on the anode of the diode on the module battery supply.
18
19
LIN2
LIN
Not in Use. The LIN2 function is not in use. Connect LIN2 to the LIN pin.
LIN Compliant Interface. All communication to and from the IC is via the LIN pin. Connect a LIN capacitor to ground
on this pin, per the LIN specification.
20
LINGND
EPAD
Local LIN Ground.
Exposed Pad. Connect the exposed pad of the LFCSP to the analog ground plane. Ensure that AGND is connected
to DGND and LINGND at a single point on the PCB.
Rev. 0 | Page 7 of 12
ADA4558
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
500
450
400
350
300
250
200
150
100
50
0
–50
0
50
100
150
200
TEMPERATURE (°C)
Figure 3. Mean Sleep Current vs. Temperature, VDD12 = 12 V
Rev. 0 | Page 8 of 12
Data Sheet
ADA4558
THEORY OF OPERATION
The ADA4558 interfaces to a range of Wheatstone resistive
bridge sensors. Figure 1 shows the block diagram of the
ADA4558. The differential signal from the bridge output is
applied to the analog front end (AFE) and then to the infinite
impulse response (IIR) filter. A correction algorithm is applied
in the processor to compensate for sensor nonlinearity and
temperature dependency.
The internal mux selects the signal from the PGA, internal
temperature sensor, external local temperature (optional), and
other miscellaneous signals, and applies them to the 14-bit on-
chip SAR ADC, which in turn converts the analog inputs into
the digital domain for further processing.
Next, the digital signal is applied to the IIR filter to filter out any
unwanted noise signals, after which time the filtered signal is
applied to the processor.
The ADA4558 power section includes the 4 V regulator output
at the VREG pin, which drives the bridge and the external
temperature sensor. The VREG pin also supplies the reference
to the ADC to create a fully ratiometric measurement system.
The ADA4558 and bridge sensor are calibrated over its signal
and temperature range by the customer via the ADA4558 LIN
interface. Correction coefficients are calculated and stored in
EEPROM. During normal operation, these correction coefficients
are applied to the correction algorithm.
The AFE consists of an input EMI filter, inverting input switch,
PGA, low-pass filter, mux switch, and 14-bit successive
approximation register (SAR) ADC.
The ADA4558 uses a LIN interface to provide linearized bridge
sensor data in customizable frame formats. The ADA4558 also
provides temperature and extensive diagnostics and status
information. LIN 2.1, LIN 2.0, and LIN 1.3 modes are supported.
The differential signal from the bridge sensor is applied to the
PGA, which amplifies the input differential signal and applies
sensor offset voltage adjustment.
For more information and register details for the ADA4558, see
the ADA4558 Hardware Reference Manual.
Rev. 0 | Page 9 of 12
ADA4558
Data Sheet
APPLICATIONS INFORMATION
TYPICAL CONNECTION DIAGRAM
EMC PERFORMANCE
Figure 4 shows the typical connection diagram for the
ADA4558, and Table 5 provides the component list.
The ADA4558 meets the electromagnetic compatibility (EMC)
requirements specified in OEM Hardware Requirements for
LIN, CAN, and FlexRay interfaces in Automotive Applications
Revision 1.3, May 2012 using the applications reference circuit
and corresponding bill of materials.
DIODE
RBAT
VIN = 12V
1.8V
10Ω
CIN
C1_8V
0.1µF
1µF
100V
1µF
100V
CIN
VDD12
DVDD
SWDIO
VREG
VREG
SWCLK
CREG
0.1µF
LIN2
PRESSURE
SENSOR
LIN BUS
LIN
VPOS
VNEG
ADA4558
CLIN
220pF
RREFN
TPOS
VREG
CPOS
(OPTIONAL)
TNEG
ISINK
LINGND
DGND
TEST1,
TEST2,
TESTD
CNEG
(OPTIONAL)
AGND
NIC
Figure 4. Typical Connection Diagram
Table 5. Component List
Product Reference
ADA4558
RBAT
CREG, C1_8V
CIN
Temperature Range
−40°C to +150°C
−40°C to +150°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
Package Description
Package
CP-20-8
0603
0402
0805
Product No.
20-lead LFCSP
10 Ω, 250 mW resistor to meet ISO transients
Murata, X7R, 16 V, 0.1 µF
TDK, X7S, 100 V, 1 µF
150 V, reverse protection diode
220 pf, LIN capacitor
ADA4558
CRCW060310R0JNEAHP
GCG155R71C104KA15D
CGA4J3X7S2A105K
BAS21-03WE6327
GCM155R72A221KA37
Diode
CLIN
SOD323
0402
Rev. 0 | Page 10 of 12
Data Sheet
ADA4558
PCB LAYOUT GUIDELINES
Figure 5. Example PCB Layout
The following items outline best practice for PCB layout.
•
•
Shield the VDD12 line from VPOS, VNEG, and VREG
using a ground plane.
Connect DGND and LINGND to AGND at a single point.
Use a short narrow trace for DGND and a wide trace for
LINGND.
TESTD is connected internally to DGND. Connect Pin 3 to
a small DGND plane to avoid multiple connections
between AGND and DGND.
To minimize total ground plane impedance, use a separate
ground layer, if available, with many via connections to the
top layer ground plane.
•
Place the 220 pF CLIN capacitor close to the IC between
the LIN and LINGND traces.
•
Place the CREG, CIN, and C1_8V capacitors close to the
IC using short, thick tracks. These components decouple
the supplies and reduce high frequency noise on these nodes.
The length of the C1_8V traces is critical. Keep the traces
as short as possible.
Shield the noisy DVDD regulator pin from the sensitive
analog circuitry at VPOS, VNEG, and VREG.
Maintain shielded matched differential lines for VNEG and
VPOS to ensure that noise pickup is both minimal and
common mode. The PGA can potentially obtain significant
noise at this point.
•
•
•
•
•
•
When a second routing layer is available, the LINGND
trace can be connected to the AGND plane with a large via
close to CDVDD. Connect DGND to AGND at this point
with a narrow trace.
•
Shield the VPOS trace from the VREG trace because
VREG can have noise pickup during EMC testing.
Rev. 0 | Page 11 of 12
ADA4558
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
5
6
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 6. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADA4558WHCPZ-RL
ADA4558WHCPZ-R7
EVAL-ADA4558EBZ
Temperature Range
–40°C to +150°C
–40°C to +150°C
Package Description
Package Option
CP-20-8
CP-20-8
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for automotive applications.
AUTOMOTIVE PRODUCTS
The ADA4558W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17245-0-6/19(0)
Rev. 0 | Page 12 of 12
相关型号：
ADA4558WHCPZ-R7
Bridge Sensor Signal Conditioner IC with LIN Interface, Nonlinearity Correction, Temperature Compensation
ADI
ADA4558WHCPZ-RL
Bridge Sensor Signal Conditioner IC with LIN Interface, Nonlinearity Correction, Temperature Compensation
ADI
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