ADA4610-4ARZ-R7_技术文档

Low Noise, Precision, Rail-to-Rail Output,

JFET Single/Dual/Quad Op Amps

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

FEATURES

PIN CONFIGURATION

Low offset voltage

B grade: 0.4 mV maximum (ADA4610-1/ADA4610-2 only)

A grade: 1 mV maximum

OUT A

–IN A

+IN A

V–

1

2

3

4

8

7

6

5

V+

ADA4610-2

TOP VIEW

(Not to Scale)

OUT B

–IN B

+IN B

Low offset voltage drift

B grade: 4 µV/°C maximum (ADA4610-1/ADA4610-2 only)

A grade: 8 µV/°C maximum (SOIC, MSOP, LFCSP packages)

Low input bias current: 5 pA typical

Dual-supply operation: 5 V to 15 V

Low voltage noise: 0.45 µV p-p at 0.1 Hz to 10 Hz

Voltage noise density: 7.30 nV/√Hz at f = 1 kHz

Low THD + N: 0.00025%

Figure 1. ADA4610-2 8-Lead SOIC (R Suffix); for Additional Packages and

Models, See the Pin Configurations and Function Descriptions Section

No phase reversal

Rail-to-rail output

Unity-gain stable

Long-term offset voltage drift (10,000 hours): 5 µV typical

Temperature hysteresis: 8 µV typical

APPLICATIONS

Instrumentation

Medical instruments

Multipole filters

Precision current measurement

Photodiode amplifiers

Sensors

Audio

GENERAL DESCRIPTION

The ADA4610-1/ADA4610-2/ADA4610-4 are precision junction

field effect transistor (JFET) amplifiers that feature low input noise

voltage, current noise, offset voltage, input bias current, and rail-to-

rail output. The ADA4610-1 is a single amplifier, the ADA4610-2 is

a dual amplifier, and the ADA4610-4 is a quad amplifier.

performance filters. Low input bias currents, low offset, and low

noise result in a wide dynamic range for photodiode amplifier

circuits. Low noise and distortion, high output current, and

excellent speed make the ADA4610-1/ADA4610-2/ADA4610-4

great choices for audio applications.

The combination of low offset, noise, and very low input bias

current makes these amplifiers especially suitable for high

impedance sensor amplification and precise current measurements

using shunts. With excellent dc precision, low noise, and fast

settling time, the ADA4610-1/ADA4610-2/ADA4610-4 provide

superior accuracy in medical instruments, electronic measurement,

and automated test equipment. Unlike many competitive

amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 maintain

fast settling performance with substantial capacitive loads. Unlike

many older JFET amplifiers, the ADA4610-1/ADA4610-2/

ADA4610-4 do not suffer from output phase reversal when input

voltages exceed the maximum common-mode voltage range.

The ADA4610-1/ADA4610-2/ADA4610-4 are specified over

the −40°C to +125°C extended industrial temperature range.

The ADA4610-1 is available in an 8-lead SOIC package and in a

5-lead SOT-23 package. The ADA4610-2 is available in 8-lead

SOIC, 8-lea d M S O P, a n d 8 -lead LFCSP packages. The ADA4610-4

is available in a 14-lead SOIC package and in a 16-lead LFCSP.

Table 1. Related Precision JFET Operational Amplifiers

Single

Dual

Quad

AD8510

AD8512

AD8513

AD8610

AD820

AD8620

AD822

Not applicable

AD824

ADA4627-1/ADA4637-1

Not applicable

ADA4001-2

Not applicable

The fast slew rate and great stability with capacitive loads make

the ADA4610-1/ADA4610-2/ADA4610-4 ideal for high

Rev. H

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Technical Support

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ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Comparative Voltage and Variable Voltage Graphs............... 17

Theory of Operation ...................................................................... 20

Applications Information .............................................................. 21

Input Overvoltage Protection................................................... 21

Peak Detector.............................................................................. 21

Current to Voltage (I to V) Conversion Applications ........... 21

Comparator Operation.............................................................. 22

Long-Term Drift......................................................................... 23

Temperature Hysteresis ............................................................. 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 27

Applications....................................................................................... 1

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Electrical Characteristics............................................................. 5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 11

Rev. H | Page 2 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

REVISION HISTORY

5/2017—Rev. G to Rev. H

11/2014—Rev. C to Rev. D

Changed CP-8-21 to CP-8-11...................................... Throughout

Changes to Features Section ............................................................1

Changes to Figure 15 Caption, Figure 16 Caption, Figure 18

Caption, and Figure 19 Caption....................................................12

Changed Functional Description Section to Theory of

Operation Section ...........................................................................20

Added Long-Term Drift Section, Temperature Hysteresis Section,

Figure 61, Figure 62, and Figure 63; Renumbered Sequentially.....23

Updated Outline Dimensions........................................................24

Changes to Ordering Guide...........................................................27

Change to Figure 56........................................................................19

5/2014—Rev. B to Rev. C

Added ADA4610-4 and 14-Lead SOIC........................... Universal

Added Voltage Noise Density to Features Section, Figure 3, and

Table 1; Renumbered Sequentially..................................................1

Changes to Table 2 ............................................................................3

Changes to Table 3 ............................................................................4

Changes to Table 4 ............................................................................6

Added Pin Configurations and Function Descriptions

Section, Figure 4 to Figure 6, Table 6, and Table 7 .......................7

Changes to Typical Performance Characteristics Section ...........8

Added Functional Description Section........................................17

Added Input Overvoltage Protection Section, Peak Detector

Section, I to V Conversion Applications Section, and

Photodiode Circuits Section..........................................................18

Change to Figure 56........................................................................18

Added Figure 62, Outline Dimensions ........................................20

Changes to Ordering Guide...........................................................20

5/2016—Rev. F to Rev. G

Changed CP-8-20 to CP-8-21...................................... Throughout

Changes to Figure 23 Caption and Figure 26 Caption...............13

Updated Outline Dimensions........................................................24

Changes to Ordering Guide...........................................................25

1/2016—Rev. E to Rev. F

Added 5-Lead SOT-23.......................................................Universal

Changed CP-8-9 to CP-8-20........................................ Throughout

Change to Features Section..............................................................1

Added Figure 3 and Table 7; Renumbered Sequentially..............8

Updated Outline Dimensions........................................................23

Changes to Ordering Guide...........................................................25

8/2012—Rev. A to Rev. B

Changes to Figure 9 ..........................................................................8

5/2012—Rev. 0 to Rev. A

Changes to Data Sheet Title and General Description Section ..1

Changed Input Impedance Parameter, Differential to Input

Capacitance Parameter, and Differential Parameter, Table 1 ......3

Added Input Resistance in Table 1..................................................3

Changed Input Impedance, Differential Parameter to Input

Capacitance, Differential Parameter, Table 2 ................................4

Added Input Resistance Parameter, Table 2 ..................................4

Added Figure 9, Figure 10, and Figure 14; Renumbered

Sequentially........................................................................................8

Added Figure 15................................................................................9

Updated Outline Dimensions........................................................16

Changes to Ordering Guide...........................................................17

4/2015—Rev. D to Rev. E

Added ADA4610-1 ............................................................Universal

Added 16-Lead LFCSP_WQ.............................................Universal

Deleted Figure 1 and Figure 3; Renumbered Sequentially ..........1

Changes to Features Section ............................................................1

Changes to Table 2 ............................................................................4

Changes to Table 3 .............................................................................5

Added Figure 2 and Table 6; Renumbered Sequentially ..............7

Added Figure 4 ..................................................................................8

Added Figure 7 ..................................................................................9

Changes to Table 8 ............................................................................9

Changes to Figure 10 Caption and Figure 13 Caption...............10

Changes to Figure 14 Caption, Figure 15, Figure 17 Caption,

and Figure 18 ...................................................................................11

Changes to Figure 22 and Figure 25 .............................................12

Changes to Figure 26 to Figure 31 ................................................13

Changes to Figure 32 and Figure 35 .............................................14

Changes to Figure 38 and Figure 40 .............................................15

Changes to Figure 42 to Figure 46 ................................................16

Changes to Figure 48, Figure 50, and Figure 53..........................17

Changes to Figure 54 and Figure 55 .............................................18

Changes to Figure 57 and Figure 58 .............................................20

Updated Outline Dimensions........................................................22

Added Figure 64 ..............................................................................23

Changes to Ordering Guide...........................................................24

12/2011—Revision 0: Initial Version

Rev. H | Page 3 of 27

ADA4610-1/ADA4610-2/ADA4610-4

SPECIFICATIONS

Data Sheet

V_SY

= 5 V, V_CM= 0 V, T_A= 25°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

V_OS

B Grade (ADA4610-1/ADA4610-2)

0.2

0.4

0.8

1

mV

−40°C < T_A< +125°C

A Grade

1.8

Offset Voltage Drift

ΔV_OS/ΔT

B Grade (ADA4610-1/ADA4610-2)¹

A Grade¹(SOIC, MSOP, LFCSP)

A Grade¹(SOT-23)

0.5

1

4

8

µV/°C

pA

nA

pA

nA

V

dB

12

25

1.5

20

0.25

+2.5

Input Bias Current

I_B

5

−40°C < T_A< +125°C

Input Offset Current

I_OS

2

Input Voltage Range

Common-Mode Rejection Ratio

−2.5

94

86

CMRR

A_VO

V_CM= −2.5 V to +2.5 V

−40°C < T_A< +125°C

R_L= 2 kΩ, V_OUT= −3.5 V to +3.5 V

110

Large Signal Voltage Gain

ADA4610-2

98

86

96

84

100

98

dB

−40°C < T_A< +125°C

ADA4610-1/ADA4610-4

−40°C < T_A< +125°C

V_CM= 0 V

Input Capacitance

Differential

Common-Mode

3.1

4.8

>10¹³

pF

Ω

Input Resistance

V_CM= 0 V

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

R_L= 2 kΩ

−40°C < T_A< +125°C

R_L= 600 Ω

−40°C < T_A< +125°C

R_L= 2 kΩ

−40°C < T_A< +125°C

R_L= 600 Ω

4.85

4.60

4.05

4.90

4.89

−4.95

−4.90

63

V

Output Voltage Low

V_OL

−4.90

−4.75

−4.80

−4.40

−40°C < T_A< +125°C

Short-Circuit Current

POWER SUPPLY

I_SC

mA

Power Supply Rejection Ratio

PSRR

V_SY= 4.5 V to 18 V

ADA4610-2

106

103

104

100

125

117

1.50

dB

mA

−40°C < T_A< +125°C

ADA4610-1/ADA4610-4

Supply Current per Amplifier

−40°C < T_A< +125°C

I_OUT= 0 mA

−40°C < T_A< +125°C

I_SY

1.70

1.85

Rev. H | Page 4 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Slew Rate

SR

R_L= 2 kΩ, A_V= 1

Rising

Falling

15¹

21

46

15.4

9.3

61

V/µs

MHz

Degrees

MHz

%

Gain Bandwidth Product

Unity-Gain Crossover

Phase Margin

GBP

UGC

φ_M

V_IN= 5 mV p-p, R_L= 2 kΩ, A_V= 100

V_IN= 5 mV p-p, R_L= 2 kΩ, A_V= 1

−3 dB Closed-Loop Bandwidth

Total Harmonic Distortion + Noise

NOISE PERFORMANCE

Voltage Noise

−3 dB

THD + N

A_V= 1, V_IN= 5 mV p-p

1 kHz, A_V= 1, R_L= 2 kΩ, V_IN= 1 V rms

10.6

0.00025

e_np-p

e_n

0.1 Hz to 10 Hz

f = 10 Hz

f = 100 Hz

f = 1 kHz

0.45

14

8.20

7.30

µV p-p

nV/√Hz

Voltage Noise Density

f = 10 kHz

¹Guaranteed by design and characterization.

ELECTRICAL CHARACTERISTICS

V_SY

= 15 V, V_CM= 0 V, T_A= 25°C, unless otherwise noted.

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

V_OS

B Grade (ADA4610-1/ADA4610-2)

0.2

0.4

0.8

1

mV

−40°C < T_A< +125°C

A Grade

1.8

Offset Voltage Drift

ΔV_OS/ΔT

B Grade (ADA4610-1/ADA4610-2)¹

A Grade¹(SOIC, MSOP, LFCSP)

A Grade¹(SOT-23)

0.5

1

4

8

12

25

µV/°C

pA

Input Bias Current

I_B

5

−40°C < T_A< +125°C

1.50

20

0.25

+12.5

nA

pA

nA

V

dB

Input Offset Current

I_OS

2

Input Voltage Range

Common-Mode Rejection Ratio

−12.5

100

96

CMRR

A_VO

V_CM= −12.5 V to +12.5 V

−40°C < T_A< +125°C

R_L= 2 kΩ, V_OUT= 13.5 V

115

Large Signal Voltage Gain

ADA4610-2

104

91

102

86

107

104

dB

−40°C < T_A< +125°C

ADA4610-1/ADA4610-4

−40°C < T_A< +125°C

V_CM= 0 V

Input Capacitance

Differential

Common-Mode

Input Resistance

3.1

4.8

>10¹³

pF

Ω

V_CM= 0 V

Rev. H | Page 5 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

R_L= 2 kΩ

−40°C < T_A< +125°C

R_L= 600 Ω

−40°C < T_A< +125°C

R_L= 2 kΩ

−40°C < T_A< +125°C

R_L= 600 Ω

14.80 14.90

14.65

14.25 14.47

13.35

V

Output Voltage Low

V_OL

−14.90

−14.85

−14.75

−14.60

−14.30

−14.68

79

−40°C < T_A< +125°C

Short-Circuit Current

POWER SUPPLY

I_SC

mA

Power Supply Rejection Ratio

ADA4610-2

PSRR

V_SY= 4.5 V to 18 V

106

103

104

100

125

117

1.60

dB

mA

−40°C < T_A< +125°C

ADA4610-1/ADA4610-4

−40°C < T_A< +125°C

I_OUT= 0 mA

−40°C < T_A< +125°C

Supply Current per Amplifier

I_SY

1.85

2.0

DYNAMIC PERFORMANCE

Slew Rate

SR

R_L= 2 kΩ, A_V= +1

Rising

Falling

17¹

25

61

16.3

9.3

66

V/µs

MHz

Degrees

MHz

%

Gain Bandwidth Product

Unity-Gain Crossover

Phase Margin

GBP

UGC

φ_M

V_IN= 5 mV p-p, R_L= 2 kΩ, A_V= 100

V_IN= 5 mV p-p, R_L= 2 kΩ, A_V= 1

−3 dB Closed-Loop Bandwidth

Total Harmonic Distortion + Noise

NOISE PERFORMANCE

Peak-to-Peak Voltage Noise

Voltage Noise Density

−3 dB

A_V= 1, V_IN= 5 mV p-p

9.5

0.00025

THD + N 1 kHz, A_V= 1, R_L= 2 kΩ, V_IN= 5 V rms

e_np-p

e_n

0.1 Hz to 10 Hz bandwidth

f = 10 Hz

f = 100 Hz

f = 1 kHz

f = 10 kHz

0.45

14

8.50

7.30

µV p-p

nV/√Hz

¹Guaranteed by design and characterization.

Rev. H | Page 6 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 4.

Parameter

Rating

Table 5. Thermal Resistance

Package Type

5-Lead SOT-23

8-Lead SOIC

8-Lead LFCSP

8-Lead MSOP

Supply Voltage

Input Voltage

Input Current¹

Storage Temperature Range

Operating Temperature Range

Junction Temperature Range

Lead Temperature (Soldering, 10 sec)

Electrostatic Discharge (ESD)

Human Body Model (HBM)²

18 V

V_S

10 mA

−65°C to +150°C

−40°C to +125°C

−65°C to +150°C

300°C

1

θ_JA

θ_JC

155.6

43

12

45

Unit

°C/W

219.4

120

57

142

115

65

14-Lead SOIC

16-Lead LFCSP

36

3.2

¹θ_JAis specified for worst-case conditions, that is, θ_JAis specified for a device

soldered in a circuit board for surface-mount packages.

2500 V

Field Induced Charge Device Model (FICDM)³1250 V

¹The input pins have clamp diodes connected to the power supply pins. Limit

the input current to 10 mA or less whenever input signals exceed the power

supply rail by 0.3 V.

ESD CAUTION

²ESDA/JEDEC JS-001-2011 applicable standard.

³JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. H | Page 7 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NIC

–IN

+IN

V–

1

2

3

4

8

7

6

5

NIC

V+

ADA4610-1

TOP VIEW

(Not to Scale)

OUT

NIC

NOTES

1. NIC = NOT INTERNALLY CONNECTED.

Figure 2. ADA4610-1 Pin Configuration, 8-Lead SOIC (R Suffix)

Table 6. ADA4610-1 Pin Function Descriptions, 8-Lead SOIC

Pin No.

Mnemonic

Description

1, 5, 8

NIC

−IN

+IN

V−

OUT

V+

Not Internally Connected.

Inverting Input.

Noninverting Input.

Negative Supply Voltage.

Output.

2

3

4

6

7

Positive Supply Voltage.

OUT

V–

1

2

3

5

4

V+

ADA4610-1

TOP VIEW

(Not to Scale)

+IN

–IN

Figure 3. ADA4610-1 Pin Configuration, 5-Lead SOT-23 (RJ Suffix)

Table 7. ADA4610-1 Pin Function Descriptions, 5-Lead SOT-23

Pin No.

Mnemonic

OUT

V−

+IN

−IN

Description

1

2

3

4

5

Output.

Negative Supply Voltage.

Noninverting Input.

Inverting Input.

V+

Positive Supply Voltage.

Rev. H | Page 8 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

OUT A

–IN A

+IN A

V–

1

2

3

4

8

7

6

5

V+

ADA4610-2

TOP VIEW

(Not to Scale)

OUT B

–IN B

+IN B

Figure 4. ADA4610-2 Pin Configuration, 8-Lead SOIC (R Suffix)

OUT A

–IN A

+IN A

V–

1

2

3

4

8

7

6

5

V+

ADA4610-2

TOP VIEW

(Not to Scale)

OUT B

–IN B

+IN B

Figure 5. ADA4610-2 Pin Configuration, 8-Lead MSOP (RM Suffix)

OUT A

–IN A

+IN A

V–

1

2

3

4

8

7

6

5

V+

OUT B

–IN B

ADA4610-2

TOP VIEW

(Not to Scale)

+IN B

NOTES

1. THE EXPOSED PAD MUST BE

CONNECTED TO V–.

Figure 6. ADA4610-2 Pin Configuration, 8-Lead LFCSP (CP Suffix)

Table 8. ADA4610-2 Pin Function Descriptions, 8-Lead SOIC, 8-Lead MSOP, and 8-Lead LFCSP

Pin No.

Mnemonic

OUT A

−IN A

+IN A

V−

+IN B

−IN B

OUT B

V+

Description

1

2

3

4

5

6

7

8

Output Channel A.

Inverting Input Channel A.

Noninverting Input Channel A.

Negative Supply Voltage.

Noninverting Input Channel B.

Inverting Input Channel B.

Output Channel B.

Positive Supply Voltage.

EPAD

Exposed Pad for the 8-Lead LFCSP (CP Suffix). The exposed pad must be connected to V−.

Rev. H | Page 9 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

–IN A

+IN A

V+

1

2

3

4

12 –IN D

11 +IN D

10 V–

ADA4610-4

TOP

VIEW

OUT A

–IN A

+IN A

V+

1

2

3

4

5

6

7

14 OUT D

13 –IN D

12 +IN D

11 V–

9

+IN C

+IN B

ADA4610-4

TOP VIEW

(Not to Scale)

+IN B

–IN B

OUT B

10 +IN C

9

8

–IN C

NOTES

OUT C

1. NIC = NOT INTERNALLY CONNECTED.

2.THE EXPOSED PAD MUST BE CONNECTED TO V–.

Figure 7. ADA4610-4 Pin Configuration, 14-Lead SOIC (R Suffix)

Figure 8. ADA4610-4 Pin Configuration, 16-Lead LFCSP (CP Suffix)

Table 9. ADA4610-4 Pin Function Descriptions, 14-Lead SOIC and 16-Lead LFCSP

Pin No.

14-Lead SOIC

16-Lead LFCSP

Mnemonic

OUT A

−IN A

+IN A

V+

Description

1

2

3

4

15

1

2

Output Channel A.

Inverting Input Channel A.

Noninverting Input Channel A.

Positive Supply Voltage.

3

5

6

7

8

9

10

11

12

4

5

6

7

8

9

+IN B

−IN B

OUT B

OUT C

−IN C

+IN C

V−

+IN D

−IN D

OUT D

NIC

Noninverting Input Channel B.

Inverting Input Channel B.

Output Channel B.

Output Channel C.

Inverting Input Channel C.

Noninverting Input Channel C.

Negative Supply Voltage.

Noninverting Input Channel D.

Inverting Input Channel D.

Output Channel D.

10

11

12

14

13, 16

13

14

Not applicable

Not Internally Connected.

Exposed Pad. The exposed pad must be connected to V−.

EPAD

Rev. H | Page 10 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, unless otherwise noted.

400

350

300

250

200

150

100

50

SOIC

350

SOIC

300

250

200

150

100

50

0

–1000 –800 –600 –400 –200

0

200 400 600 800 1000 1200

–1000 –800 –600 –400 –200

0

200 400 600 800 1000 1200

OFFSET VOLTAGE (µV)

Figure 9. Input Offset Voltage Distribution, V_SY

=

5 V

Figure 12. Input Offset Voltage Distribution, V_SY= 15 V

350

300

250

200

150

350

300

250

200

150

100

50

SOIC

100

50

0

TCV (µV/°C)

OS

TCV (µV/°C)

OS

Figure 10. Input Offset Voltage Drift (TCV_OS) Distribution, V_SY

=

5 V

Figure 13. TCV_OSDistribution, V_SY

= 15 V

1500

1000

500

0

1500

1000

500

0

–500

–1000

–1500

MEAN

MEAN + 3σ

MEAN – 3σ

MEAN

MEAN + 3σ

MEAN – 3σ

–1000

–1500

–15

–10

–5

0

5

10

15

–5

–4

–3

–2

–1

0

1

2

3

4

5

V

(V)

CM

V

(V)

CM

Figure 11. Input Offset Voltage vs. Common-Mode Input Voltage (V_CM),

V_SY5 V, R_L= ∞

Figure 14. Input Offset Voltage vs. Input Common-Mode Voltage (V_CM),

V_SY15 V, R_L= ∞

=

Rev. H | Page 11 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

50

40

50

40

30

20

10

0

30

20

10

0

–10

–20

–30

–40

–50

–10

MEAN

MEAN + 3σ

MEAN – 3σ

MEAN

MEAN + 3σ

MEAN – 3σ

–20

–30

–40

–50

–15

–10

–5

0

5

10

15

–5

–4

–3

–2

–1

0

1

2

3

4

5

V

(V)

V

(V)

CM

Figure 18. Input Bias Current vs. Common-Mode Input Voltage (V_CM),

Figure 15. Input Bias Current vs. Common-Mode Input Voltage (V_CM),

Mean and Three Standard Deviations, V_SY5 V, R_L= ∞

Mean and Three Standard Deviations, V_SY

=

15 V, R_L= ∞

=

100k

SOIC

10k

1k

10k

1k

+125°C

100

10

+125°C

100

10

+25°C

1

+25°C

–40°C

–2

1

0.1

0.01

–40°C

0.1

–15

–5

–4

–3

–1

0

1

2

3

4

5

–10

–5

0

5

10

15

V

(V)

V

(V)

CM

Figure 16. Input Bias Current vs. Common-Mode Input Voltage (V_CM),

Figure 19. Input Bias Current vs. Common-Mode Input Voltage (V_CM),

Three Temperatures, V_SY

=

5 V, R_L= ∞

Three Temperatures, V_SY

=

15 V, R_L= ∞

100

10

1

0.1

–50

0.1

–50

–25

0

25

50

75

100

125

–25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 17. Input Bias Current vs. Temperature, V_SY

=

5 V

Figure 20. Input Bias Current vs. Temperature, V_SY= 15 V

Rev. H | Page 12 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

1

0.1

0.01

0.1

0.01

0.1

1

10

SOURCE (mA)

100

1

10

SOURCE (mA)

100

I

OUT

Figure 21. Dropout Voltage (V+ − V_OUT) vs. I_OUTSource, V_SY

=

5 V

Figure 24. Dropout Voltage (V+ − V_OUT) vs. I_OUTSource, V_SY

=

15 V

10

1

0.1

0.01

0.1

1

10

100

1

10

100

I

SINK (mA)

I

SINK (mA)

OUT

Figure 25. Dropout Voltage (V_OUT− V−) vs. I_OUTSink, V_SY

= 15 V

Figure 22. Dropout Voltage (V_OUT− V−) vs. I_OUTSink, V_SY

=

5 V

120

270

120

270

100

80

225

180

135

90

100

80

225

180

135

90

GAIN

60

40

PHASE

20

0

45

20

0

45

0

–20

–40

–45

–90

–20

–40

–45

–90

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 26. Open-Loop Gain and Phase Margin vs. Frequency,

V_SY15 V, R_L= 2 kΩ, V_IN= 5 mV

Figure 23. Open-Loop Gain and Phase Margin vs. Frequency,

V_SY5 V, R_L= 2 kΩ, V_IN= 5 mV

=

Rev. H | Page 13 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

60

40

A

= +100

= +10

A

= +100

= +10

V

40

A

V

20

0

20

0

A

= +1

A = +1

V

–20

–40

–20

–40

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 27. Closed-Loop Gain vs. Frequency, V_SY

=

5 V

Figure 30. Closed-Loop Gain vs. Frequency, V_SY

=

15 V

1k

100

10

1

10

1

A

= +100

V

A

= +100

V

A

= +10

= +1

A

= +10

= +1

V

0.1

A

V

0.01

100

0.01

100

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 28. Closed-Loop Output Impedance (Z_OUT) vs. Frequency, V_SY

=

5 V

Figure 31. Closed-Loop Output Impedance (Z_OUT) vs. Frequency, V_SY

= 15 V

120

100

80

120

100

80

PSRR–

60

40

PSRR+

20

0

20

0

–20

100

–20

100

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 29. PSRR vs. Frequency, V_SY

=

5 V

Figure 32. PSRR vs. Frequency, V_SY

=

15 V

Rev. H | Page 14 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

140

120

100

140

120

100

80

60

40

60

40

20

0

100

0

100

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 33. CMRR vs. Frequency, V_SY

=

5 V

Figure 36. CMRR vs. Frequency, V_SY

=

15 V

3

12

2

1

8

4

0

–1

–4

–2

–3

–8

–12

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

TIME (µs)

Figure 37. Large Signal Transient Response, V_SY

R_L= 2 kΩ, C_L= 100 pF

= 15 V, A_V= 1,

Figure 34. Large Signal Transient Response, V_SY

R_L= 2 kΩ, C_L= 100 pF

= 5 V, A_V= 1,

75

50

25

50

25

0

–25

–50

–75

–50

–75

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

TIME (µs)

Figure 38. Small Signal Transient Response, V_SY

R_L= 2 kΩ, C_L= 100 pF

= 15 V, A_V= 1,

Figure 35. Small Signal Transient Response, V_SY

R_L= 2 kΩ, C_L= 100 pF

=

5 V, A_V= 1,

Rev. H | Page 15 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

100

10

1

10

1

10

100

1k

10k

100k

1

10

100

1k

10k

FREQUENCY (Hz)

Figure 39. Voltage Noise Density vs. Frequency, V_SY

=

5 V

Figure 41. Voltage Noise Density vs. Frequency, V_SY= 15 V

50

40

30

20

10

0

40

OS+

30

20

OS–

10

0

0.01

0.1

LOAD CAPACITANCE (nF)

1

0.01

0.1

LOAD CAPACITANCE (nF)

1

Figure 40. Overshoot vs. Load Capacitance, V_SY

R_L= 2 kΩ, V_IN= 100 mV p-p

=

5 V, A_V= 1,

Figure 42. Overshoot vs. Load Capacitance, V_SY

R_L= 2 kΩ, V_IN= 100 mV p-p

= 15 V, A_V= 1,

Rev. H | Page 16 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPHS

10

1

V

= ±5V

= 2kΩ

V

= ±15V

= 2kΩ

SY

R

f_IN^L= 1kHz

1

0.1

80kHz FILTER

0.1

0.01

0.001

0.0001

0.00001

0.001

0.0001

0.00001

0.01

0.1

1

0.001

0.01

0.1

1

10

AMPLITUDE (V rms)

Figure 43. THD + N vs. Amplitude, V_SY

=

5 V

Figure 46. THD + N vs. Amplitude, V_SY= 15 V

1

0.1

1

V

= ±5V

= 1.5V rms

SY

IN

V

= ±15V

= 5V rms

SY

IN

0.1

0.01

500kHz BAND-PASS FILTER

80kHz BAND-PASS FILTER

0.001

0.0001

0.00001

0.001

500kHz BAND-PASS FILTER

80kHz BAND-PASS FILTER

0.0001

0.00001

10

100

1k

10k

100k

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 44. THD + N vs. Frequency, V_SY

=

5 V

Figure 47. THD + N vs. Frequency, V_SY= 15 V

–40

–60

–80

16

12

8

4

0

–100

–120

–140

–160

–4

–8

–12

OUTPUT

INPUT

–16

0

100

1k

10k

100k

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

FREQUENCY (Hz)

TIME (ms)

Figure 45. Channel Separation vs. Frequency

Figure 48. No Phase Reversal, V_SY

= 15 V, A_V= +1, R_L= 2 kΩ, C_L= 100 pF

Rev. H | Page 17 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

400

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

300

+125°C

200

+85°C

100

+25°C

–40°C

0

–100

–200

–300

–400

0

1

2

3

4

5

6

7

8

9

10

0

5

10

15

V

20

(V)

25

30

35

TIME (Seconds)

SY

Figure 49. Voltage Noise, 0.1 Hz to 10 Hz

Figure 52. Supply Current (I_SY) per Amplifier vs. Supply Voltage (V_SY) at

Various Temperatures

12

10

8

12

10

8

0.01%

0.1%

6

0.01%

4

2

0

4

2

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

SETTLING TIME (µs)

Figure 50. Positive Step Settling Time

Figure 53. Negative Step Settling Time

18

16

14

12

10

8

4

2

V

= 7.3 × V

IN

OUT

V

= 7.3 × V

OUT

IN

V

OUT

0

V

IN

–2

–4

–6

6

–8

4

–10

–12

–14

–16

–18

2

V

IN

0

V

OUT

–2

–4

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

TIME (µs)

Figure 51. Positive Overload Recovery

Figure 54. Negative Overload Recovery

Rev. H | Page 18 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

3

15

10

5

V

A

R

C

= ±15V

= ±10V

= +1

SY

IN

V

A

R

C

= ±5V

SY

IN

V

L

=

±2V

V

IN

V

L

= +1

= 2kΩ

2

= 2kΩ

= 100 pF

= 100pF

INPUT

1

V

OUT

0

–1

–2

–3

0

OUTPUT

–5

–10

–15

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

–0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

TIME (µs)

Figure 55. Positive and Negative Slew Rate (V_SY

=

5 V, A_V= 1, R_L= 2 kΩ)

Figure 56. Positive and Negative Slew Rate (V_SY= 15 V, A_V= 1, R_L= 2 kΩ)

Rev. H | Page 19 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

THEORY OF OPERATION

The ADA4610-1/ADA4610-2/ADA4610-4 are manufactured

using the Analog Devices, Inc., iPolar® process, a 36 V dielectrically

isolated (DI) process with P-channel JFET technology. The

unique architecture of the ADA4610-1/ADA4610-2/ADA4610-4

makes it possible to combine high precision and high speed

characteristics into a high voltage, low power op amp. A simplified

schematic for the ADA4610-1/ADA4610-2/ADA4610-4 is

shown in Figure 57. The JFET input stage architecture offers

advantages of low input bias current, high bandwidth, high

gain, low noise, and no phase reversal when the applied input

signal exceeds the common-mode voltage range. The output

stage is rail-to-rail with high drive characteristics and low

dropout voltage for both sinking and sourcing currents.

The ADA4610-1/ADA4610-2 B grades achieve less than 0.4 mV

of offset and 4 µV/°C of offset drift; these characteristics are

usually associated with very high precision bipolar input amplifiers.

The gate current of a typical JFET doubles every 10°C, resulting

in a similar increase in input bias current over temperature. The

low power consumption characteristic of the ADA4610-1/

ADA4610-2/ADA4610-4 minimizes the die temperature, which

warrants low input bias currents even at elevated ambient tem-

peratures, making the amplifiers ideal for applications that require

low leakage specifications without active cooling. Ensure proper

printed circuit board (PCB) layout to minimize leakage currents

between PCB traces. Improper layout and board handling can

generate leakage currents exceeding the bias currents of the

operational amplifier.

The ADA4610-1/ADA4610-2/ADA4610-4 are unconditionally

stable for all gain configurations, even with capacitive loads well

in excess of 1 nF. The devices have internal protective circuitry

that allows voltages as high as 0.3 V beyond the supplies to be

applied at the input of either terminal without causing damage (for

higher input voltages, refer to the Input Overvoltage Protection

section).

The ADA4610-1/ADA4610-2/ADA4610-4 are fully specified with

supply voltages from 5 V to 15 V over the extended industrial

temperature range of −40°C to +125°C. The ADA4610-1 is

available in an 8-lead SOIC. The ADA4610-2 is available in an

8-lead MSOP, an 8-lead SOIC, and an 8-lead LFCSP. The

ADA4610-4 is available in a 14-lead SOIC and a 16-lead LFCSP.

All these packages are surface-mount type.

V+

D31

R6

R7

Q9

C3

R16

Q30

Q14

Q29

Q8

Q28

C2

RC4

+

–

1+

A2

DE5

Q12

C4

Q18

A1

Q15

DE1

R10

Q13

R11

Q5

Q1

Q4

R3

Q23

Q16

Q17

V

OUT

DE3

R2

V

J1

J2

IN+

R5

DE6

IN–

C1

DE4

Q6

Q7

Q27

DE2

R15

D26

Q25

I

4

Q24

2

3

V–

Figure 57. Simplified Schematic

Rev. H | Page 20 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

APPLICATIONS INFORMATION

The ADA4610-1/ADA4610-2/ADA4610-4, shown in Figure 58,

are ideal for building a peak detector because U2A requires dc

precision and high output current during fast peaks, and U2B

requires low input bias current (I_B) to minimize capacitance

discharge between peaks. A low leakage and low dielectric

absorption capacitor, such as polystyrene or polypropylene, is

required for C3. Reversing the diode directions causes the

circuit to detect negative peaks.

INPUT OVERVOLTAGE PROTECTION

The ADA4610-1/ADA4610-2/ADA4610-4 have internal protective

circuitry that allows voltages as high as 0.3 V beyond the supplies

to be applied at the input of either terminal without causing

damage. For higher input voltages, a series resistor is necessary

to limit the input current. Determine the resistor value by

V_IN−V_S

≤10 mA

R_S

CURRENT TO VOLTAGE (I TO V) CONVERSION

APPLICATIONS

Photodiode Circuits

where:

V_INis the input voltage.

V_Sis the voltage of either V+ or V−.

R_Sis the series resistor.

Common applications for I to V conversion include photodiode

circuits where the amplifier converts a current emitted by a diode

placed at the negative input terminal into an output voltage.

With a very low bias current of <1.5 nA up to 125°C, higher

resistor values can be used in series with the inputs. A 5 kΩ

resistor protects the inputs from voltages as high as 25 V

beyond the supplies and adds less than 10 µV to the offset.

The low input bias current, wide bandwidth, and low noise of

the ADA4610-1/ADA4610-2/ADA4610-4 make them excellent

choices for various photodiode applications, including fax

machines, fiber optic controls, motion sensors, and barcode

readers.

PEAK DETECTOR

The function of a peak detector is to capture the peak value of a

signal and produce an output equal to it. By taking advantage of

the dc precision and super low input bias current of the JFET input

amplifiers, such as the ADA4610-1/ADA4610-2/ADA4610-4, a

highly accurate peak detector can be built, as shown in Figure 58.

The circuit shown in Figure 59 uses a silicon diode with zero

bias voltage. This setup is a photovoltaic mode, which uses

many large photodiodes. This configuration limits the overall

noise and is suitable for instrumentation applications.

V

CC

C

F

+PEAK

ADA4610-1/

ADA4610-2

ADA4610-4

8

ADA4610-1/

ADA4610-2

ADA4610-4

3

2

R

F

8

5

6

U2A

4

+

–

1

U2B

D3

D4

V

EE

7

1N4148 1N4148

4

C4

50pF

C3

1µF

V

IN

4

V

EE

2

3

R7

1/2

10kΩ

ADA4610-1/

ADA4610-2

ADA4610-4

D2

1N448

1

R

C

T

D

R6

1kΩ

8

Figure 58. Positive Peak Detector

V

CC

In this application, Diode D3 and Diode D4 act as unidirectional

current switches that open up when the output is kept constant (in

hold mode). To detect a positive peak, U2A drives C3 through D3

and D4 until C3 is charged to a voltage equal to the input peak

value. Feedback from the output of the U2B + peak through R6

limits the output voltage of U2A. After detecting the peak, the

output of U2A swings low but is clamped by D2. Diode D3

reverses bias and the common node of D3, D4, and R7 is held to a

voltage equal to + peak by R7. The voltage across D4 is 0 V;

therefore, its leakage is small. The bias current of U2B is also small.

With almost no leakage, C3 has a long hold time.

Figure 59. Equivalent Preamplifier Photodiode Circuit

A larger signal bandwidth can be attained at the expense of

additional output noise. The total input capacitance (C_T) consists of

the sum of the diode capacitance (typically 30 pF to 40 pF) and

the amplifier input capacitance (<10 pF), which includes external

parasitic capacitance. C_Tcreates a zero in the frequency response

that can lead to an unstable system. To ensure stability and

optimize the bandwidth of the signal, place a capacitor in the

feedback loop of the circuit shown in Figure 59. The capacitor

creates a pole and yields a bandwidth with a corner frequency of

1/(2π(R_FC_F))

where:

R_Fis the feedback resistor.

C_Fis the feedback capacitor.

Rev. H | Page 21 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

Determine the R_Fvalue by the following ratio:

COMPARATOR OPERATION

V/I_D

Although op amps are quite different from comparators,

occasionally an unused section of a dual or a quad op amp can

be used as a comparator; however, this is not recommended for

rail-to-rail output op amps. For rail-to-rail output op amps, the

output stage is generally a ratioed current mirror with bipolar or

MOSFET transistors. With the device operating in open-loop

mode, the second stage increases the current drive to the ratioed

mirror to close the loop. However, the second stage cannot close

the loop, which results in an increase in supply current. With

the ADA4610-1/ADA4610-2/ADA4610-4 op amps configured

as comparators, the supply current can be significantly higher

(see Figure 60 for the supply current vs. the supply voltage for the

ADA4610-4). Configuring an unused section as a voltage follower

with the noninverting input connected to a voltage within the

input voltage range is recommended. The ADA4610-1/ADA4610-2/

ADA4610-4 have a unique output stage design that reduces the

excess supply current but does not entirely eliminate this effect

when the op amp is operating in open-loop mode.

where:

V is the desired output voltage of the op amp.

I_Dis the diode current.

For example, if I_Dis 100 µA and a 10 V output voltage is needed,

R_Fmust be 100 kΩ. The resistance of the photodiode (R_D) is a

junction resistance (see Figure 59).

A typical value for R_Dis 1000 MΩ. Because R_D>> R_F, the circuit

behavior is not impacted by the effect of the junction resistance.

The maximum signal bandwidth (f_MAX) is

ft

f_MAX

=

2πR_FC_T

where ft is the unity-gain frequency of the op amp.

Calculate C_Fby

C_T

C_F=

9

2πR_Fft

COMPARATOR, V

= HIGH

OUT

8

7

6

5

4

3

2

1

0

where ft is the unity-gain frequency of the op amp, and achieves a

phase margin, φ_M, of approximately 45°.

COMPARATOR, V

= LOW

OUT

Increase the C_Fvalue to obtain a higher phase margin. Setting

C_Fto twice the previous value yields approximately φ_M= 65° and a

maximal flat frequency response, but it reduces the maximum

signal bandwidth by 50%.

FOLLOWER

Using the previous parameters with a C_F≈ 7 pF, the signal

bandwidth is approximately 250 kHz.

0

5

10

15

20

(V)

25

30

35

40

V

SY

Figure 60. Supply Current (I_SY) vs. Supply Voltage (V_SY) for the ADA4610-4 Only

Rev. H | Page 22 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

LONG-TERM DRIFT

TEMPERATURE HYSTERESIS

The stability of a precision signal path over its lifetime or

between calibration procedures is dependent on the long-term

stability of the analog components in the path, such as op amps,

references, and data converters. To help system designers

predict the long-term drift of circuits that use the ADA4610-1/

ADA4610-2/ADA4610-4, Analog Devices measured the offset

voltage of multiple units for 10,000 hours (more than 13 months)

using a high precision measurement system, including an

ultrastable oil bath. To replicate real-world system performance,

the devices under test (DUTs) were soldered onto an FR4 PCB

using a standard reflow profile (as defined in the JEDEC J-STD-

020D standard), as opposed to testing them in sockets. This

manner of testing is important because expansion and

In addition to stability over time as described in the Long-Term

Drift section, it is useful to know the temperature hysteresis,

that is, the stability vs. cycling of temperature. Hysteresis is an

important parameter because it tells the system designer how

closely the signal returns to its starting amplitude after the

ambient temperature changes and subsequent return to room

temperature. Figure 62 shows the change in input offset voltage

as the temperature cycles three times from room temperature to

125°C to −40°C and back to room temperature. The dotted line

is an initial preconditioning cycle to eliminate the original

temperature-induced offset shift from exposure to production

solder reflow temperatures. In the three full cycles, the offset

hysteresis is typically only 8 µV, or 1% of its 800 µV maximum

offset voltage over the full operating temperature range. The

histogram in Figure 63 shows that the hysteresis is larger when

the device is cycled through only a half cycle, from room

temperature to 125°C and back to room temperature.

contraction of the PCB can apply stress to the integrated circuit

(IC) package and contribute to shifts in the offset voltage.

The ADA4610-1/ADA4610-2/ADA4610-4 have extremely low

long-term drift, as shown in Figure 61. The red, blue, and green

traces show sample units. Note that the ADA4610-1/

ADA4610-2/ADA4610-4 (B-grade) have a mean drift over

10,000 hours of approximately 5 µV, or less than 2% of their

maximum specified offset voltage of 400 µV at room

temperature.

150

PRECONDITION

V

= 10V

SY

CYCLE 1

CYCLE 2

CYCLE 3

100

50

60

0

MEAN

MEAN PLUS ONE STANDARD DEVIATION

MEAN MINUS ONE STANDARD DEVIATION

40

–50

20

0

–100

–150

0

–40

–20

20

40

60

80

100

120

TEMPERATURE (°C)

–20

Figure 62. Change in Offset Voltage over Three Full Temperature Cycles

SAMPLE 1

SAMPLE 2

SAMPLE 3

–40

–60

50

V

= 10V

SY

V

= 10V

HALF CYCLE

FULL CYCLE

SY

45

40

35

30

25

20

15

10

5

27 UNITS

= 25°C

27 UNITS × 3 CYCLES

HALF CYCLE = +26°C, +125°C, +26°C

FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C

T

A

TIME (Hours)

Figure 61. Measured Long-Term Drift of the ADA4610-1/ADA4610-2/

ADA4610-4 Offset Voltage over 10,000 Hours

0

50

45

40

35

30

25

20

15

10

5

0

–80

–64

–48

–32

–16

0

16

32

48

64

80

OFFSET VOLTAGE HYSTERESIS (µV)

Figure 63. Histogram Showing the Temperature Hysteresis of the Offset

Voltage over Three Full Cycles and over Three Half Cycles

Rev. H | Page 23 of 27

ADA4610-1/ADA4610-2/ADA4610-4

OUTLINE DIMENSIONS

Data Sheet

5.00 (0.1968)

4.80 (0.1890)

8

1

5

4

6.20 (0.2441)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45°

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 64. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

8

1

5

4

5.15

4.90

4.65

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.65 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.80

0.55

0.40

0.15

0.05

0.23

0.09

6°

0°

0.40

0.25

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 65. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

Rev. H | Page 24 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

3.00

2.90

2.80

5

1

4

3

3.00

2.80

2.60

1.70

1.60

1.50

2

0.95 BSC

1.90

BSC

1.30

1.15

0.90

0.20 MAX

0.08 MIN

1.45 MAX

0.95 MIN

0.55

0.45

0.15 MAX

0.05 MIN

10°

5°

0°

SEATING

PLANE

0.60

0.50 MAX

0.35 MIN

0.35

BSC

COMPLIANT TO JEDEC STANDARDS MO-178-AA

Figure 66. 5-Lead Small Outline Transistor Package [SOT-23]

(RJ-5)

Dimensions shown in millimeters

DETAIL A

(JEDEC 95)

2.44

2.34

2.24

3.10

3.00 SQ

0.50 BSC

2.90

8

5

PIN 1 INDEX

AREA

1.70

1.60

1.50

EXPOSED

PAD

0.50

0.40

0.30

4

1

0.20 MIN

TOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET

0.30

0.25

0.20

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-229-W3030D-4

Figure 67. 8-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height

(CP-8-11)

Dimensions shown in millimeters

Rev. H | Page 25 of 27

ADA4610-1/ADA4610-2/ADA4610-4

Data Sheet

8.75 (0.3445)

8.55 (0.3366)

8

7

14

1

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

1.27 (0.0500)

BSC

0.50 (0.0197)

0.25 (0.0098)

45°

1.75 (0.0689)

1.35 (0.0531)

0.25 (0.0098)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 68. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

DETAIL A

(JEDEC 95)

4.10

4.00 SQ

3.90

0.35

0.30

0.25

PIN 1

INDICATOR

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

13

16

0.65

BSC

1

12

2.25

2.10 SQ

1.95

EXPOSED

PAD

9

4

8

5

0.70

0.60

0.50

0.25 MIN

TOP VIEW

BOTTOM VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

SECTION OF THIS DATA SHEET.

0.08

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.

Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-16-23)

Dimensions shown in millimeters

Rev. H | Page 26 of 27

Data Sheet

ADA4610-1/ADA4610-2/ADA4610-4

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Package Description

Package Option

R-8

RJ-5

Branding

ADA4610-1ARZ

8-Lead Standard Small Outline Package [SOIC_N]

5-Lead Small Outline Transistor Package [SOT-23]

8-Lead Lead Frame Chip Scale Package [LFCSP]

8-Lead Mini Small Outline Package [MSOP]

ADA4610-1ARZ-R7

ADA4610-1ARZ-RL

ADA4610-1BRZ

ADA4610-1BRZ-R7

ADA4610-1BRZ-RL

ADA4610-1ARJZ-R2

ADA4610-1ARJZ-R7

ADA4610-1ARJZ-RL

ADA4610-2ACPZ-R7

ADA4610-2ACPZ-RL

ADA4610-2ARMZ

ADA4610-2ARMZ-R7

ADA4610-2ARMZ-RL

ADA4610-2ARZ

ADA4610-2ARZ-R7

ADA4610-2ARZ-RL

ADA4610-2BRZ

ADA4610-2BRZ-R7

ADA4610-2BRZ-RL

ADA4610-4ARZ

A37

A2U

RJ-5

CP-8-11

RM-8

R-8

8-Lead Mini Small Outline Package [MSOP]

8-Lead Standard Small Outline Package [SOIC_N]

14-Lead Standard Small Outline Package [SOIC_N]

16-Lead Lead Frame Chip Scale Package [LFCSP]

R-8

R-14

CP-16-23

ADA4610-4ARZ-R7

ADA4610-4ARZ-RL

ADA4610-4ACPZ-R7

ADA4610-4ACPZ-RL

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09646-0-5/17(H)

Rev. H | Page 27 of 27


型号：	ADA4610-4ARZ-R7
厂家：	ADI
描述：	Low Noise, Precision, Rail-to-Rail Output, JFET Quad Op Amplifiers 放大器光电二极管
文件：	总27页 (文件大小：1009K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADA4610-4ARZ-R7 [ADI]

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ADA4622-1ARZ

ADA4622-1ARZ-R7

ADA4622-1ARZ-RL

ADA4622-1BRZ

ADA4622-1BRZ-R7