ADA4841-1YRZ-R7 [ADI]
Low Power, Low Noise and Distortion, Rail-to-Rail Output Amplifier; 低功耗，低噪声和失真，轨到轨输出放大器
| 型号： | ADA4841-1YRZ-R7 |
| 厂家： | 
ADI |
| 描述： | Low Power, Low Noise and Distortion, Rail-to-Rail Output Amplifier |
| 文件： | 总20页 (文件大小：599K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, Low Noise and Distortion,
Rail-to-Rail Output Amplifier
ADA4841-1/ADA4841-2
CONNECTION DIAGRAMS
FEATURES
Low power: 1.1 mA/amp
Low wideband noise
2.1 nV/√Hz
1.4 pA/√Hz
Low 1/f noise
ADA4841-1
TOP VIEW
(Not to Scale)
NC
–IN
+IN
1
2
3
4
8
7
6
5
POWER DOWN
+V
S
V
OUT
–V
NC
S
7 nV/√Hz @ 10 Hz
13 pA/√Hz @ 10 Hz
Figure 1. 8-Lead SOIC (R)
Low distortion: −105 dBc @ 100 kHz, VO = 2 V p-p
High speed
80 MHz, −3 dB bandwidth (G = +1)
12 V/μs slew rate
175 ns settling time to 0.1%
Low offset voltage: 0.3 mV maximum
Rail-to-rail output
ADA4841-2
OUT1
–IN1
+IN1
1
2
3
4
8
7
6
5
+V
S
OUT2
–IN2
+IN2
–V
S
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead MSOP (RM-8) and 8-Lead SOIC_N (R)
Power down
ADA4841-1
Wide supply range: 2.7 V to 12 V
V
1
2
3
6
5
4
+V
S
OUT
APPLICATIONS
–V
POWER DOWN
–IN
S
Low power, low noise signal processing
Battery-powered instrumentation
16-bit PulSAR® ADC drivers
+IN
Figure 3. 6-Lead SOT-23 (RJ)
GENERAL DESCRIPTION
The ADA4841-1/ADA4841-2 are unity gain stable, low
noise and distortion, rail-to-rail output amplifiers that have a
quiescent current of 1.5 mA maximum. Despite their low power
consumption, these amplifiers offer low wideband voltage noise
performance of 2.1 nV/√Hz and 1.4 pA/√Hz current noise,
along with excellent spurious-free dynamic range (SFDR) of
−105 dBc at 100 kHz. To maintain a low noise environment at
lower frequencies, the amplifiers have low 1/f noise of 7 nV/√Hz
and 13 pA/√Hz at 10 Hz.
The ADA4841-1/ADA4841-2 packages feature Pb-free lead
finish. The amplifiers are rated to work over the industrial
temperature range (−40°C to +125°C).
–30
V
= ±5V
S
G = +1
–40
–50
–60
–70
2V p-p THIRD
The ADA4841-1/ADA4841-2 output can swing to less than
50 mV of either rail. The input common-mode voltage range
extends down to the negative supply. The ADA4841-1/
ADA4841-2 can drive up to 10 pF of capacitive load with
minimal peaking.
–80
–90
2V p-p SECOND
–100
–110
–120
The ADA4841-1/ADA4841-2 provide the performance required
to efficiently support emerging 16-bit to 18-bit ADCs and are
ideal for portable instrumentation, high channel count, industrial
measurement, and medical applications. The ADA4841-1/
ADA4841-2 are ideally suited to drive the AD7685/AD7686,
16-bit PulSAR ADCs.
0.01
0.1
FREQUENCY (MHz)
1
Figure 4. Harmonic Distortion
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADA4841-1/ADA4841-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Headroom Considerations........................................................ 14
Capacitance Drive ...................................................................... 15
Input Protection ......................................................................... 15
Power-Down Operation ............................................................ 16
Applications..................................................................................... 17
Typical Performance Values...................................................... 17
16-Bit ADC Driver..................................................................... 17
Reconstruction Filter ................................................................. 17
Layout Considerations............................................................... 18
Ground Plane.............................................................................. 18
Power Supply Bypassing............................................................ 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
Amplifier Description................................................................ 13
DC Errors .................................................................................... 13
Noise Considerations................................................................. 13
REVISION HISTORY
3/06—Rev. B to Rev. C
Changed DC Performance Considerations Section
Added SOT-23 Package .....................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Input Protection Section ........................................... 15
Changes to Ordering Guide .......................................................... 20
to DC Errors Section...................................................................... 13
Changes to Noise Considerations Section .................................. 14
Changes to Headroom Considerations Section and Figure 39 15
Changes to Power-Down Operation Section.............................. 16
Changes to 16-Bit ADC Driver Section,
Figure 48, and Figure 49 ................................................................ 17
Changes to Power Supply Bypassing Section ............................. 18
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide.......................................................... 20
10/05—Rev. A to Rev. B
Added ADA4841-2.............................................................Universal
Changes to General Description and Features ............................. 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 4, Table 5, and Figure 4 ..................................... 6
Changes to Figure 6.......................................................................... 7
Changes to Figure 12, Figure 13, Figure 15, and Figure 16......... 8
Deleted Figure 25; Renumber Sequentially................................. 10
Changes to Figure 24 and Figure 28............................................. 10
Changes to Figure 31...................................................................... 11
Inserted Figure 37; Renumber Sequentially................................ 12
Changes to Amplifier Description Section and Figure 39 ........ 13
9/05—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Figure 2...........................................................................1
Changes to Figure 12.........................................................................8
Changes to Figure 40...................................................................... 14
Changes to Headroom Considerations Section ......................... 15
7/05—Revision 0: Initial Version
Rev. C | Page 2 of 20
ADA4841-1/ADA4841-2
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 1 kΩ, Gain = +1, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Conditions
Min
58
Typ
Max
Unit
VO = 0.02 V p-p
VO = 2 V p-p
G = +1, VO = 9 V step, RL = 1 kΩ
G = +1, VO = 8 V step
G = +1, VO = 8 V step
80
3
13
650
1000
MHz
MHz
V/μs
ns
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3
12
ns
fC = 100 kHz, VO = 2 V p-p, G = +1
fC = 1 MHz, VO = 2 V p-p
f = 100 kHz
−111/−105
−80/−67
2.1
dBc
dBc
nV/√Hz
pA/√Hz
Input Voltage Noise
Input Current Noise
f = 100 kHz
1.4
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
40
1
3
0.1
120
300
μV
μV/°C
μA
μA
dB
5.3
0.5
VO = 4 V
103
INPUT CHARACTERISTICS
Input Resistance, Common Mode
Input Resistance, Differential Mode
Input Capacitance, Common Mode
Input Capacitance, Differential Mode
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage
90
25
1
MΩ
kΩ
pF
pF
V
3
−5.1
95
+4
VCM = Δ 4 V
115
dB
70
60
μV
nA
Input Bias Current
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enabled
>3.6
<3.2
V
V
Power down
Enable
POWER DOWN = +5 V
POWER DOWN = −5 V
1
2
μA
μA
Power Down
−13
−30
Switching Speed
Enable
Power Down
1
40
μs
μs
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current Limit
G > +1
4.9
4.955
30
60
V
Sourcing, VIN = +VS , RL = 50 Ω to GND
Sinking, VIN = −VS , RL = 50 Ω to GND
30% overshoot
mA
mA
pF
Capacitive Load Drive
POWER SUPPLY
15
Operating Range
Quiescent Current/Amplifier
2.7
12
1.5
90
V
POWER DOWN = +5 V
1.2
40
mA
μA
dB
dB
POWER DOWN = −5 V
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
+VS = +5 V to +6 V, −VS = −5 V
+VS = +5 V, −VS = −5 V to +6 V
95
96
110
120
Rev. C | Page 3 of 20
ADA4841-1/ADA4841-2
TA = 25°C, VS = 5 V, RL = 1 kΩ, Gain = +1, VCM = 2.5 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Conditions
Min
54
Typ
Max Unit
VO = 0.02 V p-p
VO = 2 V p-p
G = +1, VO = 4 V step, RL = 1 kΩ
G = +1, VO = 2 V step
G = +1, VO = 2 V step
80
3
12
175
550
MHz
MHz
V/μs
ns
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3
10
ns
fC = 100 kHz, VO = 2 V p-p
fC = 1 MHz, VO = 2 V p-p
f = 100 kHz
f = 100 kHz
f = 100 kHz
−109/−105
−78/−66
2.1
1.4
−117
dBc
dBc
nV/√Hz
pA/√Hz
dB
Input Voltage Noise
Input Current Noise
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
40
1
3
0.1
124
300
μV
μV/°C
μA
μA
dB
5.3
0.4
VO = 0.5 V to 4.5 V
103
INPUT CHARACTERISTICS
Input Resistance, Common Mode
Input Resistance, Differential Mode
Input Capacitance, Common Mode
Input Capacitance, Differential Mode
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage
90
25
1
MΩ
kΩ
pF
pF
V
3
−0.1
88
+4
VCM = Δ 1.5 V
115
dB
70
70
μV
nA
Input Bias Current
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enabled
>3.6
<3.2
Power down
V
Enable
POWER DOWN = 5 V
POWER DOWN = 0 V
1
2
μA
μA
Power Down
−13
−30
Switching Speed
Enable
Power Down
1
40
μs
μs
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current Limit
G > +1
0.08 to 4.92
0.029 to 4.974
V
Sourcing, VIN = +VS, RL = 50 Ω to VCM
Sinking, VIN = −VS, RL = 50 Ω to VCM
30% overshoot
30
60
15
mA
mA
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
2.7
12
1.4
70
V
POWER DOWN = 5 V
1.1
35
mA
μA
dB
dB
POWER DOWN = 0 V
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
+VS = +5 V to +6 V, −VS = 0 V
+VS = +5 V, −VS = 0 V to −1 V
95
96
110
120
Rev. C | Page 4 of 20
ADA4841-1/ADA4841-2
TA = 25°C, VS = 3 V, RL = 1 kΩ, Gain =+1, VCM = 1.5 V, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3
VO = 0.02 V p-p
52
10
80
12
120
250
MHz
V/μs
ns
G = +1, VO = 2 V step, RL = 1 kΩ
G = +1, VO = 1 V step
G = +1, VO = 1 V step
ns
fC = 100 kHz, VO = 1 V p-p
fC = 1 MHz, VO = 1 V p-p
f = 100 kHz
−97/−100
−79/−80
2.1
dBc
dBc
nV/√Hz
Input Voltage Noise
Input Current Noise
f = 100 kHz
1.4
pA/√Hz
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
40
1
3
0.1
123
300
μV
μV/°C
μA
μA
dB
5.3
0.5
VO = 0.5 V to 2.5 V
101
INPUT CHARACTERISTICS
Input Resistance, Common Mode
Input Resistance, Differential Mode
Input Capacitance, Common Mode
Input Capacitance, Differential Mode
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage
90
25
1
MΩ
kΩ
pF
pF
V
3
−0.1
86
+2
VCM = Δ 0.4 V
115
dB
70
60
μV
nA
Input Bias Current
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enabled
>1.6
<1.2
Power down
V
Enable
POWER DOWN = 3 V
POWER DOWN = 0 V
1
2
μA
μA
Power Down
−10
−30
Switching Speed
Enable
Power Down
1
40
μs
μs
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current Limit
G > +1
0.045 to 2.955
0.023 to 2.988
V
Sourcing, VIN = +VS, RL = 50 Ω to VCM
Sinking, VIN = −VS, RL = 50 Ω to VCM
30% overshoot
30
60
30
mA
mA
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
2.7
12
1.3
60
V
POWER DOWN = 3 V
1.1
25
mA
μA
dB
dB
POWER DOWN = 0 V
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
+VS = +3 V to +4 V, −VS = 0 V
+VS = +3 V, −VS = 0 V to −1 V
95
96
110
120
Rev. C | Page 5 of 20
ADA4841-1/ADA4841-2
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the amplifier’s drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
Rating
12.6 V
See Figure 5
−VS − 0.5 V to +VS + 0.5 V
±1.8 V
−65°C to +125°C
−40°C to +85°C
JEDEC J-STD-20
150°C
PD = Quiescent Power + (Total Drive Power − Load Power)
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS
2
VOUT
RL
VOUT
RL
PD =
(
VS ×IS
)
+
×
−
Junction Temperature
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2
VS/4
PD = VS ×IS +
( )
RL
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for device soldered in circuit board for surface-mount
packages.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θJA.
Table 5. Thermal Resistance
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead MSOP
(145°C/W), 8-lead SOIC_N (125°C/W) and the 6-lead SOT-23
(170°C/W) on a JEDEC standard 4-layer board. θJA values are
approximations.
Package Type
8-lead SOIC_N
8-lead MSOP
6-Lead SOT-23
θJA
Unit
°C/W
°C/W
°C/W
125
130
170
2.0
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4841-1/
ADA4841-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
amplifiers. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
1.5
SOIC
MSOP
1.0
SOT-23
0.5
0
–55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115 125
AMBIENT TEMPERATURE (°C)
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 6 of 20
ADA4841-1/ADA4841-2
TYPICAL PERFORMANCE CHARACTERISTICS
RL = 1 kΩ, unless otherwise noted.
3
3
0
V
V
= 5V
= 20mV p-p
V
V
= 2V pp
= 5V
S
OUT
G = +1
–40°C
+25°C
IN
S
G = +1
0
–3
G = +10
+125°C
G = +2
–3
–6
–9
–6
–9
–12
0.1
1
10
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 6. Large Signal Frequency Response vs. Gain
Figure 9. Small Signal Frequency Response vs. Temperature
6
3
2
1
V
= 20mV p-p
V
= 20mV p-p
IN
20pF
WITH
100Ω SNUBBER
IN
20pF
V
= +5V
S
G = +1
= 5V
G = +1
V = ±5V
S
V
= +3V
S
V
S
0
–1
–2
–3
–4
–5
–6
0
0pF
10pF
–3
–6
–9
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 10. Small Signal Frequency Response vs. Supply Voltage
Figure 7. Small Signal Frequency Response vs. Capacitive Load
3
3
V
V
= 20mV p-p
= 5V
V = ±5V
S
G = +1
IN
S
G = –1
G = +1
10mV p-p
0
–3
G = +10
0
–3
–6
–9
2V p-p
400mV p-p
20mV p-p
–6
–9
100mV p-p
–12
0.1
0.1
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 8. Small Signal Frequency Response vs. Gain
Figure 11. Frequency Response for Various VOUT
Rev. C | Page 7 of 20
ADA4841-1/ADA4841-2
–30
–40
140
0
V
= 5V
V
= 2V p-p
S
OUT
G = +2
MAGNITUDE
120
100
80
–20
–40
–60
–80
–100
–120
–140
–160
–50
+5V SECOND
–60
PHASE
–70
60
+3V SECOND
–80
+3V THIRD
40
–90
–100
–110
–120
–130
20
±5V THIRD
+5V THIRD
0
–20
10
±5V SECOND
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
0.01
0.1
FREQUENCY (MHz)
1
Figure 15. Harmonic Distortion vs. Frequency for Various Supplies
Figure 12. Open-Loop Gain and Phase vs. Frequency
–30
–40
10
V
V
= + 5V
OUT
S
= 2V p-p
V
= ±5V
S
–50
G = +5 THIRD
–60
–70
–80
G = +2 SECOND
G = +5 SECOND
–90
–100
–110
–120
–130
G = +1 SECOND
G = +1 THIRD
G = +2 THIRD
0.01
0.1
1
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 16. Voltage Noise vs. Frequency
Figure 13. Harmonic Distortion vs. Frequency for Various Gains
–30
100
10
1
V
= ±5V
S
V
= ±5V
G = +1
S
–40
–50
8V p-p SECOND
8V p-p THIRD
–60
–70
4V p-p THIRD
–80
4V p-p SECOND
–90
–100
–110
–120
2V p-p THIRD
2V p-p SECOND
0.01
0.1
1
0.1
10
1M
100k
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 14. Harmonic Distortion vs. Frequency for Various Output Voltages
Figure 17. Current Noise vs. Frequency
Rev. C | Page 8 of 20
ADA4841-1/ADA4841-2
55
50
45
40
35
30
25
20
15
10
5
0.25
0.24
0.23
0.22
0.21
0.20
0.19
COUNT = 190
G = +2
TIME = 50ns/DIV
V
= +3V
S
x = 0.36μV/°C
σ
= 1.21μV/°C
V
= +5V
S
V
= ±5V
S
0
–5
–4
–2
0
2
4
6
OFFSET DRIFT DISTRIBUTION (μV/°C)
Figure 21. Small Signal Transient Response for Various Supplies
Figure 18. Input Offset Voltage Drift Distribution
10
0.15
G = +2
V = 20mV p-p
IN
G = +1
V
= 5V
S
9
8
7
6
5
4
3
2
1
0
TIME = 50ns/DIV
0.14
0.13
0.12
0.11
0.10
0.09
0pF
10pF
20pF
47pF
0
1
2
3
4
5
V
(V)
IN
Figure 19. Nonlinearity vs. VIN
Figure 22. Small Signal Transient Response for Various Capacitive Loads
100
80
0.130
G = +1
TIME = 50ns/DIV
V
= ±5
S
V
= 3V
S
0.125
0.120
0.115
0.110
0.105
0.100
0.095
0.090
60
V
= 5V
40
S
20
0
–20
–40
–60
–6
–4
–2
0
2
4
6
V
(V)
OUT
Figure 20. Input Error Voltage vs. Output Voltage
Figure 23. Small Signal Transient Response for Various Supplies
Rev. C | Page 9 of 20
ADA4841-1/ADA4841-2
6
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
G = +2
= 5
TIME = 100ns/DIV
V
= 5V
V
S
IN
V
G = +1
TIME = 200ns/DIV
S
5
V
OUT
+125°C
4
3
+25°C
–40°C
2
1
0
–1
Figure 24. Input Overdrive Recovery
Figure 27. Slew Rate vs. Temperature
6
5
2.0
2.0
1.5
V
= 5V
V
⋅ 2
V
= 5V
S
IN
S
G = +2
TIME = 100ns/DIV
G = +1
V = 2V p-p
OUT
1.5
TIME = 100ns/DIV
V
OUT
1.0
1.0
4
V
OUT
0.5
0.5
V
(EXPANDED)
OUT
3
V
IN
0
0
2
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
1
0
–1
Figure 25. Output Overdrive Recovery
Figure 28. Settling Time
6
5
1.2
1.0
0.8
0.6
0.4
0.2
0
1.5
1.0
V
V
=
±
5V
= 2V p-p
S
+25°C
POWER DOWN PIN
OUT
TIME = 100ns/DIV
4
G = +2
0.5
–40°C
+125°C
3
G = +1
0
2
–0.5
–1.0
–1.5
1
V
= 5V
S
0
G = +1
V
= 1V
IN
DC
TIME = 200ns/DIV
–1
–0.2
Figure 29. Power-Up Time vs. Temperature
Figure 26. Large Signal Transient Response for Various Gains
Rev. C | Page 10 of 20
ADA4841-1/ADA4841-2
6
5
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–20
V
= 5V
S
V = 5V
S
G = +1
POWER DOWN PIN
V
= 1V
IN
DC
TIME = 10μs/DIV
4
–40
+PSR
3
+125°C
+25°C
–60
2
–80
–40°C
1
–PSR
–100
–120
0
POWER DOWN PIN
–1
–0.2
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
POWER DOWN
Figure 30.
Time vs. Temperature
Figure 33. PSR vs. Frequency
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
10
V
= 5V
V
= 5V
S
S
+125°C
+25°C
–40°C
1
0.1
0.01
0.001
–0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
POWER DOWN PIN (V)
Figure 34. Output Impedance vs. Frequency
POWER DOWN
Figure 31. Supply Current per Amplifier vs.
Pin Voltage
40
30
0
V
= ±5V
S
G = +1
–20
–40
V
= +5V
S
20
10
0
V
= ±5V
–60
–80
S
–10
–20
–30
–40
–50
V
= +3V
S
–100
–120
100
1k
10k
100k
1M
10M
100M
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 32. CMR vs. Frequency
Figure 35. Input Offset Voltage vs. Temperature for Various Supplies
Rev. C | Page 11 of 20
ADA4841-1/ADA4841-2
–40
–50
–60
–70
3.6
G = +1
V
= 5V
S
R
= 1kΩ
L
3.5
V
= +5V
S
3.4
3.3
3.2
3.1
–80
–90
A TO B
V
= +3V
S
–100
–110
–120
V
= ±5V
S
B TO A
10M
–130
–140
–40 –25 –10
5
20
35
50
65
80
95 110 125
10k
100k
1M
100M
1G
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 36. Input Bias Current vs. Temperature for Various Supplies
Figure 38. Crosstalk Output to Output
1.6
1.5
1.4
1.3
1.2
V
= ±5V
S
1.1
1.0
0.9
0.8
V
= +5V
20
S
V
= +3V
S
–40 –25 –10
5
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 37. Supply Current vs. Temperature for Various Supplies
Rev. C | Page 12 of 20
ADA4841-1/ADA4841-2
THEORY OF OPERATION
The total output voltage error is the sum of errors due to the
amplifier offset voltage and input currents. The output error
due to the offset voltage can be estimated as
AMPLIFIER DESCRIPTION
The ADA4841-1/ADA4841-2 are low power, low noise,
precision voltage-feedback op amps for single or dual voltage
supply operation. The ADA4841-1/ADA4841-2 are fabricated
on ADI’s second generation XFCB process and feature trimmed
supply current and offset voltage. The 2.1 nV/√Hz voltage noise
(very low for a 1.1 mA supply current amplifier), 40 μV offset
voltage, and sub 1 μV/°C offset drift is accomplished with an
input stage made of an undegenerated PNP input pair driving a
symmetrical folded cascode. A rail-to-rail output stage provides
the maximum linear signal range possible on low voltage
supplies and has the current drive capability needed for the
relatively low resistance feedback networks required for low
noise operation. CMRR, PSRR, and open-loop gain are all
typically above 100 dB, preserving the precision performance in
a variety of configurations. Gain bandwidth is kept high for this
power level to preserve the outstanding linearity performance
for frequencies up to 100 kHz. The ADA4841-1 has a power-
down function to further reduce power consumption. All this
results in a low noise, power efficient, precision amplifier that is
well-suited for high resolution and precision applications.
VOUT
=
ERROR
(4)
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VP −VPNOM VOUT
RF
RG
VCM
CMRR
⎛
⎞
⎟
⎠
⎜
V
+
+
+
× 1+
⎜
⎝
OFFSET
NOM
PSRR
A
where:
VOFFSET
is the offset voltage at the specified supply voltage.
NOM
This is measured with the input and output at midsupply.
VCM is the common-mode voltage.
VP is the power supply voltage.
Vp
is the specified power supply voltage.
NOM
CMRR is the common-mode rejection ratio.
PSRR is the power supply rejection ratio.
A is the dc open-loop gain.
DC ERRORS
The output error due to the input currents can be estimated as
Figure 39 shows a typical connection diagram and the major dc
error sources. The ideal transfer function (all error sources set
to 0 and infinite dc gain) can be written as
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
RF
RG
⎜
⎜
VOUT
= (RF || RG )× 1+
IB− − RS × 1+
×IB+
(5)
ERROR
⎜
⎝
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
RF
RG
⎜
VOUT = 1+
×VIP
−
×VIN
(1)
Note that setting RS equal to RF||RG compensates for the voltage
error due to the input bias current.
R
F
–
NOISE CONSIDERATIONS
– V
+
+
+ V
IN
OS
R
R
G
Figure 40 illustrates the primary noise contributors for the
typical gain configurations. The total rms output noise is
the root-mean-square of all the contributions.
+ V
–
OUT
I –
B
– V
IP
S
vn _ R
=
4kT × R
R
F
F
F
I +
B
ven
R
vn _ R
=
G
S
4kT × R
G
G
Figure 39. Typical Connection Diagram and DC Error Sources
+ vout_en –
ien
ien
This reduces to the familiar forms for inverting and
noninverting op amp gain expressions
R
vn _ R
=
4kT × R
S
S
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
⎜
VOUT = 1+
×VIP
(2)
(3)
Figure 40. Noise Sources in Typical Connection
(Noninverting gain, VIN = 0 V)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
− RF
VOUT
=
×VIN
RG
(Inverting gain, VIP = 0 V)
Rev. C | Page 13 of 20
ADA4841-1/ADA4841-2
The input stage positive limit is almost exactly a volt below the
positive supply at room temperature. Input voltages above that
start to show clipping behavior. The positive input voltage limit
increases with temperature with a coefficient of about 2 mV/°C.
The lower supply limit is nominally below the minus supply;
therefore, in a standard gain configuration, the output stage
limits the signal headroom on the negative supply side. Figure 42
and Figure 43 show the nominal CMRR behavior at the limits of
the input headroom for three temperatures—this is generated
using the subtractor topology shown in Figure 44, which avoids
the output stage limitation.
The output noise spectral density can be calculated by
vout _en =
2
2
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
RF
RG
4kTRs + ien2RS + ven
]
+
4kTRg + ien2 RF
2
2
2
⎜
4kTRf + 1+
[
⎜
⎝
(6)
where:
k is Boltzmann’s Constant.
T is the absolute temperature, degrees Kelvin.
300
260
220
180
ien
is the amplifier input current noise spectral density, pA/√Hz.
is the amplifier input voltage spectral density, nV/√Hz.
ven
140
100
+125°C
+25°C
RS is the source resistance as shown in Figure 40.
60
20
RF and RG are the feedback network resistances, as shown in
Figure 40.
–40°C
–20
–60
–100
–140
–180
–220
–260
–300
ven
Source resistance noise, amplifier voltage noise ( ), and the
ien
voltage noise from the amplifier current noise ( × RS) are
all subject to the noise gain term (1 + RF/RG). Note that with a
2.1 nV/√Hz input voltage noise and 1.4 pA/√Hz input current,
the noise contributions of the amplifier are relatively small for
source resistances between approximately 200 Ω and 30 kΩ.
Figure 41 shows the total RTI noise due to the amplifier vs. the
source resistance. In addition, the value of the feedback resistors
used impacts the noise. It is recommended to keep the value of
feedback resistors between 250 Ω and 1 kΩ to keep the total
noise low.
3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00
COMMON-MODE VOLTAGE (V)
Figure 42. +CMV vs. Common-Mode Error vs. VOS
0
–50
–100
–150
–40°C
–200
1000
–250
+25°C
–300
–350
–400
100
–450
AMPLIFIER + RESISTOR NOISE
+125°C
–500
–550
–600
–650
–700
–750
–800
10
TOTAL AMPLIFIER NOISE
1
–4.00
–6.00 –5.80 –5.60 –5.40 –5.20 –5.00 –4.80 –4.60 –4.40 –4.20
COMMON-MODE VOLTAGE (V)
SOURCE RESISTANCE NOISE
0.1
Figure 43. −CMV vs. Common-Mode Error vs. VOS
10
100
1k
10k
100k
– V
+
+ V
–
CM
SOURCE RESISTANCE (Ω)
OUT
Figure 41. RTI Noise vs. Source Resistance
HEADROOM CONSIDERATIONS
Figure 44. Common-Range Subtractor
The ADA4841-1/ADA4841-2 are designed to provide maximum
input and output signal ranges with 16-bit to 18-bit dc linearity.
As the input or output headroom limits are reached, the signal
linearity degrades.
Rev. C | Page 14 of 20
ADA4841-1/ADA4841-2
60
50
40
30
20
10
0
Figure 45 shows the amplifier frequency response as a G = −1
inverter with the input and output stage biased near the
negative supply rail.
G = +1
6
V
= 5V
S+
V
= –150mV
S–
G = –1
V
= 20mV p-p
V
= –100mV
IN
S–
V
= –200mV
3
0
S–
V
= –50mV
S–
V
= –20mV
–3
–6
–9
–12
S–
G = +2
G = +5
10
100
1000
10000
CAPACITANCE LOAD (pF)
Figure 46. Series Resistance vs. Capacitance Load
0.1
1
10
FREQUENCY (MHz)
100
INPUT PROTECTION
The ADA4841-1/ADA4841-2 are fully protected from ESD
events, withstanding human body model ESD events of 2.5 keV
and charge device model events of 1 keV with no measured
performance degradation. The precision input is protected
with an ESD network between the power supplies and diode
clamps across the input device pair, as shown in Figure 47.
Figure 45. Small Signal Frequency Response vs. Negative Supply Bias
The input voltage (VIN) and reference voltage (VIP) are both at
0 V, (see Figure 39). +VS is biased at +5 V, and −VS is swept
from −200 mV to −20 mV. With the input and output voltages
biased 200 mV above the bottom rail, the G = −1 inverter
frequency response is not much different from what is seen
with the input and output voltages biased near midsupply.
At 150 mV bias, the frequency response starts to decrease
and at 20 mV, the inverter bandwidth is less than half its
nominal value.
VCC
BIAS
ESD
VP
ESD
ESD
ESD
VN
CAPACITANCE DRIVE
Capacitance at the output of an amplifier creates a delay within
the feedback path that, if within the bandwidth of the loop, can
create excessive ringing and oscillation. The G = +1 follower
topology has the highest loop bandwidth of any typical
configuration and, therefore, is the most vulnerable to the
effects of capacitance load.
VEE
TO REST OF AMPLIFIER
Figure 47. Input Stage and Protection Diodes
For differential voltages above approximately 1.4 V, the diode
clamps start to conduct. Too much current can cause damage
due to excessive heating. If large differential voltages need to be
sustained across the input terminals, it is recommended that the
current through the input clamps be limited to below 150 mA.
Series input resistors sized appropriately for the expected
differential overvoltage provide the needed protection.
A small resistor in series with the amplifier output and the
capacitive load mitigates the problem. Figure 46 plots the
recommended series resistance vs. capacitance for gains
of +1, +2, and +5.
The ESD clamps start to conduct for input voltages more than
0.7 V above the positive supply and input voltages more than
0.7 V below the negative supply. It is recommended that the
fault current be limited to less than 150 mA if an overvoltage
condition is expected.
Rev. C | Page 15 of 20
ADA4841-1/ADA4841-2
POWER-DOWN OPERATION
Figure 48 shows the ADA4841-1 power-down circuitry. If the
POWER DOWN
pin is left unconnected, then the base of the
input PNP transistor is pulled high through the internal pull-up
resistor to the positive supply, and the part is turned on. Pulling
POWER DOWN
the
pin approximately 1.7 V below the positive
supply turns the part off, reducing the supply current to
approximately 40 μA.
VCC
I
BIAS
ESD
ESD
POWER DOWN
TO
AMPLIFIER
BIAS
VEE
POWER DOWN
Figure 48.
Circuit
POWER DOWN
The
pin is protected with ESD clamps,
as shown in Figure 48. Voltages beyond the power supplies
cause these diodes to conduct. The guidelines for limiting the
overload current in the input protection section should also be
POWER DOWN
followed for the
pin.
Rev. C | Page 16 of 20
ADA4841-1/ADA4841-2
APPLICATIONS
TYPICAL PERFORMANCE VALUES
RECONSTRUCTION FILTER
To reduce design time and eliminate uncertainty Table 6
provides a convenient reference for typical gains, component
values, and performance parameters.
The ADA4841-1/ADA4841-2 can also be used as a reconstruction
filter at the output of DACs for suppression of the sampling
frequency. The filter shown in Figure 50 is a two-pole, 500 kHz
Sallen-Key LPF with a fixed gain of G = +1.6.
16-BIT ADC DRIVER
C2
1320pF
The combination of low noise, low power, and high speed
make the ADA4841-1/ADA4841-2 the perfect driver solution
for low power, 16-bit ADCs, such as the AD7685. Figure 49
shows a typical 16-bit single-supply application.
10μF
+5V
0.1μF
R1
249Ω
R2
249Ω
There are different challenges to a single-supply, high resolution
design, and the ADA4841-1/ADA4841-2 address these nicely.
In a single-supply system, a main challenge is using the
amplifier in buffer mode with the lowest output noise and
preserving linearity compatible with the ADC.
INPUT
C1
1320pF
OUTPUT
U1
0.1μF
10μF
–5V
Rail-to-rail input amplifiers are usually higher noise than the
ADA4841-1/ADA4841-2 and cannot be used in this mode
because of the nonlinear region around the crossover point of
their input stages. The ADA4841-1/ADA4841-2, which have no
crossover region but have a wide linear input range from 100 mV
below ground to 1 V below positive rail, solve this problem, as
shown in Figure 49. The amplifier, when configured as a
follower, has a linear signal range from 0.25 V above the minus
supply voltage (limited by the amplifier’s output stage) to 1 V
below the positive supply (limited by the amplifier input stage).
A 0 V to +4.096 V signal range can be accommodated with a
positive supply as low as +5.2 V and a negative power supply of
−0.25 V. The 5.2 V supply also allows the use of a small, low
dropout, low temperature drift ADR364 reference voltage. If
ground is used as the amplifier negative supply, then note that at
the low end of the input range close to ground, the ADA4841-1/
ADA4841-2 exhibit substantial nonlinearity, as any rail-to-rail
output amplifier. The ADA4841-1/ADA4841-2 drive a one-
pole, low-pass filter. This filter limits the already very low noise
contribution from the amplifier to the AD7685.
R3
840Ω
R4
499Ω
Figure 50. Two-Pole 500 kHz Reconstruction Filter Schematic
Setting the resistors and capacitors equal to each other greatly
simplifies the design equations for the Sallen-Key filter. The
corner frequency, or −3 dB frequency, can be described by
the equation
1
fC
=
2πR1C1
The quality factor, or Q, is shown in the equation
1
Q =
3 − K
For minimum peaking, set Q equal to 0.707.
The gain, or K, of the amplifier is
R4
R3
K =
+1
+5.2V
Resistor values are kept low for minimal noise contribution,
offset voltage, and optimal frequency response.
100nF
ADR364
100nF
10μF
100nF
ADA4841
REF
VDD VIO
0V TO 4.096V
33Ω
SDI
SCK
SDO
CNV
IN+
2.7nF
AD7685
–0.25V
IN–
GND
Figure 49. ADC Driver Schematic
Rev. C | Page 17 of 20
ADA4841-1/ADA4841-2
Table 6. Recommended Values and Typical Performance
Peaking Output Noise ADA4841-1/ Total Output Noise Including
Gain RF (Ω) RG (Ω) −3 dB BW (MHz) Slew Rate (V/μs) (dB) ADA4841-2 Only (nV/√Hz) Resistors (nV/√Hz)
+1
+2
−1
+5
+10
+20
0
N/A
499
499
124
54.9
26.1
77
34
38
11
5
12.5
12.5
12.5
12
12
11.2
0.9
0.3
0.4
0
0
0
2
4
4
10
20
40
2
499
499
499
499
499
5.73
5.73
11.9
21.1
42.2
2.3
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors, are good choices for filter elements. Figure 51
shows the filter response.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect in the performance
of the ADA4841-1/ADA4841-2. A parallel connection of
capacitors from each of the power supply pins to ground works
best. A typical connection is shown in Figure 50. Smaller value
capacitors offer better high frequency response where larger
value electrolytics offer better low frequency performance.
Paralleling different values and sizes of capacitors helps to
ensure that the power supply pins are provided a low ac impedance
across a wide band of frequencies. This is important for minimizing
the coupling of noise into the amplifier. This can be especially
important when the amplifier PSR is starting to roll off—the
bypass capacitors can help lessen the degradation in PSR
performance.
5
0
–5
–10
–15
–20
–25
–30
–35
–40
Starting directly at the ADA4841-1/ADA4841-2 power supply
pins, the smallest value capacitor should be placed on the same
side of the board as the amplifier, and as close as possible to the
amplifier power supply pin. The ground end of the capacitor
should be connected directly to the ground plane. Keeping the
capacitors’ distance short but equal from the load is important
and can improve distortion performance. This process should
be repeated for the next largest value capacitor.
0.03
0.1
1
10
FREQUENCY (MHz)
Figure 51. Filter Frequency Response
LAYOUT CONSIDERATIONS
To ensure optimal performance, careful and deliberate attention
must be paid to the board layout, signal routing, power supply
bypassing, and grounding.
It is recommended that a 0.1 μF ceramic 0508 case be used. The
0508 case size offers low series inductance and excellent high
frequency performance. A 10 μF electrolytic capacitor should be
placed in parallel with the 0.1 μF capacitor. Depending on the
circuit parameters, some enhancement to performance can be
realized by adding additional capacitors. Each circuit is different
and should be individually analyzed for optimal performance.
GROUND PLANE
It is important to avoid ground in the areas under and around
the input and output of the ADA4841-1/ADA4841-2. Stray
capacitance created between the ground plane and the input
and output pads of a device are detrimental to high speed
amplifier performance. Stray capacitance at the inverting input,
along with the amplifier input capacitance, lowers the phase
margin and can cause instability. Stray capacitance at the output
creates a pole in the feedback loop. This can reduce phase
margin and can cause the circuit to become unstable.
Rev. C | Page 18 of 20
ADA4841-1/ADA4841-2
OUTLINE DIMENSIONS
2.90 BSC
5.00 (0.1968)
4.80 (0.1890)
6
1
5
2
4
3
8
1
5
4
2.80 BSC
1.60 BSC
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
PIN 1
INDICATOR
0.95 BSC
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
1.90
BSC
1.30
1.15
0.90
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
1.45 MAX
0.22
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
0.08
10°
4°
0°
0.60
0.45
0.30
0.50
0.30
0.15 MAX
COMPLIANT TO JEDEC STANDARDS MS-012-AA
SEATING
PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Figure 54. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. C | Page 19 of 20
ADA4841-1/ADA4841-2
ORDERING GUIDE
Model
ADA4841-1YRZ1
Temperature Range
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package Option
Ordering Quantity
Branding
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
R-8
R-8
R-8
RJ-6
RJ-6
RJ-6
RM-8
RM-8
RM-8
R-8
1
ADA4841-1YRZ-R71
ADA4841-1YRZ-RL1
ADA4841-1YRJZ-R21
ADA4841-1YRJZ-R71
ADA4841-1YRJZ-RL1
ADA4841-2YRMZ1
ADA4841-2YRMZ-R71
ADA4841-2YRMZ-RL1
ADA4841-2YRZ1
1,000
2,500
250
3,000
10,000
1
1,000
3,000
1
1,000
2,500
HQB
HQB
HQB
HRB
HRB
HRB
ADA4841-2YRZ-R71
ADA4841-2YRZ-RL1
R-8
R-8
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05614–0–3/06(C)
Rev. C | Page 20 of 20
相关型号：
ADA4841-2YCPZ-R7
DUAL OP-AMP, 300 uV OFFSET-MAX, PDSO8, 3 X 3 MM, ROHS COMPLIANT, MO-229WEED, LFCSP-8
ROCHESTER
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