ADA4891-2ARM-EBZ [ADI]
Low Cost CMOS, High Speed, Rail-to-Rail Amplifiers; 低成本CMOS ，高速，轨到轨放大器
| 型号： | ADA4891-2ARM-EBZ |
| 厂家： | 
ADI |
| 描述： | Low Cost CMOS, High Speed, Rail-to-Rail Amplifiers |
| 文件： | 总24页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost CMOS, High Speed,
Rail-to-Rail Amplifiers
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
FEATURES
CONNECTION DIAGRAMS
ADA4891-1
High speed and fast settling
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
+V
−3 dB bandwidth: 220 MHz (G = +1)
Slew rate: 170 V/μs
Settling time to 0.1%: 28 ns
S
OUT
NC
–V
S
Video specifications (G = +2, RL = 150 Ω)
0.1 dB gain flatness: 25 MHz
Differential gain error: 0.05%
Differential phase error: 0.25°
Single-supply operation
Wide supply range: 2.7 V to 5.5 V
Output swings to within 50 mV of supply rails
Low distortion: 79 dBc SFDR at 1 MHz
Linear output current: 125 mA at −40 dBc
Low power: 4.4 mA per amplifier
NC = NO CONNECT
Figure 1. 8-Lead SOIC_N (R-8)
ADA4891-1
1
2
3
+V
S
OUT
–V
5
4
S
+IN
–IN
Figure 2. 5-Lead SOT-23 (RJ-5)
APPLICATIONS
ADA4891-2
Imaging
Consumer video
Active filters
Coaxial cable drivers
Clock buffers
OUT1
–IN1
1
2
3
4
8
7
6
5
+V
S
OUT2
–IN2
+IN2
+IN1
–V
S
NC = NO CONNECT
Photodiode preamp
Contact image sensor and buffers
Figure 3. 8-Lead SOIC_N (R-8) and 8-Lead MSOP (RM-8)
ADA4891-3
GENERAL DESCRIPTION
PD1
PD2
PD3
1
2
3
4
5
6
7
14 OUT2
13 –IN2
12 +IN2
The ADA4891-1 (single), ADA4891-2 (dual), ADA4891-3 (triple),
and ADA4891-4 (quad) are CMOS, high speed amplifiers that
offer high performance at a low cost. The amplifiers feature true
single-supply capability, with an input voltage range that extends
300 mV below the negative rail.
+V
11 –V
S
S
+IN1
–IN1
10 +IN3
9
8
–IN3
In spite of their low cost, the ADA4891 family provides high
performance and versatility. The rail-to-rail output stage enables
the output to swing to within 50 mV of each rail, enabling maxi-
mum dynamic range.
OUT1
OUT3
Figure 4. 14-Lead SOIC_N (R-14) and 14-Lead TSSOP (RU-14)
ADA4891-4
The ADA4891 family of amplifiers is ideal for imaging applica-
tions, such as consumer video, CCD buffers, and contact image
sensor and buffers. Low distortion and fast settling time also
make them ideal for active filter applications.
1
2
3
4
5
6
7
14
13
OUT4
–IN4
OUT1
–IN1
12 +IN4
+IN1
11
–V
S
+V
S
10
9
+IN3
–IN3
The ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4 are avail-
able in a wide variety of packages. The ADA4891-1 is available
in 8-lead SOIC and 5-lead SOT-23 packages. The ADA4891-2
is available in 8-lead SOIC and 8-lead MSOP packages. The
ADA4891-3 and ADA4891-4 are available in 14-lead SOIC and
14-lead TSSOP packages. The amplifiers are specified to operate
over the extended temperature range of −40°C to +125°C.
+IN2
–IN2
8
OUT3
OUT2
Figure 5. 14-Lead SOIC_N (R-14) and 14-Lead TSSOP (RU-14)
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Values ............................................................... 15
Effect of RF on 0.1 dB Gain Flatness ........................................ 16
Driving Capacitive Loads.......................................................... 17
Terminating Unused Amplifiers .............................................. 18
Disable Feature (ADA4891-3 Only) ........................................ 18
Single-Supply Operation ........................................................... 18
Video Reconstruction Filter...................................................... 19
Multiplexer.................................................................................. 19
Layout, Grounding, and Bypassing.............................................. 20
Power Supply Bypassing............................................................ 20
Grounding................................................................................... 20
Input and Output Capacitance ................................................. 20
Input-to-Output Coupling........................................................ 20
Leakage Currents........................................................................ 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagrams...................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Operation ............................................................................... 3
3 V Operation ............................................................................... 4
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Applications Information .............................................................. 15
Using the ADA4891 ................................................................... 15
Wideband, Noninverting Gain Operation.............................. 15
Wideband, Inverting Gain Operation ..................................... 15
REVISION HISTORY
7/10—Rev. A to Rev. B
Changes to Figure 52...................................................................... 16
Added Figure 53 ............................................................................. 16
Changed Layout of Driving Capacitive Loads Section.............. 17
Added Disable Feature (ADA4891-3 Only) Section
and Single-Supply Operation Section.......................................... 18
Added Multiplexer Section ........................................................... 19
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide.......................................................... 23
Added ADA4891-3 and ADA4891-4...............................Universal
Added 14-Lead SOIC and 14-Lead TSSOP Packages....Universal
Deleted Figure 4; Renumbered Figures Sequentially................... 1
Changes to Features Section and General Description Section. 1
Added Figure 4 and Figure 5........................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Maximum Power Dissipation Section
and Figure 6....................................................................................... 6
Added Table 4; Renumbered Tables Sequentially ........................ 6
Deleted Figure 11.............................................................................. 6
Changes to Typical Performance Characteristics Section........... 7
Deleted Figure 12.............................................................................. 7
Changes to Wideband, Noninverting Gain Operation Section,
Wideband, Inverting Gain Operation Section, and Table 5 ..... 15
Added Table 6.................................................................................. 16
6/10—Rev. 0 to Rev. A
Changes to Figure 26.........................................................................9
Changes to Figure 33 and Figure 34............................................. 10
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 18
2/10—Revision 0: Initial Version
Rev. B | Page 2 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
SPECIFICATIONS
5 V OPERATION
TA = 25°C, VS = 5 V, RL = 1 kΩ to 2.5 V, unless otherwise noted. All specifications are for the ADA4891-1, ADA4891-2, ADA4891-3, and
ADA4891-4, unless otherwise noted. For the ADA4891-1 and ADA4891-2, RF = 604 ꢀ; for the ADA4891-3 and ADA4891-4, RF = 453 ꢀ,
unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth
ADA4891-1/ADA4891-2, G = +1, VO = 0.2 V p-p
ADA4891-3/ADA4891-4, G = +1, VO = 0.2 V p-p
ADA4891-1/ADA4891-2, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V
240
220
90
MHz
MHz
MHz
ADA4891-3/ADA4891-4, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V
ADA4891-1/ADA4891-2, G = +2, VO = 2 V p-p,
RL = 150 Ω to 2.5 V, RF = 604 Ω
ADA4891-3/ADA4891-4, G = +2, VO = 2 V p-p,
RL = 150 Ω to 2.5 V, RF = 374 Ω
96
25
25
MHz
MHz
MHz
Bandwidth for 0.1 dB Gain Flatness
Slew Rate, tR/tF
−3 dB Large-Signal Frequency Response
Settling Time to 0.1%
G = +2, VO = 2 V step, 10% to 90%
G = +2, VO = 2 V p-p, RL = 150 Ω
G = +2, VO = 2 V step
170/210
40
28
V/μs
MHz
ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3
fC = 1 MHz, VO = 2 V p-p, G = +1
fC = 1 MHz, VO = 2 V p-p, G = −1
f = 1 MHz
G = +2, RL = 150 Ω to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
f = 5 MHz, G = +2, VO = 2 V p-p
−79/−93
−75/−91
9
0.05
0.25
dBc
dBc
nV/√Hz
%
Degrees
dB
Input Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
All-Hostile Crosstalk
−80
DC PERFORMANCE
Input Offset Voltage
2.5
3.1
6
+2
83
71
10
mV
mV
μV/°C
pA
dB
dB
TMIN to TMAX
Offset Drift
Input Bias Current
Open-Loop Gain
−50
77
+50
RL = 1 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
5
3.2
−VS − 0.3 to
+VS − 0.8
GΩ
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 3.0 V
OUTPUT CHARACTERISTICS
88
dB
Output Voltage Swing
RL = 1 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
1% THD with 1 MHz, VO = 2 V p-p
0.01 to 4.98
0.08 to 4.90
125
V
V
mA
Output Current
Short-Circuit Current
Sourcing
205
307
mA
mA
Sinking
POWER-DOWN PINS (PD1, PD2, PD3)
Threshold Voltage, VTH
Bias Current
ADA4891-3 only
2.4
65
−22
V
nA
μA
Part enabled
Part powered down
Rev. B | Page 3 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
Parameter
Test Conditions/Comments
Min
Typ
166
49
Max
Unit
ns
ns
Turn-On Time
Turn-Off Time
Part enabled, output rises to 90% of final value
Part powered down, output falls to 10% of final
value
POWER SUPPLY
Operating Range
2.7
5.5
V
Quiescent Current per Amplifier
Supply Current When Powered Down
Power Supply Rejection Ratio (PSRR)
Positive PSRR
4.4
0.8
mA
mA
ADA4891-3 only
+VS = 5 V to 5.25 V, −VS = 0 V
+VS = 5 V, −VS = −0.25 V to 0 V
65
63
dB
dB
°C
Negative PSRR
OPERATING TEMPERATURE RANGE
−40
+125
3 V OPERATION
TA = 25°C, VS = 3 V, RL = 1 kΩ to 1.5 V, unless otherwise noted. All specifications are for the ADA4891-1, ADA4891-2, ADA4891-3, and
ADA4891-4, unless otherwise noted. For the ADA4891-1 and ADA4891-2, RF = 604 ꢀ; for the ADA4891-3 and ADA4891-4, RF = 453 ꢀ,
unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth
ADA4891-1/ADA4891-2, G = +1, VO = 0.2 V p-p
ADA4891-3/ADA4891-4, G = +1, VO = 0.2 V p-p
ADA4891-1/ADA4891-2, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 1.5 V
190
175
75
MHz
MHz
MHz
ADA4891-3/ADA4891-4, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 1.5 V
ADA4891-1/ADA4891-2, G = +2, VO = 2 V p-p,
RL = 150 Ω to 1.5 V, RF = 604 Ω
ADA4891-3/ADA4891-4, G = +2, VO = 2 V p-p,
RL = 150 Ω to 1.5 V, RF = 374 Ω
G = +2, VO = 2 V step, 10% to 90%
80
18
18
MHz
MHz
MHz
Bandwidth for 0.1 dB Gain Flatness
Slew Rate, tR/tF
140/230
40
30
V/μs
MHz
ns
−3 dB Large-Signal Frequency Response G = +2, VO = 2 V p-p, RL = 150 Ω
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3
Input Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
All-Hostile Crosstalk
G = +2, VO = 2 V step
fC = 1 MHz, VO = 2 V p-p, G = −1
f = 1 MHz
G = +2, RL = 150 Ω to 0.5 V, +VS = 2 V, −VS = −1 V
G = +2, RL = 150 Ω to 0.5 V, +VS = 2 V, −VS = −1 V
f = 5 MHz, G = +2
−70/−89
9
0.23
0.77
−80
dBc
nV/√Hz
%
Degrees
dB
DC PERFORMANCE
Input Offset Voltage
2.5
3.1
6
+2
76
65
10
mV
mV
μV/°C
pA
dB
dB
TMIN to TMAX
Offset Drift
Input Bias Current
Open-Loop Gain
−50
72
+50
RL = 1 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
5
3.2
−VS − 0.3 to
+VS − 0.8
GΩ
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 1.5 V
87
dB
Rev. B | Page 4 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
1% THD with 1 MHz, VO = 2 V p-p
0.01 to 2.98
0.07 to 2.87
37
V
V
mA
Output Current
Short-Circuit Current
Sourcing
80
163
mA
mA
Sinking
POWER-DOWN PINS (PD1, PD2, PD3)
Threshold Voltage, VTH
Bias Current
ADA4891-3 only
1.3
48
−13
185
58
V
Part enabled
nA
μA
ns
ns
Part powered down
Turn-On Time
Turn-Off Time
Part enabled, output rises to 90% of final value
Part powered down, output falls to 10% of final
value
POWER SUPPLY
Operating Range
2.7
5.5
V
Quiescent Current per Amplifier
Supply Current When Powered Down
Power Supply Rejection Ratio (PSRR)
Positive PSRR
3.5
0.73
mA
mA
ADA4891-3 only
+VS = 3 V to 3.15 V, −VS = 0 V
+VS = 3 V, −VS = −0.15 V to 0 V
76
72
dB
dB
°C
Negative PSRR
OPERATING TEMPERATURE RANGE
−40
+125
Rev. B | Page 5 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
ABSOLUTE MAXIMUM RATINGS
To ensure proper operation, it is necessary to observe the maxi-
mum power derating curves shown in Figure 6. These curves
are derived by setting TJ = 150°C in Equation 1. Figure 6 shows
the maximum safe power dissipation in the package vs. the
ambient temperature on a JEDEC standard 4-layer board.
2.0
Table 3.
Parameter
Rating
Supply Voltage
6 V
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
−VS − 0.5 V to +VS
VS
−65°C to +125°C
−40°C to +125°C
300°C
T
= 150°C
J
14-LEAD TSSOP
1.5
1.0
0.5
0
8-LEAD SOIC_N
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
8-LEAD MSOP
5-LEAD SOT-23
14-LEAD SOIC_N
MAXIMUM POWER DISSIPATION
–55 –35 –15
5
25
45
65
85
105
125
The maximum power that can be safely dissipated by the
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4 is limited
by the associated rise in junction temperature. The maximum
safe junction temperature for plastic encapsulated devices is
determined by the glass transition temperature of the plastic,
approximately 150°C. Temporarily exceeding this limit can
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure.
AMBIENT TEMPERATURE (°C)
Figure 6. Maximum Power Dissipation vs. Ambient Temperature
Table 4 lists the thermal resistance (θJA) for each ADA4891-1/
ADA4891-2/ADA4891-3/ADA4891-4 package.
Table 4.
Package Type
5-Lead SOT-23
8-Lead SOIC_N
8-Lead MSOP
14-Lead SOIC_N
14-Lead TSSOP
θJA
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
146
115
133
162
108
The still-air thermal properties of the package (θJA), the ambient
temperature (TA), and the total power dissipated in the package
(PD) can be used to determine the junction temperature of the die.
The junction temperature can be calculated as
ESD CAUTION
TJ = TA + (PD × θJA)
(1)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. It can be calculated by
PD = (VT × IS) + (VS − VOUT) × (VOUT/RL) (2)
where:
VT is the total supply rail.
IS is the quiescent current.
VS is the positive supply rail.
V
OUT is the output of the amplifier.
RL is the output load of the amplifier.
Rev. B | Page 6 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, all plots are characterized for the ADA4891-1, ADA4891-2, ADA4891-3, and ADA4891-4. For the ADA4891-1
and ADA4891-2, the typical RF value is 604 ꢀ. For the ADA4891-3 and ADA4891-4, the typical RF value is 453 ꢀ.
4
3
5
4
3
G = –1 OR +2
2
2
G = +1
1
1
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
G = +1
G = –1
OR +2
–1
–2
–3
–4
–5
–6
–7
G = +10
G = +5
G = +5
G = +10
V
V
= 5V
S
V
V
R
R
= 5V
S
= 200mV p-p
OUT
= 200mV p-p
OUT
–8
–9
R
R
= 453ꢀ
= 1kꢀ
F
L
= 604Ω
= 1kΩ
F
L
–10
0.1
0.1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-1/ADA4891-2
Figure 10. Small-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-3/ADA4891-4
6
6
V
= 2.7V
S
V = 3V
S
V
= 2.7V
S
3
0
V
= 3V
= 5V
S
3
0
–3
–6
V
S
V
= 5V
S
–3
–6
–9
–9
–12
–15
G = +1
= 200mV p-p
–12
–15
V
R
G = +1
= 200mV p-p
L
OUT
= 1kꢀ
V
R
OUT
= 1kΩ
L
0.1
1
10
FREQUENCY (MHz)
100
1k
0.1
1
10
FREQUENCY (MHz)
100
1k
Figure 8. Small-Signal Frequency Response vs. Supply Voltage,
ADA4891-1/ADA4891-2
Figure 11. Small-Signal Frequency Response vs. Supply Voltage,
ADA4891-3/ADA4891-4
5
4
5
+125°C
+85°C
+25°C
4
0°C
–40°C
+25°C
3
3
2
+85°C
0°C
2
+125°C
1
1
–40°C
0
–1
–2
–3
–4
0
–1
–2
–3
–4
V
= 5V
S
V
= 5V
S
G = +1
= 200mV p-p
G = +1
= 200mV p-p
V
R
OUT
= 1kꢀ
V
R
OUT
= 1kΩ
L
L
0.1
1
10
100
1k
0.1
1
10
FREQUENCY (MHz)
100
1k
FREQUENCY (MHz)
Figure 9. Small-Signal Frequency Response vs. Temperature, VS = 5 V,
ADA4891-1/ADA4891-2
Figure 12. Small-Signal Frequency Response vs. Temperature, VS = 5 V,
ADA4891-3/ADA4891-4
Rev. B | Page 7 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
7
7
6
+25°C
+85°C
6
+85°C
–40°C
+125°C
+25°C
0°C
5
4
5
0°C
+125°C
4
3
3
2
2
1
1
0
0
–40°C
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
V
= 3V
V = 3V
S
S
G = +1
= 200mV p-p
G = +1
V = 200mV p-p
V
R
OUT
= 1kꢀ
OUT
R = 1kꢀ
L
L
–6
0.1
–6
0.1
1
10
100
1k
1
10
FREQUENCY (MHz)
100
1k
FREQUENCY (MHz)
Figure 13. Small-Signal Frequency Response vs. Temperature, VS = 3 V,
ADA4891-1/ADA4891-2
Figure 16. Small-Signal Frequency Response vs. Temperature, VS = 3 V,
ADA4891-3/ADA4891-4
0.1
0
0.1
0
V
= 3V
S
V
V
= 5V
S
V
= 2V p-p
OUT
= 1.4V p-p
OUT
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
V
= 5V
S
V
= 1.4V p-p
OUT
V
V
= 3V
S
= 2V p-p
OUT
V
= 5V
S
V
= 5V
V
= 2V p-p
S
OUT
V
= 2V p-p
OUT
–0.4
–0.5
G = +2
G = +2
V
= 3V
S
R
R
= 374ꢀ
= 150ꢀ
R
R
= 604ꢀ
F
L
V
= 3V
F
L
V
= 1.4V p-p
S
OUT
= 150ꢀ
V
= 1.4V p-p
OUT
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. 0.1 dB Gain Flatness vs. Supply Voltage, G = +2,
ADA4891-1/ADA4891-2
Figure 17. 0.1 dB Gain Flatness vs. Supply Voltage, G = +2,
ADA4891-3/ADA4891-4
1
1
0
0
G = –1
R
= 453ꢀ
F
G = +1
F
–1
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
R
= 0ꢀ
G = +2
F
R
= 604ꢀ
–2
–3
–4
–5
–6
–7
G = +5
= 453ꢀ
G = +1
R
F
R = 0ꢀ
F
G = +5
F
R
= 604ꢀ
G = –1
F
R
= 604ꢀ
V
R
V
= 5V
= 150ꢀ
–8
–9
S
V
= 5V
L
S
L
G = +2
= 453ꢀ
R
V
= 150ꢀ
= 2V p-p
OUT
R
= 2V p-p
F
OUT
–10
0.1
0.1
1
10
100
1k
1
10
FREQUENCY (MHz)
100
1k
FREQUENCY (MHz)
Figure 15. Large-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-1/ADA4891-2
Figure 18. Large-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-3/ADA4891-4
Rev. B | Page 8 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
1
0
1
0
G = –1
= 2V p-p
G = –1
V = 2V p-p
OUT
–1
–1
V
OUT
G = +2
V = 2V p-p
–2
–3
–4
–5
–6
–7
–2
–3
–4
–5
–6
–7
OUT
G = +2
= 2V p-p
G = +1
V = 1V p-p
OUT
G = +1
= 1V p-p
V
OUT
V
OUT
G = +5
= 2V p-p
V
OUT
G = +5
= 2V p-p
V
OUT
V
R
R
= 3V
= 604ꢀ
= 150ꢀ
V
R
R
= 3V
S
–8
–9
–8
–9
S
= 453ꢀ
F
L
F
L
= 150ꢀ
–10
0.1
–10
0.1
1
10
FREQUENCY (MHz)
100
1k
1
10
FREQUENCY (MHz)
100
1k
Figure 19. Large-Signal Frequency Response vs. Gain, VS = 3 V,
ADA4891-1/ADA4891-2
Figure 22. Large-Signal Frequency Response vs. Gain, VS = 3 V,
ADA4891-3/ADA4891-4
–40
–30
V
= 5V
V
= 3V
S
L
S
L
R
V
= 1kꢀ
R
V
= 1kꢀ
G = +2
G = +1
THIRD HARMONIC
= 2V p-p
–50
–60
= 2V p-p
OUT
OUT
SECOND HARMONIC
–40
–50
–60
–70
–80
–90
G = +1
SECOND HARMONIC
–70
G = +1
G = +2
SECOND HARMONIC
SECOND HARMONIC
–80
+V = +1.9V
S
–90
OUT
–100
–110
–120
G = +2
THIRD HARMONIC
IN
50ꢀ
1kꢀ
G = +2
THIRD HARMONIC
–V = –1.1V
S
G = +1
THIRD HARMONIC
G = +1 CONFIGURATION
0.1
1
10
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 5 V
Figure 23. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 3 V
–40
–40
V
= 5V
= 604ꢀ
= 1kꢀ
G = +1
SECOND HARMONIC
G = –1
+V = +1.9V
S
S
SECOND HARMONIC
R
R
F
G = +1
–50
–60
–50
–60
fCL= 1MHz
CONFIGURATION
OUT
IN
50ꢀ
1kꢀ
G = –1
SECOND HARMONIC
–70
–70
–V = –1.1V
S
–80
–80
G = –1
–90
–90
THIRD HARMONIC
G = +1
SECOND HARMONIC
G = –1
–100
–110
–120
–100
–110
–120
G = +1
THIRD HARMONIC
THIRD HARMONIC
G = +1
V
= 3V
fCS= 1MHz
THIRD HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5 3.0
OUTPUT VOLTAGE (V p-p)
OUTPUT VOLTAGE (V p-p)
Figure 24. Harmonic Distortion (HD2, HD3) vs. Output Voltage, VS = 3 V
Figure 21. Harmonic Distortion (HD2, HD3) vs. Output Voltage, VS = 5 V
Rev. B | Page 9 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
–40
1k
100
10
G = +2
V
= 3V
S
R
R
= 604ꢀ
= 150ꢀ
SECOND HARMONIC
F
fCL= 1MHz
V
= 3V
S
–50
–60
THIRD HARMONIC
–70
V
= 5V
S
V
= 5V
S
THIRD HARMONIC
SECOND HARMONIC
–80
–90
V
= 5V
S
G = +1
–100
1
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
100
1k
10k
100k
1M
10M
OUTPUT VOLTAGE (V p-p)
FREQUENCY (Hz)
Figure 25. Harmonic Distortion (HD2, HD3) vs. Output Voltage, G = +2
Figure 28. Input Voltage Noise vs. Frequency
90
80
70
60
50
40
30
20
10
0
0
0.06
0.04
0.02
0
V
= 5V
= 1kꢀ
S
L
R
–18
–36
–54
–72
–90
–108
–126
–144
–162
–180
GAIN
–0.02
–0.04
–0.06
V
R
= 5V, G = +2
= 604ꢀ, R = 150ꢀ
L
S
F
PHASE
ST
1
ND
RD
TH
TH
TH
TH
TH
TH
TH
10
2
3
4
5
6
7
8
9
0.3
0.2
0.1
0
–0.1
–0.2
V
= 5V, G = +2
= 604ꢀ, R = 150ꢀ
L
S
R
F
–0.3
ST
ND
RD
TH
TH
TH
TH
TH
TH
TH
10
–10
0.001
1
2
3
4
5
6
7
8
9
0.01
0.1
1
10
100
1k
MODULATING RAMP LEVEL (IRE)
FREQUENCY (MHz)
Figure 29. Differential Gain and Phase Errors
Figure 26. Open-Loop Gain and Phase vs. Frequency
7
6
5
4
3
2
7
6
5
4
3
2
C
= 47pF
C
= 47pF
L
L
C
= 22pF
= 10pF
L
C
= 22pF
= 10pF
L
C
L
C
L
1
0
1
0
C
= 0pF
L
C
L
= 0pF
–1
–2
–1
V
= 5V
V
= 5V
S
S
–2
–3
–4
G = +2
R
V
G = +2
R
V
= 150ꢀ
= 150ꢀ
–3
–4
L
L
= 200mV p-p
1
= 200mV p-p
OUT
OUT
0.1
10
100
1k
0.1
1
10
FREQUENCY (MHz)
100
1k
FREQUENCY (MHz)
Figure 27. Small-Signal Frequency Response vs. CL,
ADA4891-1/ADA4891-2
Figure 30. Small-Signal Frequency Response vs. CL,
ADA4891-3/ADA4891-4
Rev. B | Page 10 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
100
10
100k
10k
1k
V
= 5V
S
G = +1
1
100
10
0.1
V
= 5V
S
G = +1
1
0.01
0.01
0.01
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 31. Closed-Loop Output Impedance vs. Frequency, Part Enabled
Figure 34. Closed-Loop Output Impedance vs. Frequency, Part Disabled
(ADA4891-3 Only)
1.5
G = +1
G = +2
= 2V p-p
V
L
= 5V
S
V
= 200mV p-p
OUT
R = 1kꢀ
L
V
R
= 1kꢀ
OUT
V
= 3V
S
1.0
0.5
100
0
V
= 5V
V
= 3V
= 150ꢀ
S
S
L
R
= 150ꢀ
R
L
V
= 5V
S
V
= 3V
= 1kꢀ
S
L
R
0
–0.5
–1.0
–1.5
–100
50mV/DIV
5ns/DIV
10
20
30
40
50
60
70
80
90
TIME (ns)
Figure 32. Small-Signal Step Response, G = +1
Figure 35. Large-Signal Step Response, G = +2
V
= 5V
V = 3V
S
S
R
= 1kꢀ
R
= 1kꢀ
G = +1
= 1V p-p
L
G = +1
L
V
OUT
V
= 2V p-p
OUT
0.5
1
0
R
= 150ꢀ
L
R
= 150ꢀ
L
0
–1
–0.5
5ns/DIV
5ns/DIV
0.5V/DIV
0.5V/DIV
Figure 36. Large-Signal Step Response, VS = 3 V, G = +1
Figure 33. Large-Signal Step Response, VS = 5 V, G = +1
Rev. B | Page 11 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
200
190
180
170
160
150
140
0.30
V
= 5V
S
G = +2
R
V
= 5V
S
G = +2
= 150ꢀ
= 150ꢀ
L
0.20
0.10
0
R
L
V
= 2V p-p
OUT
FALLING EDGE
–0.10
–0.20
–0.30
RISING EDGE
0
25
30
35
40
45
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TIME (ns)
OUTPUT STEP (V)
Figure 37. Short-Term Settling Time to 0.1%
Figure 40. Slew Rate vs. Output Step
1
0
3
2
V
= ±2.5V
V
= ±2.5V
S
S
G = +1
= 1kꢀ
G = +1
INPUT
R
R
= 1kꢀ
L
L
INPUT
OUTPUT
1
–1
–2
–3
OUTPUT
0
1V/DIV
5ns/DIV
1V/DIV
5ns/DIV
–1
Figure 38. Input Overdrive Recovery from Positive Rail
Figure 41. Input Overdrive Recovery from Negative Rail
3
2
3
V
= ±2.5V
V
= ±2.5V
S
S
OUTPUT
INPUT
G = –2
= 1kꢀ
G = –2
= 1kꢀ
R
R
L
L
2
1
1
INPUT
0
0
–1
–2
–3
–1
–2
–3
OUTPUT
1V/DIV
1V/DIV
5ns/DIV
5ns/DIV
Figure 39. Output Overdrive Recovery from Positive Rail
Figure 42. Output Overdrive Recovery from Negative Rail
Rev. B | Page 12 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
–10
–20
–30
–40
0
V
= 5V
V
= 5V
S
S
–10
–20
–30
–40
–50
–60
–70
G = +2
= 150ꢀ
R
L
TSSOP
–50
–60
SOIC
–70
–80
–80
–90
–100
–90
0.01
0.1
1
10
FREQUENCY (MHz)
100
1k
0.1
1
10
100
FREQUENCY (MHz)
Figure 46. Forward Isolation vs. Frequency (ADA4891-3 Only)
Figure 43. CMRR vs. Frequency
1.0
–10
–20
–30
–40
–50
–60
–70
–80
Vs = 5V
G = +1
V = 5V
S
G = –2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
R
= 604ꢀ
F
V
, +125°C
OH
V
V
, +25°C
, –40°C
OH
OH
V
V
V
, +125°C
OL
OL
OL
, +25°C
, –40°C
+PSRR
–PSRR
0
10
20
30
40
50
60
70
80
90
100
0.01
0.1
1
10
100
I
(mA)
FREQUENCY (MHz)
LOAD
Figure 44. PSRR vs. Frequency
Figure 47. Output Saturation Voltage vs. Load Current and Temperature
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
6.0
Vs = 5V
G = +2
V
= 5V
S
R
= 1 kꢀ
L
OUT
5.5
5.0
4.5
4.0
3.5
3.0
V
= 2V p-p
0.1
1
10
100
1k
–40
–20
0
20
40
60
80
100
120
FREQUENCY (MHz)
TEMPERATURE (ºC)
Figure 45. All-Hostile Crosstalk (Output-to-Output) vs. Frequency
Figure 48. Supply Current per Amplifier vs. Temperature
Rev. B | Page 13 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
SUPPLY VOLTAGE (V)
Figure 49. Supply Current per Amplifier vs. Supply Voltage
Rev. B | Page 14 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
APPLICATIONS INFORMATION
USING THE ADA4891
WIDEBAND, INVERTING GAIN OPERATION
+V
S
Understanding the subtleties of the ADA4891 family of amplifiers
provides insight into how to extract the peak performance from
the device. The following sections describe the effect of gain,
component values, and parasitics on the performance of the
ADA4891. The wideband, noninverting gain configuration of
the ADA4891 is shown in Figure 50; the wideband, inverting
gain configuration of the ADA4891 is shown in Figure 51.
0.1µF
10µF
V
O
ADA4891
R
L
50ꢀ
SOURCE
R
T
R
F
G
V
I
WIDEBAND, NONINVERTING GAIN OPERATION
R
+V
S
0.1µF
10µF
0.1µF
10µF
50ꢀ
SOURCE
–V
S
Figure 51. Inverting Gain Configuration
V
I
V
O
R
ADA4891
T
Figure 51 shows the inverting gain configuration. For the
inverting gain configuration, set the parallel combination of
RT and RG to match the input source impedance.
R
L
R
F
R
G
Note that a bias current cancellation resistor is not required in
the noninverting input of the amplifier because the input bias
current of the ADA4891 is very low (less than 2 pA). Therefore,
the dc errors caused by the bias current are negligible.
0.1µF
10µF
–V
S
Figure 50. Noninverting Gain Configuration
For both noninverting and inverting gain configurations, it is
often useful to increase the RF value to decrease the load on the
output. Increasing the RF value improves harmonic distortion at
the expense of reducing the 0.1 dB bandwidth of the amplifier.
This effect is discussed further in the Effect of RF on 0.1 dB Gain
Flatness section.
In Figure 50, RF and RG denote the feedback and gain resistors,
respectively. Together, RF and RG determine the noise gain of the
amplifier. The value of RF defines the 0.1 dB bandwidth (for
more information, see the Effect of RF on 0.1 dB Gain Flatness
section). Typical RF values range from 549 ꢀ to 698 ꢀ for the
ADA4891-1/ADA4891-2. Typical RF values range from 301 ꢀ
to 453 ꢀ for the ADA4891-3/ADA4891-4.
RECOMMENDED VALUES
Table 5 and Table 6 provide a quick reference for various configu-
rations and show the effect of gain on the −3 dB small-signal
bandwidth, slew rate, and peaking of the ADA4891-1/ADA4891-2/
ADA4891-3/ADA4891-4. Note that as the gain increases, the
small-signal bandwidth decreases, as is expected from the gain
bandwidth product relationship. In addition, the phase margin
improves with higher gains, and the amplifier becomes more
stable. As a result, the peaking in the frequency response is
reduced (see Figure 7 and Figure 10).
In a controlled impedance signal path, RT is used as the input
termination resistor designed to match the input source imped-
ance. Note that RT is not required for normal operation. RT is
generally set to match the input source impedance.
Table 5. Recommended Component Values and Effect of Gain on ADA4891-1/ADA4891-2 Performance (RL = 1 kΩ)
Feedback Network Values
−3 dB Small-Signal Bandwidth (MHz)
Slew Rate (V/μs)
Gain
−1
+1
+2
+5
RF (Ω)
RG (Ω)
604
Open
604
151
67.1
VOUT = 200 mV p-p
tR
tF
Peaking (dB)
604
0
604
604
604
118
240
120
32.5
12.7
188
154
170
149
71
192
263
210
154
72
1.3
2.6
1.4
0
+10
0
Rev. B | Page 15 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
Table 6. Recommended Component Values and Effect of Gain on ADA4891-3/ADA4891-4 Performance (RL = 1 kΩ)
Feedback Network Values
−3 dB Small-Signal Bandwidth (MHz)
Slew Rate (V/μs)
Gain
−1
+1
+2
+5
RF (Ω)
RG (Ω)
453
Open
453
90.6
45.3
VOUT = 200 mV p-p
tR
tF
Peaking (dB)
453
0
453
453
453
97
220
97
31
13
186
151
181
112
68
194
262
223
120
67
0.9
4.1
0.9
0
+10
0
0.3
EFFECT OF RF ON 0.1 dB GAIN FLATNESS
R
= R = 453ꢀ
F
G
0.2
0.1
R = R = 402ꢀ
G F
Gain flatness is an important specification in video applications.
It represents the maximum allowable deviation in the signal
amplitude within the pass band. Tests have revealed that the
human eye is unable to distinguish brightness variations of
less than 1%, which translates into a 0.1 dB signal drop within
the pass band or, put simply, 0.1 dB gain flatness.
R
= R = 357ꢀ
F
G
0
R
= R = 301ꢀ
–0.1
G
F
–0.2
The PCB layout configuration and bond pads of the chip often
contribute to stray capacitance. The stray capacitance at the
inverting input forms a pole with the feedback and gain resistors.
This additional pole adds phase shift and reduces phase margin
in the closed-loop phase response, causing instability in the
amplifier and peaking in the frequency response.
–0.3
–0.4
V
= 5V
S
G = +2
V
R
= 2V p-p
OUT
= 150ꢀ
L
–0.5
0.1
1
10
100
FREQUENCY (MHz)
Figure 53. 0.1 dB Gain Flatness, Noninverting Gain Configuration,
ADA4891-3/ADA4891-4
Figure 52 and Figure 53 show the effect of using various values
for Feedback Resistor RF on the 0.1 dB gain flatness of the parts.
Figure 52 shows the effect for the ADA4891-1/ADA4891-2.
Figure 53 show the effect for the ADA4891-3/ADA4891-4.
Note that a larger RF value causes more peaking because the
additional pole formed by RF and the input stray capacitance
shifts down in frequency and interacts significantly with the
internal poles of the amplifier.
To obtain the desired 0.1 dB bandwidth, adjust the feedback
resistor, RF, as shown in Figure 52 and Figure 53. If RF cannot
be adjusted, a small capacitor can be placed in parallel with RF
to reduce peaking.
The feedback capacitor, CF, forms a zero with the feedback
resistor, which cancels out the pole formed by the input stray
capacitance and the gain and feedback resistors. For a first pass
in determining the CF value, use the following equation:
0.2
R
R
= R = 698ꢀ
F
G
R
= R = 649ꢀ
F
G
= R = 604ꢀ
G
F
0.1
0
RG × CS = RF × CF
where:
R
= R = 549ꢀ
G
F
RG is the gain resistor.
CS is the input stray capacitance.
RF is the feedback resistor.
CF is the feedback capacitor.
–0.1
–0.2
–0.3
–0.4
Using this equation, the original closed-loop frequency response of
the amplifier is restored, as if there is no stray input capacitance.
Most often, however, the value of CF is determined empirically.
V
= 5V
S
G = +2
V
R
= 2V p-p
OUT
= 150ꢀ
L
0.1
1
10
100
Figure 54 shows the effect of using various values for the feedback
capacitor to reduce peaking. In this case, the ADA4891-1/
ADA4891-2 are used for demonstration purposes and RF = RG =
604 ꢀ. The input stray capacitance, together with the board
parasitics, is approximately 2 pF.
FREQUENCY (MHz)
Figure 52. 0.1 dB Gain Flatness, Noninverting Gain Configuration,
ADA4891-1/ADA4891-2
Rev. B | Page 16 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
0.2
0.1
These four methods minimize the output capacitive loading effect.
C
= 0pF
•
Reducing the output resistive load. This pushes the pole
further away and, therefore, improves the phase margin.
Increasing the phase margin with higher noise gains. As
the closed-loop gain is increased, the larger phase margin
allows for large capacitive loads with less peaking.
Adding a parallel capacitor (CF) with RF, from −IN to the
output. This adds a zero in the closed-loop frequency
response, which tends to cancel out the pole formed by the
capacitive load and the output impedance of the amplifier.
See the Effect of RF on 0.1 dB Gain Flatness section for
more information.
F
C
= 1pF
•
F
0
C
= 3.3pF
F
•
•
–0.1
–0.2
–0.3
V
= 5V
S
G = +2
R
R
= 604ꢀ
= 150ꢀ
= 2V p-p
F
L
V
OUT
0.1
1
10
FREQUENCY (MHz)
100
Placing a small value resistor (RS) in series with the output
to isolate the load capacitor from the output stage of the
amplifier.
Figure 54. 0.1 dB Gain Flatness vs. CF, VS = 5 V,
ADA4891-1/ADA4891-2
Figure 57 shows the effect of using a snub resistor (RS) on reducing
the peaking in the worst-case frequency response (gain of +1).
Using RS = 100 Ω reduces the peaking by 3 dB, with the trade-off
that the closed-loop gain is reduced by 0.9 dB due to attenuation
at the output. RS can be adjusted from 0 Ω to 100 Ω to maintain
an acceptable level of peaking and closed-loop gain, as shown in
Figure 57.
DRIVING CAPACITIVE LOADS
A highly capacitive load reacts with the output impedance of
the amplifiers, causing a loss of phase margin and subsequent
peaking or even oscillation. The ADA4891-1/ADA4891-2 are
used to demonstrate this effect (see Figure 55 and Figure 56).
8
6
4
8
V
V
= 5V
OUT
G = +1
S
= 200mV p-p
6
4
R
C
= 1kꢀ
= 6.8pF
L
L
2
0
2
R
= 0ꢀ
S
–2
–4
0
R
= 100ꢀ
S
–2
–4
–6
–8
–10
–6
–8
V
V
= 5V
S
= 200mV p-p
OUT
R
S
G = +1
V
OUT
IN
R
C
= 1kꢀ
L
L
200mV
STEP
= 6.8pF
R
C
L
L
–10
0.1
50ꢀ
1
10
100
FREQUENCY (MHz)
0.1
1
10
FREQUENCY (MHz)
100
Figure 55. Closed-Loop Frequency Response, CL = 6.8 pF,
ADA4891-1/ADA4891-2
Figure 57. Closed-Loop Frequency Response with Snub Resistor, CL = 6.8 pF
Figure 58 shows that the transient response is also much improved
by the snub resistor (RS = 100 Ω) compared to that of Figure 56.
V
= 5V
S
G = +1
R
C
= 1kꢀ
= 6.8pF
L
L
V
= 5V
S
G = +1
100
R
C
R
= 1kꢀ
= 6.8pF
= 100ꢀ
L
L
S
100
0
0
–100
–100
50mV/DIV
50ns/DIV
Figure 56. 200 mV Step Response, CL = 6.8 pF,
ADA4891-1/ADA4891-2
50mV/DIV
50ns/DIV
Figure 58. 200 mV Step Response, CL = 6.8 pF, RS = 100 Ω
Rev. B | Page 17 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
TERMINATING UNUSED AMPLIFIERS
SINGLE-SUPPLY OPERATION
Terminating unused amplifiers in a multiamplifier package is
an important step in ensuring proper operation of the functional
amplifier. Unterminated amplifiers can oscillate and draw
excessive power. The recommended procedure for terminating
unused amplifiers is to connect any unused amplifiers in a
unity-gain configuration and to connect the noninverting input
to midsupply voltage. With symmetrical bipolar power supplies,
this means connecting the noninverting input to ground, as
shown in Figure 59.
The ADA4891 can also be operated from a single power supply.
Figure 61 shows the ADA4891-3 configured as a single 5 V
supply video driver.
•
The input signal is ac-coupled into the amplifier via
Capacitor C1.
•
•
Resistor R2 and Resistor R4 establish the input midsupply
reference for the amplifier.
Capacitor C5 prevents constant current from being drawn
through the gain set resistor (RG) and enables the ADA4891-3
at dc to provide unity gain to the input midsupply voltage,
thereby establishing the output voltage at midsupply.
Capacitor C6 is the output coupling capacitor.
+V
S
•
ADA4891
The large-signal frequency response obtained with single-
supply operation is identical to the bipolar supply operation
(Figure 18 shows the large-signal frequency response).
–V
S
Figure 59. Terminating Unused Amplifier with
Symmetrical Bipolar Power Supplies
Four pairs of low frequency poles are formed by R2/2 and C2,
R3 and C1, RG and C5, and RL and C6. With this configuration,
the −3 dB cutoff frequency at low frequency is 12 Hz. The
values of C1, C2, C5, and C6 can be adjusted to change the low
frequency −3 dB cutoff point to suit individual design needs.
In single power supply applications, a synthetic midsupply
source must be created. This can be accomplished with a simple
resistive voltage divider. Figure 60 shows the proper connection
for terminating an unused amplifier in a single-supply
configuration.
For more information about single-supply operation of op amps,
see the Analog Dialogue article “Avoiding Op Amp Instability
Problems in Single-Supply Applications” (Volume 35, Number 2)
at www.analog.com.
+V
S
2.5kꢀ
2.5kꢀ
+5V
C2
1µF
C3
10µF
ADA4891
R4
50kꢀ
R2
50kꢀ
C4
0.01µF
+5V
R1
Figure 60. Terminating Unused Amplifier with Single Power Supply
R3
100kꢀ
DISABLE FEATURE (ADA4891-3 ONLY)
C6
V
22µF
IN
The ADA4891-3 includes a power-down feature that can be
used to save power when an amplifier is not in use. When an
amplifier is powered down, its output goes to a high impedance
state. The output impedance decreases as frequency increases;
this effect can be observed in Figure 34. With the power-down
function, a forward isolation of −40 dB can be achieved at
50 MHz. Figure 46 shows the forward isolation vs. frequency
C1
22µF
V
OUT
50ꢀ
R
150ꢀ
L
R
453ꢀ
F
R
453ꢀ
G
ADA4891-3
C5
22µF
–V
S
Figure 61. Single-Supply Video Driver Schematic
PD1
data. The power-down feature is asserted by pulling the
PD2 PD3
,
, or
pin low.
Table 7 summarizes the operation of the power-down feature.
Table 7. Disable Function
Power-Down Pin Connection (PDx)
Amplifier Status
Enabled
Disabled
>VTH or floating
<VTH
Rev. B | Page 18 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
VIDEO RECONSTRUCTION FILTER
MULTIPLEXER
A common application for active filters is at the output of video
digital-to-analog converters (DACs)/encoders. The filter, or more
appropriately, the video reconstruction filter, is used at the output
of a video DAC/encoder to eliminate the multiple images that
are created during the sampling process within the DAC. For
portable video applications, the ADA4891 is an ideal choice due
to its lower power requirements and high performance.
The ADA4891-3 has a disable pin used to power down the
amplifier to save power or to create a mux circuit. If two or
more ADA4891-3 outputs are connected together and only one
output is enabled, then only the signal of the enabled amplifier
appears at the output. This configuration is used to select from
various input signal sources. Additionally, the same input signal
is applied to different gain stages, or differently tuned filters, to
make a gain-step amplifier or a selectable frequency amplifier.
For active filters, a good rule of thumb is that the −3 dB band-
width of the amplifiers be at least 10 times higher than the corner
frequency of the filter. This ensures that no initial roll-off is
introduced by the amplifier and that the pass band is flat until
the cutoff frequency.
Figure 64 shows a schematic of two ADA4891-3 devices used
to create a mux that selects between two inputs. One input is a
1 V p-p, 3 MHz sine wave; the other input is a 2 V p-p, 1 MHz
sine wave.
+2.5V
An example of a 15 MHz, 3-pole, Sallen-Key, low-pass video
reconstruction filter is shown in Figure 62. This circuit features
a gain of +2, a 0.1 dB bandwidth of 7.3 MHz, and over 17 dB
attenuation at 29.7 MHz (see Figure 63). The filter has three
poles: two poles are active, with a third passive pole (R6 and C4)
placed at the output. C3 improves the filter roll-off. R6, R7, and
R8 make up the video load of 150 Ω. Components R6, C4, R7,
R8, and the input termination of the network analyzer form a
6 dB attenuator; therefore, the reference level is roughly 0 dB,
as shown in Figure 63.
0.1µF
10µF
10µF
49.9ꢀ
ADA4891-3
1V p-p
3MHz
0.1µF
49.9ꢀ
49.9ꢀ
–2.5V
+2.5V
453ꢀ
V
OUT
453ꢀ
49.9ꢀ
C2
51pF
0.1µF
10µF
10µF
R2
R3
+5V
47ꢀ 125ꢀ
49.9ꢀ
R6
6.8ꢀ
R7
2V p-p
1MHz
ADA4891-3
–2.5V
68.1ꢀ
V
OUT
V
C1
51pF
IN
R8
75ꢀ
R1
C4
1nF
0.1µF
R4
1kꢀ
453ꢀ
453ꢀ
C3
15pF
R5
1kꢀ
HCO4
SELECT
Figure 62. 15 MHz Video Reconstruction Filter Schematic
Figure 64. Two-to-One Multiplexer Using Two ADA4861-3 Devices
The select signal and the output waveforms for this circuit are
shown in Figure 65.
0
–3
–6
1V/DIV
1µs/DIV
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
OUTPUT
SELECT
5V/DIV
1µs/DIV
0.03
0.1
1
10
100
FREQUENCY (MHz)
Figure 65. ADA4861-3 Mux Output
Figure 63. Video Reconstruction Filter Frequency Performance
Rev. B | Page 19 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
LAYOUT, GROUNDING, AND BYPASSING
POWER SUPPLY BYPASSING
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling between the inputs and outputs
and to avoid any positive feedback, the input and output signal
traces should not be parallel. In addition, the input traces should
not be close to each other. A minimum of 7 mils between the
two inputs is recommended.
Power supply pins are additional op amp inputs, and care must
be taken so that a noise-free, stable dc voltage is applied. The
purpose of bypass capacitors is to create a low impedance path
from the supply to ground over a range of frequencies, thereby
shunting or filtering the majority of the noise to ground. Bypassing
is also critical for stability, frequency response, distortion, and
PSRR performance.
LEAKAGE CURRENTS
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces sets
up a leakage path through the PCB. Consider a 1 V signal and
100 GΩ to ground present at the input of the amplifier. The
resultant leakage current is 10 pA; this is 5× the typical input
bias current of the amplifier. Poor PCB layout, contamination,
and the board material can create large leakage currents. Common
contaminants on boards are skin oils, moisture, solder flux, and
cleaning agents. Therefore, it is imperative that the board be
thoroughly cleaned and that the board surface be free of
contaminants to take full advantage of the low input bias
currents of the ADA4891.
If traces are used between components and the package, chip
capacitors of 0.1 μF (X7R or NPO) are critical and should be
placed as close as possible to the amplifier package. The 0508
case size for such a capacitor is recommended because it offers
low series inductance and excellent high frequency performance.
Larger chip capacitors, such as 0.1 μF capacitors, can be shared
among a few closely spaced active components in the same
signal path. A 10 μF tantalum capacitor is less critical for high
frequency bypassing, but it provides additional bypassing for
lower frequencies.
GROUNDING
When possible, ground and power planes should be used. Ground
and power planes reduce the resistance and inductance of the
power supply feeds and ground returns. If multiple planes are
used, they should be stitched together with multiple vias. The
returns for the input, output terminations, bypass capacitors,
and RG should all be kept as close to the ADA4891 as possible.
Ground vias should be placed at the side or at the very end of
the component mounting pads to provide a solid ground return.
The output load ground and the bypass capacitor grounds should
be returned to a common point on the ground plane to minimize
parasitic inductance and to help improve distortion performance.
To significantly reduce leakage paths, a guard ring/shield should
be used around the inputs. The guard ring circles the input pins
and is driven to the same potential as the input signal, thereby
reducing the potential difference between pins. For the guard ring
to be completely effective, it must be driven by a relatively low
impedance source and should completely surround the input
leads on all sides, above and below, using a multilayer board
(see Figure 66).
GUARD RING
INPUT AND OUTPUT CAPACITANCE
GUARD RING
NONINVERTING
Parasitic capacitance can cause peaking and instability and,
therefore, should be minimized to ensure stable operation.
INVERTING
Figure 66. Guard Ring Configurations
High speed amplifiers are sensitive to parasitic capacitance between
the inputs and ground. A few picofarads of capacitance reduce
the input impedance at high frequencies, in turn increasing the
gain of the amplifier and causing peaking of the frequency
response or even oscillations, if severe enough. It is recommended
that the external passive components that are connected to the
input pins be placed as close as possible to the inputs to avoid
parasitic capacitance.
The 5-lead SOT-23 package for the ADA4891-1 presents a
challenge in keeping the leakage paths to a minimum. The
pin spacing is very tight, so extra care must be used when
constructing the guard ring (see Figure 67 for the recom-
mended guard ring construction).
+V
+V
OUT
S
OUT
S
ADA4891-1
ADA4891-1
–V
S
–V
S
In addition, the ground and power planes under the pins of
the ADA4891 should be cleared of copper to prevent parasitic
capacitance between the input and output pins to ground. This
is because a single mounting pad on a SOIC footprint can add
as much as 0.2 pF of capacitance to ground if the ground or
power plane is not cleared under the ADA4891 pins. In fact, the
ground and power planes should be kept at a distance of at least
0.05 mm from the input pins on all layers of the board.
+IN
–IN
+IN
–IN
NONINVERTING
INVERTING
Figure 67. Guard Ring Layout, 5-Lead SOT-23
Rev. B | Page 20 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
45°
1.27 (0.0500)
BSC
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0099)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
5
1
4
3
3.00
2.80
2.60
1.70
1.60
1.50
2
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
5°
0°
SEATING
PLANE
0.20
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 69. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Rev. B | Page 21 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 70. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 71. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
8°
0°
0.15
0.05
COPLANARITY
0.10
0.60
0.45
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. B | Page 22 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
ORDERING GUIDE
Model1
ADA4891-1ARZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
R-8
R-8
R-8
RJ-5
Branding
8-Lead SOIC_N
ADA4891-1ARZ-RL
ADA4891-1ARZ-R7
ADA4891-1ARJZ-R7
ADA4891-1ARJZ-RL
ADA4891-2ARZ
ADA4891-2ARZ-RL
ADA4891-2ARZ-R7
ADA4891-2ARMZ
ADA4891-2ARMZ-RL
ADA4891-2ARMZ-R7
ADA4891-3ARUZ
ADA4891-3ARUZ-R7
ADA4891-3ARUZ-RL
ADA4891-3ARZ
ADA4891-3ARZ-R7
ADA4891-3ARZ-RL
ADA4891-4ARUZ
ADA4891-4ARUZ-R7
ADA4891-4ARUZ-RL
ADA4891-4ARZ
ADA4891-4ARZ-R7
ADA4891-4ARZ-RL
ADA4891-1AR-EBZ
ADA4891-1ARJ-EBZ
ADA4891-2AR-EBZ
ADA4891-2ARM-EBZ
ADA4891-3AR-EBZ
ADA4891-3ARU-EBZ
ADA4891-4AR-EBZ
ADA4891-4ARU-EBZ
8-Lead SOIC_N, 13”Tape and Reel
8-Lead SOIC_N, 7”Tape and Reel
5-Lead SOT-23, 7”Tape and Reel
5-Lead SOT-23, 13”Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13”Tape and Reel
8-Lead SOIC_N, 7”Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
14-Lead TSSOP
14-Lead TSSOP, 7”Tape and Reel
14-Lead TSSOP, 13”Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 7”Tape and Reel
14-Lead SOIC_N, 13”Tape and Reel
14-Lead TSSOP
14-Lead TSSOP, 7”Tape and Reel
14-Lead TSSOP, 13”Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 7”Tape and Reel
14-Lead SOIC_N, 13”Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 5-Lead SOT-23
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 8-Lead MSOP
Evaluation Board for 14-Lead SOIC_N
Evaluation Board for 14-Lead TSSOP
Evaluation Board for 14-Lead SOIC_N
Evaluation Board for 14-Lead TSSOP
H1W
H1W
RJ-5
R-8
R-8
R-8
RM-8
RM-8
RM-8
RU-14
RU-14
RU-14
R-14
H1U
H1U
H1U
R-14
R-14
RU-14
RU-14
RU-14
R-14
R-14
R-14
1 Z = RoHS Compliant Part.
Rev. B | Page 23 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08054-0-7/10(B)
Rev. B | Page 24 of 24
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