ADA4940-1ACP-EBZ [ADI]
Ultralow Power, Low Distortion; 超低功耗，低失真
| 型号： | ADA4940-1ACP-EBZ |
| 厂家： | 
ADI |
| 描述： | Ultralow Power, Low Distortion |
| 文件： | 总32页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Power, Low Distortion
Fully Differential ADC Driver
Data Sheet
ADA4940-1/ADA4940-2
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Small signal bandwidth: 260 MHz
Ultralow power 1.25mA
Extremely low harmonic distortion
−122 dB THD at 50 kHz
−96 dB THD at 1 MHz
Low input voltage noise: 3.9 nV/√Hz
0.35 mV maximum offset voltage
Balanced outputs
ADA4940-1
–IN1 1
+FB1 2
18 +OUT1
17 V
12 DISABLE
11 –OUT
–FB
1
OCM1
16 –V
+IN 2
–IN 3
+V
+V
3
4
S2
S2
S1
ADA4940-2
–V
15
14
S1
10 +OUT
–FB2 5
+IN2 6
DISABLE2
+FB
4
9 V
OCM
13 –OUT2
Settling time to 0.1%: 34 ns
Rail-to-rail output: −VS + 0.1 V to +VS − 0.1 V
Adjustable output common-mode voltage
Flexible power supplies: 3 V to 7 V (LFCSP)
Disable pin to reduce power consumption
ADA4940-1 is available in LFCSP and SOIC packages
Figure 1.
0
C
F
+D
IN
2.5V
IN+ REF VDD
–20
–40
–60
–80
R3
R4
+
33Ω
+IN
–OUT
2.7nF
2.7nF
V
AD7982
APPLICATIONS
OCM
ADA4940-1
+OUT
33Ω
IN–
GND
–IN
Low power PulSAR®/SAR ADC drivers
Single-ended-to-differential conversion
Differential buffers
–
R1
R2
–D
IN
C
F
–100
–120
–140
–160
Line drivers
Medical imaging
Industrial process controls
Portable electronics
GENERAL DESCRIPTION
0
20k
40k
60k
80k
100k
FREQUENCY (Hz)
The ADA4940-1/ADA4940-2 are low noise, low distortion fully
differential amplifiers with very low power consumption. They
are an ideal choice for driving low power, high resolution, high
performance SAR and sigma-delta (Σ-Δ) analog-to-digital
converters (ADCs) with resolutions up to 16 bits from dc to
1 MHz on only 1.25 mA of quiescent current. The adjustable
level of the output common-mode voltage allows the ADA4940-1/
ADA4940-2 to match the input common-mode voltage of
multiple ADCs. The internal common-mode feedback loop
provides exceptional output balance, as well as suppression of
even-order harmonic distortion products.
Figure 2. ADA4940-1 Driving the AD7982 ADC
The ADA4940-1 is available in a Pb-free, 3 mm × 3 mm, 16-lead
LFCSP, and an 8-lead SOIC. The ADA4940-2 is available in a Pb-
free, 4 mm × 4 mm, 24-lead LFCSP. The pinout is optimized to
facilitate printed circuit board (PCB) layout and minimize
distortion. The ADA4940-1/ADA4940-2 are specified to
operate over the −40°C to +125°C temperature range.
Table 1. Similar Products to the ADA4940-1/ADA4940-2
Isupply
(mA)
Bandwidth
(MHz)
Slew Rate
(V/µs)
Noise
(nV/√Hz)
Product
AD8137
ADA4932-x
ADA4941-1
3
9
2.2
110
560
31
450
2800
22
8.25
3.6
5.1
With the ADA4940-1/ADA4940-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors determining the closed-loop gain of the amplifier.
The ADA4940-1/ADA4940-2 are fabricated using Analog Devices,
Inc., SiGe complementary bipolar process, enabling them to
achieve very low levels of distortion with an input voltage noise
of only 3.9 nV/√Hz. The low dc offset and excellent dynamic
performance of the ADA4940-1/ADA4940-2 make them well
suited for a variety of data acquisition and signal processing
applications.
Table 2. Complementary Products to the ADA4940-1/ADA4940-2
Power
(mW)
Throughput
(MSPS)
Resolution
(Bits)
SNR
(dB)
Product
AD7982
AD7984
AD7621
AD7623
7.0
10.5
65
1
18
18
16
16
98
96.5
88
1.333
3
1.333
45
88
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADA4940-1/ADA4940-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.............................................................. 22
Analyzing an Application Circuit ............................................ 22
Setting the Closed-Loop Gain .................................................. 22
Estimating the Output Noise Voltage...................................... 22
Impact of Mismatches in the Feedback Networks................. 23
Calculating the Input Impedance of an Application Circuit 23
Input Common-Mode Voltage Range..................................... 24
Input and Output Capacitive AC Coupling............................ 25
Setting the Output Common-Mode Voltage.......................... 25
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
VS = 5 V.......................................................................................... 3
VS = 3 V.......................................................................................... 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 19
Terminology .................................................................................... 20
Definition of Terms.................................................................... 20
Theory of Operation ...................................................................... 21
DISABLE
Pin .............................................................................. 25
Driving a Capacitive Load......................................................... 25
Driving a High Precision ADC ................................................ 26
Layout, Grounding, and Bypassing.............................................. 27
ADA4940-1 LFCSP Example.................................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 29
REVISION HISTORY
3/12—Rev. A to Rev. B
Circuit Section ................................................................................ 23
Changes to Figure 71...................................................................... 25
Changes to Driving a High Precision ADC Section
and Figure 73................................................................................... 26
Changed ADA4940-1 Example Section to ADA4940-1 LFCSP
Example Section ............................................................................. 27
Changes to Ordering Guide.......................................................... 29
Reorganized Layout............................................................Universal
Added ADA4940-1 8-Lead SOIC Package......................Universal
Changes to Features Section, Table 1, and Figure 1; Replaced
Figure 2 .............................................................................................. 1
Changed VS = 2 Vꢀor +5 V) Section to VS = +5 V
Section................................................................................................ 3
Changes to VS = +5 V Section and Table 3.................................... 3
Changes to Table 4 and Table 5....................................................... 4
Changes to VS = 3 V Section and Table 6...................................... 5
Changes to Table 7 and Table 8....................................................... 6
Added Figure 5 and Table 12, Renumbered Sequentially ........... 9
Changes to Figure 7, Figure 8, and Figure 9................................ 10
Added Figure 15 and Figure 18; Changes to Figure 13,
12/11—Rev. 0 to Rev. A
Changes to Features Section, General Description
Section, Table 1 ..................................................................................1
Replaced Figure 1 and Figure 2 .......................................................1
Changes to VS = 2.5 V ꢀor +5 V) Section and Table 3................3
Changes to Table 6.............................................................................5
Replaced Figure 7, Figure 8, Figure 9, and Figure 10 ...................9
Replaced Figure 14, Figure 15, and Figure 17............................. 10
Replaced Figure 24 and Figure 27................................................ 12
Changes to Figure 37...................................................................... 14
Replaced Figure 43 and Figure 46................................................ 15
Replaced Figure 53 ......................................................................... 18
Changes to Estimating the Output Noise Voltage Section, Table
14, Table 15, and Calculating the Input Impedance of an
Application Circuit Section........................................................... 21
Changes to Input Common-Mode Voltage Range Section....... 22
Changes to Driving a High Precision ADC Section and
Figure 65 .......................................................................................... 24
Figure 14, and Figure 16 ................................................................ 11
Changes to Figure 19 and Figure 20............................................. 12
Changes to Figure 25, Figure 26, and Figure 27; Added
Figure 28, Figure 29, and Figure 30.............................................. 13
Changes to Figure 31, Figure 32, Figure 33, Figure 34, Figure 35,
and Figure 36................................................................................... 14
Changes to Figure 37, Figure38, Figure 39, and Figure 41........ 15
Changes to Figure 49, Figure 50, and Figure 51 ......................... 17
Added Figure 55 and Figure 57..................................................... 18
Changes to Differential VOS, Differential CMRR, and VOCM
CMRR Section ................................................................................ 20
Changes to Calculating the Input Impedance of an Application
10/11—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADA4940-1/ADA4940-2
SPECIFICATIONS
VS = 5 V
VOCM = Mid Supply, RF = RG = 1 kΩ, RL, dm = 1 kΩ, TA = 25°C, LFCSP package, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
(See Figure 61 for the definition of terms.)
+DIN or –DIN to VOUT, dm Performance
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
VOUT, dm = 0.1 V p-p, G = 1
VOUT, dm = 0.1 V p-p, G = 2
VOUT, dm = 0.1 V p-p, G = 5
VOUT, dm = 2 V p-p, G = 1
VOUT, dm = 2 V p-p, G = 2
VOUT, dm = 2 V p-p, G = 5
VOUT, dm = 2 V p-p, G = 1 and G = 2
VOUT, dm = 2 V step
260
220
75
25
22
19
14.5
95
34
86
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
HD2/HD3
VOUT, dm = 2 V step
G = 2, VIN, dm = 6 V p-p, triangle wave
ns
VOUT, dm = 2 V p-p, fC = 10 kHz
VOUT, dm = 2 V p-p, fC = 50 kHz
VOUT, dm = 2 V p-p, fC = 50 kHz, G = 2
VOUT, dm = 2 V p-p, fC = 1 MHz
VOUT, dm = 2 V p-p, fC = 1 MHz, G = 2
VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz
f = 100 kHz
−125/−118
−123/−126
−124/−117
−102/−96
−100/–92
−99
3.9
0.81
−110
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
IMD3
Input Voltage Noise
Input Current Noise
Crosstalk
f = 100 kHz
VOUT, dm = 2 V p-p, fC = 1 MHz
INPUT CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Common-Mode Voltage Range
VIP = VIN = VOCM = 0 V
TMIN to TMAX
−0.35
−1.6
0.06
1.2
−1.1
−4.5
50
+0.35 mV
µV/°C
µA
TMIN to TMAX
nA/°C
nA
−500
+500
−VS − 0.2 to
+VS − 1.2
V
Input Resistance
Differential
Common mode
33
50
1
kΩ
MΩ
pF
Input Capacitance
Common-Mode Rejection Ratio (CMRR) ΔVOS, dm/ΔVIN, cm, ∆VIN, cm = 1 V dc
Open-Loop Gain
86
91
119
99
dB
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Each single-ended output
−VS + 0.1 to
+VS − 0.1
−VS + 0.07 to
+VS − 0.07
V
Linear Output Current
Output Balance Error
f = 1 MHz, RL, dm = 22 Ω, SFDR = −60 dBc
f = 1 MHz, ΔVOUT, cm/ΔVOUT, dm
46
−65
mA peak
dB
−60
Rev. B | Page 3 of 32
ADA4940-1/ADA4940-2
Data Sheet
VOCM to VOUT, cm Performance
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
Input Voltage Noise
Gain
VOUT, cm = 0.1 V p-p
VOUT, cm = 1 V p-p
VOUT, cm = 1 V p-p
f = 100 kHz
ΔVOUT, cm/ΔVOCM, ΔVOCM = 1 V
36
29
52
83
1
MHz
MHz
V/µs
nV/√Hz
V/V
0.99
−6
1.01
VOCM CHARACTERISTICS
Input Common-Mode Voltage Range
−VS + 0.8 to
+VS − 0.7
250
1
20
+4
100
V
Input Resistance
Offset Voltage
Input Offset Voltage Drift
Input Bias Current
CMRR
kΩ
VOS, cm = VOUT, cm − VOCM; VIP = VIN = VOCM = 0 V
TMIN to TMAX
+6
+7
mV
µV/°C
µA
−7
86
ΔVOS, dm/ΔVOCM, ΔVOCM = 1 V
dB
General Performance
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
LFCSP
3
7
V
SOIC
3
6
V
Quiescent Current per Amplifier
Quiescent Current Drift
Enabled
TMIN to TMAX
Disabled
ΔVOS, dm/ΔVS, ΔVS = 1 V p-p
ΔVOS, dm/ΔVS, ΔVS = 1 V p-p
1.05
1.25
4.25
13.5
90
1.38
mA
µA/°C
µA
dB
dB
28.5
+PSRR
−PSRR
80
80
96
DISABLE (DISABLE PIN)
DISABLE Input Voltage
Disabled
Enabled
≤(−VS + 1)
≥(−VS + 1.8)
10
V
V
µs
µs
Turn-Off Time
Turn-On Time
0.6
DISABLE Pin Bias Current per Amplifier
Enabled
Disabled
DISABLE = +2.5 V
DISABLE = −2.5 V
2
5
µA
µA
°C
−10
−40
−5
OPERATING TEMPERATURE RANGE
+125
Rev. B | Page 4 of 32
Data Sheet
ADA4940-1/ADA4940-2
VS = 3 V
VOCM = Mid Supply, RF = RG = 1 kΩ, RL, dm = 1 kΩ, TA = 25°C, LFCSP package, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
(See Figure 61 for the definition of terms.)
+DIN or –DIN to VOUT, dm Performance
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
VOUT, dm = 0.1 V p-p
240
200
70
24
20
17
14
90
37
85
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
VOUT, dm = 0.1 V p-p, G = 2
VOUT, dm = 0.1 V p-p, G = 5
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p, G = 2
VOUT, dm = 2 V p-p, G = 5
VOUT, dm = 0.1 V p-p
VOUT, dm = 2 V step
VOUT, dm = 2 V step
G = 2, VIN, dm = 3.6 V p-p, triangle wave
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
HD2/HD3
ns
VOUT, dm = 2 V p-p, fC = 50 kHz (HD2/HD3)
VOUT, dm = 2 V p-p, fC = 1 MHz (HD2/HD3)
VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz
f = 100 kHz
f = 100 kHz
VOUT, dm = 2 V p-p, fC = 1 MHz
−115/−121
−104/−96
−98
3.9
0.84
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
IMD3
Input Voltage Noise
Input Current Noise
Crosstalk
−110
INPUT CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Common-Mode Voltage Range
VIP = VIN = VOCM = 1.5 V
TMIN to TMAX
−0.4
−1.6
−500
0.06
1.2
−1.1
−4.5
50
+0.4
mV
µV/°C
µA
TMIN to TMAX
nA/°C
+500 nA
V
−VS − 0.2 to
+VS − 1.2
Input Resistance
Differential
Common mode
33
50
1
kΩ
MΩ
pF
Input Capacitance
Common-Mode Rejection Ratio (CMRR) ΔVOS, dm/ΔVIN, cm, ∆VIN, cm = 0.25 V dc
Open-Loop Gain
86
91
114
99
dB
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Each single-ended output
−VS + 0.08 to
+VS − 0.08
−VS + 0.04 to
+VS − 0.04
V
Linear Output Current
Output Balance Error
f = 1 MHz, RL, dm = 26 Ω, SFDR = −60 dBc
f = 1 MHz, ΔVOUT, cm/ΔVOUT, dm
38
−65
mA peak
dB
−60
Rev. B | Page 5 of 32
ADA4940-1/ADA4940-2
Data Sheet
VOCM to VOUT, cm Performance
Table 7.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
Input Voltage Noise
Gain
VOUT, cm = 0.1 V p-p
VOUT, cm = 1 V p-p
VOUT, cm = 1 V p-p
f = 100 kHz
ΔVOUT, cm/ΔVOCM, ΔVOCM = 0.25 V
36
26
48
92
1
MHz
MHz
V/µs
nV/√Hz
V/V
0.99
−7
1.01
VOCM CHARACTERISTICS
Input Common-Mode Voltage Range
−VS + 0.8 to
+VS − 0.7
250
1
20
+1
100
V
Input Resistance
Offset Voltage
Input Offset Voltage Drift
Input Bias Current
CMRR
kΩ
VOS, cm = VOUT, cm − VOCM; VIP = VIN = VOCM = 1.5 V
TMIN to TMAX
+7
+5
mV
µV/°C
µA
−5
80
ΔVOS,dm/ΔVOCM, ΔVOCM = 0.25 V
dB
General Performance
Table 8.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
LFCSP
SOIC
Enabled
TMIN to TMAX
Disabled
ΔVOS, dm/ΔVS, ΔVS = 0.25 V p-p
ΔVOS, dm/ΔVS, ΔVS = 0.25 V p-p
3
3
1
7
6
1.33
V
V
Quiescent Current per Amplifier
1.18
4.25
7
90
96
mA
µA/°C
µA
dB
dB
22
+PSRR
−PSRR
80
80
DISABLE (DISABLE PIN)
DISABLE Input Voltage
Disabled
Enabled
≤(−VS + 1)
≥(−VS + 1.8)
16
V
V
µs
µs
Turn-Off Time
Turn-On Time
0.6
DISABLE Pin Bias Current per Amplifier
Enabled
Disabled
DISABLE = +3 V
DISABLE = 0 V
0.3
−3
1
µA
µA
−6
OPERATING TEMPERATURE RANGE
−40
+125 °C
Rev. B | Page 6 of 32
Data Sheet
ADA4940-1/ADA4940-2
ABSOLUTE MAXIMUM RATINGS
Table 9.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power dissipation is the voltage between the supply pins ( VS)
times the quiescent current (IS). The load current consists of the
differential and common-mode currents flowing to the load, as
well as currents flowing through the external feedback networks
and internal common-mode feedback loop. The internal
resistor tap used in the common-mode feedback loop places a
negligible differential load on the output. RMS voltages and
currents should be considered when dealing with ac signals.
Parameter
Rating
Supply Voltage
VOCM
8 V
VS
1.2 V
−40°C to +125°C
−65°C to +150°C
300°C
Differential Input Voltage
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
ESD
150°C
Field Induced Charged Device Model (FICDM)
Human Body Model (HBM)
1250 V
2000 V
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces the θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC (θJA =
158°C/W, single)the 16-lead LFCSP (θJA = 91.3°C/W, single) and
24-lead LFCSP (θJA = 65.1°C /W, dual) packages on a JEDEC
standard 4-layer board. θJA values are approximations.
3.5
THERMAL RESISTANCE
3.0
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered on a circuit board in still air.
ADA4940-2 (LFCSP)
2.5
Table 10.
Package Type
ADA4940-1 (LFCSP)
2.0
θJA
Unit
°C/W
°C/W
°C/W
8-Lead SOIC (Single)/4-Layer Board
16-Lead LFCSP (Single)/4-Layer Board
24-Lead LFCSP (Dual)/4-Layer Board
158
91.3
65.1
1.5
1.0
ADA4940-1 (SOIC)
0.5
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4940-1/
ADA4940-2 packages is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4940-1/ADA4940-2. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. B | Page 7 of 32
ADA4940-1/ADA4940-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
–IN
1
2
3
4
8
7
6
5
+IN
DISABLE
–V
V
ADA4940-1
OCM
12 DISABLE
11 –OUT
–FB
+IN
–IN
1
2
3
4
+V
S
S
+OUT
–OUT
10 +OUT
ADA4940-1
+FB
9 V
OCM
NOTES
1. CONNECT THE EXPOSED PAD TO
–V OR GROUND.
S
Figure 4. ADA4940-1 Pin Configuration (16-Lead LFCSP)
Figure 5.ADA4940-1 Pin Configuration (SOIC)
Table 11. ADA4940-1 Pin Function Descriptions (16-Lead
LFCSP)
Table 12. ADA4940-1 Pin Function Descriptions (8-Lead
SOIC)
Pin No.
Mnemonic
Description
Pin No.
Mnemonic
Description
1
−FB
Negative Output for Feedback
Component Connection.
Positive Input Summing Node.
Negative Input Summing Node.
Positive Output for Feedback
Component Connection.
Positive Supply Voltage.
Output Common-Mode Voltage.
Positive Output for Load
Connection.
Negative Output for Load
Connection.
1
2
3
4
−IN
VOCM
+VS
+OUT
Negative Input Summing Node.
Output Common-Mode Voltage.
Positive Supply Voltage.
Positive Output for Load
Connection.
Negative Output for Load
Connection.
Negative Supply Voltage.
Disable Pin.
2
3
4
+IN
−IN
+FB
5
−OUT
5 to 8
9
10
+VS
VOCM
+OUT
6
7
8
−VS
DISABLE
+IN
Positive Input Summing Node.
11
−OUT
12
DISABLE
−VS
Exposed
Disable Pin.
13 to 16
Negative Supply Voltage.
Connect the exposed pad to −VS or
paddle (EPAD) ground.
Rev. B | Page 8 of 32
Data Sheet
ADA4940-1/ADA4940-2
–IN1
+FB1
1
2
3
4
5
6
18 +OUT1
17 V
OCM1
16 –V
+V
S2
S2
S1
ADA4940-2
–V
15
14
+V
S1
–FB2
+IN2
DISABLE2
13 –OUT2
NOTES
1. CONNECT THE EXPOSED PAD TO
–V OR GROUND.
S
Figure 6. ADA4940-2 Pin Configuration (24-Lead LFCSP)
Table 13. ADA4940-2 Pin Function Descriptions (24-Lead LFCSP)
Pin No.
1
2
3, 4
5
6
7
8
9, 10
11
12
Mnemonic
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
Description
Negative Input Summing Node 1.
Positive Output Feedback Pin 1.
Positive Supply Voltage 1.
Negative Output Feedback Pin 2.
Positive Input Summing Node 2.
Negative Input Summing Node 2.
Positive Output Feedback Pin 2.
Positive Supply Voltage 2.
Output Common-Mode Voltage 2.
Positive Output 2.
VOCM2
+OUT2
−OUT2
DISABLE2
−VS2
13
14
Negative Output 2.
Disable Pin 2.
15, 16
17
18
19
20
Negative Supply Voltage 2.
Output Common-Mode Voltage 1.
Positive Output 1.
Negative Output 1.
Disable Pin 1.
VOCM1
+OUT1
−OUT1
DISABLE1
−VS1
−FB1
+IN1
21, 22
23
24
Negative Supply Voltage 1.
Negative Output Feedback Pin 1.
Positive Input Summing Node 1.
Connect the exposed pad to −VS or ground.
Exposed paddle (EPAD)
Rev. B | Page 9 of 32
ADA4940-1/ADA4940-2
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 2.5 V, G = 1, RF = RG = 1 kΩ, RT = 52.3 Ω (when used), RL = 1 kΩ, unless otherwise noted. See Figure 59 and Figure 60 for the
test circuits.
3
2
3
2
G = 1, R = 1kΩ
L
1
1
G = 2, R = 1kΩ
L
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–1
–2
–3
–4
–5
–6
–7
–8
G = 1, R = 200Ω
L
G = 2, R = 1kΩ
L
G = 2, R = 200Ω
L
G = 2, R = 200Ω
L
G = 1, R = 200Ω
L
G = 1, R = 1kΩ
L
V
= 0.1V p-p
1
OUT, dm
V
= 2V p-p
OUT
–9
0.1
–9
0.1
1
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Large Signal Frequency Response for Various Gains and Loads
Figure 7. Small Signal Frequency Response for Various Gains and Loads
(LFCSP)
3
2
3
V
= ±3.5V
S
2
1
1
0
V
= ±3.5V
S
0
V
= ±2.5V
S
–1
–2
–3
–4
–5
–6
–7
–8
–9
–1
–2
–3
–4
–5
–6
–7
–8
–9
V
= ±2.5V
S
V
= ±1.5V
S
V
= ±1.5V
S
V
= 0.1V p-p
1
V
= 2V p-p
OUT, dm
OUT
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
10
FREQUENCY (MHz)
100
1000
Figure 11. Large Signal Frequency Response for Various Supplies
Figure 8. Small Signal Frequency Response for Various Supplies (LFCSP)
3
2
1
3
2
–40°C
1
0
0
–40°C
–1
–1
+25°C
+25°C
–2
–2
+125°C
–3
–3
+125°C
–4
–4
–5
–6
–7
–8
–5
–6
–7
–8
V
= 2V p-p
OUT, dm
V
= 0.1V p-p
OUT, dm
–9
–9
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response for Various Temperatures (LFCSP)
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. B | Page 10 of 32
Data Sheet
ADA4940-1/ADA4940-2
4
3
3
2
SOIC-1
LFCSP-1
LFCSP-1
LFCSP-2: CH1
LFCSP-2: CH2
SOIC-1
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–7
–8
LFCSP-2: CH2
–1
–2
–3
–4
–5
–6
–7
LFCSP-2:CH1
–8
V
= 0.1V p-p
1
OUT, dm
V
= 2V p-p
OUT
–9
0.1
–9
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Packages
Figure 16. Large Signal Frequency Response for Various Packages
3
3
V
V
V
= –1V
= 0V
= +1V
OCM
OCM
OCM
2
1
V
= 0V
2
1
OCM
V
0
0
= –1V
OCM
–1
–2
–3
–4
–5
–6
–7
–8
–9
–1
–2
–3
–4
–5
–6
–7
–8
–9
V
= +1V
OCM
V
= 0.1V p-p
1
V
= 2V p-p
1
OUT, dm
OUT, dm
0.1
10
FREQUENCY (MHz)
100
1000
0.1
10
100
1000
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response at Various VOCM Levels (LFCSP)
Figure 17. Large Signal Frequency Response at Various VOCM Levels
4
4
SOIC: R = 1kΩ
V
= 0V
L
OCM
3
2
3
SOIC: R = 200Ω
L
2
1
1
0
0
LFCSP: R = 1kΩ
L
V
= –1V
–1
–2
–3
–4
–5
–6
–7
–8
–9
–1
–2
–3
–4
–5
–6
–7
–8
–9
OCM
V
= +1V
LFCSP: R = 200Ω
OCM
L
V
= 0.1V p-p
1
V
= 0.1V p-p
1
OUT, dm
OUT, dm
0.1
10
FREQUENCY (MHz)
100
1000
0.1
10
100
1000
FREQUENCY (MHz)
Figure 15. Small Signal Frequency Response for Various VOCM (SOIC)
Figure 18. Small Signal Frequency Response for Various Packages and Loads
Rev. B | Page 11 of 32
ADA4940-1/ADA4940-2
Data Sheet
4
4
3
C
= C
= 2pF
COM1
COM2
C
C
C
C
= C
= C
= C
= C
= 0pF
= 0.5pF
= 1pF
= 2pF
COM1
COM1
COM1
COM1
COM2
COM2
COM2
COM2
3
2
2
1
1
0
0
C
= C
COM2
= 1pF
–1
–2
–3
–4
–5
–6
–7
–8
–9
–1
–2
–3
–4
–5
–6
–7
–8
–9
COM1
C
= C
= 0.5pF
= 0pF
COM2
COM1
COM2
C
= C
COM1
C
V
= 0pF
C
V
= 0pF
= 2V p-p
DIFF
DIFF
= 0.1V p-p
OUT
OUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19. Small Signal Frequency Response for Various Capacitive Loads
(LFCSP)
Figure 22. Large Signal Frequency Response for Various Capacitive Loads
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
G = 1, R = 1kΩ
L
–0.05
–0.05
–0.10
–0.15
–0.20
–0.25
G = 2, R = 200Ω
L
G = 2, R = 200Ω
L
–0.10
–0.15
–0.20
–0.25
G = 2, R = 1kΩ
L
G = 2, R = 1kΩ
L
G = 1, R = 200Ω
L
G = 1, R = 200Ω
L
G = 1, R = 1kΩ
V
= 0.1V p-p
1
L
V
= 2V p-p
1
OUT, dm
OUT, dm
0.1
10
100
1000
0.1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 20. 0.1 dB Flatness Small Signal Frequency Response for
Various Gains and Loads (LFCSP)
Figure 23. 0.1 dB Flatness Large Signal Frequency Response for
Various Gains and Loads
3
2
1
0
3
2
1
0
V
= ±2.5V
S
–1
–2
–3
–4
–5
–6
–7
–8
–9
–1
–2
–3
–4
–5
–6
–7
–8
–9
V = ±2.5V
S
V
= ±1.5V
S
V
= ±1.5V
S
V
= 1V p-p
V
= 0.1V p-p
OUT, dm
OUT, dm
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 24. VOCM Large Signal Frequency Response for Various Supplies
Figure 21. VOCM Small Signal Frequency Response for Various Supplies
Rev. B | Page 12 of 32
Data Sheet
ADA4940-1/ADA4940-2
–20
–20
–30
V
= 2V p-p
OUT, dm
V
= 2V p-p
OUT, dm
–30
–40
HD3, G = 2
HD3, G = 1
–40
–50
–50
–60
–60
HD3, G = 2
HD3, G = 1
HD2, G = 2
–70
–70
–80
–80
HD2, G = 2
HD2, G = 1
–90
–90
HD2, G = 1
–100
–110
–120
–130
–100
–110
–120
–130
0.01
0.1
1
10
0.01
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. Harmonic Distortion vs. Frequency for Various Gains (LFCSP)
Figure 28. Harmonic Distortion vs. Frequency vs. Gain (SOIC)
–20
–20
V
= 2V p-p
V
= 2V p-p
OUT, dm
OUT, dm
–30
–40
–30
–40
–50
–50
HD3, R = 200ꢀ
L
–60
–60
HD3, R = 200Ω
L
–70
–70
HD3, R = 1kΩ
L
–80
–80
HD2, R = 200ꢀ
L
–90
–90
HD2, R = 1kꢀ
L
–100
–110
–120
–130
–100
–110
–120
–130
HD2, R = 1kΩ
L
HD2, R = 200Ω
L
HD3, R = 1kꢀ
L
0.01
0.1
1
10
0.01
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. Harmonic Distortion vs. Frequency for Various Loads (SOIC)
Figure 26. Harmonic Distortion vs. Frequency for Various Loads (LFCSP)
–20
–20
V
= 2V p-p
OUT, dm
V
= 2V p-p
OUT, dm
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
HD2, V = ±3.5V
S
–90
–90
HD3, V = ±1.5V
S
–100
–110
–120
–130
–100
–110
–120
–130
HD2, ±2.5V
HD2, V = ±1.5V
S
HD2, ±1.5V
HD3, V = ±3.5V
S
HD2, V = ±2.5V
S
HD3, V = ±2.5V
HD3, ±2.5V
HD3, ±1.5V
0.01
S
0.01
0.1
1
10
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27. Harmonic Distortion vs. Frequency for Various Supplies (LFCSP)
Figure 30. Harmonic Distortion vs. Frequency for Various Supplies (SOIC)
Rev. B | Page 13 of 32
ADA4940-1/ADA4940-2
Data Sheet
–20
–20
–30
f = 1MHz
V
= ±1.5V HD2
S
V
= 2V p-p
OUT, dm
–30
–40
V
= ±1.5V HD3
S
–40
–50
–50
V
= +3V, 0V HD3
= +3V, 0V HD2
–60
S
–60
–70
V
S
–70
–80
V
= ±3.5V HD2
S
V
= ±2.5V HD2
–80
S
–90
SOIC: R = 200Ω
L
–90
–100
–110
–120
–130
–140
SOIC: R = 1kΩ
V
= ±3.5V HD3
= ±2.5V HD3
L
S
–100
–110
–120
–130
V
S
LFCSP: R = 1kΩ
L
LFCSP: R = 200Ω
L
0
1
2
3
4
5
6
7
8
9
10
0.01
0.1
1
10
FREQUENCY (MHz)
V
(V p-p)
OUT, dm
Figure 31. Spurious-Free Dynamic Range vs. Frequency at
RL = 200 Ω and RL = 1kΩ
Figure 34. Harmonic Distortion vs. VOUT, dm for Various Supplies, f = 1 MHz
(LFCSP)
–20
–30
–20
+V = +3V, –V = 0V
V
= 2V p-p
S
S
OUT, dm
–30
–40
V
= 2V p-p
OUT, dm
–40
–50
–50
–60
–60
–70
–70
HD3 AT 1MHz
–80
–80
HD2 AT 1MHz
–90
HD2 AT 1MHz
–90
–100
–110
–120
–130
–140
–150
HD3 AT 1MHz
–100
–110
–120
–130
–140
HD2 AT 100kHz
HD3 AT 100kHz
HD2 AT 100kHz
HD3 AT 100kHz
1.0 1.5 2.0
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
V
(V)
OCM
OCM
Figure 32. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz,
2.5 V Supplies (LFCSP)
Figure 35. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz, 3 V Supply
(LFCSP)
–20
–20
V
= 2V p-p
OUT, dm
–30
–40
–30
–40
HD3 AT V
HD2 AT V
HD3 AT V
= 8V p-p
= 8V p-p
= 4V p-p
OUT, dm
OUT, dm
OUT, dm
–50
–50
–60
–60
HD2 AT V
OUT, dm
= 4V p-p
–70
–70
HD3, R = R = 499Ω
F
G
HD2 AT V
OUT, dm
= 2V p-p
–80
–80
–90
–90
–100
–110
–120
–130
–140
HD2, R = R = 499Ω
F G
HD3 AT V
OUT, dm
= 2V p-p
–100
–110
–120
–130
HD3, R = R = 1kΩ
F
G
HD2, R = R = 1kΩ
F
G
0.01
0.1
1
FREQUENCY (MHz)
10
0.01
0.1
1
10
FREQUENCY (MHz)
Figure 36. Harmonic Distortion vs. Frequency for Various RF and RG (LFCSP)
Figure 33. Harmonic Distortion vs. Frequency for Various VOUT, dm (LFCSP)
Rev. B | Page 14 of 32
Data Sheet
ADA4940-1/ADA4940-2
10
–60
–70
V
= 2V p-p
OUT, dm
(ENVELOPE)
V
= 2V p-p
OUT, dm
0
–10
–20
–80
–30
CHANNEL 1 TO CHANNEL 2
–40
–90
–50
–60
–100
–110
–120
–130
–70
–80
–90
CHANNEL 2 TO CHANNEL 1
–100
–110
–120
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 37. 2 MHz Intermodulation Distortion (LFCSP)
Figure 40. Crosstalk vs. Frequency, ADA4940-2
130
120
110
100
90
120
110
100
90
LFCSP
SOIC
–PSRR
+PSRR
80
70
80
60
70
50
60
40
50
30
40
0.1
20
0.1
1
10
100
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 38. CMRR vs. Frequency
Figure 41. PSRR vs. Frequency
–10
–20
–30
–40
–50
–60
–70
–80
100
0
V
= 2V p-p
OUT, dm
–15
90
80
–30
–45
70
–60
60
50
–75
40
–90
30
–105
–120
–135
–150
–165
–180
–195
–210
20
10
0
–10
–20
–30
–40
0.1
1
10
100
10k
100k
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 39. Output Balance vs. Frequency
Figure 42. Open-Loop Gain and Phase vs. Frequency
Rev. B | Page 15 of 32
ADA4940-1/ADA4940-2
Data Sheet
8
2.0
1.6
0.5
G = +2
0.4
6
V
1.2
0.3
OUT, dm
INPUT
4
2
0.8
0.2
OUTPUT
2 × V
IN
0.4
0.1
%ERROR
0
0
0
–0.4
–0.8
–1.2
–1.6
–0.1
–0.2
–0.3
–0.4
–0.5
–2
–4
–6
V
= 2V p-p
20
OUT, dm
10
–8
–2.0
0
100 200 300 400 500 600 700 800 900 1000
0
30
40
TIME (ns)
50
60
70
80
TIME (ns)
Figure 43. Output Overdrive Recovery, G = 2
Figure 46. 0.1% Settling Time
100
100
10
10
1
0.1
1
10
0.01
100
1k
10k
100k
1M
10M
0.1
1
10
100
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 44. Voltage Noise Spectral Density, Referred to Input
Figure 47. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1
1.50
1.25
1.00
0.75
0.50
0.25
0
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0
0V
+2.5V
R1
R2
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
–2.25
–2.50
–2.75
–2.5V
–0.25
DISABLE
–OUT
–FB
–OUT, V
= 1V
ICM
+IN
DISABLE
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
–2.25
–2.50
–2.75
V
OCM
0.1µF
+OUT
V
ICM
0V
+2.5V
–IN
R1
R2
+FB
–2.5V
DISABLE
–OUT
R1
R2
–FB
VOCM
+FB
–2.5V
+IN
DISABLE
0.1µF
+OUT
–2.5V
VICM
–IN
–0.25
–0.50
–0.75
–1.00
–OUT, V
= 1V
ICM
R1
R2
+OUT, V
= 1V
+OUT, V
= 1V
40
ICM
ICM
–1.25
–0.25
0
10
20
30
50
60
70
80
90
100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TIME (µs)
TIME (µs)
DISABLE
Figure 45.
Pin Turn-Off Time
DISABLE
Figure 48.
Pin Turn-On Time
Rev. B | Page 16 of 32
Data Sheet
ADA4940-1/ADA4940-2
100
80
1.5
1.0
G = 1, R = 200Ω
L
G = 2, R = 200Ω
L
60
40
0.5
G = 2, R = 1kΩ
L
20
G = 1, R = 1kΩ
L
0
0
–20
–40
–60
–80
–0.5
–1.0
–1.5
G = 1, R = 1kΩ
L
G = 1, R = 200Ω
L
G = 2, R = 1kΩ
L
G = 2, R = 200Ω
L
V
= 0.1V p-p
V
= 2V p-p
OUT, dm
OUT, dm
–100
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
TIME (ns)
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns)
Figure 49. Small Signal Transient Response for Various Gains and Loads
(LFCSP)
Figure 52. Large Signal Transient Response for Various Gains and Loads
100
80
1.5
V
= ±1.5V
S
V
= ±3.5V
S
V
= ±1.5V
S
1.0
0.5
60
40
V
= ±2.5V
S
V
= ±2.5V
S
20
0
0
–20
–40
–60
–80
–100
–0.5
–1.0
–1.5
V
= ±3.5V
S
V
= 0.1V
V
= 2V p-p
OUT, dm
OUT, dm
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
TIME (ns)
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns)
Figure 50. Small Signal Transient Response for Various Supplies (LFCSP)
Figure 53. Large Signal Transient Response for Various Supplies
100
80
60
40
20
0
1.5
1.0
0.5
0
C
C
C
C
= C
= C
= C
= C
= 0pF
= 0.5pF
= 1pF
= 2pF
C
C
C
C
= C
= C
= C
= C
= 0pF
= 0.5pF
= 1pF
= 2pF
COM1
COM1
COM1
COM1
COM2
COM2
COM2
COM2
COM1
COM1
COM1
COM1
COM2
COM2
COM2
COM2
–20
–40
–0.5
–1.0
–1.5
–60
C
= 0pF
= 0.1V p-p
C
= 0pF
DIFF
–80
DIFF
V
V
= 2V p-p
OUT, dm
OUT, dm
–100
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
TIME (ns)
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns)
Figure 51. Small Signal Transient Response for Various Capacitive Loads
(LFCSP)
Figure 54. Large Signal Transient Response for Various Capacitive Loads
Rev. B | Page 17 of 32
ADA4940-1/ADA4940-2
Data Sheet
100
80
100
80
LFCSP-1
LFCSP-1
LFCSP-2: CH1
LFCSP-2: CH2
SOIC-1
LFCSP-2: CH1
LFCSP-2: CH2
SOIC-1
60
60
40
40
20
20
0
0
–20
–40
–60
–80
–20
–40
–60
–80
–100
V
= 0.1V p-p
V
= 0.1V p-p
OUT, dm
OUT, dm
–100
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
TIME (ns)
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
TIME (ns)
Figure 55. Small Signal Transient Response for Various Packages, CL = 0 pF
Figure 57. Small Signal Transient Response for Various Packages, CL = 2 pF
100
80
1.00
0.75
0.50
0.25
0
V
= ±2.5V
V
= ±2.5V
S
S
60
40
V
= ±1.5V
S
V
= ±1.5V
20
S
0
–20
–40
–60
–80
–100
–0.25
–0.50
–0.75
–1.00
V
= 0.1V p-p
V
= 1V p-p
OUT, dm
OUT, dm
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
TIME (ns)
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns)
Figure 56. VOCM Small Signal Transient Response
Figure 58. VOCM Large Signal Transient Response
Rev. B | Page 18 of 32
Data Sheet
ADA4940-1/ADA4940-2
TEST CIRCUITS
1kΩ
+2.5V
NETWORK
ANALYZER
OUTPUT
NETWORK
ANALYZER
INPUT
50Ω
1kΩ
475Ω
54.9Ω
54.9Ω
475Ω
50Ω
52.3Ω
25.5Ω
V
ADA4940-1/
ADA4940-2
V
IN
OCM
1kΩ
50Ω
–2.5V
1kΩ
Figure 59. Equivalent Basic Test Circuit
1kΩ
DC-COUPLED
GENERATOR
+2.5V
100Ω
50Ω
50Ω
1kΩ
475Ω
475Ω
HP
2:1
DUAL
FILTER
LOW-PASS
FILTER
LP
54.9Ω
54.9Ω
CT
ADA4940-1/
ADA4940-2
V
V
IN
OCM
52.3Ω
1kΩ
25.5Ω
–2.5V
1kΩ
Figure 60. Test Circuit for Distortion Measurements
Rev. B | Page 19 of 32
ADA4940-1/ADA4940-2
Data Sheet
TERMINOLOGY
DEFINITION OF TERMS
–FB
Common-Mode Offset Voltage
The common-mode offset voltage is defined as the difference
between the voltage applied to the VOCM terminal and the
common mode of the output voltage.
R
F
R
G
+IN
+D
IN
VOS, cm = VOUT, cm − VOCM
–OUT
+OUT
–
+
R
Differential VOS, Differential CMRR, and VOCM CMRR
ADA4840-1/
ADA4940-2
L, dm
+V
OCM
V
OUT, dm
The differential mode and common-mode voltages each have
their own error sources. The differential offset (VOS, dm) is the
voltage error between the +IN and −IN terminals of the amplifier.
Differential CMRR reflects the change of VOS, dm in response to
changes to the common-mode voltage at the input terminals
+DIN and −DIN.
R
G
–IN
–D
IN
R
F
+FB
Figure 61. Circuit Definitions
Differential Voltage
ΔVIN,cm
CMRRDIFF
=
Differential voltage refers to the difference between two node
voltages. For example, the differential output voltage (or
equivalently, output differential mode voltage) is defined as
ΔVOS,dm
V
OCM CMRR reflects the change of VOS, dm in response to
changes to the common-mode voltage at the output terminals.
VOUT, dm = (V+OUT − V−OUT)
ΔVOCM
CMRRV
=
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
OCM
ΔVOS,dm
Balance
Similarly, the differential input voltage is defined as
Balance is a measure of how well the differential signals are
matched in amplitude; the differential signals are exactly 180°
apart in phase. By this definition, the output balance is the
magnitude of the output common-mode voltage divided by
the magnitude of the output differential mode voltage.
V
IN, dm = (+DIN − (−DIN))
Common-Mode Voltage (CMV)
CMV refers to the average of two node voltages. The output
common-mode voltage is defined as
V
OUT, cm = (V+OUT + V−OUT)/2
Similarly, the input common-mode voltage is defined as
IN, cm = (+DIN + (−DIN))/2
VOUT, cm
Output Balance Error =
VOUT, dm
V
Rev. B | Page 20 of 32
Data Sheet
ADA4940-1/ADA4940-2
THEORY OF OPERATION
The differential feedback loop forces the voltages at +IN and −IN
to equal each other. This fact sets the following relationships:
The ADA4940-1/ADA4940-2 are high speed, low power
differential amplifiers fabricated on Analog Devices advanced
dielectrically isolated SiGe bipolar process. They provide two
closely balanced differential outputs in response to either
differential or single-ended input signals. An external feedback
network that is similar to a voltage feedback operational
amplifier sets the differential gain. The output common-mode
voltage is independent of the input common-mode voltage and
is set by an external voltage at the VOCM terminal. The PNP
input stage allows input common-mode voltages between the
negative supply and 1.2 V below the positive supply. A rail-to-
rail output stage supplies a wide output voltage range.
V−OUT
RF
+DIN
RG
= −
= −
V+OUT
RF
−DIN
RG
Subtracting the previous equations gives the relationship that
shows RF and RG setting the differential gain.
RF
RG
(V+OUT − V−OUT) = (+DIN – (−DIN)) ×
DISABLE
the amplifier to 13.5 µA.
The
pin can be used to reduce the supply current of
The common-mode feedback loop drives the output common-
mode voltage that is sampled at the midpoint of the output
voltage divider to equal the voltage at VOCM. This results in the
following relationships:
Figure 62 shows the ADA4940-1/ADA4940-2 architecture.
The differential feedback loop consists of the differential trans-
conductance GDIFF working through the GO output buffers and
the RF/RG feedback networks. The common-mode feedback
loop is set up with a voltage divider across the two differential
outputs to create an output voltage midpoint and a common-
VOUT,dm
V+OUT = VOCM
+
2
VOUT,dm
2
V−OUT = VOCM
−
mode transconductance, GCM
.
Note that the differential amplifier’s summing junction input
voltages, +IN and −IN, are set by both the output voltages and
the input voltages.
R
R
F
G
+D
IN
C
C
RF
RF + RG
RG
RF + RG
V+IN = +DIN
V−IN = −DIN
+V−OUT
+V+OUT
G
–OUT
O
RF
RF + RG
RG
RF + RG
+IN
–IN
G
G
CM
DIFF
V
OCM
V
REF
G
+OUT
O
R
C
G
C
–D
IN
R
F
Figure 62. ADA4940-1/ADA4940-2 Architectural Block
Rev. B | Page 21 of 32
ADA4940-1/ADA4940-2
Data Sheet
APPLICATIONS INFORMATION
ANALYZING AN APPLICATION CIRCUIT
V
V
nRF1
nRG1
R
R
F1
G1
The ADA4940-1/ADA4940-2 use open-loop gain and negative
feedback to force their differential and common-mode output
voltages in such a way as to minimize the differential and common-
mode error voltages. The differential error voltage is defined as
the voltage between the differential inputs labeled +IN and −IN (see
Figure 61). For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output common-
mode voltage and the voltage applied to VOCM can also be assumed
to be zero. Starting from these two assumptions, any application
circuit can be analyzed.
inIN+
+
V
ADA4940-1/
ADA4940-2
nIN
V
nOD
inIN–
V
OCM
V
nCM
R
R
F2
G2
V
V
nRG2
nRF2
Figure 63. ADA4940-1/ADA4940-2 Noise Model
As with conventional op amp, the output noise voltage densities
can be estimated by multiplying the input-referred terms at +IN
and −IN by the appropriate output factor,
SETTING THE CLOSED-LOOP GAIN
The differential mode gain of the circuit in Figure 61 can be
determined by
where:
2
VOUT, dm
RF
RG
=
GN =
is the circuit noise gain.
VIN, dm
(
β1 + β2
RG1
)
RG2
This assumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
β1 =
and β2 =
are the feedback factors.
RF1 + RG1
RF2 + RG2
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
becomes
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4940-1/ADA4940-2 can
be estimated using the noise model in Figure 63. The input-referred
noise voltage density, vnIN, is modeled as a differential input, and
the noise currents, inIN− and inIN+, appear between each input and
ground. The noise currents are assumed to be equal and produce
a voltage across the parallel combination of the gain and feedback
resistances. vnCM is the noise voltage density at the VOCM pin. Each
of the four resistors contributes (4kTRx)1/2. Table 14 summarizes
the input noise sources, the multiplication factors, and the
output-referred noise density terms. For more noise calculation
information, go to the Analog Devices Differential Amplifier
Calculator (DiffAmpCalc™), click ADIDiffAmpCalculator.zip
and follow the on-screen prompts.
1
β
RF
RG
GN
=
=1+
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
8
vnOD
=
v2
nOi
∑
i=1
Table 14. Output Noise Voltage Density Calculations
Input Noise
Voltage Density
Output
Multiplication Factor
Output-Referred Noise
Voltage Density Term
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
Input Noise Term
vnIN
inIN−
inIN+
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
GN
GN
GN
vnO1 = GN (vnIN)
vnO2 = GN [inIN− × (RG2||RF2)]
vnO3 = GN [inIN+ × (RG1||RF1)]
inIN− × (RG2||RF2)
inIN+ × (RG1||RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
GN (β1 − β2)
GN (1 − β2)
GN (1 − β1)
1
1
vnO4 = GN (β1 − β2)(vnCM)
vnO5 = GN (1 − β2)(4kTRG1)1/2
vnO6 = GN (1 − β1)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
Rev. B | Page 22 of 32
Data Sheet
ADA4940-1/ADA4940-2
Table 15 and Table 16 list several common gain settings, recommended resistor values, input impedances, and output noise density for both
balanced and unbalanced input configurations.
Table 15. Differential Ground-Referenced Input, DC-Coupled, RL = 1 kΩ (See Figure 64)
Nominal Gain (dB)
RF (Ω)
1000
1000
1000
1000
RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
RTI (nV/√Hz)
0
1000
500
318
196
2000
1000
636
11.3
15.4
20.0
27.7
11.3
7.7
6
10
14
6.8
392
5.5
Table 16. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, RL = 1 kΩ (See Figure 65)
Nominal Gain (dB) RF (Ω)
RG (Ω) RT (Ω)
RIN, se (Ω)
1333
750
512
337
RG1 (Ω)1
1025
526
344
223
Differential Output Noise Density (nV/√Hz)
RTI (nV/√Hz)
0
1000
1000
1000
1000
1000
500
318
196
52.3
53.6
54.9
59.0
11.2
15.0
19.0
25.3
11.2
7.5
6.3
5
6
10
14
1 RG1 = RG + (RS||RT)
For an unbalanced, single-ended input signal (see Figure 65),
the input impedance is
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
Even if the external feedback networks (RF/RG) are mismatched,
the internal common-mode feedback loop still forces the outputs
to remain balanced. The amplitudes of the signals at each output
remain equal and 180° out of phase. The input-to-output,
differential mode gain varies proportionately to the feedback
mismatch, but the output balance is unaffected.
RG
RF
RG + RF
RIN, se
=
1−
2×
(
)
R
F
+V
S
As well as causing a noise contribution from VOCM, ratio-matching
errors in the external resistors result in a degradation of the ability
of the circuit to reject input common-mode signals, much the
same as for a four resistors difference amplifier made from a
conventional op amp.
R
R
G
+IN
+D
–D
IN
V
OCM
ADA4940-1/
ADA4940-2
V
OUT, dm
IN
–IN
G
R
F
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential mode, output offset voltage. When G = 1, with a
ground-referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of about 40 dB, a worst-case differential mode
output offset of 25 mV due to the 2.5 V level-shift, and no
significant degradation in output balance error.
Figure 64. ADA4940-1/ADA4940-2 Configured for Balanced (Differential) Inputs
R
F
+V
S
R
R
G
S
+IN
R
V
OCM
T
ADA4940-1/
ADA4940-2
V
OUT, dm
R
G
–IN
R
R
T
S
R
F
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
Figure 65. ADA4940-1/ADA4940-2Configured for Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 64, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
the voltage across the input resistor RG1
.
Rev. B | Page 23 of 32
ADA4940-1/ADA4940-2
Data Sheet
R
R
S
TH
Terminating a Single-Ended Input
50Ω
R
52.3Ω
25.5Ω
T
V
V
This section describes how to properly terminate a single-ended
input to the ADA4940-1/ADA4940-2 with a gain of 1, RF = 1 kΩ
and RG = 1 kΩ. An example using an input source with a terminated
output voltage of 1 V p-p and source resistance of 50 Ω illustrates
the three steps that must be followed. Because the terminated
output voltage of the source is 1 V p-p, the open-circuit output
voltage of the source is 2 V p-p. The source shown in Figure 66
indicates this open-circuit voltage.
S
TH
1.02V p-p
2V p-p
Figure 68. Calculating the Thevenin Equivalent
RTS = RTH = RS||RT = 25.5 Ω. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 Ω. The modified
circuit with the Thevenin equivalent (closest 1% value used for
RTH) of the terminated source and RTS in the lower feedback
loop is shown in Figure 69.
R
F
1kΩ
+V
R
R
F
IN, se
1.33kΩ
S
1kΩ
+V
R
R
S
S
G
50Ω
1kΩ
R
R
TH
G
V
S
ADA4940-1
ADA4940-2
V
OCM
R
V
OUT, dm
2V p-p
25.5Ω
1kΩ
L
V
TH
1.02V p-p
ADA4940-1
ADA4940-2
R
G
V
OCM
V
OUT, dm
R
L
1kΩ
R
G
1kΩ
R
TS
25.5Ω
–V
S
R
F
–V
S
1kΩ
R
F
Figure 66. Calculating Single-Ended Input Impedance, RIN
1kΩ
1. The input impedance is calculated by
Figure 69. Thevenin Equivalent and Matched Gain Resistors
Figure 69 presents a tractable circuit with matched feedback
loops that can be easily evaluated.
RG
RF
2×(RG + RF )
1000
1000
RIN, se
=
=
= 1.33 kΩ
It is useful to point out two effects that occur with a terminated
input. The first is that the value of RG is increased in both loops,
lowering the overall closed-loop gain. The second is that VTH
is a little larger than 1 V p-p, as it would be if RT = 50 Ω.
These two effects have opposite impacts on the output voltage,
and for large resistor values in the feedback loops (~1 kΩ), the
effects essentially cancel each other out. For small RF and RG,
or high gains, however, the diminished closed-loop gain is not
cancelled completely by the increased VTH. This can be seen by
evaluating Figure 69.
1−
1−
2×( 1000 + 1000)
2. To match the 50 Ω source resistance, calculate the
termination resistor, RT, using RT||1.33 kΩ = 50 Ω.
The closest standard 1% value for RT is 52.3 Ω.
R
F
1kΩ
+V
R
IN, se
50Ω
S
R
R
S
G
50Ω
1kΩ
R
T
V
S
52.3Ω
ADA4940-1
ADA4940-2
V
The desired differential output in this example is 1 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 1. The actual differential output voltage,
however, is equal to (1.02 V p-p)(1000/1025.5) = 0.996 V p-p.
This is within the tolerance of the resistors, so no change to
the feedback resistor, RF, is required.
OCM
R
V
OUT, dm
2V p-p
L
R
G
1kΩ
–V
S
R
F
1kΩ
Figure 67. Adding Termination Resistor RT
INPUT COMMON-MODE VOLTAGE RANGE
3. Figure 67 shows that the effective RG in the upper feedback
loop is now greater than the RG in the lower loop due to the
addition of the termination resistors. To compensate for the
imbalance of the gain resistors, add a correction resistor (RTS)
in series with RG in the lower loop. RTS is the Thevenin
equivalent of the source resistance, RS, and the termination
resistance, RT, and is equal to RS||RT.
The ADA4940-1/ADA4940-2 input common-mode range is
shifted down by approximately 1 VBE, in contrast to other ADC
drivers with centered input ranges, such as the ADA4939-x. The
downward-shifted input common-mode range is especially
suited to dc-coupled, single-ended-to-differential, and single-
supply applications.
For 2.5 V or +5 V supply operation, the input common-mode
range at the summing nodes of the amplifier is specified as −2.7 V
to +1.3 V or −0.2 V to 3.8 V, and is specified as −0.2 V to +1.8 V
with a +3 V supply.
Rev. B | Page 24 of 32
Data Sheet
ADA4940-1/ADA4940-2
+V
S
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Although the ADA4940-1/ADA4940-2 is best suited to dc-
coupled applications, it is nonetheless possible to use it in ac-
coupled circuits. Input ac coupling capacitors can be inserted
between the source and RG. This ac coupling blocks the flow
of the dc common-mode feedback current and causes the
ADA4940-1/ADA4940-2 dc input common-mode voltage to
equal the dc output common-mode voltage. These ac coupling
capacitors must be placed in both loops to keep the feedback
factors matched. Output ac coupling capacitors can be placed in
series between each output and its respective load.
AMPLIFIER
BIAS CURRENT
DISABLE
–V
S
DISABLE
Figure 70.
Pin Circuit
DRIVING A CAPACITIVE LOAD
SETTING THE OUTPUT COMMON-MODE VOLTAGE
A purely capacitive load reacts with the bond wire and pin
inductance of the ADA4940-1/ADA4940-2, resulting in high
frequency ringing in the transient response and loss of phase
margin. One way to minimize this effect is to place a resistor in
series with each output to buffer the load capacitance. The resistor
and load capacitance form a first-order, low-pass filter; therefore,
the resistor value should be as small as possible. In some cases,
the ADCs require small series resistors to be added on their inputs.
The VOCM pin of the ADA4940-1/ADA4940-2 is internally
biased at a voltage approximately equal to the midsupply point,
[(+VS) + (−VS)]/2. Relying on this internal bias results in an
output common-mode voltage that is within approximately
100 mV of the expected value.
In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source, or
resistor divider (10 kΩ or greater resistors), be used. The output
common-mode offset listed in the Specifications section assumes
that the VOCM input is driven by a low impedance voltage source.
Figure 71 illustrates the capacitive load vs. the series resistance
required to maintain a minimum 45° of phase margin.
120
VIN
+2.5V
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 250 kΩ.
R3
R4
–FB
RS
–OUT
+OUT
+IN
100
80
60
40
20
0
C
C
L
V
OCM
L
0.1µF
–IN
R
S
+FB
DISABLE PIN
The ADA4940-1/ADA4940-2 feature a
R1
R2
–2.5V
DISABLE
pin that can
be used to minimize the quiescent current consumed when the
DISABLE
pin. The threshold between high and
device is not being used.
DISABLE
is asserted by applying a low
logic level to the
low logic levels is nominally 1.4 V above the negative supply rail.
See Table 5 and Table 8 for the threshold limits.
5
10
100
LOAD CAPACITANCE (pF)
1000
DISABLE
The
enables the amplifier for normal operation. The ADA4940-1/
DISABLE
pin features an internal pull-up network that
Figure 71. Capacitive Load vs. Series Resistance (LFSCP)
ADA4940-2
pin can be left floating (that is, no
external connection is required) and does not require an
external pull-up resistor to ensure normal on operation (see
Figure 70). When the ADA4940-1/ADA4940-2 is disabled, the
output is high impedance. Note that the outputs are tied to the
inputs through the feedback resistors and to the source using the
gain resistors. In addition, there are back-to-back diodes on the
input pins that limit the differential voltage to 1.2 V.
Rev. B | Page 25 of 32
ADA4940-1/ADA4940-2
Data Sheet
mode voltage of 2.5 V, each ADA4940-1 output swings between 0
V and 5 V, opposite in phase, providing a gain of 1 and a 10 V p-
p differential signal to the ADC input. The differential RC section
between the ADA4940-1 output and the ADC provides single-pole,
low-pass filtering with a corner frequency of 1.79 MHz and extra
buffering for the current spikes that are output from the ADC input
when its sample-and-hold (SHA) capacitors are discharged.
DRIVING A HIGH PRECISION ADC
The ADA4940-1/ADA4940-2 are ideally suited for broadband
dc-coupled applications. The circuit in Figure 73 shows a front-
end connection for an ADA4940-1 driving an AD7982, which is
an 18-bit, 1 MSPS successive approximation, analog-to-digital
converter (ADC) that operates from a single power supply, 3 V
to 5 V. It contains a low power, high speed, 18-bit sampling
ADC and a versatile serial interface port. The reference voltage,
REF, is applied externally and can be set independent of the
supply voltage. As shown in Figure 73, the ADA4940-1 is dc-
coupled on the input and the output, which eliminates the need
for a transformer to drive the ADC. The amplifier performs a
single-ended-to-differential conversion if needed and level
shifts the input signal to match the input common mode of the
ADC. The ADA4940-1 is configured with a dual 7 V supply
(+6 V and −1 V) and a gain that is set by the ratio of the
feedback resistor to the gain resistor. In addition, the circuit
can be used in a single-ended-input-to-differential output or
differential-input-to-differential output configuration. If needed,
a termination resistor in parallel with the source input can be
used. Whether the input is a single-ended input or differential,
the input impedance of the amplifier can be calculated as shown in
the Terminating a Single-Ended Input section. If R1 = R2 = R3 =
R4 = 1 kΩ, the single-ended input impedance is approximately
1.33 kΩ, which, in parallel with a 52.3 Ω termination resistor,
provides a 50 Ω termination for the source. An additional 25.5 Ω
(1025.5 Ω total) at the inverting input balances the parallel
impedance of the 50 Ω source and the termination resistor driving
the noninverting input. However, if a differential source input is
used, the differential input impedance is 2 kΩ. In this case, two
52.3 Ω termination resistors are used to terminate the inputs.
The total system power in Figure 73 is under 35 mW. A large
portion of that power is the current coming from supplies to the
output, which is set at 2.5 V, going back to the input through the
feedback and gain resistors. To reduce that power to 25 mW,
increase the value of the feedback and gain resistor from 1 kΩ
to 2 kΩ and set the value of the resistors R5 and R6 to 3 kΩ. The
ADR435 is used to regulate the +6 V supply to +5 V, which ends
up powering the ADC and setting the reference voltage for the
V
OCM pin.
Figure 72 shows the fft of a 20 kHz differential input tone
sampled at 1 MSPS. The second and third harmonics are down
at −118 dBc and −122 dBc.
0
–20
–40
–60
–80
–100
–120
–140
–160
In this example, the signal generator has a 10 V p-p symmetric,
ground-referenced bipolar output. The VOCM input is bypassed for
noise reduction and set externally with 1% resistors to 2.5 V to
maximize the output dynamic range. With an output common-
0
20k
40k
60k
80k
100k
FREQUENCY (Hz)
Figure 72. Distortion Measurement of a 20 kHz Input Tone (CN-0237)
+6V
ADR435
+5V
+D
IN
10µF
+6V
R3
R4
–FB
+2.5V
+IN
33Ω
–OUT
+OUT
REF
VDD
R5
R6
IN+
IN–
V
2.7nF
2.7nF
OCM
ADA4940-1
AD7982
0.1µF
33Ω
GND
–IN
SERIAL
INTERFACE
+FB
R2
R1
–1V
–D
IN
Figure 73. ADA4940-1 (LFCSP) Driving the AD7982 ADC
Rev. B | Page 26 of 32
Data Sheet
ADA4940-1/ADA4940-2
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4940-1/ADA4940-2 are
sensitive to the PCB environment in which they operate.
Realizing their superior performance requires attention to
the details of high speed PCB design.
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. Use two parallel bypass capacitors (1000 pF and
0.1 µF) for each supply. Place the 1000 pF capacitor closer to the
device. Further away, provide low frequency bypassing using
10 µF tantalum capacitors from each supply to ground.
ADA4940-1 LFCSP EXAMPLE
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4940-1 as possible.
However, clear the area near the feedback resistors (RF), gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3)
of all ground and power planes (see Figure 74). Clearing the
ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the
amplifier at high frequencies.
Ensure that signal routing is short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance. When
routing differential signals over a long distance, ensure that
PCB traces are close together, and twist any differential wiring
such that loop area is minimized. Doing this reduces radiated
energy and makes the circuit less susceptible to interference.
1.30
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
0.80
1.30 0.80
Figure 75. Recommended PCB Thermal Attach Pad Dimensions (mm)
Figure 74. Ground and Power Plane Voiding in Vicinity of RF and RG
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
POWER PLANE
BOTTOM METAL
Figure 76. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)
Rev. B | Page 27 of 32
ADA4940-1/ADA4940-2
OUTLINE DIMENSIONS
Data Sheet
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
16
1
0.45
(BOTTOM VIEW)
12
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 77. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-2)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 78. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 28 of 32
Data Sheet
ADA4940-1/ADA4940-2
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
TOP
VIEW
3.75
BSC SQ
EXPOSED
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
12
7
0.23 MIN
0.80 MAX
0.65 TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
Figure 79. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
8-Lead SOIC_N
Package Option
CP-16-2
CP-16-2
Ordering Quantity
Branding
H29
H29
ADA4940-1ACPZ-R2
ADA4940-1ACPZ-RL
ADA4940-1ACPZ-R7
ADA4940-1ACP-EBZ
ADA4940-1ARZ
ADA4940-1ARZ-RL
ADA4940-1ARZ-R7
ADA4940-1AR-EBZ
ADA4940-2ACPZ-R2
ADA4940-2ACPZ-RL
ADA4940-2ACPZ-R7
ADA4940-2ACP-EBZ
250
5,000
1,500
CP-16-2
H29
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
R-8
R-8
R-8
98
2,500
1,000
8-Lead SOIC_N
8-Lead SOIC_N
Evaluation Board
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
CP-24-3
CP-24-3
CP-24-3
250
5,000
1,500
1 Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
ADA4940-1/ADA4940-2
NOTES
Data Sheet
Rev. B | Page 30 of 32
Data Sheet
NOTES
ADA4940-1/ADA4940-2
Rev. B | Page 31 of 32
ADA4940-1/ADA4940-2
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08452-0-3/12(B)
Rev. B | Page 32 of 32
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