ADATE318BCPZ [ADI]
600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip; 600 MHz双通道集成DCL与PPMU ， VHH驱动功能，电平设置DAC和片
| 型号： | ADATE318BCPZ |
| 厂家： | 
ADI |
| 描述： | 600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip |
| 文件： | 总80页 (文件大小：1351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
600 MHz Dual Integrated DCL with PPMU, VHH Drive
Capability, Level Setting DACs, and On-Chip Calibration
Engine
ADATE318
FEATURES
GENERAL DESCRIPTION
600 MHz/1200 Mbps data rate
The ADATE318 is a complete, single-chip ATE solution that
performs the pin electronics functions of driver, comparator,
and active load (DCL), four quadrant, per pin, parametric
measurement unit (PPMU). It has VHH drive capability per
chip to support flash memory testing applications and integ-
rated 16-bit DACs with an on-chip calibration engine to
3-level driver with high-Z and reflection clamps
Window and differential comparators
±25 mA active load
Per pin PPMU with −2.0 V to +6.5 V range
Low leakage mode (typically 4 nA)
Integrated 16-bit DACs with offset and gain correction
High speed operating voltage range: –1.5 V to +6.5 V
Dedicated VHH output pin range: 0.0 V to 13.5 V
1.1 W power dissipation per channel
Driver
3-level voltage range: –1.5 V to +6.5 V
Precision trimmed output resistance
Unterminated swing: 200 mV minimum to 8 V maximum
725 ps minimum pulse width, VIH − VIL = 2.0 V
Comparator
Differential and single-ended window modes
>1.2 GHz input equivalent bandwidth
Load
±25 mA current range
Per pin PPMU (PPMU)
provide all necessary dc levels for operation of the part.
The driver features three active states: data high, data low, and
terminate mode, as well as a high impedance inhibit state. The
inhibit state, in conjunction with the integrated dynamic
clamps, facilitates the implementation of a high speed active
termination. The output voltage capability is −1.5 V to +6.5 V
to accommodate a wide range of ATE and instrumentation
applications.
The ADATE318 can be used as a dual, single-ended drive/
receive channel or as a single differential drive/receive channel.
Each channel of the ADATE318 features a high speed window
comparator as well as a programmable threshold differential
comparator for differential ATE applications. A four quadrant
PPMU is also provided per channel.
Force voltage/compliance range: –2.0 V to +6.5 V
5 current ranges: 40 mA, 1 mA, 100 μA, 10 ꢀA, 2 ꢀA
External sense input for system PMU
Go/no-go comparators
All dc levels for DCL and PPMU functions are generated by 24
on-chip 16-bit DACs. To facilitate accurate levels programming,
the ADATE318 contains an integrated calibration function to
correct gain and offset errors for each functional block.
Correction coefficients can be stored on chip, and any values
written to the DACs are automatically adjusted using the
appropriate correction factors.
Levels
Fully integrated 16-bit DACs
On-chip gain and offset calibration registers and
add/multiply engine
The ADATE318 uses a serial programmable interface (SPI) bus
to program all functional blocks, DACs, and on-chip calibration
constants. It also has an on-chip temperature sensor and
over/undervoltage fault clamps for monitoring and reporting
the device temperature and any output pin or PPMU voltage
faults that may occur during operation.
Package
84-lead 10 mm × 10 mm LFCSP (0.4 mm pitch)
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADATE318
TABLE OF CONTENTS
Features .............................................................................................. 1
Level Setting DACs......................................................................... 63
DAC Update Modes................................................................... 63
DAC Transfer Functions ........................................................... 67
Gain and Offset Correction ...................................................... 68
X2 Registers.................................................................................. 68
Sample Calculations of m and c ............................................... 68
Power Supply, Grounding, and Decoupling Strategy ................ 70
User Information and Truth Tables ............................................. 71
Alarm Functions......................................................................... 72
PPMU External Capacitors....................................................... 72
Temperature Sensor ................................................................... 72
Default Test Conditions............................................................. 73
Detailed Functional Block Diagrams........................................... 74
Outline Dimensions....................................................................... 80
Ordering Guide .......................................................................... 80
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
SPI Timing Details ..................................................................... 22
Absolute Maximum Ratings.......................................................... 27
Thermal Resistance .................................................................... 27
ESD Caution................................................................................ 27
Pin Configuration and Function Descriptions........................... 28
Typical Performance Characteristics ........................................... 31
SPI Interconnect Details ................................................................ 49
BUSY
Use of the SPI
Pin................................................................ 50
RST
Reset Sequence and the
Pin .................................................. 51
SPI Register Definitions and Memory Map................................ 52
Control Register Details................................................................. 55
REVISION HISTORY
4/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 80
ADATE318
FUNCTIONAL BLOCK DIAGRAM
ADATE318
VOH
OVDH
OVDL
0
PPMU
GO/NO-GO
TO ALARM
(HIGH/LOW
VOLTAGE FAULT)
PPMU_CMPH0
PPMU_CMPL0
TO ALARM
OVER-
VOLTAGE
(PPMU HIGH/LOW
CLAMP FAULT)
VOL
0
THERM
PPMU_VIN0
MUX
PPMU_MEAS0
PPMU_S0
OUT
VCH0
VCL0
PPMU
MUX
S
F
VIH0
VIT/VCOM0
VIL0
VCH0
VCL0
PMU_S0
DUT0
DAT0
100Ω
50Ω
DRIVER
DAT0
RCV0
IOL0
100Ω
+
–
ACTIVE
LOAD
RCV0
VCOM
0
IOH0
VTTC0
50Ω
50Ω
CMPH0
CMPH0
VOH0
VOL0
NWC
COMPARATOR
DIFF
CH0 ONLY
CMPL0
CMPL0
NWC
CHANNEL 0
VHH
VIH0
VIL0
TEMP
SENSOR
DAT
RCV
0
THERM
ALARM
HVOUT
ALARM
0
VHH
DRIVER
VPLUS
VDD
SDI
SCLK
CS
VCC
GAIN/OFFSET
CORRECTION
SPI
2 × 12
16-BIT DACs
PGND
DGND
VSS
SDO
MUX
BUSY
RST
COMMON
CHANNEL 1
(SAME AS CHANNEL 0 EXCEPT WHERE NOTED)
Figure 1.
Rev. 0 | Page 3 of 80
ADATE318
SPECIFICATIONS
VDD = +10.0 V, VCC = +2.5 V, VSS= −6.0 V, VPLUS= +16.75 V, VTTCx = +1.2 V, VREF = 5.000 V, VREFGND = 0.000 V. All test
conditions are as defined in Table 32. All specified values are at TJ = 50°C, where TJ corresponds to the internal temperature sensor
reading (THERM pin), unless otherwise noted. Temperature coefficients are measured around TJ = 50° 20°C, unless otherwise noted.
Typical values are based on statistical mean of design, simulation analyses, and/or limited bench evaluation data. Typical values are
neither tested nor guaranteed. See Table 16 for an explanation of test levels.
Table 1. Detailed Electrical Specifications
Test
Parameter
Min
Typ
Max
Unit
Level Conditions
TOTAL FUNCTION
Output Leakage Current, DCL Disable
PPMU Range E
−10.0
4.0
4.0
+10.0 nA
nA
P
−2.0 V < VDUTx < +6.5 V, PPMU and DCL disabled, PPMU
Range E, VCL = −2.5 V, VCH = +7.5 V
PPMU Range A, Range B, Range C, and
Range D
CT
−2.0 V < VDUTx < +6.5 V, PPMU and DCL disabled, PPMU
Range A, Range B, Range C, Range D, VCL = −2.5 V,
VCH = +7.5 V
Output Leakage Current,
Driver High-Z Mode
−2
+2
μA
P
−2.0 V < VDUTx < +7.0 V, PPMU disabled and DCL enabled,
RCVx active, VCL = −2.5 V, VCH = +7.5 V
DUTx Pin Capacitance
DUTx Pin Voltage Range
POWER SUPPLIES
1.2
pF
V
S
Drive VIT = 0.0 V
−2.0
+7.0
D
Total Supply Range,
VPLUS to VSS
22.75 23.55
16.75 17.60
V
D
VPLUS Supply, VPLUS
15.90
9.5
V
D
D
D
D
D
P
Defines dc PSR conditions
Defines dc PSR conditions
Defines dc PSR conditions
Defines dc PSR conditions
Positive Supply, VDD
10.0
−6.0
2.5
10.5
−5.7
3.5
V
Negative Supply, VSS
−6.3
2.3
V
Logic Supply, VCC
V
Comparator Output Termination, VTTCx
VPLUS Supply Current, VPLUS
0.5
1.2
3.3
V
1.1
2.5
mA
mA
VHH pin disabled
4.75
13.28 16.25
P
VHH pin enabled, RCVx active, no load,
VHH programmed level = 13.0 V
Logic Supply Current, VCC
−125
1
+125
μA
P
S
Quiescent (SPI is static); VCC = 2.5 V
7.5
mA
Current drawn during clocked portion of device reset
sequence
Termination Supply Current, VTTCx
Positive Supply Current, VDD
Negative Supply Current, VSS
Total Power Dissipation
30
45
50
mA
mA
mA
W
P
90
99
115
185
2.3
P
Load power-down (IOH = IOL = 0 mA)
Load power-down (IOH = IOL = 0 mA)
Load power-down (IOH = IOL = 0 mA)
Load active off (IOH = IOL = 25 mA)
Load active off (IOH = IOL = 25 mA)
Load active off (IOH = IOL = 25 mA)
Load active off (IOH = IOL = 25 mA), calibrated
Load active off (IOH = IOL = 25 mA), calibrated
Load active off (IOH = IOL = 25 mA), calibrated
Load power-down, PPMU standby
155
1.9
145
210
3.0
172
2.1
P
P
Positive Supply Current, VDD
Negative Supply Current, VSS
Total Power Dissipation
174
246
3.3
210
280
3.6
mA
mA
W
P
P
P
Positive Supply Current, VDD
Negative Supply Current, VSS
Total Power Dissipation
167
238
3.2
mA
mA
W
CT
CT
CT
CT
CT
CT
Positive Supply Current, VDD
Negative Supply Current, VSS
Total Power Dissipation
109
183
2.3
mA
mA
W
Load power-down, PPMU standby
Load power-down, PPMU standby
Rev. 0 | Page 4 of 80
ADATE318
Test
Parameter
Min
Typ
Max
Unit
Level Conditions
TEMPERATURE MONITOR
Temperature Sensor Gain
10
6
mV/K
K
D
Temperature Sensor Accuracy over
Temperature Range
CT
VREF INPUT REFERENCE
DAC Reference Input Voltage Range
(VREF Pin)
4.950
5.000 5.050
100
V
D
P
Provided externally:
VREF pin = +5.000 V
VREFGND pin = 0.000 V (not referenced to VDUTGND
)
Input Bias Current
DUTGND INPUT
μA
Tested with 5.000 V applied
Input Voltage Range,
Referenced to AGND
−0.1
V
D
P
+0.1
Input Bias Current
−100
μA
+100
Tested at −100 mV and +100 mV
Table 2. Driver (VIH − VIL ≥ 100 mV to Meet DC and AC Performance Specifications)
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
DC SPECIFICATIONS
High-Speed Differential Input
Characteristics
High Speed Input Termination
Resistance: DATx, RCVx
92
100
0.4
108
Ω
P
Impedance between each pair of DATx and RCVx pins;
push 4 mA into positive pin, force 0.8 V on negative pin,
measure voltage between pins; calculate resistance (ΔV/ΔI)
Input Voltage Differential: DATx, RCVx
Input Voltage Range: DATx, RCVx
Output Characteristics
0.2
0.0
1.0
3.3
V
V
D
D
0.2 V < VDM < 1.0 V
0.0 V < (VCM VDM/2) < 3.3 V
Output High Range, VIH
−1.4
−1.5
−1.5
0.0
+6.5
+6.4
+6.5
V
V
V
V
D
D
D
D
Output Low Range, VIL
Output Term Range, VIT
Functional Amplitude
(VIH – VIL)
8.0
DC Output Current Limit Source
DC Output Current Limit Sink
Output Resistance, 40 mA
75
130
−75
51
mA
mA
Ω
P
P
P
Drive high, VIH = +6.5 V, short DUTx pin to −1.5 V, measure
current
−130
46
Drive low, VIL = −1.5 V, short DUTx pin to +6.5 V, measure
current
48.6
ΔVDUT/ΔIDUT; source: VIH = 3.0 V, IDUT = +1 mA, +40 mA;
sink: VIL = 0.0 V, IDUT = −1 mA, −40 mA
DC ACCURACY
VIH tests with VIL = −2.5 V, VIT = −2.5 V
VIL tests with VIH = +7.5 V, VIT = +7.5 V
VIT tests with VIL = −2.5 V, VIH = +7.5 V, unless otherwise
specified
VIH, VIL, VIT Offset Error
VIH, VIL, VIT Offset Tempco
VIH, VIL, VIT Gain
−500
1.0
+500
1.1
mV
P
Measured at DAC Code 0x4000 (0 V), uncalibrated
625
μV/°C
V/V
CT
P
Gain derived from measurements at DAC Code 0x4000
(0 V) and DAC Code 0xC000 (5 V); based on ideal DAC
transfer functions (see Table 21)
VIH, VIL, VIT Gain Tempco
VIH, VIL, VIT DNL
40
1
ppm/°C CT
mV
CT
After two point gain/offset calibration; calibration points at
0x4000 (0 V) output; 0xC000 (+5 V) output; measured over
full specified output range
VIH, VIL, VIT INL
−7
mV
P
After two point gain/offset calibration; applies to nominal
VDD = +10.0 V supply case only
+7
Rev. 0 | Page 5 of 80
ADATE318
Test
Level
Parameter
Min
Typ
153
2
Max
Unit
ꢀV
Conditions
VIH, VIL, VIT Resolution
DUTGND Voltage Accuracy
D
P
−7
mV
Over 0.1 V range; measured at end points of VIH, VIL, and
VIT functional range
+7
DC Levels Interaction
VIH vs. VIL
DC interaction on VIL, VIH, and VIT output level while other
driver DAC levels are varied
0.2
1
mV
mV
mV
mV
mV
mV
mV
mV/V
CT
CT
CT
CT
CT
CT
CT
CT
Monitor interaction on VIH = +6.5 V; sweep VIL = −1.5 V to
+6.4 V, VIT = +1.0 V
VIH vs. VIT
Monitor interaction on VIH = +6.5 V; sweep VIT = −1.5 V to
+6.5 V, VIL = 0.0 V
VIL vs. VIH
0.2
1
Monitor interaction on VIL = −1.5 V; sweep VIH = −1.4 V to
+6.5 V, VIT = +1.0 V
VIL vs. VIT
Monitor interaction on VIL = −1.5 V; sweep VIT = −1.5 V to
+6.5 V, VIH = +2.0 V
VIT vs. VIH
1
Monitor interaction on VIT = +1.0 V; sweep VIH = −1.4 V to
+6.5 V, VIL = −1.5 V
VIT vs. VIL
1
Monitor interaction on VIT = +1.0 V; sweep VIL = −1.5 V to
+6.4 V, VIH = +6.5 V
Overall Voltage Accuracy
8
VIH − VIL ≥ 100 mV; sum of INL, dc interaction, DUTGND,
and tempco errors over 5ºC, after calibration
VIH, VIL, VIT DC PSRR
10
Measured at calibration points
AC SPECIFICATIONS
All ac specifications performed after calibration
Toggle DATx
Rise/Fall Times
0.2 V Programmed Swing, TRISE
0.2 V Programmed Swing, TFALL
0.5 V Programmed Swing, TRISE
0.5 V Programmed Swing, TFALL
1.0 V Programmed Swing, TRISE
1.0 V Programmed Swing, TFALL
2.0 V Programmed Swing, TRISE
2.0 V Programmed Swing, TFALL
3.0 V Programmed Swing, TRISE
3.0 V Programmed Swing, TFALL
5.0 V Programmed Swing, TRISE
5.0 V Programmed Swing, TFALL
Rise to Fall Matching
215
277
218
274
222
283
297
322
447
397
1117
798
−25
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
CB
CB
CB
CB
P
20% to 80%, VIH = 0.2 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 0.2 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 0.5 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 0.5 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 1.0 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 1.0 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 2.0 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 2.0 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 3.0 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 3.0 V, VIL = 0.0 V, terminated
10% to 90%, VIH = 5.0 V, VIL = 0.0 V, unterminated
10% to 90%, VIH = 5.0 V, VIL = 0.0 V, unterminated
150
150
320
320
P
CB
CB
CB
CB
CB
CB
CB
Rise to fall within one channel, VIH = 2.0 V, VIL = 0.0 V,
terminated
−61
ps
CB
Rise to fall within one channel; VIH = 1.0 V, VIL = 0.0 V,
terminated
Minimum Pulse Width
Toggle DATx
0.5 V Programmed Swing
725
725
2040
725
725
ps
CB
CB
CB
CB
CB
VIH = 0.5 V, VIL = 0.0 V, terminated, timing error less than
+69/−33 ps
ps
VIH = 0.5 V, VIL = 0.0 V, terminated, less than 10%
amplitude loss
Maximum Toggle Rate
Mbps
ps
VIH = 0.5 V, VIL = 0.0 V, terminated, less than 10% loss at
50% duty
1.0 V Programmed Swing
VIH = 1.0 V, VIL = 0.0 V, terminated, timing error less than
+58/−35 ps
ps
VIH = 1.0 V, VIL = 0.0 V, terminated, less than 10%
amplitude loss
Rev. 0 | Page 6 of 80
ADATE318
Test
Level
Parameter
Maximum Toggle Rate
Min
Typ
Max
Unit
Conditions
2040
Mbps
CB
CB
CB
CB
CB
CB
CB
VIH = 1.0 V, VIL = 0.0 V, terminated, less than 10% loss at
50% duty
2.0 V Programmed Swing
725
ps
VIH = 2.0 V, VIL = 0.0 V, terminated, timing error less than
+80/−48 ps
725
ps
VIH = 2.0 V, VIL = 0.0 V, terminated, less than 10%
amplitude loss
Maximum Toggle Rate
1400
900
Mbps
ps
VIH = 2.0 V, VIL = 0.0 V, terminated, less than 10% loss at
50% duty
3.0 V Programmed Swing
VIH = 3.0 V, VIL = 0.0 V, terminated, timing error less than
+50/−83 ps
900
ps
VIH = 3.0 V, VIL = 0.0 V, terminated, less than 10%
amplitude loss
Maximum Toggle Rate
1100
Mbps
VIH = 3.0 V, VIL = 0.0 V, terminated, less than 10%
amplitude loss at 50% duty cycle
Dynamic Performance,
Drive (VIH to VIL)
Toggle DATx
Propagation Delay Time
1.26
1.4
43
ns
CB
CB
CB
CB
VIH = 2.0 V, VIL = 0.0 V, terminated
Propagation Delay Tempco
Delay Matching, Edge to Edge
Delay Matching, Channel to Channel
ps/ºC
ps
VIH = 2.0 V, VIL = 0.0 V, terminated
VIH = 2.0 V, VIL = 0.0 V, terminated, rising vs. falling
32
ps
VIH = 2.0 V, VIL = 0.0 V, terminated, rising vs. rising, falling
vs. falling
Delay Change vs. Duty Cycle
Overshoot and Undershoot
Settling Time (VIH to VIL)
−28
ps
CB
CB
VIH = 2.0 V, VIL = 0.0 V, terminated, 5% to 95% duty cycle
VIH = 2.0 V, VIL = 0.0 V, terminated, driver CLC set to 0
Toggle DATx
−116
mV
To Within 3% of Final Value
To Within 1% of Final Value
1.7
45
ns
ns
CB
CB
VIH = 2.0 V, VIL= 0.0 V, terminated
VIH = 2.0 V, VIL= 0.0 V, terminated
Toggle RCVx
Dynamic Performance,
VTerm (VIH or VIL to/from VIT)
Propagation Delay Time
1.39
2.3
ns
CB
CB
CB
CB
VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated
VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated
20% to 80%, VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated
Toggle RCVx
Propagation Delay Tempco
Transition Time, Active to VIT
Transition Time, VIT to Active
ps/ºC
ps
310
329
ps
Dynamic Performance,
Inhibit (VIH or VIL to/from Inhibit)
Transition Time, Inhibit to Active
Transition Time, Active to Inhibit
Prop Delay, Inhibit to VIH
357
1.34
2.6
ps
ns
ns
CB
CB
CB
20% to 80%, VIH = +1.0 V, VIL = −1.0 V, terminated
20% to 80%, VIH = +1.0 V, VIL = −1.0 V, terminated
VIH = +1.0 V, VIL = −1.0 V, terminated; measured from RCVx
input crossing to DUTx pin output 50%
Prop Delay, Inhibit to VIL
2.8
52
ns
ps
CB
CB
VIH = +1.0 V, VIL = −1.0 V, terminated
VIH = +1.0 V, VIL = −1.0 V, terminated
Prop Delay Matching,
Inhibit to VIL vs. Inhibit to VIH
Prop Delay, VIH to Inhibit
2.29
ns
CB
VIH = +1.0 V, VIL = −1.0 V, terminated, measured from RCVx
input crossing to DUTx pin output 50%
Prop Delay, VIL to Inhibit
I/O Spike
2.02
24
ns
CB
CB
VIH = +1.0 V, VIL = −1.0 V, terminated
VIH = 0.0 V, VIL = 0.0 V, terminated
mV pk-
pk
Driver Pre-Emphasis (CLC)
Pre-Emphasis Amplitude Rising
35
14
24
16
%
%
%
%
CB
CB
CB
CB
VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 7
VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 0
VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 7
VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 0
Pre-Emphasis Amplitude Falling
Rev. 0 | Page 7 of 80
ADATE318
Test
Level
Parameter
Min
Typ
2
Max
Unit
%
Conditions
Pre-Emphasis Resolution
Pre-Emphasis Time Constant
D
0.8
ns
CB
VIH = 2.0 V, VIL = 0.0 V, terminated
Table 3. Reflection Clamp (Clamp Accuracy Specifications Apply Only When VCH − VCL > 0.8 V)
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
VCH/VCL PROGRAMMABLE RANGE
−2.5
+7.5
V
D
DC specifications apply over full functional range unless
noted.
VCH
VCH Functional Range
VCH Offset Error
−1.2
+7.0
V
D
P
−300
+300
mV
Driver high-Z, sinking 1 mA, measured at DAC Code 0x4000,
uncalibrated.
VCH Offset Tempco
VCH Gain
0.5
mV/ºC
V/V
CT
P
1.0
1.1
Driver high-Z, sinking 1 mA, gain derived from
measurements at DAC Code 0x4000 (0 V) and DAC Code
0xC000 (5 V), based on ideal DAC transfer function (see
Table 21).
VCH Gain Tempco
VCH Resolution
VCH DNL
30
153
1
ppm/°C
ꢀV
CT
D
mV
CT
Driver high-Z, sinking 1 mA, after two point gain/offset
calibration; calibration points at DAC Code 0x4000 (0 V) and
DAC Code 0xC000 (5 V), measured over functional clamp
range.
VCH INL
−20
+20
mV
P
Driver high-Z, sinking 1 mA, after two point gain/offset
calibration; calibration points at 0x4000 (0 V) and 0xC000
(5 V), measured over functional clamp range.
VCL
VCL Functional Range
VCL Offset Error
−2
+6.2
V
D
P
−300
+300
mV
Driver high-Z, sourcing 1 mA, measured at DAC Code
0x4000, uncalibrated.
VCL Offset Tempco
VCL Gain
0.5
mV/°C
V/V
CT
P
1.0
1.1
Drive high-Z, sourcing 1 mA, gain derived from
measurements at DAC Code 0x4000 (0 V) and DAC Code
0xC000 (5 V), based on ideal DAC transfer function (see
Table 21).
VCL Gain Tempco
VCL Resolution
VCL DNL
30
153
1
ppm/°C
ꢀV
CT
D
mV
CT
Driver high-Z, sourcing 1 mA, after two point gain/offset
calibration; calibration points at 0x4000 (0 V) and 0xC000
(+5 V), measured over functional clamp range.
VCL INL
−20
+20
mV
P
Driver high-Z, sourcing 1 mA, after two point gain/offset
calibration; calibration points at 0x4000 (0 V) and 0xC000
(+5 V), measured over functional clamp range.
DC Clamp Current Limit, VCH
DC Clamp Current Limit, VCL
DUTGND Voltage Accuracy
−120
+75
−7
−75
+120
+7
mA
mA
mV
P
P
P
Driver high-Z, VCH = 0 V, VCL = −2.0 V, VDUTx = +5.0 V.
Driver high-Z, VCH = +6.0 V, VCL = +5.0 V, VDUTx = 0.0 V.
2
Over 0.1 V range, measured at end points of VCH and VCL
functional range.
Rev. 0 | Page 8 of 80
ADATE318
Table 4. Normal Window Comparator (NWC) (Unless Otherwise Specified: VOH Tests at VOL = −1.5 V, VOL Tests at
VOH = +6.5 V, Specifications Apply to Both Comparators)
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
DC SPECIFICATIONS
Input Voltage Range
Differential Voltage Range
Comparator Input Offset Voltage
−1.5
0.1
V
D
D
P
+6.5
8.0
V
−250
mV
Measured at DAC Code 0x4000 (0V), uncalibrated
+250
Input Offset Voltage Tempco
Gain
100
ꢀV/ºC
V/V
CT
P
1.0
1.1
Gain derived from measurements at DAC Code
0x4000 (0 V) and DAC Code 0xC000 (5 V); based on
ideal DAC transfer function (see Table 21)
Gain Tempco
25
153
1
ppm/°C CT
Threshold Resolution
Threshold DNL
ꢀV
D
mV
CT
Measured over −1.5 V to +6.5 V functional range
after two point gain/offset calibration; calibration
points at 0x4000 (0 V) and 0xC000 (5 V)
Threshold INL
−7
−7
mV
P
+7
+7
Measured over −1.5 V to +6.5 V functional range
after two point gain/offset calibration; calibration
points at 0x4000 (0 V) and 0xC000 (5 V)
DUTGND Voltage Accuracy
Uncertainty Band
2
5
mV
mV
P
Over 0.1 V range; measured at end points of VOH
and VOL functional range
CB
VDUTx = 0 V, sweep comparator threshold to
determine the uncertainty band
Maximum Programmable Hysteresis
Hysteresis Resolution
96
5
mV
CB
D
mV
Calculated over hystersis control Code 10 to Code 31
Measured at calibration points
DC PSRR
5
mV/V
CT
Digital Output Characteristics
Internal Pull-Up Resistance to
Comparator, VTTC
46
50
54
Ω
V
P
Pull 1 mA and 10 mA from Logic 1 leg and measure
∆V to calculate resistance; measured ∆V/9 mA; done
for both comparator logic states
Comparator Termination Voltage,
VTTC
0.5
1.2
3.3
D
Common Mode Voltage
V
V
CT
P
Measured with 100 Ω differential termination
Measured with no external termination
VTTC − 0.3
VTTC −
0.5
VTTC
550
Differential Voltage
250
500
166
mV
mV
ps
CT
P
Measured with 100 Ω differential termination
Measured with no external termination
450
Rise/Fall Times, 20% to 80%
AC SPECIFICATIONS
CB
Measured with 50 Ω to external termination voltage
(VTTC)
All ac specifications performed after dc level
calibration, input transition time of ~200 ps, 20% to
80%, measured with 50 Ω to external termination
voltage (VTTC); peaking set to CLC = 2, unless
otherwise specified
Propagation Delay, Input to Output
Propagation Delay Tempco
0.93
1.6
7
ns
CB
CB
CB
CB
VDUTx: 0 V to 1.0 V swing, driver term mode,
VIT = 0.0 V, comparator threshold = 0.5 V
ps/ºC
ps
VDUTx: 0 V to 1.0 V swing, driver term mode,
VIT = 0.0 V, comparator threshold = 0.5 V
Propagation Delay Matching
High Transition to Low Transition
VDUTx: 0 V to 1.0 V swing, driver term mode,
VIT = 0.0 V, comparator threshold = 0.5 V
Propagation Delay Matching
High to Low Comparator
7
ps
VDUTx: 0 V to 1.0 V swing, driver term mode,
VIT = 0.0 V, comparator threshold = 0.5 V
Rev. 0 | Page 9 of 80
ADATE318
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
Propagation Delay Dispersion
Slew Rate
400 ps vs. 1 ns (20% to 80%)
19
40
ps
ps
CB
CB
VDUTx: 0 V to 0.5 V swing, driver term mode,
VIT = 0.0 V, comparator threshold = 0.25 V
Overdrive
250 mV vs. 1.0 V
For 250 mV, VDUTx: 0 V to 0.5 V swing; for 1.0 V,
VDUTx: 0 V to 1.25 V swing, driver term mode,
VIT = 0.0 V, comparator threshold = 0.25 V
1 V Pulse Width
0.7 ns, 1 ns, 5 ns, 10 ns
+2/− 17
+3/− 24
21
ps
ps
ps
ns
CB
CB
CB
CB
VDUTx: 0 V to 1.0 V swing at~32.0 MHz; driver term
mode, VIT = 0.0 V, comparator threshold = 0.5 V
0.5 V Pulse Width
0.6 ns, 1 ns, 5 ns, 10 ns
VDUTx: 0 V to 0.5 V swing at~32.0 MHz, driver term
mode, VIT = 0.0 V; comparator threshold = 0.25 V
Duty Cycle
5% to 95%
VDUTx: 0 V to 1.0 V swing at~32.0 MHz; driver term
mode, VIT =0.0 V, comparator threshold = 0.5 V
Minimum Detectable Pulse Width
0.5
VDUTx: 0 V to 1.0 V swing at 32.0 MHz, driver term
mode, VIT = 0.0 V; greater than 50% output
differential amplitude
Input Equivalent Bandwidth,
Terminated
1520
721
MHz
ps
CB
CB
VDUTx: 0 V to 1.0 V swing; driver term mode,
VIT = 0.0 V, CLC = 2; as measured by shmoo plot;
2
fEQUIV = 0.22/√(tMEAS2 − tDUT
)
ERT High-Z Mode, 3 V, 20% to 80%
VDUTx: 0 V to 3.0 V swing, driver high-Z as measured
2
by shmoo plot; fEQUIV = 0.22/√(tMEAS2 – tDUT
)
Comparator Pre-Emphasis (CLC)
CLC Amplitude Range
16
%
CB
VDUTx: 0 V to 1.0 V swing, driver term mode,
VIT = 0.0 V, comparator pre-emphasis set to
maximum
CLC Resolution
2.3
4.3
% per
bit
CB
CB
3-bit amplitude control
Pre-Emphasis Time Constant
ns
VDUTx: 0 V to 1.0 V swing, driver term mode,
VIT = 0.0 V, comparator pre-emphasis set to
maximum
Table 5. Differential Mode Comparator (DMC) (Unless Otherwise Specified: VOH Tests at VOL = −1.1 V, VOL Tests at
VOH = +1.1 V)
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
DC SPECIFICATIONS
Input Voltage Range
Functional Differential Range
Maximum Differential Input
Input Offset Voltage
−1.5
V
D
D
D
P
+6.5
1.1
0.05
V
8
V
−250
1.0
mV
Offset extrapolated from measurements at DAC Code
0x2666 (−1 V) and DAC Code 0x599A (+1 V), with VCM = 0 V
+250
Offset Voltage Tempco
Gain
150
ꢀV/ºC
V/V
CT
P
1.1
Gain derived from measurements at DAC Code 0x2666
(−1 V) and DAC Code 0x599A (+1 V), based on ideal DAC
transfer function (see Table 21)
Gain Tempco
25
153
1
ppm/°C
ꢀV
CT
D
VOH, VOL Resolution
VOH, VOL DNL
mV
CT
After two point gain/offset calibration, VCM = 0.0 V,
calibration points at 0x2666 (−1 V) and 0x599A (+1 V)
VOH, VOL INL
−7
mV
mV
P
After two point gain/offset calibration, measured over
VOH/VOL range of −1.1 V to +1.1 V, VCM = 0.0 V; calibration
points at 0x2666 (−1 V) and 0x599A (+1 V)
+7
Uncertainty Band
7
CB
VDUTx = 0 V; sweep comparator threshold to determine
the uncertainty band
Rev. 0 | Page 10 of 80
ADATE318
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
Maximum Programmable
Hysteresis
117
mV
CB
Hysteresis Resolution
CMRR
5.6
5
mV
D
P
Calculated over hystersis control Code 10 to Code 31
−1
+1
mV/V
Offset measured at VCM = −1.5 V and +6.5 V with VDM = 0.0 V,
offset error change
DC PSRR
mV/V
CT
Measured at calibration points
AC SPECIFICATIONS
All ac specifications performed after dc level calibration,
unless noted; input transition time ~200 ps, 20% to 80%,
measured with 50 Ω to external termination voltage (VTTC),
peaking set to CLC = 2, unless otherwise specified
Propagation Delay,
Input to Output
0.83
2.6
15
ns
CB
CB
CB
CB
VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
Propagation Delay Tempco
ps/ºC
ps
VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
Propagation Delay Matching,
High Transition to Low
Transition
VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
Propagation Delay Matching,
High to Low Comparator
17
ps
VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
Propagation Delay Change
(Dispersion) With Respect To
Slew Rate:
400 ps and 1 ns
(20% to 80%)
31
32
ps
ps
CB
CB
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V, repeat for
other channel
Overdrive:
250 mV and 750 mV
VDUT0 = 0.0 V; for 250 mV: VDUT1: 0 V to 0.5 V swing; for
750 mV: VDUT1: 0 V to 1.0 V swing; driver term mode,
VIT = 0.0 V; comparator threshold = −0.25 V; repeat for
other channel with comparator threshold = +0.25 V
1 V Pulse Width:
0.7 ns, 1 ns, 5 ns, 10 ns
+1/−
21
ps
ps
ps
ns
CB
CB
CB
CB
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
repeat for other channel
0.5 V Pulse Width:
0.6 ns, 1 ns, 5 ns, 10 ns
+1/−
31
VDUT0 = 0.0 V; VDUT1: −0.25 V to +0.25 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
repeat for other channel
Duty Cycle:
5% to 95%
18
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
repeat for other channel
Minimum Detectable
Pulse Width
0.5
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
greater than 50% output differential amplitude; repeat for
other channel
Input Equivalent Bandwidth,
Terminated
1038
11
MHz
%
CB
CB
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V, CLC = 2 as
measured by shmoo; repeat for other channel
Comparator Pre-Emphasis (CLC)
CLC Amplitude Range
VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V;
comparator CLC set to maximum; repeat for other channel
CLC Resolution
1.6
4.8
% per bit
ns
CB
CB
3-bit amplitude control
Pre-Emphasis Time Constant
VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V;
comparator CLC set to maximum; repeat for other channel
Rev. 0 | Page 11 of 80
ADATE318
Table 6. Active Load
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
DC SPECIFICATIONS
Input Characteristics
Load active on, RCVx active, unless otherwise noted
VCOM Voltage Range
−1.5
V
V
D
D
| IOL and IOH | ≤ 1 mA
+6.5
−1.0
| IOL and IOH | ≤ 25 mA
+5.5
VCOM Offset
−200
mV
P
Measured at DAC Code 0x4000, uncalibrated
+200
VCOM Offset Tempco
VCOM Gain
25
ꢀV/°C
V/V
CT
P
1.0
1.1
Gain derived from measurements at DAC Code 0x4000 (0 V) and
DAC Code 0xC000 (+5 V), based on ideal DAC transfer function (see
Table 21)
VCOM Gain Tempco
VCOM Resolution
VCOM DNL
25
153
1
ppm/°C
ꢀV
CT
D
mV
CT
IOH = IOL = 12.5 mA; after two point gain/offset calibration;
measured over VCOM range of −1.5 V to +6.5 V; calibration points
at 0x4000 (0 V) and 0xC000 (+5 V)
VCOM INL
−7
−7
mV
mV
P
P
IOH = IOL = 12.5 mA; after two point gain/offset calibration;
measured at end points of VCOM functional range
+7
+7
DUTGND Voltage
Accuracy
2
Over 0.1 V range
Output Characteristics
Maximum Source
Current
25
mA
ꢀA
D
P
−1.5 V to +5.5 V DUT range
IOL Offset
−600
IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; offset extrapolated
from measurements at DAC Code 0x451F (1 mA) and DAC Code
0xA666 (20 mA)
+600
IOL Offset Tempco
IOL Gain Error
1
ꢀA/°C
%
CT
P
0
25
IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; gain derived from
measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666
(20 mA); based on ideal DAC transfer function (see Table 21 and
Table 22)
IOL Gain Tempco
IOL Resolution
IOL DNL
25
763
4
ppm/°C
nA
CT
D
ꢀA
CT
IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; after two point
gain/offset calibration; measured over IOL range, 0 mA to 25 mA;
calibrated at Code 0x451F (1 mA) and Code 0xA666 (20 mA)
IOL INL
−100
20
ꢀA
V
P
P
IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; after two point
gain/offset calibration
+100
IOL 90% Commutation
Voltage
0.25
0.4
IOH = IOL = 25 mA, VCOM = 2.0 V; measure IOL reference at
VDUTx = −1.0 V; measure IOL current at VDUTx = 1.6 V; check
>90% of reference current
IOL 90% Commutation
Voltage
0.1
V
CT
IOH = IOL = 1 mA, VCOM = 2.0 V; measure IOL reference at
VDUTx = −1.0 V; measure IOL current at VDUTx = 1.9 V; check
>90% of reference current
Maximum Sink Current
IOH Offset
25
mA
ꢀA
D
P
−1.0 V to +6.5 V output range
−600
IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; offset extrapolated
from measurements at DAC Code 0x451F (1 mA) and DAC Code
0xA666 (20 mA)
+600
IOH Offset Tempco
IOH Gain Error
1
ꢀA/°C
%
CT
P
0
25
IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; gain derived from
measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666
(20 mA); based on ideal DAC transfer function (see Table 21 and
Table 22)
Rev. 0 | Page 12 of 80
ADATE318
Test
Level
Parameter
IOH Gain Tempco
Min
Typ
25
Max
Unit
ppm/°C
nA
Conditions
CT
D
IOH Resolution
IOH DNL
763
4
ꢀA
CT
IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; after two point
gain/offset calibration; measured over IOH range, 0 mA to 25 mA;
calibrated at Code 0x451F (1 mA) and Code 0xA666 (20 mA)
IOH INL
−100
25
ꢀA
V
P
P
IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; after two point
gain/offset calibration
+100
IOH 90% Commutation
Voltage
0.25
0.4
IOH = IOL = 25 mA, VCOM = 2.0 V; measure IOH reference at
VDUTx = 5.0 V; measure IOH current at VDUTx = 2.4 V; ensure >90%
of reference current
0.1
V
CT
IOH = IOL = 1 mA, VCOM = 2.0 V; measure IOH reference at
VDUTx = 5.0 V; measure IOH current at VDUTx = 2.1 V; ensure >90%
of reference current
AC SPECIFICATIONS
All ac specifications performed after dc level calibration unless
noted; load active on
Dynamic Performance
Propagation Delay, Load
Active On to Load
Active Off; 50%, 90%
3.1
4.1
ns
ns
ns
CB
CB
Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA,
VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH;
RCVx
measured from 50% point of RCVx −
to 90% point of final
output; repeat for drive low and drive high
Propagation Delay, Load
Active Off to Load
Active On; 50%, 90%
Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA,
VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH;
RCVx
measured from 50% point of RCVx −
to 90% point of final
output; repeat for drive low and drive high
Propagation Delay
Matching
1.0
106
1.6
CB
CB
CB
Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA,
VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH;
active on vs. active off; repeat for drive low and drive high
Load Spike
mV pk-
pk
Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 0 mA,
VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; repeat
for drive low and drive high
Settling Time to 90%
ns
Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA,
VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH;
measured at 90% of final value
Table 7. PPMU (PPMU Enabled in FV, DCL Disabled)
Test
Parameter
Min
Typ
Max
Unit
Level Conditions
FORCE VOLTAGE
Current Range A
Current Range B
Current Range C
Current Range D
Current Range E
Voltage Range at Output
Range A
−40
−1
mA
mA
ꢀA
ꢀA
ꢀA
D
D
D
D
D
+40
+1
−100
−10
−2
+100
+10
+2
−2.0
−2.0
−2.0
V
V
V
D
D
D
Output range for full-scale source and sink.
+5.75
+6
Output range for 25 mA.
Range B, Range C, Range D, and
Range E
Output range for full-scale source and sink.
+6.5
Offset
Range C
−100
mV
P
Measured at DAC Code 0x4000 (0 V).
Measured at DAC Code 0x4000 (0 V).
+100
All Ranges
10
25
mV
CT
CT
Offset Tempco, All Ranges
ꢀV/°C
Rev. 0 | Page 13 of 80
ADATE318
Test
Parameter
Gain
Min
Typ
Max
Unit
Level Conditions
Range C
1.0
1.1
V/V
P
Gain derived from measurements at DAC
Code 0x4000 (0 V) and DAC Code 0xC000
(5 V); based on ideal DAC transfer function
(see Table 21 and Table 23).
All Ranges
1.05
25
V/V
CT
CT
Gain derived from measurements at DAC
Code 0x4000 (0 V) and DAC Code 0xC000
(5 V); based on ideal DAC transfer function
(see Table 21 and Table 23).
Gain Tempco, All Ranges
ppm/°C
Gain derived from measurements at DAC
Code 0x4000 (0V) and DAC Code 0xC000
(5 V); calibration point 0x4000 (0 V) and
0xC000 (+5 V) output.
INL
Range A
1
mV
CT
After two point gain/offset calibration, output
range of −2.0 V to +5.75 V, PPMU Current
Range A only.
Range C
−1.7
mV
mV
P
After two point gain/offset calibration;
output range of −2.0 V to +6.5 V.
+1.7
Range B, Range D, and Range E
1
CT
After two point gain/offset calibration, output
range of −2.0 V to +6.5 V.
Compliance vs. Current Load
Range A
40
mV
mV
mV
%FS
CT
CT
CT
P
Force −2.0 V; measure voltage while sinking
zero and full-scale current; measure ΔV; force
+5.75 V; measure voltage while sourcing zero
and full-scale current; measure ΔV.
25
1
Force −2.0 V; measure voltage while sinking
zero and 25 mA current; measure ΔV; force
+6 V; measure voltage while sourcing zero
and 25 mA current; measure ΔV.
Range B, Range C, Range D, and
Range E
Force −2.0 V; measure voltage while sinking
zero and full-scale current; measure ΔV; force
+6.5 V; measure voltage while sourcing zero
and full-scale current; measure ΔV.
Current Limit, Source and Sink
All Ranges
120
140
180
Sink: force −2.0 V, short DUTx to +6.5 V;
source: force +6.5 V, short DUTx to −2.0 V;
repeat for each current range; example:
Range A
FS = 40 mA,
120% FS = 48 mA
180% FS = 72 mA
DUTGND Voltage Accuracy
−7
2
mV
P
Over 0.1 V range; measured at endpoints
of PPMU_VINFV functional range (see
Figure 136).
+7
MEASURE CURRENT
PPMU enabled in FIMI, DCL disabled.
DUTx Pin Voltage Range at Full Current
Range A
−2.0
−2.0
+5.75
+6.5
V
V
D
D
Range B, Range C, Range D, and
Range E
Zero-Current Offset, Range B
−2
2
%FSR
P
Interpolated from measurements sourcing
and sinking 80% FSR current each range;
FSR = 80 mA for Range A, 2 mA for Range B,
200 ꢀA for Range C, 20 ꢀA for Range D, 4 ꢀA
for Range E (see Table 21and Table 23).
All Ranges
0.5
%FSR
CT
CT
See Table 21and Table 23.
See Table 21 and Table 23.
Zero-Current Offset Tempco, Range A
0.001
%FSR/°C
Rev. 0 | Page 14 of 80
ADATE318
Test
Parameter
Range B, Range C, and Range D
Min
Typ
0.001
Max
Unit
Level Conditions
%FSR/°C
CT
CT
Range E
0.002
%FSR/°C
Gain Error
Range B
−30
%
%
P
Based on measurements sourcing and
sinking, 80% FSR current.
+5
All Ranges
−10
CT
Based on measurements sourcing and
sinking, 80% FSR current.
Gain Tempco
Range A
50
25
ppm/°C
ppm/°C
CT
CT
Range B, Range C, Range D, and
Range E
INL
Range A
0.0125
0.01
2
%FSR
%FSR
%FSR
ꢀA
CT
P
Range A, after two point gain/offset
calibration at 80% FSR current; measured
over FSR output of −40 mA to +40 mA.
Range B
−0.03
+0.03
After two point gain/offset calibration at
80% FSR current; measured over FSR output
of −1 mA to +1 mA.
Range C, Range D, and Range E
DUTx Pin Voltage Rejection
DUTGND Voltage Accuracy
CT
P
After two point gain/offset calibration at
80% FSR current; measured over each FSR
output for Range C, Range D, and Range E.
−1.2
−7
Range B, FVMI, force −1 V and 5 V into load of
0.5 mA, measure ΔI reported at PPMU_MEASx
pin.
+1.2
+7
mV
P
Over 0.1 V range (see Figure 136).
FORCE CURRENT
PPMU enabled in FIMI, DCL disabled.
At full-scale source and sink current.
At 25 mA source and sink current.
DUTx Pin Voltage Range in Range A
−2.0
−2.0
−2.0
V
V
V
D
D
D
+5.75
+6
DUTx Pin Voltage Range at Full Current,
Range B, Range C, Range D, and
Range E
+6.5
Zero-Current Offset, All Ranges
−14.5
−5
%FSR
P
Extrapolated from measurements at Code
0x4CCC and Code 0xB333 for each range (see
Table 21and Table 23).
+14.5
+25
Zero-Current Offset Tempco
Gain Error, All Ranges
0.002
%FSR/°C
%
CT
P
Derived from measurements at Code 0x4CCC
and Code 0xB333 for each range (see
Table 21 and Table 23).
Gain Tempco
Range A
50
25
ppm/°C
ppm/°C
CT
CT
Significant PPMU self-heating effects in
Range A can influence gain drift/tempco
measurements.
Range B, Range C, Range D, and
Range E
INL
Range A
−0.12
−0.03
0.02
+0.12
+0.03
%FSR
%FSR
P
P
After two point gain/offset calibration;
measured over FSR output of −40 mA to
+40 mA.
Range B, Range C, and Range D
After two point gain/offset calibration;
measured over FSR output; repeat for
Range B, Range C, and Range D.
Rev. 0 | Page 15 of 80
ADATE318
Test
Parameter
Min
Typ
Max
Unit
Level Conditions
Range E
−0.045
+0.045
%FSR
P
After two point gain/offset calibration;
measured over FSR output.
Force Current Compliance vs. Voltage
Load
Range A
−0.3
+0.3
%FSR
P
Force positive full-scale current driving
−2.0 V and +5.75 V; measure ΔI at DUTx pin;
force negative full-scale current driving
−2.0 V and +5.75 V; measure ΔI at DUTx pin.
−0.3
+0.3
%FSR
%FSR
P
P
Force +25 mA driving −2.0 V and +6.0 V;
measure ΔI at DUTx pin; force −25 mA driving
−2.0 V and +6.0 V; measure ΔI at DUTx pin.
−0.06
+0.06
Force positive full-scale current driving
0.0 V and +4.0 V; measure ΔI at DUTx pin;
force negative full-scale current driving
0.0 V and +4.0 V; measure ΔI at DUTx pin.
Range B and Range C
−0.3
−0.06
−0.3
+0.3
+0.06
+0.3
%FSR
%FSR
%FSR
P
P
P
Force positive full-scale current driving
−2.0 V and +6.5 V; measure ΔI at DUTx pin;
force negative full-scale current driving
−2.0 V and +6.5 V; measure ΔI at DUTx pin.
Force positive full-scale current driving
0.0 V and +4.0 V; measure ΔI at DUTx pin;
force negative full-scale current driving
0.0 V and +4.0 V; measure ΔI at DUTx pin.
Range D
Range E
Force positive full-scale current driving
−2.0 V and +6.5 V; measure ΔI at DUTx pin;
force negative full-scale current driving
−2.0 V and +6.5 V; measure ΔI at DUTx pin;
allows for 10 nA of DUTx pin leakage.
−0.85
+0.85
%FSR
P
Force positive full-scale current driving
−2.0 V and +6.5 V; measure ΔI at DUTx pin;
force negative full-scale current driving −2.0 V
and +6.5 V; measure ΔI at DUTx pin; allows for
10 nA of DUTx pin leakage.
MEASURE VOLTAGE
Voltage Range
Offset
PPMU enabled, FVMV, DCL disabled.
−2.0
−25
+6.5
+25
V
D
P
mV
Range B, VDUTx = 0 V; offset = (PPMU_MEAS
− VDUTx).
Offset Tempco
Gain
10
1
ꢀV/°C
V/V
CT
P
0.98
1.02
Range B, gain derived from measurements at
VDUTx = 0.0 V and +5.0 V.
Gain Tempco
ppm/°C
mV
CT
P
INL
−1.7
−2.0
+1.7
Range B, measured over −2.0 V to +6.5 V.
Measure Pin DC Characteristics
Output Range
V
D
D
P
+6.5
4
DC Output Current
Output Impedance
mA
Ω
200
PPMU enabled in FVMV, DCL disabled;
Source resistance:
PPMU force +6.5 V with 0 mA, +4 mA load
Sink resistance:
PPMU force −2.0 V with 0 mA, −4 mA load
Resistance = ΔV/ΔI at PPMU_MEAS pin.
Output Leakage Current When
Tristated
−1
ꢀA
P
+1
Tested at −2.0 V and +6.5 V.
Rev. 0 | Page 16 of 80
ADATE318
Test
Parameter
Output Short-Circuit Current
Min
Typ
Max
Unit
Level Conditions
−25
mA
P
PPMU enabled in FVMV, DCL disabled;
Source:
PPMU force +6.5 V, PPMU_MEAS to −2.0 V
Sink:
+25
PPMU force −2.0 V, PPMU_MEAS to +6.5 V
PPMU_MEASx Pin, Output
Capacitance
2
pF
pF
S
S
PPMU_MEASx Pin, Load Capacitance
100
Maximum load capacitance.
VOLTAGE CLAMPS
PPMU enabled in FIMI, DCL disabled, PPMU
clamps enabled; clamp accuracy specifica-
tions apply only when VCH > VCL.
Low Clamp Range (VCL)
−2.0
0.0
V
D
D
P
+4.0
+6.5
+300
High Clamp Range (VCH)
Positive Clamp Voltage Droop
V
−300
1
1
mV
ΔV seen at DUTx pin, Range A, VCH = +5.0 V,
VCL = −1 V; PPMU force 5 mA and 40 mA into
open.
Negative Clamp Voltage Droop
Offset, PPMU Clamp VCH/VCL
−300
−300
mV
mV
P
P
+300
+300
ΔV seen at DUTx pin, Range A, VCH = +5.0 V,
VCL = −1 V, PPMU force −5 mA and 40 mA
into open.
Range B, PPMU force 0.5 mA into open; VCH
measured at DAC Code 0x4000 (0 V) with VCL
at Code 0x0000 (−2.5 V); VCL measured at
DAC Code 0x4000 (0 V) with VCH at 0xFFFF
(+7.5 V).
Offset Tempco, PPMU Clamp VCH/VCL
Gain, PPMU Clamp VCH/VCL
0.5
mV/°C
V/V
CT
P
1.0
1.2
Range B, PPMU force 0.5 mA into open; VCH
gain derived from measurements at DAC
Code 0x4000 (0 V) and DAC Code 0xC000
(+5.0 V) with VCL at Code 0x0000 (−2.5 V); VCL
gain derived from measurements at DAC
Code 0x4000 (0 V) and DAC Code 0xA666
(+4.0 V) with VCH at 0xFFFF (+7.5 V).
Gain Tempco, PPMU Clamp VCH/VCL
INL, PPMU Clamp VCH/VCL
25
2
ppm/°C
mV
CT
P
−20
−7
Range B, PPMU force 0.5 mA into open,
after two point gain/offset calibration;
measured over PPMU clamp functional range.
+20
+7
DUTGND Voltage Accuracy
SETTLING/SWITCHING TIMES
mV
P
Over 0.1 V range; measured at end points of
clamp functional range.
Force Voltage Settling Time to 0.1% of
Final Value
Range A,
200 pF and 2000 pF Load
10
12
32
ꢀs
ꢀs
ꢀs
S
S
S
PPMU enabled in FV, Range A, DCL disabled;
program VIN steps from 0 V to 0.5 V and 5.0 V.
Range B,
200 pF and 2000 pF Load
PPMU enabled in FV, Range B, DCL disabled;
program VIN steps from 0 V to 0.5 V and 5.0 V.
Range C,
200 pF and 2000 pF Load
PPMU enabled in FV, Range C, DCL disabled;
program VIN steps from 0 V to 0.5 V and 5.0 V.
Force Voltage Settling Time to 1.0% of
Final Value
Range A,
200 pF & 2000 pf Load
8.1
8.1
8.1
ꢀs
ꢀs
ꢀs
CB
CB
CB
PPMU enabled in FV, Range A, DCL disabled;
program VIN steps from 0 V to 5.0 V.
Range B,
200 pF and 2000 pf Load
PPMU enabled in FV, Range B, DCL disabled;
program VIN steps from 0 V to 5.0 V.
Range C,
200 pF and 2000 pf Load
PPMU enabled in FV, Range C, DCL disabled;
program VIN steps from 0 V to 5.0 V.
Rev. 0 | Page 17 of 80
ADATE318
Test
Parameter
Min
Typ
Max
Unit
Level Conditions
Range A,
200 pF and 2000 pf Load
2.5
ꢀs
CB
CB
CB
PPMU enabled in FV, Range A, DCL disabled;
program VIN steps from 0 V to 0.5 V.
Range B,
6.3
8.1
ꢀs
ꢀs
PPMU enabled in FV, Range B, DCL disabled;
program VIN steps from 0 V to 0.5 V.
200 pF and 2000 pf Load
Range C,
PPMU enabled in FV, Range C, DCL disabled;
program VIN steps from 0 V to 0.5 V.
200 pF and 2000 pf Load
Force Current Settling Time to 0.1% of
Final Value
Range A,
200 pF in Parallel with 120 Ω
16
10
40
ꢀs
ꢀs
ꢀs
S
S
S
PPMU enabled in FI, Range A, DCL disabled;
program VIN step of 0 mA to 40 mA.
Range B,
200 pF in Parallel with 1.5 KΩ
PPMU enabled in FI, Range B, DCL disabled;
program VIN step of 0 mA to 1 mA.
Range C,
200 pF in Parallel with 15.0 KΩ
PPMU enabled in FI, Range C, DCL disabled;
program VIN step of 0 mA to 100 μA.
Force Current Settling Time to 1.0% of
Final Value
Range A,
200 pF in Parallel with 120 Ω
8.1
7.5
8.1
ꢀs
ꢀs
ꢀs
CB
CB
CB
PPMU enabled in FI, Range A, DCL disabled;
program VIN step of 0 mA to 40 mA.
Range B,
200 pF in Parallel with 1.5 KΩ
PPMU enabled in FI, Range B, DCL disabled;
program VIN step of 0 mA to 1 mA.
Range C,
200 pF in Parallel with 15.0 KΩ
PPMU enabled in FI, Range C, DCL disabled;
program VIN step of 0 mA to 100 μA.
INTERACTION and CROSSTALK
Measure Voltage Channel-to-Channel
Crosstalk
0.01
%FSR
%FSR
CT
0.01% × 8.5 V = 0.85 mV, PPMU enabled in
FIMV, DCL disabled; CHx under test: Range B,
forcing 0 mA into 0 V load; other channel:
Range A, sweep 0 mA to 40 mA into 0 V load;
report ΔV of PPMU_MEASx pin under test.
Measure Current Channel-to-Channel
Crosstalk
0.01
CT
0.01% × 5.0 V = 0.5 mV, PPMU enabled in
FVMI, DCL disabled; CHx under test: Range E,
forcing 0 V into 0 mA current load; other
channel: Range E, sweep −2.0 V to +6.5 V into
0 mA current load; report ΔV of PPMU_MEASx
pin under test.
Table 8. PPMU_Go/No-Go Comparators
Test
Level
Parameter
Min
Typ
Max
+6.5
+250
Unit
V
Conditions
Compare Voltage Range
Input Offset Voltage
Input Offset Voltage Tempco
Gain
−2.0
D
P
−250
mV
Measured at DAC Code 0x4000 (0 V)
50
μV/ºC
V/V
CT
P
1.0
1.1
Gain derived from measurements at DAC
Code 0x4000 (0 V) and DAC Code 0xC000
(+5.0 V)
Gain Tempco
25
153
1
ppm/ºC
ꢀV
CT
D
Applies at m = 1.0 and c = 0.0
Comparator Threshold Resolution
Comparator Threshold DNL
mV
CT
After two point gain/offset calibration;
measured over VOH/VOL range − 2.0 V to
+6.5 V; calibration points at 0x4000 (0 V) and
0xC000 (+5 V)
Comparator Threshold INL
DUTGND Voltage Accuracy
−7
−7
mV
mV
P
P
After two point gain/offset calibration;
measured at end points of VOH and VOL
functional range
+7
+7
2
Over 0.1 V range
Rev. 0 | Page 18 of 80
ADATE318
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
Comparator Uncertainty Band
1.6
mV
CB
Sweep comparator threshold to determine
uncertainty (oscillation) band
DC Hysteresis
<1
mV
CB
Sweep comparator threshold
COMPARATOR OUTPUTS
Output Logic High
PPMU_CMPHx, PPMU_CMPLx
VDD/4
− 0.5
VDD/4
+ 0.5
V
V
PF
PF
Sourcing 100 μA
Output Logic Low
0
0.5
Sinking 100 μA
Table 9. PPMU_Sense Pin
Test
Level
Parameter
Min
Typ
Max
Unit
Condition
PMU_Sx (SYSTEM PMU)
SENSE PIN CHARACTERISTICS
Voltage Range
−2.0
+7.0
2.5
V
D
P
DCL high-Z compliance range is −2.0 V to
+7.0 V
Ext Sense Switch RON
kΩ
Push 0.5 mA into PMU_Sx with switch closed
and DUTx pin at 0 V; calculate R = V/0.0005
Leakage
−2
+2
nA
pF
P
S
Tested at −2.0 V and +7.0 V, switch open
Switch open
Pin Capacitance (PMU_Sx)
0.5
PPMU_Sx (INTERNAL PPMU)
SENSE PIN CHARACTERISTICS
Voltage Range
Leakage
−2.0
−2
V
D
P
S
PPMU input select in all states
+6.5
+2
nA
nF
Tested at −2.0 V and +6.5 V
Max Load Capacitance
2
RST CS
BUSY
)
Table 10. Serial Programmable Interface (SPI) (SDI,
,
, SCLK, SDO,
Test
Level
Parameter
Min
Typ
Max
Unit
Condition
Input Logic High
1.8
VCC
V
PF
RST CS
SDI, , , SCLK.
Input Logic Low
0
0.7
V
PF
Input Bias Current
−10
0.5
1
ꢀA
P
Tested at 0.0 V and VCC volts.
+10
SCLK Clock Rate
50
MHz
ns
D
SCLK Pulse Width, Minimum
SCLK Crosstalk on DUTx Pin
9
CT
CB
30
mV
DCL disabled; PPMU FV enabled and forcing
0.0 V.
Serial Output Logic High
Serial Output Logic Low
VCC − 0.5
VCC
0.5
V
V
V
PF
PF
D
SDO; sourcing 2 mA.
Sinking 2 mA.
0
BUSY
2.3
2.5
0.2
3.5
BUSY
Pull-Up Voltage
is an open drain output that pulls low
when the SPI requires additional SCLK cycles.
BUSY
0.8
V
PF
BUSY
active, sinking 2 mA.
Active Voltage
Rev. 0 | Page 19 of 80
ADATE318
Table 11. VHH Driver (VHH Mode Enabled, RCV Active)
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
VHH BUFFER
Voltage Range
Output High
Output Low
VHH mode enabled, RCVx active
0.0
13.5
V
D
P
P
P
13.5
V
VHH level = full scale, sourcing 15 mA
VHH level = zero-scale, sinking 15 mA
5.9
V
Extrapolated Offset
−500
mV
Extrapolated from measurements at DAC
Code 0x8000 (+7 V) and DAC Code 0xC000
(+12 V)
+500
Extrapolated Offset Tempco
Gain
0.5
mV/ºC
V/V
CT
P
2
2.2
Gain derived from measurements at DAC
Code 0x8000 (+7 V) and DAC Code 0xC000
(+12 V); based on ideal DAC transfer function
(see Table 21)
Gain Tempco
Resolution
INL
25
ppm/ºC
ꢀV
CT
D
P
305
−25
mV
VHH mode enabled, RCVx active; after two
point gain/offset calibration; measured over
+5.9 V to +13.5 V; calibrate at Code 0x8000
(+7 V) and Code 0xC000 (+12 V)
+25
DUTGND Voltage Accuracy
Output Resistance
4
mV
Ω
CT
P
Over 0.1 V range; measured at end points of
VHH functional range
10
ΔV/ΔI; VHH mode enabled, RCVx active;
Source: VHH = +10.0 V, I = 0 mA, +15 mA
Sink: VHH = +6.5 V, I = 0 mA, −15 mA
DC Output Current Limit Source
DC Output Current Limit Sink
mA
mA
ns
P
VHH mode enabled, RCVx active; VHH = +13.5 V,
short HVOUT pin to +5.9 V, measure current
+60
+100
−100
−60
P
VHH mode enabled, RCVx active, VHH = 5.9 V,
short HVOUT pin to 13.5 V, measure current
VHH Rise Time
(from VIL or VIH to VHH)
163
30
CB
20% to 80%, VHH mode enabled, toggle RCVx:
VHH = 13.5 V, VIL = 0.0 V, VIH = 3.0 V, DATx =
high; VHH = 13.5 V, VIL = 3.0 V, VIH = 4.0 V,
DATx = low
VHH Fall Time
(from VHH to VIL or VIH)
ns
CB
CB
20% to 80%, VHH mode enabled, toggle RCVx;
VHH = 13.5 V, VIL = 0.0 V, VIH = 3.0 V, DATx =
high; VHH = 13.5 V, VIL = 3.0 V, VIH = 4.0 V,
DATx = low
Preshoot, Overshoot, and Undershoot
40.0
mV
VHH mode enabled, toggle RCVx; VHH =
13.5 V, VIL = 0.0 V, VIH = 3.0 V, DATx = high;
VHH = 13.5 V, VIL = 3.0 V, VIH = 4.0 V, DATx =
low
VIL/VIH DRIVE FUNCTION
Voltage Range
VHH mode enabled, RCVx inactive
−0.1
V
D
P
+6.5
Offset Voltage
−500
mV
Measured at DAC Code 0x4000 (0 V), for DATx
= high and DATx = low
+500
Offset Voltage Tempco
Gain
1
mV/ºC
V/V
CT
P
1.0
1.1
Gain derived from measurements at DAC
Code 0x4000 (0 V) and DAC Code 0xC000 (5 V);
based on ideal DAC transfer function (see
Table 21)
Gain Tempco
Resolution
INL
75
153
ppm/ºC
ꢀV
CT
D
P
−20
mV
VHH mode enabled, RCVx inactive; after two
point gain/offset calibration; measured over
−0.1 V to +6.0 V; calibrate at Code 0x4000 (0 V)
and Code 0xC000 (+5.0 V)
+20
Rev. 0 | Page 20 of 80
ADATE318
Test
Level
Parameter
Min
Typ
Max
Unit
Conditions
DUTGND Voltage Accuracy
2
mV
CT
Over 0.1 V range; measured at end points of
VIH and VIL functional range
Output Resistance
46
48
50
Ω
P
ΔV/ΔI; VHH mode enabled, RCVx inactive;
Source: VIH = +3.0 V, I = +1 mA, +50 mA;
Sink: VIL = +2.0 V; I = −1 mA, −50 mA
DC Output Current Limit Source
DC Output Current Limit Sink
Rise Time, VIL to VIH
60
100
−60
mA
mA
ns
P
VHH mode enabled, RCVx inactive,
VIH = +6.0 V, short HVOUT pin to −0.1 V,
DATx high, measure current
−100
P
VHH mode enabled, RCVx inactive,
VIL = −0.1 V, short HVOUT pin to +6.0 V,
DATx low, measure current
6.4
7.3
30
CB
CB
CB
20% to 80%, VHH mode enabled, RCVx
inactive, VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω,
toggle DATx
Fall Time, VIH to VIL
ns
20% to 80%, VHH mode enabled, RCVx
inactive, VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω,
toggle DATx
Preshoot, Overshoot, and Undershoot
mV
VHH mode enabled, RCVx inactive,
VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω,
toggle DATx
Table 12. Alarm Functions
Test
Parameter
Min
Typ
Max
Unit
Level
Condition
DC CHARACTERISTICS
Overvoltage Detect (OVD)
Programmable Voltage Range
See Figure 137
V
D
P
−2.5
+7.5
mV
Uncalibrated Error at −2.0 V
−200
+200
Measured at DAC Code 0x0CCC (−2.0 V); OVD comparators not
guaranteed to function as specified if VDUTx is outside
absolute maximum voltage range
mV
P
Uncalibrated Error at +7.0 V
−450
+450
Measured at DAC Code 0xF333 (+7.0 V)
Offset Voltage Tempco
0.5
mV/°C CT
Gain derived from measurements at DAC Code 0x4000 and
DAC Code 0xC000
Gain
1.045
125
V/V
mV
CT
CT
Hysteresis
Thermal Alarm
Setpoint Error
Thermal Hysteresis
PPMU Clamp Alarm
See Figure 137
10
°C
°C
CT
CT
Relative to default value, 100°C
−15
See Figure 137 and Table 29 for electrical characteristics
ALARM
Output Characteristics
Off State Leakage
10
500
0.7
nA
V
P
ALARM
Disable alarm, apply 2.5 V to
current
pin, measure leakage
Max On Voltage at100 ꢀA
Propagation Delay
0.1
1.5
P
ALARM
Activate alarm, force 100 ꢀA into
alarm voltage
pin, measure active
ꢀs
CB
For OVD_HI:
VDUTx: 0 V to 6 V swing,
OVDH = +3.0 V, OVDL = −1.0 V
For OVD_LO:
VDUTx: 0 V to 6 V swing,
OVDH = +7.0 V, OVDL= +3.0 V
Rev. 0 | Page 21 of 80
ADATE318
SPI TIMING DETAILS
SCLK
tCH
tCSAM
0
1
2
3
4
5
6
7
8
9
10
11
tCL
24
25
0
1
2
3
4
5
6
7
tCSRS
tCSAS
CS
tCSAH
tCSRH
tDS
SDI
C1 C0 A6 A5 A4 A3 A2 A1 A0
D15 D14
D1 D0
C1 C0 A6 A5 A4 A3 A2 A1
R/W
tCSZ
tCSO
tDH
tDO
NOTE 1
SDO
NOTE 1
C1 C0 A6 A5 A4 A3 A2 A1 A0
D15 D14
D1
D0
C1 C0 A6 A4 A3 A2 A1 A0
R/W
tBUSA
tBUSR
BUSY
SEE TABLE 18
tBUSW
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE
FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE
SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.
Figure 2. SPI Detailed Read/Write Timing Diagram
SCLK
CS
CH[1:0]
ADDR[6:0]
DATA[15:0]
SDI
W
NOTE 1
NOTE 1
ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI
FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18)
SDO
SEE TABLE 18
BUSY
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE
FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE
SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.
Figure 3. SPI Write Instruction
Rev. 0 | Page 22 of 80
ADATE318
tCH
SCLK
tCL
tRMIN
tRS
RST
ASYNCHRONOUS
ASSERT
tBUSA
tBUSR
BUSY
tBUSW
3µs
SEE TABLE 18
(DAC DEGLITCH)
V
DAC
0
PREVIOUS CODE
PREVIOUS CODE
DEFAULT DAC CODE
DUTGND
0
V
DAC
1
DEFAULT DAC CODE
1
DUTGND
DAC
23
V
DEFAULT DAC CODE
23
PREVIOUS CODE
DUTGND
RESET
CONDITION
INITIALIZED
CONDITION
Figure 4. SPI Detailed Hardware Reset Timing Diagram
Rev. 0 | Page 23 of 80
ADATE318
tCH
SCLK
tCL
CS
SDI
SPI RESET
tBUSA
tBUSR
BUSY
tBUSW
SEE TABLE 18
3µs
(DAC DEGLITCH)
V
V
DEFAULT DAC CODE
0
PREVIOUS CODE
PREVIOUS CODE
DAC
DAC
DUTGND
0
1
DEFAULT DAC CODE
1
DUTGND
DEFAULT DAC CODE
23
V
DAC
PREVIOUS CODE
DUTGND
23
RESET
CONDITION
INITIALIZED
CONDITION
Figure 5. SPI Detailed Software Reset Timing Diagram
SCLK
CS
CH[1:0]
ADDR[6:0]
DATA[15:0] = DON’T CARE
SDI
R
NOTE 1
NOTE 1
ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI
FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18)
SDO
BUSY
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THEASSERTION
OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN ALWAYS
REMAINS ACTIVE INDEPENDENT OF CS.
Figure 6. SPI Read Request Instruction (Prior to Readout)
Rev. 0 | Page 24 of 80
ADATE318
SCLK
CS
SDI
CH[1:0] ADDR[6:0] (COULD BE NOP) R/W
NOTE 2
DATA[15:0] = (IF NOP, THEN DON’T CARE)
READ OUT DATA[15:0]
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
SDO
NOTE 1
CH[1:0]
ADDR[6:0]
0
NOTE 1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
BUSY
SEE TABLE 18
NOTES
1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION
OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS
ACTIVE INDEPENDENT OF CS.
2. THE FIRST 10 BITS OF SDO FOLLOWING A READ REQUEST ECHO ADDRESS AND CHANNEL BITS OF THE PRECEDING REQUEST.
THE R/W BIT POSITION IS SET LOW. THE FOLLOWING 16 BITS CONTAIN DATA FROM THE REQUESTED ADDRESS AND CHANNEL.
Figure 7. SPI Readout Instruction (Subsequent to Read Request)
Rev. 0 | Page 25 of 80
ADATE318
Table 13. SPI Detailed Timing Requirements
Test
Level
Parameter Min
Max
Unit
MHz
ns
ns
ns
Description
fCLK
tCH
0.5
9
50
CT
CT
CT
CT
CT
CT
CT
CT
SCLK operating frequency.
SCLK high time.
SCLK low time.
Setup of CS to rising SCLK at assert.
Hold of CS to rising SCLK at assert.
Setup of CS to rising SCLK at release.
Hold of CS to rising SCLK at release.
tCL
9
tCSAS
tCSAH
tCSRS
tCSRH
3
3
ns
3
ns
3
ns
4
ns
Hold of CS release prior to rising SCLK. This parameter is critical only if the number
of SCLK cycles from the previous release of CS is the minimum specified by the
tCSAM parameter.
tCSO
tCSZ
6
ns
ns
CT
CT
Delay from CS assert to SDO active.
10
Delay from CS release to SDO high-Z, depends greatly on external pin loading.
tCSAM
3
Cycles CT
Width of CS release between consecutive assertions of CS. This parameter is
specified in units of SCLK cycles, more specifically in terms of rising edges of the
SCLK input.
tDS
tDH
tDO
tBUSA
3
4
ns
ns
ns
ns
CT
CT
CT
CT
Setup of SDI data prior to rising SCLK.
Hold of SDI data following rising SCLK.
Delay of SDO data from rising SCLK.
Delay of BUSY assert from first rising SCLK following a valid CS release or an
asynchronous RSTb release.
12
12
tBUSW
3
26
Cycles CT
Width of BUSY assert. To ensure proper SPI operation, the SCLK must be provided
for as long as BUSY remains asserted. Note that the number of SCLK cycles within
any BUSY period is variable but deterministic and is based on the previous SPI
write instruction type. See the Use of the SPI BUSY Pin section and Figure 3,
Figure 6, Figure 8, and Table 18 for more information.
tBUSR
12
ns
CT
Delay of BUSY release from first rising SCLK, satisfying the requirements detailed in
the Use of the SPI BUSY Pin section.
tRMIN
tRS
10
3
ns
ns
CT
CT
Width of asynchronous RST assert.
Setup of RST to rising SCLK at release.
tSPI
29
Cycles CT
Number of SCLK rising edge cycles per SPI word write plus the additional tCSAM
requirement.
tDAC
5
10
μs
S
Settling time of analog DAC levels to ±0.5 LSB relative to the beginning of the DAC
deglitch period, which begins x SCLK cycles following the release of CS and four
SCLK cycles prior to the release of the BUSY pin. The number of SCLK cycles, x, is
defined by Table 18. Also see Figure 124 for more information.
Rev. 0 | Page 26 of 80
ADATE318
ABSOLUTE MAXIMUM RATINGS
Table 14. Absolute Maximum Ratings
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltages
Positive Supply Voltage (VDD to PGND) −0.5 V to +11.0 V
Positive VCC Supply Voltage (VCC to
DGND)
−0.5 V to +4.0 V
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Negative Supply Voltage (VSS to PGND) −6.5 V to +0.5 V
Supply Voltage Difference (VDD to VSS) −1.0 V to +17.0 V
Reference Ground (DUTGND to AGND)
−0.5 V to +0.5 V
Table 15. Thermal Resistance
VPLUS Supply Voltage (VPLUS to PGND) −0.5 V to +19.0 V
Package Type
θJA
θJC
Unit
m/s
Supply Sequence or Dropout
Condition1
Input/Output Voltages
Airflow
0
1
2
LFCSP
45
40
37
1
°C/W
Analog Input Common-Mode
Voltage
VSS to VDD
Table 16. Explanation of Test Levels
Test Level
Description
DUTx Output Short Circuit Voltage2
−3.0 V to +8.0 V
−0.5 V to VTTC + 0.5 V
D
S
P
Definition
Design verification simulation
100% production tested
High Speed Input Voltage Absolute
Range3
High Speed Differential Input
Voltage3
DUTx I/O Pin Current
DCL Maximum Short-Circuit Current4
−1.0 V to +1.0 V
140 mA
PF
CT
CB
Functionally checked during production test
Characterized on tester
Characterized on bench
Temperature
Operating Temperature, Junction
Storage Temperature Range
1 No supply should exceed the given ratings.
125°C
ESD CAUTION
−65°C to +150°C
2 RLOAD = 0 Ω, VDUTx continuous short-circuit condition (VIH, VIL, VIT),
high-Z, VCOM, and clamp modes).
3
DAT
RCV
DAT,
, RCV,
, RSOURCE = 0 Ω.
4 RLOAD = 0 Ω, VDUTx = −3 V to +8 V; DCL current limit. Continuous short-circuit
condition. ADATE318 current limits and survives a continuous short-circuit
fault.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Rev. 0 | Page 27 of 80
ADATE318
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD_THERM
PPMU_S1
THERM
1
2
3
4
5
6
7
8
9
63 VPLUS
62 PPMU_S0
61 HVOUT
60 DAT0
59 DAT0
58 NC
PIN 1
IDENTIFIER
DAT1
DAT1
NC
RCV1
RCV1
RCV0
RCV0
57
56
ADATE318
SCAP1
55 SCAP0
54 FFCAPB0
53 FFCAPA0
TOP VIEW
FFCAPB1 10
FFCAPA1 11
CMPL1 12
CMPL1
VTTC1
(Not to Scale)
84-LEAD 10mm × 10mm LFCSP
(HEATSINK FACE UP,
DIE FACE DOWN)
CMPL0
CMPL0
52
51
13
14
15
50 VTTC0
49
CMPH1
CMPH0
CMPH1 16
PGND 17
48 CMPH0
47 PGND
VDD 18
46 VDD
VSS 19
45 VSS
PPMU_CMPH1 20
AGND 21
44 PPMU_CMPH0
43 AGND
NOTES
1. EXPOSED PADDLE IS INTERNALLY CONNECTED VIA HIGH IMPEDANCE TO VSS (SUBSTRATE).
2. NC = THIS PIN IS OPEN. NO INTERNAL CONNECTION.
Figure 8. LFCSP Pin Configuration
Table 17. Pin Function Descriptions
Pin
EP
1
2
3
Mnemonic
Exposed Paddle
VDD_THERM
PPMU_S1
THERM
DAT1
Description
Exposed paddle is internally connected via high impedance to VSS (substrate).
Temperature Sensor VDD Supply.
PPMU External Sense Connect, Channel 1.
Temperature Sensor Analog Output.
4
High Speed Data Input, Channel 1.
5
DAT1
High Speed Data Input Complement, Channel 1.
This pin is open. No internal connection.
High Speed Receive Input, Channel 1.
High Speed Receive Input Complement, Channel 1.
PPMU External Compensation Capacitor, Channel 1.
PPMU External Feed Forward Capacitor Pin B, Channel 1.
PPMU External Feed Forward Capacitor Pin A, Channel 1.
High Speed Comparator Low Output, Channel 1.
High Speed Comparator Low Output Complement, Channel 1.
Comparator Supply Termination, Channel 1.
High Speed Comparator High Output Complement, Channel 1.
High Speed Comparator High Output, Channel 1.
Power Ground.
6
7
8
NC
RCV1
RCV
9
SCAP1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
FFCAPB1
FFCAPA1
CMPL1
CMPL1
VTTC1
CMPH1
CMPH1
PGND
VDD
VSS
PPMU_CMPH1
AGND
AGND
VDD Supply.
VSS Supply.
PPMU Go/No-Go Comparator High Output, Channel 1.
Analog Ground.
Analog Ground.
PPMU_CMPL1
PPMU Go/No-Go Comparator Low Output, Channel 1.
Rev. 0 | Page 28 of 80
ADATE318
Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Mnemonic
PPMU_MEAS1
DGND
DUTGND
ALARM
VSS
Description
PPMU Analog Measure Output, Channel 1.
Digital Logic Ground.
DUT Ground Sense Input.
Fault Alarm Open Drain Output.
VSS Supply.
Digital Logic Ground.
Serial Programmable Interface (SPI) Chip Select Input (Active Low).
Serial Programmable Interface (SPI) Busy Output (Active Low).
Serial Programmable Interface (SPI) Serial Data Output.
Serial Programmable Interface (SPI) Clock Input.
Serial Programmable Interface (SPI) Serial Data Input.
VCC Supply.
DGND
CS
BUSY
SDO
SCLK
SDI
VCC
VDD
RST
VDD Supply.
Reset Input (Active Low).
VREF
DAC Precision +5.0 V Reference Input.
DAC Precision +0.0 V Reference Input.
PPMU Analog Measure Output, Channel 0.
PPMU Go/No-Go Comparator Low Output, Channel 0.
Analog Ground.
Analog Ground.
PPMU Go/No-go Comparator High Output, Channel 0.
VSS Supply.
VREFGND
PPMU_MEAS0
PPMU_CMPL0
AGND
AGND
PPMU_CMPH0
VSS
VDD
PGND
VDD Supply.
Power Ground.
CMPH0
CMPH0
VTTC0
CMPL0
CMPL0
FFCAPA0
FFCAPB0
SCAP0
RCV0
High Speed Comparator High Output, Channel 0.
High Speed Comparator High Output Complement, Channel 0.
Comparator Supply Termination, Channel 0.
High Speed Comparator Low Output Complement, Channel 0.
High Speed Comparator Low Output, Channel 0.
PPMU External Feed Forward Capacitor Pin A, Channel 0.
PPMU External Feed Forward Capacitor Pin B, Channel 0.
PPMU External Compensation Capacitor, Channel 0.
High Speed Receive Input Complement, Channel 0.
High Speed Receive Input, Channel 0.
This pin is open. No internal connection.
High Speed Data Input Complement, Channel 0.
High Speed Data Input, Channel 0.
VHH Output Pin.
PPMU External Sense Connect, Channel 0.
VPLUS Supply.
VSS Supply.
System PMU Sense Input, Channel 0.
VDD Supply.
VDD Supply, Driver Output Stage, Channel 0.
DUT Pin, Channel 0.
RCV0
NC
DAT0
DAT0
HVOUT
PPMU_S0
VPLUS
VSS
PMU_S0
VDD
VDDO0
DUT0
VSSO0
VSS
VSS Supply, Driver Output Stage, Channel 0.
VSS Supply.
Power Ground.
VDD Supply.
VSS Supply.
PGND
VDD
VSS
AGND
Analog Ground.
Rev. 0 | Page 29 of 80
ADATE318
Pin
75
76
77
78
79
80
81
82
83
84
Mnemonic
VSS
VDD
PGND
VSS
VSSO1
DUT1
VDDO1
VDD
Description
VSS Supply.
VDD Supply.
Power Ground.
VSS Supply.
VSS Supply, Driver Output Stage, Channel 1.
DUT Pin, Channel 1.
VDD Supply, Driver Output Stage, Channel 1.
VDD Supply.
System PMU Sense Input, Channel 1.
VSS Supply.
PMU_S1
VSS
Rev. 0 | Page 30 of 80
ADATE318
TYPICAL PERFORMANCE CHARACTERISTICS
0.35
0.30
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1V
2V
3V
500mV
0.25
0.20
0.15
200mV
0.10
0.05
0
–0.05
–0.10
–0.2
–0.4
0
2
4
6
8
10
TIME (ns)
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
Figure 12. 100 MHz Driver Response, VIH = 1. 0 V, 2.0 V, 3.0 V; VIL = 0.0 V,
50 Ω Termination
Figure 9. Driver Small Signal Response, VIH = 0.2 V, 0.5 V, VIL = 0.0 V,
50 Ω Termination
1.8
1.8
1.6
1V
2V
1.6
3V
3V
1.4
1.2
1.4
1.2
2V
1.0
1.0
0.8
0.6
0.4
0.2
0.8
1V
0.6
0.4
0.2
0
–0.2
–0.4
0
–0.2
0
2
4
6
8
10
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 13. 300 MHz Driver Response, VIH = 1.0 V, 2.0 V, 3.0 V; VIL = 0.0 V,
50 Ω Termination
Figure 10. Driver Large Signal Response, VIH = 1.0 V, 2.0 V, 3.0 V;
VIL = 0.0 V, 50 Ω Termination
1.8
6
0.5V
1V
2V
3V
1.6
1.4
1.2
5V
5
4
3V
1.0
0.8
0.6
0.4
0.2
3
2
1V
1
0
0
–0.2
–1
0
2
4
6
8
10
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 11. Driver Large Signal Response, VIH = 1.0 V, 3.0 V, 5.0 V;
VIL = 0.0 V, 50 Ω Unterminated
Figure 14. 400 MHz Driver Response, VIH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;
VIL = 0.0 V, 50 Ω Termination
Rev. 0 | Page 31 of 80
ADATE318
1.6
1.4
1.2
1.0
0.8
1.2
0.5V
1V
2V
1.0
VIH TO/FROM VIT
0.8
0.6
0.6
0.4
0.2
0.4
0.2
VIL TO/FROM VIT
0
0
–0.2
–0.2
0
0
5
10
15
20
1
2
3
4
5
TIME (ns)
TIME (ns)
Figure 15. 600 MHz Driver Response, VIH = 0.5 V, 1.0 V, 2.0 V; VIL = 0.0 V,
50 Ω Termination
Figure 18. Driver Active (VIH/VIL) to/from VTERM Transition; VIH =3.0 V,
VIT = 1.5 V; VIL = 0.0 V, 50 Ω Termination
0.6
POSITIVE PULSE
90
NEGATIVE PULSE
0.5
70
VIH TO/FROM VIT
0.4
50
30
10
0.3
0.2
0.1
–10
–30
–50
VIL TO/FROM VIT
0
–0.1
0
2
4
6
8
10
0
5
10
15
20
PULSE WIDTH (ns)
TIME (ns)
Figure 19. Driver Trailing Edge Timing Error Pulse Width, VIH = 0.2 V;
VIL = 0.0 V, 50 Ω Termination
Figure 16. Driver Active (VIH/VIL) to/from VTERM Transition; VIH = 1.0 V,
VIT = 0.5 V; VIL = 0.0 V, 50 Ω Termination
1.2
POSITIVE PULSE
90
NEGATIVE PULSE
1.0
70
VIH TO/FROM VIT
0.8
0.6
0.4
0.2
50
30
10
–10
–30
–50
VIL TO/FROM VIT
0
–0.2
0
2
4
6
8
10
0
5
10
15
20
PULSE WIDTH (ns)
TIME (ns)
Figure 17. Driver Active (VIH/VIL) to/from VTERM Transition; VIH = 2.0 V,
VIT = 1.0 V; VIL = 0.0 V, 50 Ω Termination
Figure 20. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 0.5 V;
VIL = 0.0 V, 50 Ω Termination
Rev. 0 | Page 32 of 80
ADATE318
70
1.5
POSITIVE PULSE
NEGATIVE PULSE
50
30
1.0
0.5
0
10
0
–10
–0.5
–30
–50
–1.0
0
2
4
6
8
10
–2
–1
0
1
2
3
4
5
6
7
DRIVER OUTPUT VOLTAGE (V)
PULSE WIDTH (ns)
Figure 21. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 1.0 V;
VIL = 0.0 V, 50 Ω Termination
Figure 24. Driver VIH Linearity Error
1.5
POSITIVE PULSE
90
NEGATIVE PULSE
70
1.0
0.5
0
50
30
10
–10
–30
–50
–0.5
–1.0
0
2
4
6
8
10
–2
–1
0
1
2
3
4
5
6
7
PULSE WIDTH (ns)
DRIVER OUTPUT VOLTAGE (V)
Figure 22. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 2.0 V;
VIL = 0.0 V, 50 Ω Termination
Figure 25. Driver VIL Linearity Error
1.5
100
POSITIVE PULSE
NEGATIVE PULSE
80
1.0
0.5
0
60
40
20
0
–20
–40
–60
–0.5
–80
–1.0
–100
–2
–1
0
1
2
3
4
5
6
7
0
2
4
6
8
10
DRIVER OUTPUT VOLTAGE (V)
PULSE WIDTH (ns)
Figure 26. Driver VIT Linearity Error
Figure 23. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 3.0 V;
VIL = 0.0 V, 50 Ω Termination
Rev. 0 | Page 33 of 80
ADATE318
0.25
0.20
0.15
50.0
49.5
49.0
48.5
48.0
47.5
0.10
0.05
0
–0.05
–0.10
–2
–1
0
1
2
3
4
5
6
7
–60
–40
–20
0
20
40
60
VIL PROGRAMMED DAC VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
Figure 27. Driver Interaction Error VIH vs. VIL, VIH = +6.5 V,
VIL Swept from −1.5 V to +6.5 V
Figure 30. Driver Output Resistance vs. Output Current
0.08
120
0.06
0.04
100
80
60
40
20
0
0.02
0
–0.02
–0.04
–0.06
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
VIH PROGRAMMED DAC VOLTAGE (V)
V
(V)
DUT
Figure 28. Driver Interaction Error VIL vs. VIH; VIL = −1.5 V, VIH
Swept from −1.5 V to +6.5 V
Figure 31. Driver Output Current Limit; Driver Programmed to −1.5 V,
VDUT Swept −1.5 V to +6.5 V
0.8
0.7
0
–20
0.6
0.5
0.4
–40
–60
0.3
0.2
–80
0.1
–100
0
–0.1
–120
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
VIH PROGRAMMED DAC VOLTAGE (V)
V
(V)
DUT
Figure 29. Driver Interaction Error VIT vs. VIH, VIT = +1.0 V, VIH Swept
from −1.5 V to +6.5 V
Figure 32. Driver Output Current Limit. Driver Programmed to 6.5 V,
VDUT Swept −1.5 V to +6.5 V
Rev. 0 | Page 34 of 80
ADATE318
16
14
12
10
10
5
VHH OUTPUT
0
8
–5
–10
–15
6
4
2
0
0
0.5
1.0
TIME (µs)
1.5
2.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
HVOUT OUTPUT VOLTAGE (V)
Figure 36. HVOUT VHH Linearity Error
Figure 33. HVOUT Transient Response, VHH = 13.5 V
100
90
3
2
1
80
0
–1
–2
70
60
50
40
–3
–4
–5
–6
–7
30
20
10
0
–1
0
1
2
3
4
5
6
7
5
6
7
8
9
10
11
(V)
12
13
14
15
V
HVOUT OUTPUT VOLTAGE (V)
HVOUT
Figure 37. HVOUT VHH Output Current Limit; VHH = 5.9 V, HVOUT
Swept 5.9 V to 13.5 V
Figure 34. HVOUT VIH Linearity Error
3
20
10
0
2
1
–10
–20
0
–1
–2
–30
–40
–50
–60
–70
–80
–90
–3
–4
–5
–6
–7
–1
0
1
2
3
4
5
6
7
5
6
7
8
9
10
11
(V)
12
13
14
15
HVOUT OUTPUT VOLTAGE (V)
V
HVOUT
Figure 35. HVOUT VIL Linearity Error
Figure 38. HVOUT VHH Output Current Limit; VHH = 13.5 V, HVOUT
Swept 5.9 V to 13.5 V
Rev. 0 | Page 35 of 80
ADATE318
80
1.2
70
1.0
0.8
60
50
40
0.6
0.4
0.2
0
30
20
10
INPUT
EDGE
SHMOO
0
–10
–1
–0.2
0
1
2
3
4
5
6
7
0
2
4
6
8
10
V
(V)
TIME (ns)
HVOUT
Figure 39. HVOUT VIL Output Current Limit; VIL = −0.1 V, HVOUT
Swept −0.1 V to 6.0 V
Figure 42. Normal Window Comparator Shmoo; 1.0 V Swing, 50 Ω
Termination, 200 ps (20% to 80%)
10
0
5
0
–10
–20
–30
–5
–10
POSITIVE PULSE
NEGATIVE PULSE
–40
–50
–60
–70
–80
–90
–15
–20
–25
–30
–1
0
1
2
3
4
5
6
7
0
2
4
6
8
10
V
(V)
PULSE WIDTH (ns)
HVOUT
Figure 40. HVOUT VIH Output Current Limit; VIH = 6.0 V, HVOUT
Swept −0.1 V to 6.0 V
Figure 43. Normal Window Comparator Trailing Edge Timing Error vs. Input
Pulse Width; 50 Ω Termination, 1.0 V Swing, 200 ps (20% to 80%)
1.2
0
INPUT VOLTAGE SWING = 1V
COMPARATOR THRESHOLD = 0.5V
–2
1.0
0.8
–4
–6
0.6
0.4
–8
–10
INPUT
SHMOO
EDGE
INPUT RISING EDGE
–12
INPUT FALLING EDGE
0.2
0
–14
–16
–18
–0.2
0
2
4
6
8
10
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TIME (ns)
INPUT TRANSITION TIME (20%/80%) (ns)
Figure 44. Normal Window Comparator Input Transition Time (20%/80%),
50 Ω Termination
Figure 41. Normal Window Comparator Shmoo 1.0 V Swing; 50 Ω
Termination, 200 ps (20% to 80%)
Rev. 0 | Page 36 of 80
ADATE318
0.8
0.7
0.6
0.5
0.20
0.15
0.10
0.05
0
0.4
0.3
–0.05
–0.10
–0.15
–0.20
–0.25
0.2
0.1
0
0
5
10
15
20
–3
–2
–1
0
1
2
3
4
5
6
7
TIME (ns)
THRESHOLD VOLTAGE (V)
Figure 48. PPMU Go/No-Go Comparator Linearity Error
Figure 45. Comparator Output Waveform
0
2.5
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
2.0
1.5
1.0
0.5
0
–1.4
–1.6
–1.8
–2.0
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
INPUT COMMON-MODE VOLTAGE (V)
THRESHOLD VOLTAGE (V)
Figure 49. Differential Comparator CMR Error
Figure 46. Normal Window Comparator Threshold Linearity Error
30
25
2.0
CURRENT VIL TO LOAD
CURRENT LOAD TO VIL
1.5
1.0
0.5
0
20
15
10
5
–0.5
–1.0
0
–1.5
–2.0
–5
0
5
10
15
15
20
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
TIME (ns)
THRESHOLD VOLTAGE (V)
Figure 50. Active Load Response to/from Drive VIL = 0 V, 50 Ω Termination,
IOL = 25 mA, VCOM = 2 V
Figure 47. Differential Comparator Threshold Linearity Error
Rev. 0 | Page 37 of 80
ADATE318
30
10
8
20
6
10
0
4
2
0
–10
–2
–20
–30
–4
–6
–3
–2
–1
0
1
2
3
4
5
6
7
0
5
10
15
20
25
ACTIVE LOAD CURRENT (mA)
V
(V)
DUT
Figure 51. Active Load Commutation Response, VCOM = 2.0 V,
IOH = IOL = 25 mA
Figure 54. Active Load IOL Linearity Error
20
15
10
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
5
0
–5
–10
–15
0
5
10
15
20
25
–3
–2
–1
0
1
2
3
4
5
6
7
V
(V)
ACTIVE LOAD CURRENT (mA)
DUT
Figure 52. Active Load IOH Linearity Error
Figure 55. DUTx Pin Leakage in Low Leakage Mode
0
–0.2
–0.4
–0.6
–0.8
250
200
150
100
50
–1.0
–1.2
0
–50
–3
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
8
VCOM VOLTAGE (V)
V
(V)
DUT
Figure 53. Active Load VCOM Linearity Error
Figure 56. DUTx Pin Leakage in High-Z Mode
Rev. 0 | Page 38 of 80
ADATE318
3.0
2.5
0.15
0.10
0.05
0
2.0
1.5
1.0
–0.05
–0.10
–0.15
0.5
0
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
–1.0
–0.5
0
0.5
1.0
DUTGND VOLTAGE (V)
PMU OUTPUT CURRENT (mA)
Figure 57. Typical DUTGND Transfer Function Voltage Error,
Drive Low VIL = 0 V
Figure 60. PPMU Range B Force Current Linearity Error
0.018
0.016
0.014
0.2
0.1
0
0.012
0.010
0.008
–0.1
–0.2
–0.3
0.006
0.004
0.002
0
–0.4
–0.5
–0.10
–0.05
0
0.05
0.10
–2
–1
0
1
2
3
4
5
6
7
PMU OUTPUT CURRENT (mA)
PMU OUTPUT VOLTAGE (V)
Figure 61. PPMU Range C Force Current Linearity Error
Figure 58. PPMU Force Voltage Linearity Error, All Ranges
15
0.0015
0.0010
10
5
0.0005
0
0
–0.0005
–0.0010
–5
–10
–40
–30
–20
–10
0
10
20
30
40
–0.010
–0.005
0
0.005
0.010
PMU OUTPUT CURRENT (mA)
PMU OUTPUT CURRENT (mA)
Figure 59. PPMU Range A Force Current Linearity Error
Figure 62. PPMU Range D Force Current Linearity Error
Rev. 0 | Page 39 of 80
ADATE318
0.0004
0.0003
0.5
0.4
0.0002
0.3
0.2
0.0001
0
0.1
0
–0.0001
–0.1
–0.2
–0.3
–0.0002
–0.0003
–0.0004
–0.0005
–0.0006
–0.4
–0.5
–1.0
–0.5
0
0.5
1.0
–0.0020 –0.0015 –0.0010 –0.0005
0
0.0005 0.0010 0.0015 0.0020
I
(mA)
DUT
PMU OUTPUT CURRENT (mA)
Figure 63. PPMU Range E Force Current Linearity Error
Figure 66. PPMU Force Voltage Range B Compliance Error at −2.0 V vs.
Output Current, Internal Sense
25
20
0.3
0.2
15
0.1
0
10
5
0
–0.1
–0.2
–5
–10
–15
–20
–25
–0.3
–0.4
–1.0
–0.5
0
0.5
1.0
–40
–30
–20
–10
0
10
20
30
40
I
(mA)
I
(mA)
DUT
DUT
Figure 64. PPMU Force Voltage Range A Compliance Error at −2.0 V vs.
Output Current, Internal Sense
Figure 67. PPMU Force Voltage Range B Compliance Error at +6.5 V vs.
Output Current, Internal Sense
20
15
10
5
25
20
15
10
5
0
–5
–10
–15
–20
–25
0
–5
–2
–1
0
1
2
3
4
5
6
–40
–30
–20
–10
0
10
20
30
40
V
(V)
I
(mA)
DUT
DUT
Figure 68. PPMU Force Current Range A Compliance Error at −40 mA vs.
Output Voltage
Figure 65. PPMU Force Voltage Range A Compliance Error at +5.75 V vs.
Output Current, Internal Sense
Rev. 0 | Page 40 of 80
ADATE318
35
30
25
20
15
0.0020
0.0015
0.0010
0.0005
0
10
5
–0.0005
0
–5
–0.0010
–2
–1
0
1
2
3
4
5
6
–2
–1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
DUT
DUT
Figure 69. PPMU Force Current Range A Compliance Error at +40 mA vs.
Output Voltage
Figure 72. PPMU Force Current Range E Compliance Error at −2 μA vs.
Output Voltage
0.30
0.25
0.20
0.0020
0.0015
0.0010
0.0005
0.15
0.10
0.05
0
0
–0.05
–0.0005
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
DUT
DUT
Figure 73. PPMU Force Current Range E Compliance Error at +2 μA vs.
Output Voltage
Figure 70. PPMU Force Current Range B Compliance Error at −1 mA vs.
Output Voltage
60
0.5
50
0.4
40
30
20
0.3
0.2
0.1
0
10
0
–0.1
–3
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
DUT
DUT
Figure 74. PPMU Force Voltage Output Current Limit Range A, FV = −2.0 V,
VDUT Swept −2.0 V to +6.5 V
Figure 71. PPMU Force Current Range B Compliance Error at +1 mA vs.
Output Voltage
Rev. 0 | Page 41 of 80
ADATE318
10
0.04
0.03
0
0.02
0.01
0
–10
–20
–30
–40
–50
–60
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–3
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
DUT
DUT
Figure 75. PPMU Force Voltage Output Current Limit Range A, FV = +6.5 V,
VDUT Swept −2.0 V to +6.5 V
Figure 78. PPMU Range B Measure Voltage Linearity Error
2.90
2.85
2.80
2.75
2.70
2.65
2.60
0.12
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–3
–2
–1
0
1
2
3
4
5
6
7
–1.0
–0.5
0
0.5
1.0
V
(V)
DUT
I
(mA)
DUT
Figure 76. PPMU Force Voltage Output Current Limit Range E, FV = −2.0 V,
VDUT Swept −2.0 V to +6.5 V
Figure 79. PPMU Range B Measure Current Linearity Error
0.10
0.05
3
2
0
–0.05
–0.10
–0.15
1
0
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–1
–2
–3
–4
–2
–1
0
1
2
3
4
5
6
–3
–2
–1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
DUT
DUT
Figure 80. PPMU Measure Current CMR Error, (FVMI), Sourcing 0.5 mA
Figure 77. PPMU Force Voltage Output Current Limit Range E, FV = 6.5 V,
VDUT Swept −2.0 V to +6.5 V
Rev. 0 | Page 42 of 80
ADATE318
2.0
1.5
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
0.5
0
–0.5
–1.0
–0.2
–0.4
–0.6
–1.5
–2.0
0
1
2
3
4
5
6
7
–3
–2
–1
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 84. PPMU Voltage Clamp VCH Linearity Error
Figure 81. Reflection Clamp VCL Linearity Error
0
0.5
0.4
–10
–20
–30
0.3
0.2
–40
0.1
–50
–60
0
–0.1
–0.2
–0.3
–70
–80
–90
–0.4
–0.5
–100
–3
–2
–1
0
1
2
3
4
5
6
–2
–1
0
1
2
3
4
5
6
7
8
V
(V)
OUTPUT VOLTAGE (V)
DUT
Figure 85. VCL Reflection Clamp Current Limit; VCH = 6 V, VCL = 5 V,
VDUT Swept −2.0 V to +5.0 V
Figure 82. Reflection Clamp VCH Linearity Error
2
1
90
80
70
60
50
40
0
–1
–2
–3
30
20
10
0
–4
–5
–3
–2
–1
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
OUTPUT VOLTAGE (V)
V
(V)
DUT
Figure 83. PPMU Voltage Clamp VCL Linearity Error
Figure 86. VCH Reflection Clamp Current Limit; VCH = 0 V, VCL = −2 V,
VDUT Swept −2.0 V to +5.0 V
Rev. 0 | Page 43 of 80
ADATE318
0
100
90
RESOLUTION (0 TO 31) = ~ 3.0mV/BIT
RESOLUTION (10 TO 31) = ~ 4.6mV/BIT
–20
80
70
60
–40
–60
–80
50
40
30
20
10
0
–100
–120
–140
–160
VOL_HYSTERESIS
VOH_HYSTERESIS
–180
0
1
2
3
4
5
6
7
0
5
10
15
20
25
30
35
DRIVER CLC SETTING 3-BIT VALUE
HYSTERESIS CODE
Figure 87. Driver Offset Error vs. Driver CLC Setting
Figure 90. Normal Window Comparator Hysteresis Transfer Function
20
15
140
RESOLUTION (0 TO 31) = ~ 3.6mV/BIT
RESOLUTION (10 TO 31) = ~ 5.6mV/BIT
120
10
5
100
80
60
40
0
–5
–10
–15
–20
20
VOL_HYSTERESIS
VOH_HYSTERESIS
0
0
1
2
3
4
5
6
7
0
5
10
15
20
25 30 35
COMPARATOR CLC SETTING 3-BIT VALUE
HYSTERESIS CODE
Figure 91. Differential Comparator Hysteresis Transfer Function
Figure 88. Normal Window Comparator Offset Error vs. CLC Setting
20
15
10
5
0
–5
–10
–15
–20
C1
1ns/DIV
0
1
2
3
4
5
6
7
DIFFERENTIAL COMPARATOR CLC SETTING 3-BIT VALUE
Figure 92. Driver Eye Diagram, 400 Mbps, PRBS31; VIH = 1 V, VIL = 0 V
Figure 89. Differential Comparator Offset error vs. CLC Setting
Rev. 0 | Page 44 of 80
ADATE318
C1
C1
500ps/DIV
200ps/DIV
Figure 93. Driver Eye Diagram, 800 Mbps, PRBS31; VIH = 1 V, VIL = 0 V
Figure 96. Driver Eye Diagram, 1600 Mbps, PRBS31; VIH = 2 V, VIL = 0 V
C1
C1
500ps/DIV
200ps/DIV
Figure 94. Driver Eye Diagram, 800 Mbps, PRBS31; VIH = 2 V, VIL = 0 V
Figure 97. Driver Eye Diagram, 2000 Mbps, PRBS31; VIH = 1 V, VIL = 0 V
C1
C1
200ps/DIV
200ps/DIV
Figure 95. Driver Eye Diagram, 1600 Mbps, PRBS31; VIH = 1 V, VIL = 0 V
Figure 98. Driver Eye Diagram, 2000 Mbps, PRBS31; VIH = 2 V, VIL = 0 V
Rev. 0 | Page 45 of 80
ADATE318
0.8
0.6
0.4
0.2
0.16
0.14
0.12
0.10
CLC0
CLC3
CLC7
0.08
0.06
0.04
0
–0.2
0.02
0
–0.4
–0.6
VIH TO HIGH-Z
VIL TO HIGH-Z
–0.02
–0.04
–0.8
0
5
10
15
20
0
2
4
6
8
10
12
14
16
18
20
TIME (µs)
TIME (ns)
Figure 99. Drive to/from High-Z Transition, VIH = 1 V, VIL = −1 V,
50 Ω Termination
Figure 102. Driver 0.2 V Response vs. CLC Settings
0.8
0.7
0.6
0.5
100
CLC0
CLC3
CLC7
VIL TO IOL
VIL TO IOH
VIH TO IOL
VIH TO IOH
IOL TO VIL
IOL TO VIH
80
60
40
IOH TO VIL
IOH TO VIH
20
0
0.4
0.3
0.2
–20
–40
0.1
0
–60
–0.1
–0.2
–80
–100
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
TIME (µs)
TIME (ns)
Figure 100. Drive to/from Active Load Transient, VIL = VIH = 0 V,
IOH = IOL = 0 V
Figure 103. Driver 1 V Response vs. CLC Settings
50
2.0
1.5
CLC0
CLC3
CLC7
VIL TO HIZ
VIH TO HIZ
HIZ TO VIL
HIZ TO VIH
40
30
20
10
0
1.0
–10
–20
–30
–40
–50
0.5
0
–0.5
0
5
10
15
20
25
30
35
40
45
50
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 101. Drive to/from High-Z Transient, VIL = VIH = 0 V, 50 Ω Termination
Figure 104. Driver 3 V Response vs. CLC Settings
Rev. 0 | Page 46 of 80
ADATE318
6
5
4
3
2
6
5
4
3
2
1
0
RISE
FALL
RISE
FALL
1
0
–1
0
10
20
30
40
50
60
0
10
20
30
40
50
60
TIME (µs)
TIME (µs)
Figure 105. PPMU Transient Response, FI Range A, Full -Scale Transition,
Uncalibrated, CLOAD = 200 pF, RLOAD = 120 Ω
Figure 108. PPMU Transient Response, FV Range A, 0 V to 5 V, Uncalibrated,
CLOAD = 200 pF
2.0
1.5
1.0
0.6
0.5
0.4
0.3
RISE
FALL
RISE
FALL
0.5
0
0.2
0.1
0
–0.5
0
5
10
15
20
25
30
0
2
4
6
8
10
TIME (µs)
TIME (µs)
Figure 106. PPMU Transient Response, FI Range B, Full-Scale Transition,
Uncalibrated, CLOAD = 200 pF, RLOAD = 1.5 kΩ
Figure 109. PPMU Transient Response, FV Range A, 0 V to 0.5 V, Uncalibrated,
CLOAD = 200 pF
2.0
1.5
1.0
0.7
0.6
0.5
0.4
RISE
FALL
0.3
RISE
FALL
0.5
0
0.2
0.1
0
–0.5
–0.1
0
10
20
30
40
50
60
0
5
10
15
20
TIME (µs)
TIME (µs)
Figure 107. PPMU Transient Response, FI Range C, Full-Scale Transition,
Uncalibrated, CLOAD = 200 pF, RLOAD = 15 kΩ
Figure 110. PPMU Transient Response, FV Range C, 0 V to 0.5 V, Uncalibrated,
CLOAD = 200 pF
Rev. 0 | Page 47 of 80
ADATE318
0.7
0.6
0.6
0.5
0.4
0.3
0.2
0.5
0.4
0.3
0.2
RISE
FALL
RISE
FALL
0.1
0
0.1
–0.1
0
0
0
10
20
30
40
2
4
6
8
10
TIME (µs)
TIME (µs)
Figure 111. PPMU Transient Response, FV Range A, 0 V to 0.5 V, Uncalibrated,
CLOAD = 2000 pF
Figure 112. PPMU Transient Response, FV Range C, 0 V to 0.5 V, Uncalibrated,
CLOAD = 2000 pF
Rev. 0 | Page 48 of 80
ADATE318
SPI INTERCONNECT DETAILS
ADATE318
ADATE318
ADATE318
(CHIP 0)
(CHIP 1)
(CHIP x)
. . . . . . . . . . . .
SCLK
SDI
SCLK
SCLK
SDI
SDI
SDO
BUSY
CS
SDO
BUSY
CS
SDO
BUSY
CS
SCLK
SDI
SDO
BUSY
CS[3:0]
x
NOTES
1. x ≤ 4.
Figure 113. Multiple SPI with Shared SDO Line
Rev. 0 | Page 49 of 80
ADATE318
USE OF THE SPI
PIN
BUSY
After any valid SPI instruction is written to the ADATE318, the
pin electronics functions. In every case (with no exception for
reset recovery), it is the purpose of the pin to notify the
pin becomes asserted to indicate a busy status of the DAC
BUSY
BUSY
update and calibration engines. The
pin is an open drain
external test processor that it is again safe to stop the SCLK
signal to the ADATE318. Running the SCLK for extra periods
BUSY
type output capable of sinking a minimum of 5 mA from the
VCC supply. Because it is an open drain type output, it can be
wire-or’ed in common with many other similar open drain
devices. In such cases, it is the user’s responsibility either to
determine which device is indicating the busy state or, alter-
natively, to wait until all devices on the shared line become not
when
is not active is never a problem except for the
BUSY
possibility of adding unwanted digital switching noise to the
analog pin electronics circuitry as already noted.
While the length of the
period (tBUSW) is variable depending
BUSY
on the particular preceding SPI instruction, it is nevertheless
deterministic. The parameter tBUSW depends only on factors
such as whether the previous instruction involved a write to one
or more DAC addresses and, if so, then how many channels
were involved and whether or not the calibration function was
enabled. Table 18 describes the precise length of the tBUSW period
in units of rising edge SCLK cycles for each possible SPI
busy. It is recommended that the
pin be tied to VCC with
BUSY
an external 1 kΩ pull-up.
It is not a requirement to wait for release of
prior to a
BUSY
subsequent assertion of the
pin. This is not the purpose of
CS
the
pin. As long as the minimum number of SCLK cycles
BUSY
following the previous release of
is met according to the
CS
instruction scenario as well as recovery from a hard
reset.
RST
tCSAM parameter, the
pin can be asserted again for a
CS
subsequent SPI operation. With the one exception of recovery
from a reset request (either by hardware assertion of the
Because tBUSW is deterministic, it is therefore possible to predict
in advance the minimum number of rising edge SCLK cycles
required to complete any given SPI instruction. This makes it
possible to operate the ADATE318 without a need to monitor
RST
pin or a sofware setting of the internal SPI_RESET control bit),
there is no scenario in normal operation of the ADATE318 in
which the user must wait for release of
the state of the
pin. For applications in which it is neither
BUSY
prior to asserting
BUSY
possible nor desireable to monitor the pin, it is acceptable to use
the information in Table 18 to guarantee that the minimum
the
for another SPI operation. The only requirement on the
CS
assertion of
is that the tCSAM parameter be defined as in
CS
number of cycles is provided in lieu of monitoring
BUSY
Figure 4 and Table 13.
following release of
or reset. All DAC addresses have been
CS
It is very important, however, that the SCLK continue to operate
assigned to the contiguous address block from 0x00 through
0x0F; therefore, it is possible to decode this information within
the external test processor to provide a software indication that
extra SCLK cycles may be required according to the scenarios
listed in Table 18. All other operations not involving these
addresses require only the standard number of clock cycles
determined by tCSAM. As stated above, however, it is extremely
important to honor the minimum number of required rising
for as long as the
pin state remains active. This minimum
BUSY
period of time is defined by the tBUSW parameter (see Figure 4,
Figure 6, Figure 7, and Table 18). If the SCLK does not remain
active for at least the time specified by the tBUSW parameter, oper-
ations pending to the internal processor may not fully complete
or, worse, they may complete in an incorrect fashion. In either
case, a temporary malfunction of the ADATE318 may occur.
After the ADATE318 releases the
pin, the SCLK may
edge SCLK cycles as defined by tBUSW following the release of
BUSY
CS
again be stopped to prevent unwanted digital noise from
coupling into the analog levels during normal operation of the
for each of the SPI instruction scenarios listed in Table 18 to
ensure proper operation of the ADATE318.
Table 18.
SPI Instruction Type
Minimum SCLK Cycle Requirements
BUSY
Calibration Engine1
Maximum tBUSW (SCLK Cycles)
Following the Release of the Asynchronous Reset Pin (Hardware Reset)
Following Assertion of the SPI_RESET Control Bit (Software Reset)
No Operation (NOP) Instruction
X
X
X
64
64
3
Read Request to Any Valid ADATE318 Address and/or Channel (0x00 – 0x7F)
Single/Double Channel Write Request to Any Valid ADATE318 Address ≥ 0x10
Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)
Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)
Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)
Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)
X
X
3
3
Disabled
Disabled
Enabled
Enabled
10
16
20
26
1 X = don’t care.
Rev. 0 | Page 50 of 80
ADATE318
RESET SEQUENCE AND THE
PIN
RST
The internal state of the ADATE318 is indeterminate following
power-up. For this reason, it is necessary to perform a complete
reset sequence once the power supplies have stabilized. Further,
The part remains in this static reset state indefinitely until the
clocked portion of the sequence begins with either the first
rising edge of SCLK following the release of
(asynch-
RST
ronous reset) or the second rising edge of SCLK following the
release of (soft reset). No matter how the reset sequence is
the
pin must be held in the asserted state before and during
RST
the power-up sequence and released only after all power supplies
are known to be stable.
CS
initiated, the clocked portion of the reset sequence requires 64
SCLK cycles to run to completion, and the pin remains
BUSY
The ADATE318 has an active low pin (
) that asynchron-
RST
asserted until these clock cycles have been received. The
following actions take place during the clocked portion of the
reset sequence:
ously starts a reset sequence. A soft reset sequence can also be
initiated under SPI software control by writing to the
SPI_RESET bit in the SPI Control Register (SPI 0x12[0] (see
Figure 13)). In the case of a soft reset, the sequence begins on
•
•
Complete internal SPI controller initialization
Write the appropriate values to specific DAC X2 registers
(see Table 19)
the first rising edge of SCLK following the release of , subject
CS
to the normal setup and hold times. Certain actions take place
immediately upon initiation of the reset request, whereas other
actions require SCLK.
•
Enable the thermal alarm with a 100C threshold; disable
PPMU and the overvoltage detect (OVD) alarms
The following asynchronous actions take place as soon as a
reset request is detected, whether or not SCLK is active:
The 64th rising edge of SCLK releases
and starts a self-
BUSY
timed DAC deglitch period of approximately 3 μs. DAC voltages
begin to change once the deglitch circuits have timed out, and
they then require an additional 10 ꢀs to settle to their final
values. Thus, a full reset sequence requires approximately 15 ꢀs,
comprising 1.28 ꢀs (64 cycles × 20 ns) for the reset state
machine, 3 ꢀs for DAC deglitch, and another 10 ꢀs for settling.
•
•
Assert
pin
BUSY
Force all control registers to the default reset state as
defined by control register definitions
•
•
Clear all calibration registers to the default reset state as
defined by calibration register definitions
Override all DAC output voltages and force analog levels to
VDUTGND
•
•
Disable DCLs and PPMUs; open system PMU switches
Soft connect the DUT0 and DUT1 pins to VDUTGND (see
Figure 114)
CLAMPS
TO PPMU
DRIVER
LOAD
50Ω
DUTx
10kΩ
DUT PULLDOWNx
ADDR 0x19[7]
DUT PULL-DOWN SWITCH DEFAULTS TO A
CLOSED STATE IMMEDIATELY FOLLOWING
AN ASSERT OF RST (FOR HARD RESET)
OR AT THE FIRST RISING EDGE OF SCLK
FOLLOWING THE SPI CS (FOR SOFT RESET).
SEE DCL CONTROL REGISTER 0x19[7].
DUTGND
COMPARATORS
Figure 114. DUTx to VDUTGND Soft Connect Detail
Rev. 0 | Page 51 of 80
ADATE318
SPI REGISTER DEFINITIONS AND MEMORY MAP
SPI CLOCK INDEX
SPI WORD INDEX
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
C
C
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
R/W
1
0
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CH[1:0]
CHANNEL SELECT
00 = NOP
01 = READ/WRITE CHANNEL 0
10 = READ/WRITE CHANNEL 1
11 = READ NOP
11 = WRITE CHANNEL 0 AND 1
ADDR[6:0]
ADDRESS FIELD
R/W
READ/WRITE SELECT
0 = READ:
THE CONTENTS OF REGISTER SPECIFIED BY ADDR[6:0]
AND CH[1:0] ARE SHIFTED OUT ON THE SDO PIN
DURING THE NEXT SPI INSTRUCTION CYCLE.
1 = WRITE: DATA[15:0] IS WRITTEN TO THE REGISTER
SPECIFIED BY ADDR[6:0] AND CH[1:0].
DATA[15:0]
DATA FIELD
Figure 115. SPI Word Definition
Table 19. SPI Register Memory Map
1
CH[1:0]1, 2
XX
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
01
ADDR[6:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
DATA[15:0]1, 3
XXXX
Register Description
Reset Value1
XXXX
R
/W
X
No operation (NOP)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
VIH DAC level (reset value = 0.0 V)
0x4000
0x4000
0x4000
0x4CCC
0x3333
0xFFFF
0x0000
0x4040
0x4040
0x4000
0x2666
0xFFFF
0x0000
0x4000
XXXX
VIT/VCOM DAC level (reset value = 0.0 V)
VIL DAC level (reset value = 0.0 V)
VOH DAC level (reset value = +0.5 V))
VOL DAC level (reset value = −0.5 V)
VCH DAC level (reset value = +7.5 V)
VCL DAC level (reset value = −2.5 V)
VIOH DAC level (reset value = 50 μA)
VIOL DAC level (reset value = 50 μA)
PPMU DAC level (reset value = 0.0 V)
VHH DAC level (reset value = 0.0 V)
OVDH DAC level (reset value = +7.5 V)
OVDL DAC level (reset value = −2.5 V)
Spare DAC level (reset value = 0.0 V)
Reserved
01
01
01
XX
XX
CC
01
0x0F
0x10
0x11
0x12
0x13 to 0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
X
XXXX
No operation (NOP)
XXXX
R/W
R/W
X
DDDD
DDDD
XXXX
DAC control register
0x0000
0x0000
XXXX
SPI control register
XX
01
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
VHH control register
0x0000
0x0080
0x0000
0x0000
0x07FE
0x0045
0x0000
0x0000
XXXX
CC
CC
CC
CC
CC
CC
CC
XX
CC
CC
CC
CC
DCL control register
PPMU control register
PPMU MEAS control register
CMP control register
ALARM mask register
ALARM state register
0x1F
R/W
X
CLC control register
0x20
0x21
0x22
0x23
0x24
No operation (NOP)
R/W
R/W
R/W
R/W
DDDD
DDDD
DDDD
DDDD
VIH (driver) m-coefficient
VIT (driver) m-coefficient
0xFFFF
0xFFFF
0xFFFF
0xFFFF
VIL (driver) m-coefficient
VOH (normal window comparator) m-coefficient
Rev. 0 | Page 52 of 80
ADATE318
1
CH[1:0]1, 2
CC
CC
CC
CC
CC
CC
01
ADDR[6:0]
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
DATA[15:0]1, 3
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
Register Description
Reset Value1
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
XXXX
R
/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
VOL (normal window comparator) m-coefficient
VCH (reflection clamp) m-coefficient
VCL (reflection clamp) m-coefficient
VIOH (active load) m-coefficient
VIOL (active load) m-coefficient
PPMU (PPMU force-voltage) m-coefficient
VHH (HVOUT) m-coefficient
01
OVDH (overvoltage) m-coefficient
OVDL (overvoltage) m-coefficient
Spare DAC m-coefficient
01
01
XX
XX
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
01
Reserved
X
XXXX
No operation (NOP)
XXXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
XXXX
VIH (driver) c-coefficient
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
XXXX
VIT (driver) c-coefficient
VIL (driver) c-coefficient
VOH (normal window comparator) c-coefficient
VOL (normal window comparator) c-coefficient
VCH (reflection clamp) c-coefficient
VCL (reflection clamp) c-coefficient
VIOH (active load) c-coefficient
VIOL (active load) c-coefficient
PPMU (PPMU force voltage) c-coefficient
VHH (HVOUT) c-coefficient
01
OVDH (overvoltage) c-coefficient
OVDL (overvoltage) c-coefficient
01
01
Spare DAC c-coefficient
XX
XX
01
Reserved
X
XXXX
No operation (NOP)
XXXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
DDDD
VIH (HVOUT) m-coefficient
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x8000
0x8000
0x8000
0x8000
0x8000
CC
01
VCOM (active load) m-coefficient
VIL (HVOUT) m-coefficient
01
VOH (differential comparator) m-coefficient
VOH (PPMU measure voltage) m-coefficient
VOH (PPMU measure current, Range A) m-coefficient
VOH (PPMU measure current Range B) m-coefficient
VOH (PPMU measure current, Range C) m-coefficient
VOH (PPMU measure current, Range D) m-coefficient
VOH (PPMU measure current, Range E) m-coefficient
VOL (differential comparator) m-coefficient
VOL (PPMU measure voltage) m-coefficient
VOL (PPMU measure current, Range A) m-coefficient
VOL (PPMU measure current, Range B) m-coefficient
VOL (PPMU measure current, Range C) m-coefficient
VOL (PPMU measure current, Range D) m-coefficient
VOL (PPMU measure current, Range E) m-coefficient
VCH (PPMU) m-coefficient
CC
CC
CC
CC
CC
CC
01
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
01
VCL (PPMU) m-coefficient
PPMU force current, Range A m-coefficient
PPMU force current, Range B m-coefficient
PPMU force current, Range C m-coefficient
PPMU force current Range D m-coefficient
PPMU force current, Range E m-coefficient
VIH (HVOUT) c-coefficient
CC
01
VCOM (active load) c-coefficient
VIL (HVOUT) c-coefficient
01
VOH (differential comparator) c-coefficient
VOH (PPMU measure voltage) c-coefficient
CC
Rev. 0 | Page 53 of 80
ADATE318
1
CH[1:0]1, 2
ADDR[6:0]
DATA[15:0]1, 3
DDDD
XXXX
Register Description
Reset Value1
0x8000
XXXX
R
/W
CC
XX
01
0x5E
R/W
X
VOH (PPMU measure current) c-coefficient
Reserved
0x5F to 0x62
0x63
R/W
R/W
R/W
X
DDDD
DDDD
DDDD
XXXX
VOL (differential comparator) c-coefficient
VOL (PPMU measure voltage) c-coefficient
VOL (PPMU measure current) c-coefficient
Reserved
0x8000
0x8000
0x8000
XXXX
CC
CC
XX
CC
CC
CC
XX
0x64
0x65
0x66 to 0x69
0x6A
R/W
R/W
R/W
X
DDDD
DDDD
DDDD
XXXX
VCH (PPMU) c-coefficient
VCL (PPMU) c-coefficient
0x8000
0x8000
0x8000
XXXX
0x6B
0x6C
PPMU force current c-coefficient
Reserved
0x6D to 0x70
1 X = don’t care.
2 CC corresponds to the channel address bits and indicates that there is dedicated register space for each channel.
3 DDDD stands for data.
Rev. 0 | Page 54 of 80
ADATE318
CONTROL REGISTER DETAILS
Reserved bits in any register are undefined. In some cases, a
physical (but unused) memory bit may be present, in other
cases not. Write operations have no effect. Read operations
result in meaningless but deterministic data.
Any SPI write operation to a control bit or control register
defined only on Channel 0 must be addressed to at least
Channel 0. Any such write that is addressed only to Channel 1
is ignored. Further, any such write that is addressed to both
Channel 0 and Channel 1 (as a multichannel write) proceeds as
if the write were addressed only to Channel 0. The data
addressed to the undefined Channel 1 control bit or control
register is ignored.
Any SPI read operation from any reserved bit or register results
in an unknown but deterministic readback value.
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:3]
RESERVED
DAC_LOAD[2]
DAC LOAD SOFT PIN, SELF-RESETTING, CHANNEL 0/CHANNEL 1
[0] = DEFAULT STATE OF THE DAC_LOAD SOFT PIN
1
= BEGIN DAC LOAD OPERATION (PULSE, SELF-CLEAR TO ZERO)
A WRITE TO THIS BIT PARALLEL UPDATES ALL DACs OF CHANNEL x
WITH PREVIOUSLY BUFFERED DATA ASSUMING THAT THE
DAC_LOAD_MODE CONTROL BIT OF CHANNEL x IS NOT SET TO
WRITE DAC IMMEDIATE MODE. THIS BIT AUTOMATICALLY SELF-CLEARS.
DAC_LOAD_MODE[1]
DAC LOAD MODE, CHANNEL 0/CHANNEL 1
[0] = WRITE DAC IMMEDIATE MODE.
1
= WRITE DAC DEFERRED MODE.
IN WRITE DAC IMMEDIATE MODE, EACH RESPECTIVE DAC IS UPDATED
IMMEDIATELY SUBSEQUENT TO A VALID SPI WRITE INSTRUCTION TO
THAT DAC ADDRESS. IN WRITE DAC DEFERRED MODE, EACH VALID
SPI WRITE TO A DAC ADDRESS IS BUFFERED, AND DACs ARE ONLY
UPDATED FOLLOWING ASSERTION OF THE DAC_LOAD SOFT PIN.
IN THIS MODE, ALL ANALOG DAC DATA FOR EITHER OR BOTH
CHANNELS CAN BE UPDATED IN PARALLEL.
DAC_CAL_ENABLE[0]
DAC CALIBRATION ENGINE ENABLE, CHANNEL 0 ONLY
[0] = CALIBRATION ENGINE IS DISABLED
1
= CALIBRATION ENGINE IS ENABLED
WHEN DAC CALIBRATION IS ENABLED, EACH WRITE TO A VALID DAC
ADDRESS RESULTS IN A SUBSEQUENT MULTIPLY AND ACCUMULATE
(MAC) OPERATION TO THE DATA FOR THE RESPECTIVE DAC USING
CALIBRATION DATA CONTAINED IN THE APPROPRIATE m- AND c-
COEFFICIENT REGISTERS. WHEN THE CALIBRATION ENGINE IS
DISABLED, DATA WRITTEN TO A VALID DAC ADDRESS IS NOT
MODIFIED BY THE ON-CHIP CALIBRATION COEFFICIENTS.
Figure 116. DAC Control Register (ADDR = 0x11)
Rev. 0 | Page 55 of 80
ADATE318
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:2]
RESERVED
SPI_SDO_HIZ[1]
SPI SERIAL DATA OUTPUT PIN, HIGH-Z CONTROL, CHANNEL 0 ONLY
[0] = SDO PIN IS ALWAYS ACTIVE, INDEPENDENT OF THE CS INPUT.
1 = SDO PIN IS ACTIVE ONLY WHEN CS IS ACTIVE, OTHERWISE HIGH-Z.
SPI_RESET[0]
SPI SOFTWARE RESET, CHANNEL 0 ONLY
[0] = DEFAULT SETTING, NO ACTION IS TAKEN UNTIL A 1 IS WRITTEN.
1 = RESET (PULSE, SELF-CLEAR TO ZERO).
FOLLOWING A WRITE TO SET THIS BIT, THE ADATE318 BEGINS
A FULL RESET SEQUENCE JUST AS IF THE RST PIN HAD BEEN
ASSERTED ASYNCHRONOUSLY. FOLLOWING RESET THIS BIT
SELF-CLEARS TO THE DEFAULT 0 CONDITION.
Figure 117. SPI Control Register (ADDR = 0x12)
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:1]
RESERVED
VHH_ENABLE[0]
VHH (HVOUT) ENABLE, CHANNEL 0 ONLY
[0] = HVOUT PIN IS DISABLED.
1 = HVOUT PIN IS ENABLED.
WHEN VHH MODE IS ENABLED, THE HVOUT PIN IS SET TO THE LEVELS
ACCORDING TO THE VHH AND VIH/VIL DRIVER TRUTH TABLE (TABLE 25).
WHEN VHH MODE IS DISABLED, THE IMPEDANCE OF THE HVOUT PIN
IS APPROXIMATELY 50Ω TO VDUTGND.
Figure 118. VHH Control Register (ADDR = 0x18) Active Truth Table
Rev. 0 | Page 56 of 80
ADATE318
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:8]
RESERVED
DUT_PULLDOWN_x[7]
DUTx PIN 10K SOFT PULL-DOWN, CHANNEL 0/CHANNEL 1
0 = HVOUT PIN IS DISABLED.
[1]
= DUTx PIN HAS 10kΩ PULL-DOWN TO DUTGND.
WHEN DUT_PULLDOWN IS ASSERTED, THE DUTx PIN ON CHANNEL x
HAS A 10kΩ PULL-DOWN TO DUTGND. THIS CONTROL BIT IS
ASYNCHRONOUSLY SET AT THE BEGINNING OF ANY RESET OPERATION,
AND IT REMAINS SET UNTIL CLEARED BY THE USER. THIS CONTROL
BIT DOES NOT DEPEND ON OTHER CONTROL BITS IN THIS REGISTER.
DRIVE_VT_HIZ_x[6]
DRIVER VT/HiZ MODE SELECT, CHANNEL 0/CHANNEL 1
[0] = DRIVER GOES TO HIGH-Z STATE WHEN RCVx = 1.
1 = DRIVER GOES TO VIT STATE WHEN RCVx = 1.
WHEN DRV_VT_HIZ IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMES
THE VIT LEVEL ON ASSERTION OF THE RCVx HIGH SPEED INPUT IN
ACCORDANCE WITH THE DRIVER TRUTH TABLE. THIS CONTROL BIT IS
SUBORDINATE TO THE DCL_ENABLE AND FORCE_DRIVE CONTROL BITS.
LOAD_ENABLE_x[5]
ACTIVE LOAD ENABLE, CHANNEL 0/CHANNEL 1
[0] = ACTIVE LOAD IS DISABLED AND POWERED DOWN.
1 = ACTIVE LOAD IS ENABLED.
WHEN LOAD_ENABLE IS ASSERTED, THE ACTIVE LOAD ON CHANNEL x IS ENABLED
AND CONNECTS TO THE DUTx PIN ON ASSERTION OF THE RCVn HIGH SPEED INPUT
IN ACCORDANCE WITH THE ACTIVE LOAD TRUTH TABLE. THIS CONTROL BIT IS
SUBORDINATE TO THE DCL_ENABLE AND FORCE_LOAD CONTROL BITS BUT TAKES
PRECEDENCE OVER THE RCVn HIGH SPEED INPUTS.
FORCE_DRIVE_STATE_x[4:3]
DRIVER STATE WHEN FORCE_DRIVE, CHANNEL 0/CHANNEL 1
[00] = FORCE DRIVE VIL STATE.
01 = FORCE DRIVE VIH STATE.
10 = FORCE DRIVE HIGH-Z STATE.
11 = FORCE DRIVE VIT STATE.
WHEN THE FORCE_DRIVE CONTROL BIT IS ACTIVE, THE DRIVER ON CHANNEL x
ASSUMES THE INDICATED STATE IN ACCORDANCE WITH THE DRIVER TRUTH TABLE.
FORCE_LOAD_x[2]
FORCE ACTIVE LOAD TO ACTIVE ON STATE, CHANNEL 0/CHANNEL 1
[0] = ACTIVE LOAD RESPONDS TO RCVx.
1 = FORCE ACTIVE ON STATE.
WHEN FORCE_LOAD IS ASSERTED, THE ACTIVE LOAD ON CHANNEL x ASSUMES THE ACTIVE ON
STATE AND IS CONNECTED TO THE DUTx PIN IN ACCORDANCE WITH THE ACTIVE LOAD TRUTH
TABLE. THIS CONTROL BIT IS SUBORDINATE TO THE DCL_ENABLE CONTROL BIT BUT TAKES
PRECEDENCE OVER BOTH THE LOAD_ENABLE AND DRV_VT_HIZ CONTROL BITS, AS WELL AS
THE RCVx INPUTS. THIS BIT DOES NOT FORCE SELECTION OF VCOM CALIBRATION CONSTANTS.
FORCE_DRIVE_x[1]
FORCE DRIVER TO FORCE_STATE, CHANNEL 0/CHANNEL 1
[0] = DRIVER RESPONDS TO DATx AND RCVx.
1 = FORCE DRIVER STATE TO FORCE_STATE.
WHEN FORCE_DRIVE IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMES THE STATE INDICATED
BY FORCE_STATE IN ACCORDANCE WITH THE DRIVER TRUTH TABLE. THIS CONTROL BIT IS SUBORDINATE
TO THE DCL_ENABLE CONTROL BIT BUT TAKES PRECEDENCE OVER DRV_VT_HIZ, AS WELL AS THE
DATx AND RCVx INPUTS. THIS BIT DOES NOT FORCE SELECTION OF VCH AND VCL CALIBRATION
CONSTANTS NOR DOES IT FORCE SELECTION OF VIT CALIBRATION CONSTANTS.
DCL_ENABLE_x[0]
ENABLE DCL ON CHANNEL 0/CHANNEL 1
[0] = DCL IS DISABLED (LOW LEAKAGE MODE).
1 = DCL IS ENABLED.
WHEN DCL_ENABLE IS NOT ASSERTED, THE DRIVER, COMPARATOR, AND ACTIVE LOAD ON
CHANNEL x ASSUME THE LOW LEAKAGE STATE IN ACCORDANCE WITH DRIVER AND
ACTIVE LOAD TRUTH TABLES. THIS CONTROL BIT TAKES PRECEDENCE OVER ALL OTHER CONTROL
BITS IN THE DCL CONTROL REGISTER EXCEPT FOR DUT_PULLDOWN.
Figure 119. DCL Control Register (ADDR = 0x19)
Rev. 0 | Page 57 of 80
ADATE318
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PPMU_POWER_x[15]
PPMU POWER, CHANNEL 0/CHANNEL 1
[0] = PPMU POWER OFF.
1
= PPMU POWER ON.
WHEN PPMU_POWER_x[15] = 1, THE NWC
AND DMC HYSTERESIS IS FORCED TO A
MAXIMUM, BUT THE HYSTERESIS
REGISTER VALUES ARE LEFT UNCHANGED.
RESERVED[14:12]
RESERVED
PMU_S_ENABLE_x[11]
PMU SENSE INPUT ENABLE, CHANNEL 0/CHANNEL 1
[0] = PMU SENSE INPUT SWITCH OPEN.
1
= PMU SENSE INPUT SWITCH CLOSED.
RESERVED
PPMU_CLAMP_ENABLE_x[9]
PPMU CLAMP ENABLE, CHANNEL 0/CHANNEL 1
[0] = PPMU CLAMPS DISABLED.
1
= PPMU CLAMPS ENABLED.
PPMU_SENSE_PATH_x[8]
PPMU SENSE PATH, CHANNEL 0/CHANNEL 1
[0] = PPMU INTERNAL SENSE PATH.
1
= PPMU EXTERNAL SENSE PATH.
PPMU_INPUT_SEL_x[7:6]
PPMU INPUT SELECT, CHANNEL 0/CHANNEL 1
[00] = PPMU INPUT FROM DUTGND.
01 = PPMU INPUT FROM DUTGND + 2.5V.
= PPMU INPUT FROM DAC
LEVEL.
1X
PPMU
PPMU_MEAS_VI_x[5]
PPMU MEASURE V OR MEASURE I, CHANNEL 0/CHANNEL 1
[0] = PPMU MEASURE V MODE.
1
= PPMU MEASURE I MODE.
PPMU_FORCE_VI_x[4]
PPMU FORCE V OR FORCE I, CHANNEL 0/CHANNEL 1
[0] = PPMU FORCE V MODE.
1
= PPMU FORCE I MODE.
PPMU_RANGE_x[3:1]
PPMU RANGE, CHANNEL 0/CHANNEL 1
[0XX] = PPMU RANGE E (2µA).
100 = PPMU RANGE D (10µA).
101 = PPMU RANGE C (100µA).
110 = PPMU RANGE B (1mA).
111 = PPMU RANGE A (40mA).
PPMU_ENABLE_x[0]
PPMU ENABLE, CHANNEL 0/CHANNEL 1
[0] = PPMU FULL POWER STANDBY.
1
= PPMU ACTIVE.
Figure 120. PPMU Control Register (ADDR = 0x1A)
Rev. 0 | Page 58 of 80
ADATE318
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:3]
RESERVED
PPMU_MEAS_SEL_x[2:1]
PPMU ANALOG MEASURE OUT PIN SELECT, CHANNEL 0/CHANNEL 1
[X0] = PPMU CHANNEL x TO PPMU_MEASx OUTPUT PIN.
X1 = CHANNEL 0: TEMPERATURE SENSOR OUTPUT (THERM).
CHANNEL 1: TEMPERATURE SENSOR GND REFERENCE.
PPMU_MEAS_ENABLE_x[0]
PPMU ANALOG MEASURE OUT PIN ENABLE, CHANNEL 0/CHANNEL 1
[0] = PPMU MEASURE OUT PIN ON CHANNEL x IS DISABLED, HIGH-Z.
1
= PPMU MEASURE OUT PIN ON CHANNEL x IS ENABLED.
Figure 121. PPMU MEAS Control Register (ADDR = 0x1B)
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:11]
RESERVED
NWC_HYST_x[10:6]
NORMAL WINDOW COMPARATOR HYSTERESIS VALUE, CHANNEL 0/CHANNEL 1
0x00 = DISABLE HYSTERESIS.
0x01 = ENABLE MINIMUM HYSTERESIS.
[0x1F] = ENABLE MAXIMUM HYSTERESIS.
WHEN SET TO 0x00, THE NORMAL WINDOW COMPARATOR ON CHANNEL x
HAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUE
OTHER THAN 0x00, HYSTERESIS IS ADDED AND THE AMOUNT IS CONTROLLED
BY THE VALUE IN THIS REGISTER.
WHEN ADDR 0x1A PPMU _POWER_x[15] = 1, THE NWC HYSTERESIS IS FORCED TO A
MAXIMUM, BUT THE HYSTERESIS REGISTER VALUE IS LEFT UNCHANGED.
DMC_HYST[5:1]
DIFFERENTIAL COMPARATOR HYSTERESIS VALUE, CHANNEL 0 ONLY
0x00 = DISABLE HYSTERESIS.
0x01 = ENABLE MINIMUM HYSTERESIS.
[0x1F]
= ENABLE MAXIMUM HYSTERESIS.
WHEN SET TO 0x00, THE DIFFERENTIAL COMPARATOR ON CHANNEL 0
HAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUE
OTHER THAN 0x00, HYSTERESIS IS ADDED AND THE AMOUNT IS CONTROLLED
BY THE VALUE IN THIS REGISTER.
WHEN ADDR 0x1A PPMU _POWER_x[15] = 1, THE DMC HYSTERESIS IS FORCED TO A
MAXIMUM, BUT THE HYSTERESIS REGISTER VALUE IS LEFT UNCHANGED.
DMC_ENABLE[0]
DIFFERENTIAL MODE COMPARATOR ENABLE, CHANNEL 0 ONLY
[0] = DISABLE DIFFERENTIAL MODE COMPARATOR.
1 = ENABLE DIFFERENTIAL MODE COMPARATOR.
WHEN DMC_ENABLE IS ASSERTED, THE NORMAL WINDOW COMPARATOR
ON CHANNEL 0 IS DISABLED, THE DIFFERENTIAL MODE COMPARATOR ON
CHANNEL 0 IS ENABLED, AND ITS OUTPUTS GOES TO THE CMPH0 AND CMPL0
HIGH SPEED OUTPUT PINS. THE OPERATION OF THE NORMAL WINDOW
COMPARATOR ON CHANNEL 1 IS NOT AFFECTED. THIS CONTROL BIT EXISTS
AT ADDR 0x1C CHANNEL 0 ONLY.
Figure 122. CMP Control Register (ADDR = 0x1C)
Rev. 0 | Page 59 of 80
ADATE318
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:7]
RESERVED
THERM_ALARM_THRESH[6:4]
THERMAL ALARM THRESHOLD, CHANNEL 0 ONLY
000 = 0°C (FOR TEST USE ONLY)
001 = 25°C
010 = 50°C
011 = 75°C
[100] = 100°C
101 = 125°C
110 = 150°C
111 = 175°C
THERM_ALARM_MASK[3]
THERMAL ALARM MASK BIT, CHANNEL 0 ONLY
[0] = THERMAL ALARM ENABLED.
1
= THERMAL ALARM DISABLED.
WHEN THE THERMAL ALARM IS ENABLED, A TEMPERATURE SENSOR READING
ABOVE THE THRESHOLD SPECIFIED BY THERM_ALARM_THRESH
ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT PIN.
PPMU_ALARM_MASK_x[2]
PPMU CLAMP ALARM MASK, CHANNEL 0/CHANNEL 1
0
= PPMU CLAMP ALARM ENABLED.
[1] = PPMU CLAMP ALARM DISABLED.
WHEN THE PPMU CLAMP IS ENABLED, A CLAMP CONDITION ON CHANNEL x
PPMU CLAMPS ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT
PIN. THE PPMU CLAMP LEVELS ARE DEFINED BY THE VCL AND VCH DAC
REGISTERS.
RESERVED[1]
RESERVED
OVD_ALARM_MASK_n[0]
OVERVOLTAGE DETECTOR ALARM MASK, CHANNEL 0/CHANNEL 1
0
[1]
= OVERVOLTAGE ALARM ENABLED.
= OVERVOLTAGE ALARM DISABLED.
WHEN THE OVD ALARM IS ENABLED, AN OVERVOLTAGE FAULT CONDITION
ON DUTx ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT PIN.
THE OVERVOLTAGE THRESHOLDS ARE DEFINED BY THE OVDH AND
OVDL DAC REGISITERS.
Figure 123. Alarm Mask Register (ADDR = 0x1D)
Rev. 0 | Page 60 of 80
ADATE318
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED[15:4]
RESERVED
THERM_ALARM_FLAG[3]
THERMAL ALARM FLAG, CHANNEL 0 ONLY
[0] = THERMAL FAULT NOT DETECTED.
1 = THERMAL FAULT DETECTED.
WHEN THE THERM_ALARM_FLAG BIT IS SET, A FAULT WAS DETECTED
ON THE DIE ACCORDING TO THE THERMAL THRESHOLD SET IN THE
THERM_ALARM_THRESH REGISTER. THIS FLAG IS SUBORDINATE TO THE
THERM_ALARM_MASK CONTROL BIT, AND IT IS AUTOMATICALLY
RESET AFTER ANY READ FROM THE ALARM STATE REGISTER.
PPMU_ALARM_FLAG_x[2]
PPMU CLAMP ALARM FLAG, CHANNEL 0/CHANNEL 1
[0] = PPMU CLAMP CONDITION NOT DETECTED.
1 = PPMU CLAMP CONDITION DETECTED.
WHEN THE PPMU_ALARM_FLAG BIT IS SET, A PPMU CLAMP CONDITION WAS
DETECTED ON CHANNEL x ACCORDING TO THE THRESHOLDS SET IN THE
VCH AND VCL CLAMP REGISTERS. THIS FLAG IS SUBORDINATE TO THE
PPMU_ALARM_MASK_x CONTROL BIT, AND IT AUTOMATICALLY RESETS
AFTER ANY READ FROM THE ALARM STATE REGISTER.
OVDH_ALARM_FLAG_x[1]
OVER VOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1
[0] = OVER VOLTAGE FAULT NOT DETECTED.
1 = OVER VOLTAGE FAULT DETECTED.
WHEN OVDH_ALARM_FLAG IS SET, AN OVER VOLTAGE FAULT CONDITION
WAS DETECTED ON CHANNEL x DUTx PIN ACCORDING TO THE THRESHOLD SET
IN THE OVDH DAC REGISTER. THIS FLAG IS SUBORDINATE TO THE
OVD_ALARM_MASK_x CONTROL BIT, AND IT IS AUTOMATICALLY RESET
AFTER ANY READ FROM THE ALARM STATE REGISTER.
OVDL_ALARM_FLAG_x[0]
UNDER VOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1
[0] = UNDER VOLTAGE FAULT NOT DETECTED.
1 = UNDER VOLTAGE FAULT DETECTED.
WHEN OVDL_ALARM_FLAG IS SET, AN UNDER VOLTAGE FAULT CONDITION
WAS DETECTED ON CHANNEL x DUTx PIN ACCORDING TO THE THRESHOLD SET
IN THE OVDL DAC REGISTER. THIS FLAG IS SUBORDINATE TO THE
OVD_ALARM_MASK_x CONTROL BIT, AND IT IS AUTOMATICALLY RESET
AFTER ANY READ FROM THE ALARM STATE REGISTER.
Figure 124. Alarm State Register (ADDR = 0x1E) (Read Only)
Rev. 0 | Page 61 of 80
ADATE318
SPI CLOCK INDEX
DATA-WORD INDEX
10 11 12 13 14 15 16 17 18 19 20
21 22 23
24 25
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DRV_CLC_x[15:13]
DRIVER CABLE LOSS COMPENSATION,
CHANNEL 0/CHANNEL 1
[000] = DISABLE DRIVER CLC.
001 = ENABLE DRIVER MINIMUM CLC.
111 = ENABLE DRIVER MAXIMUM CLC.
WHEN SET TO 0x00, THE DRIVER ON CHANNEL x HAS
ZERO CABLE LOSS COMPENSATION (CLC) ADDED
TO ITS OUTPUT CHARACTERISTIC. WHEN SET TO A
VALUE OTHER THAN 0x00, CABLE LOSS COMPENSATION
PRE-EMPHASIS IS ADDED AND THE PERCENTAGE
IS CONTROLLED BY THE REGISTER VALUE.
RESERVED[12:11]
RESERVED
NWC_CLC_x[10:8]
NORMAL WINDOW COMPARATOR CABLE LOSS COMPENSATION,
CHANNEL 0/CHANNEL 1
[000] = DISABLE NWC CLC.
001 = ENABLE NWC MINIMUM CLC.
111 = ENABLE NWC MAXIMUM CLC.
WHEN SET TO 0x00, THE NORMAL WINDOW COMPARATOR (NWC) ON CHANNEL x
HAS NO CABLE LOSS COMPENSATION (CLC) ADDED TO THE INPUT ADDED TO
THE INPUT WAVEFORM CHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN
0x00, PRE-EMPHASIS IS ADDED AND THE PERCENTAGE IS CONTROLLED BY
THE VALUE IN THIS REGISTER.
RESERVED[7:6]
RESERVED
DMC_CLC[5:3]
DIFFERENTIAL MODE COMPARATOR CABLE LOSS COMPENSATION, CHANNEL 0 ONLY
[000] = DISABLE DMC CLC.
001 = ENABLE DMC MINIMUM CLC.
111 = ENABLE DMC MAXIMUM CLC.
WHEN SET TO 0x00, THE DIFFERENTIAL MODE COMPARATOR (ON CHANNEL 0 ONLY)
HAS NO CABLE LOSS COMPENSATION (CLC) ADDED TO THE INPUT WAVEFORM
CHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN 0x00, PRE-EMPHASIS IS ADDED
AND THE PERCENTAGE IS CONTROLLED BY THE VALUE IN THIS REGISTER.
RESERVED[2:0]
RESERVED
Figure 125. CLC Control Register (ADDR = 0x1F)
Rev. 0 | Page 62 of 80
ADATE318
LEVEL SETTING DACS
operation can address corresponding DACs on both channels at
the same time even though the channels may be configured
with different DAC update modes. In such a case, the part
behaves as expected. For example, if both channels are in
immediate update mode, the update of analog levels of both
DAC UPDATE MODES
The ADATE318 provides 24- × 16-bit integrated level setting
DACs organized as two channel banks of 12 DACs each. The
detailed mapping of the DAC register to pin electronics
function is shown in Table 19. Each DAC can be programmed
by writing data to the respective SPI register address and
channel.
channel banks begins after the associated release of the
pin.
CS
If both channels are in deferred update mode, the update of
analog levels is deferred for both channels until the corres-
ponding DAC_LOAD bits are set. If one channel is in deferred
update mode and the other channel is in immediate update
mode, the former channel defers analog updates until the
corresponding DAC_LOAD bit is written, and the latter
channel begins analog updates immediately after the associated
The ADATE318 provides two methods for updating analog
DAC levels: DAC immediate update mode and DAC deferred
update mode. At release of the
pin associated with any valid
CS
SPI write to a DAC address, the update of analog levels may
start immediately1, or it can be deferred, depending on the state
of the DAC_LOAD_MODE control bits in the DAC control
register (SPI ADDR 0x11[1] (see Figure 116)). The DAC update
mode can be selected independently for each channel bank.
release of the
pin.
CS
An on-chip deglitch circuit with a period of approximately 3 μs
is provided to prevent DAC-to-DAC crosstalk whenever an
analog update is processed. Only one deglitch circuit is
provided per chip, and it must operate over all physical DACs
(both channels) at the same time. The deglitch circuit can be
retriggered when an analog levels update is initiated before a
previous update operation has completed. In the case of a dual-
channel immediate mode DAC write using a single SPI
command, the deglitch circuit is triggered once after data is
loaded into both DAC channels. Analog transitions at the DAC
outputs do not begin until the deglitch circuit has timed out,
and final settling to full precision requires an additional 7 μs
beyond the end of the 3 μs deglitch interval. Total settling time
If the DAC_LOAD_MODE control bit for a given channel bank
is cleared, the DACs assigned to that channel are then in the
DAC immediate update mode. Writing to any DAC of that
channel causes the corresponding analog level to be updated
immediately following the associated release of . Because all
CS
analog levels are updated on a per-channel basis, any previously
pending DAC writes queued to the channel (while in deferred
update mode) are also updated at this time. This situation can
arise if DAC writes are queued to the channel while in deferred
update mode, and the DAC_LOAD_MODE bit is subsequently
changed to immediate update mode before the analog levels are
updated by writing to the respective DAC_LOAD soft pin. The
queued data is not lost. Note that writing to the DAC_LOAD
soft pin has no effect in immediate update mode.
following release of the associated
is approximately 10 μs.
CS
Note that prolonged and consecutive retriggering of the deglitch
circuit by one channel may cause the apparent settling time of
analog levels on the other channel to be much longer than the
specified 10 μs.
If the DAC_LOAD_MODE control bit for a given channel is set,
the DACs assigned to that channel are in the deferred update
mode. Writing to any DAC of that channel only queues the
DAC data into that channel. The analog update of queued DAC
levels is deferred until the respective DAC_LOAD soft pin is set
(SPI ADDR 0x11[2] (see Figure 116)). The DAC deferred
update mode, in conjunction with the respective DAC_LOAD
soft pin, provides the means to queue all DAC level writes to a
given channel bank before synchronously updating the analog
levels with a single SPI command.
A typical DAC update sequence is illustrated in Figure 126 in
which two immediate mode DAC update commands are
written in direct succession. This example illustrates what
happens when a DAC update command is written subsequent
to a previous update command that has not yet finished its
deglitch and settling sequence.
Recommended Sequence for OVDH DAC Level
Addressing
Certain pin electronics functions, such as VHH, OVDH,
OVDL, and the spare DAC, do not fit neatly within a particular
channel bank. However, they must be updated as a part of the
channel bank to which they are assigned as shown in Table 19.
For correct OVDH addressing, first write data to the OVDH
DAC level at SPI 0x0C at CH0. If in DAC immediate mode, the
OVDH data write must be followed by either a DAC_LOAD
command to SPI 0x11[2] at CH1 or a subsequent write to any
other CH1 DAC data address before the OVDH value will be
updated. If in DAC deferred mode, the OVDH DAC level write
must be followed by a DAC_LOAD command to SPI 0x11[2] at
CH1 (not CH0) before the analog OVDH value will be updated.
The ADATE318 provides a feature in which a single SPI write
operation can address two channels at one time (see Figure 115).
This feature makes possible a scenario in which a SPI write
1 Initiation of the analog level update sequence (and triggering of the on-chip
deglitch circuit) actually begins four SCLK cycles following the associated
CS
release of the pin. For the purpose of this discussion, it is assumed to start
CS
.
coincident with the release of
Rev. 0 | Page 63 of 80
ADATE318
tSPI
SCLK
CS
WRITE DAC
WRITE DAC
1
SDI
0
SEE TABLE 18
NOTE 1
SEE TABLE 18
NOTE 1
BUSY
±0.5 LSB
DAC
DAC
DAC
0
1
2
BEGINNING OF 3µs
DEGLITCH PERIOD
RETRIGGER OF 3µs
DEGLITCH PERIOD
COMPLETION OF 3µs
DEGLITCH PERIOD
DAC
23
3µs
NOTES
1. DAC DEGLITCH PERIOD ALWAYS BEGINS FOUR
SCLK CYCLES BEFORE RELEASE OF BUSY.
tDAC
Figure 126. SPI DAC Write and Settling Time
Addressing M and C Registers
Some DACs have pairs of m/c-coefficients that are controlled depending on other register status. Table 20 details the specific register
settings and register addresses for the different pairs (X = don’t care).
Table 20. M- and C-Register Mapping
PPMU_
LOAD_
PPMU_
MEAS_
SPI
VHH_
DMC_
PPMU_
Address
(Channel)
DAC
Name
Functional (DAC
Usage) Description
m-
register
c-
ENABLE
0x18[0]
ENABLE
0x1C[0]
ENABLEx
0x19[5]
POWERx
0x1A[15]
VIx
0x1A[5]
PPMU_FORCE
_VIx 0x1A[4]
RANGEx
(0x1A[3:1])
register
0x0D[0]
0x04[0]
OVDL
VOH0
Overvoltage detect low
0x2D[0]
0x24[0]
0x3D[0]
0x34[0]
X
X
X
0
X
X
X
0
X
X
X
X
XXX
XXX
NWC high level,
Channel 0
DMC high level
0x44[0]
0x45[0]
0x5C[0]
0x5D[0]
X
X
1
X
X
0
1
X
0
X
X
XXX
XXX
PPMU go/no-go MV
high level, Channel 0
X
PPMU go/no-go MI
Range A high level,
Channel 0
0x46[0]
0x47[0]
0x48[0]
0x49[0]
0x4A[0]
0x5E[0]
0x5E[0]
0x5E[0]
0x5E[0]
0x5E[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
111
110
101
100
0XX
PPMU go/no-go MI
Range B high level,
Channel 0
PPMU go/no-go MI
Range C high level,
Channel 0
PPMU go/no-go MI
Range D high level,
Channel 0
PPMU go/no-go MI
Range E high level,
Channel 0
Rev. 0 | Page 64 of 80
ADATE318
PPMU_
MEAS_
VIx
LOAD_
ENABLEx
0x19[5]
PPMU_
POWERx
0x1A[15]
SPI
Address
(Channel)
VHH_
ENABLE
0x18[0]
DMC_
ENABLE
0x1C[0]
PPMU_
RANGEx
(0x1A[3:1])
DAC
Name
Functional (DAC
Usage) Description
m-
register
c-
PPMU_FORCE
_VIx 0x1A[4]
register
0x1A[5]
0x05[0]
VOL0
NWC low level,
Channel 0
0x25[0]
0x35[0]
X
0
X
0
X
X
XXX
DMC low level
0x4B[0]
0x4C[0]
0x63[0]
0x64[0]
X
X
1
X
X
0
1
X
0
X
X
XXX
XXX
PPMU go/no-go MV low
level, Channel 0
X
PPMU go/no-go MI
Range A low level,
Channel 0
0x4D[0]
0x4E[0]
0x4F[0]
0x50[0]
0x51[0]
0x65[0]
0x65[0]
0x65[0]
0x65[0]
0x65[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
111
110
101
100
0XX
PPMU go/no-go MI
Range B low level,
Channel 0
PPMU go/no-go MI
Range C low level,
Channel 0
PPMU go/no-go MI
Range D low level,
Channel 0
PPMU go/no-go MI
Range E low level,
Channel 0
0x08[0]
0x09[0]
0x02[0]
VIOH0
VIOL0
Load IOH level,
Channel 0
0x28[0]
0x29[0]
0x22[0]
0x42[0]
0x21[0]
0x41[0]
0x23[0]
0x43[0]
0x26[0]
0x52[0]
0x27[0]
0x53[0]
0x2A[0]
0x54[0]
0x55[0]
0x56[0]
0x57[0]
0x58[0]
0x38[0]
0x39[0]
0x32[0]
0x5A[0]
0x31[0]
0x59[0]
0x33[0]
0x5B[0]
0x36[0]
0x6A[0]
0x37[0]
0x6B[0]
0x3A[0]
0x6C[0]
0x6C[0]
0x6C[0]
0x6C[0]
0x6C[0]
X
X
X
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
111
110
101
100
0XX
Load IOL level,
Channel 0
VIT0/
VCOM0
Drive term level,
Channel 0
Load commutation
voltage, Channel 0
1
0x01[0]
0x03[0]
0x06[0]
0x07[0]
0x0A[0]
VIH0
Drive high level,
Channel 0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HVOUT drive high level,
Channel 0
VIL0
Drive low level,
Channel 0
HVOUT drive low level,
Channel 0
VCH0
VCL0
PPMU0
Ref clamp high level,
Channel 0
PPMU clamp high level,
Channel 0
Ref clamp low level,
Channel 0
PPMU clamp low level,
Channel 0
PPMU VIN FV level,
Channel 0
PPMU VIN FI Range A
level, Channel 0
PPMU VIN FI Range B
level, Channel 0
PPMU VIN FI Range C
level, Channel 0
PPMU VIN FI Range D
Level, Channel 0
PPMU VIN FI Range E
level, Channel 0
0x0B[0]
0x0C[0]
VHH
VHH level
0x2B[0]
0x2C[0]
0x3B[0]
0x3C[0]
X
X
X
X
X
X
X
X
X
X
X
X
XXX
XXX
OVDH
Overvoltage detect
high
Rev. 0 | Page 65 of 80
ADATE318
PPMU_
MEAS_
VIx
LOAD_
ENABLEx
0x19[5]
PPMU_
POWERx
0x1A[15]
SPI
Address
(Channel)
VHH_
ENABLE
0x18[0]
DMC_
ENABLE
0x1C[0]
PPMU_
RANGEx
(0x1A[3:1])
DAC
Name
Functional (DAC
Usage) Description
m-
register
c-
PPMU_FORCE
_VIx 0x1A[4]
register
0x1A[5]
0x04[1]
VOH1
NWC high level,
Channel 1
0x24[1]
0x45[1]
0x46[1]
0x34[1]
0x5D[1]
0x5E[1]
X
X
X
X
X
X
X
X
X
0
1
1
X
0
1
X
X
X
XXX
XXX
111
PPMU go/no-go MV
high level, Channel 1
PPMU go/no-go MI
Range A high level,
Channel 1
PPMU go/no-go MI
Range B high level,
Channel 1
0x47[1]
0x48[1]
0x49[1]
0x4A[1]
0x5E[1]
0x5E[1]
0x5E[1]
0x5E[1]
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
110
101
100
0XX
PPMU go/no-go MI
Range C high level,
Channel 1
PPMU go/no-go MI
Range D high level,
Channel 1
PPMU go/no-go MI
Range E high level,
Channel 1
0x05[1]
VOL1
NWC low level,
Channel 1
0x25[1]
0x4C[1]
0x4D[1]
0x35[1]
0x64[1]
0x65[1]
X
X
X
X
X
X
X
X
X
0
1
1
X
0
1
X
X
X
XXX
XXX
111
PPMU go/no-go MV low
level, Channel 1
PPMU go/no-go MI
Range A low level,
Channel 1
PPMU go/no-go MI
Range B low level,
Channel 1
0x4E[1]
0x4F[1]
0x50[1]
0x51[1]
0x65[1]
0x65[1]
0x65[1]
0x65[1]
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
110
101
100
0XX
PPMU go/no-go MI
Range C low level,
Channel 1
PPMU go/no-go MI
Range D low level,
Channel 1
PPMU go/no-go MI
Range E low level,
Channel 1
0x08[1]
0x09[1]
0x02[1]
VIOH1
VIOL1
Load IOH level,
Channel 1
0x28[1]
0x29[1]
0x22[1]
0x42[1]
0x21[1]
0x23[1]
0x26[1]
0x52[1]
0x27[1]
0x53[1]
0x2A[1]
0x54[1]
0x55[1]
0x56[1]
0x57[1]
0x58[1]
0x38[1]
0x39[1]
0x32[1]
0x5A[1]
0x31[1]
0x33[1]
0x36[1]
0x6A[1]
0x37[1]
0x6B[1]
0x3A[1]
0x6C[1]
0x6C[1]
0x6C[1]
0x6C[1]
0x6C[1]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
111
110
101
100
0XX
Load IOL level,
Channel 1
VIT1/
VCOM1
Drive term level,
Channel 0
Load commutation
voltage, Channel 1
0x01[1]
0x03[1]
0x06[1]
VIH1
VIL1
Drive high level,
Channel 1
Drive low level,
Channel 1
VCH1
Ref clamp high level,
Channel 1
PPMU clamp high level,
Channel 1
0x07[1]
0x0A[1]
VCL1
Ref clamp low level,
Channel 1
PPMU clamp low level,
Channel 1
PPMU1
PPMU VIN FV level,
Channel 1
PPMU VIN FI Range A
level, Channel 1
PPMU VIN FI Range B
level, Channel 1
PPMU VIN FI Range C
level, Channel 1
PPMU VIN FI Range D
level, Channel 1
PPMU VIN FI Range E
level, Channel 1
Rev. 0 | Page 66 of 80
ADATE318
PPMU_
MEAS_
VIx
LOAD_
ENABLEx
0x19[5]
PPMU_
POWERx
0x1A[15]
SPI
Address
(Channel)
VHH_
ENABLE
0x18[0]
DMC_
ENABLE
0x1C[0]
PPMU_
RANGEx
(0x1A[3:1])
DAC
Name
Functional (DAC
Usage) Description
m-
register
c-
PPMU_FORCE
_VIx 0x1A[4]
register
0x1A[5]
0x0E[0]
Spare
Spare level
0x2E[0]
0x3E[1]
X
X
X
X
X
X
XXX
DAC TRANSFER FUNCTIONS
Table 21. Detailed DAC Code to Voltage Level Transfer Functions
Programmable DAC
Range1, 0x0000 to
Levels
0xFFFF
DAC-to-Level and Level-to-DAC Transfer Functions
VIHx, VILx, VITx/VCOMx,
VOLx, VOHx, VCHx, VCLx,
OVDHx, OVDLx
−2.5 V to +7.5 V
VOUT = 2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) + VDUTGND
DAC = [VOUT − VDUTGND + 0.5 × (VREF − VREFGND)] × [(216)/(2 × (VREF − VREFGND))]
VHH
−3.0 V to +17.0 V
−12.5 mA to +37.5 mA
−2.5 V to +7.5 V
VOUT = 4 × (VREF − VREFGND) × (DAC/216 ) − 0.6 × (VREF − VREFGND) + VDUTGND
DAC = [VOUT − VDUTGND + 0.6 × (VREF − VREFGND)] × [216/(4 × (VREF − VREFGND))]
IOHx, IOLx
IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND)] × (25 mA/5)
DAC = [(IOUT × (5/25 mA)) + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]
PPMU_VINx (FV)
VOUT = 2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) + VDUTGND
DAC = [VOUT − VDUTGND + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]
PPMU_VINx (FI, Range A)
PPMU_VINx (FI, Range B)
PPMU_VINx (FI, Range C)
PPMU_VINx (FI, Range D)
PPMU_VINx (FI, Range E)
−80 mA to +80 mA
−2 mA to +2 mA
−200 μA to +200 μA
−20 μA to +20 μA
−4 μA to +4 μA
IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (80 mA/5)
DAC = [(IOUT × (5/80 mA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]
IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) − 2.5] × (2 mA/5)
DAC = [(IOUT × (5/2 mA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]
IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) − 2.5] × (200 μA/5)
DAC = [(IOUT × (5/200 μA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]
IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (20 μA/5)
DAC = [(IOUT × (5/20 μA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]
IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (4 μA/5)
DAC = [(IOUT × (5/4 μA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]
1 Programmable ranges include the margin outside the specified performance range, allowing for offset and gain calibration.
Table 22. Load Transfer Functions
Load Level
Transfer Functions
Notes
IOLx
IOHx
VIOLx/( VREF − VREFGND) × 25 mA
VIOHx/( VREF − VREFGND) × 25 mA
VIOLx and VIOHx DAC levels are not referenced to VDUTGND.
Table 23. PPMU Transfer Functions
PPMU
Mode
Uncalibrated PPMU_VIN DAC Settings to Achieve
Specified PPMU Range
Transfer Functions1
FV
VOUT = PPMU_VINx
−2.0 V < PPMU_VINx < +6.5 V
MV
MV
FI
VPPMU_MEASx = VDUTx (internal sense path)
VPPMU_MEASx = VPPMU_Sx (external sense path)
IOUT = [PPMU_VINx − (VREF − VREFGND)/2]/(5 × RPPMU)
VPPMU_MEASx = [VREF − VREFGND)/2] + (5 × IOUT × RPPMU) +
VDUTGND
N/A
N/A
0.0 V < PPMU_VINx < 5.0 V
N/A
MI
1 RPPMU = 12.5 Ω for Range A, 500 Ω for Range B, 5.0 kΩ for Range C, 50 kΩ for Range D, and 250 kΩ for Range E.
Table 24. VHH Transfer Functions
VHH Mode
Transfer Functions
VHH
VIL
HVOUT = 2 × [VHH + (VREF − VREFGND)/5] + VDUTGND
HVOUT = VIL0 + VDUTGND
VIH
HVOUT = VIH0 + VDUTGND
Rev. 0 | Page 67 of 80
ADATE318
that the new X2 value is calculated correctly following the new
data write, provided the desired m and c values are stored in
advance. The sequence of operations is critical in that the mode
or range change must be performed prior to writing the new
DAC data, and both m and c values must be present before the
new DAC data is written. The m and/or c value can be written
either before or after a mode or range change but must be
written prior to the DAC data to have the intended effect.
GAIN AND OFFSET CORRECTION
Each DAC within the ADATE318 has independent gain (m)
and offset (c) correction registers that allow digital trim of gain
and offset errors. DACs that are shared between functions or
levels are provided with per-level or per-function gain and
offset correction registers, as appropriate. These registers
provide the ability to calibrate out errors in the complete signal
chain, which includes error in pin electronics function as well as
the DACs. All m- and c-registers are volatile and must be
loaded after power-on as part of a calibration cycle if values
other than the defaults are required.
SAMPLE CALCULATIONS OF M AND C
Because the ADATE318’s on-chip DACs have a theoretical
output range that exceeds the operating capabilities of the
remainder of its signal channels, calibration points must be
chosen to be within the normal operating span. Subject to this
constraint, calibration is straightforward. One of the keys to
understanding the calibration method is to recognize that the
intrinsic DAC offset is defined by its output when the input
code is 0x0000. This is quite different from the case of the
analog signal paths, where a 0 V level occurs when the DAC
code is programmed to near quarter-scale.
The gain and offset correction function can be bypassed by
clearing the DAC_CAL_ENABLE bit in the SPI DAC contol
register (SPI ADDR 0x11[0]; see Figure 116). This bypass mode
is available on a per-chip basis only; that is, it is not possible to
bypass calibration for a subset of the DACs.
The calibration function, when enabled, adjusts the numerical
data sent to each DAC according to the following equation:
m 1
X2
X
c 2n1
As a first example, consider the calibration of a drive high level
with a theoretical output span of −2.5 V to 7.5 V, a convenient
10.0 V span in which DAC quarter-scale corresponds to
precisely 0.0 V out. The ADATE318 drivers do not of course
support this full span, but it is a useful choice for illustration of
the calibration methodology.
1
2n
where:
X2 = the data-word loaded into the DAC and returned by an SPI
read operation.
X1 = the 16-bit data-word written to the DAC SPI input register.
m = the code in the respective DAC gain register (default code
= 0xFFFF = 2n − 1).
1. Set the channel to drive high and program the VIL and
VIT DACs for roughly −1.0 V outputs (Code 0x2700, not
critical). Program the VIH DAC to quarter-scale (0x4000)
and measure Output Voltage V1; then program the DAC to
three-quarter-scale (0xC000) and measure Output Voltage
V2. Note that V1 and V2 should be measured with respect to
DUTGND.
c = the code in the respective DAC offset register (default code
= 0x8000 = 2n−1).
n = the DAC resolution (n = 16).
From this equation, it can be seen that the gain applied to the X1
value is always less than or equal to 1.0, with the effect that a
DAC’s output voltage can only be made smaller. To compensate
for this numerically imposed limitation, the ADATE318’s signal
paths are designed to have gain guaranteed to be greater than
1.0 when the default m values (0xFFFF) are applied. This
guarantees that proper gain calibration is always possible. Note
also that the value of c is expressed in raw DAC LSBs; that is, it
is calculated without considering the effect of the m-register.
2. Calculate
Actual _ DAC _ FSR 2
V2 V1
where (V2 − V1) represents half the full-scale span.
3. Calculate the extrapolated DAC voltage at Code 0x0000.
Actual _ DAC _ FSR
V V
0
1
4
When enabled, the calibration function applies the above
operation to the X2 register(s) only after a SPI write to the
respective X1 register(s). The X2 registers are not updated after
writes to either the m- or c-register. In the case of a dual
channel write to the DAC, two respective X2 registers are
sequentially updated using the appropriate m and c values.
4. Calculate
Actual _ DAC _ LSB
V2 V1
32,768
5. Calculate
X2 REGISTERS
5
m
65,536 1
Each DAC has associated with it a single X2 register. There is no
provision for storing separate X2 values for DACs shared
between functions or ranges. Thus, new data must be written to
any shared DAC after a mode or range change is performed,
even if the old and new DAC data is identical. The ADATE318
provides separate m- and c-registers for all ranges and modes so
V2 V1
6. Calculate the offset from the ideal −2.5 V.
Offset 2.5 V0
Rev. 0 | Page 68 of 80
ADATE318
7. Calculate
c 32,768
3. Calculate the offset from the desired −1.5 V.
Offset 1.5 V0
4. Calculate DAC
Offset
Actual _ DAC _ LSB
Offset
Actual _ DAC _ LSB
8. Calculate volts
c 32,768
5
Post _Calibration _ DAC _ LSB Actual _ DAC _ LSB
5. Calculate
Post _ Calibration _ DAC _ LSB
V2 V1
8
Volts
The above procedure places the DAC’s theoretical 0x0000
65,536
output at −2.5 V and its theoretical 0xFFFF output at 7.49985 V
(1 LSB below +7.5 V). The useful range extends from below
0x199A (−1.5 V) to above 0xE666 (+6.5 V), a span of at least
52,428 actual DAC codes.
An alternative calibration approach can be used to map all 216
DAC codes onto the part’s specified output range by mapping
the zero-code to −1.5 V and the full-scale code to +6.5 V.
Although this second approach gives an apparent 16 bits of
resolution covering the full signal range, it must be kept in
mind that this is achieved purely by mathematical alteration of
the DAC data. The DAC’s internal LSB step size is not changed.
In this example, the number of internal DAC codes used to
cover the signal span remains roughly 52,428 even though the
number of user codes has increased to 65,536. A consequence
of this is that apparent DNL errors are increased as more input
codes are mapped onto the same number of DAC codes. While
the second calibration method is included here as an example of
what is possible, its use can provide a false sense of improved
accuracy and it is therefore not recommended.
1. Repeat Step 1 to Step 4 above.
2. Calculate
4
m
65,535
V2 V1
Rev. 0 | Page 69 of 80
ADATE318
POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY
The ADATE318 product is internally divided into a digital core
and an analog core.
(with the exception of VIOH and VIOL active load currents and
VPMU when in PPMU FI mode) are adjusted relative to this
DUTGND input. Further, the PPMU measure out pins
(PPMU_MEASx) are referenced to DUTGND not AGND.
This, therefore, requires the system ADC to reference its inputs
relative to DUTGND as well. Referencing the system ADC to
AGND results in errors, except in the case that DUTGND is tied
to AGND. For applications that do not distinguish between DUT
ground reference and system analog ground reference, the
DUTGND pin can be connected to the same ground plane
as AGND.
The VCC and DGND pins provide power and ground,
respectively, for the digital core, which includes the SPI and all
digital calibration functions. DGND is the logic ground
reference for the VCC supply, and VCC should be adequately
bypassed to DGND with low ESR bypass capacitors. To reduce
transient digital switching noise coupling from the VCC and
DGND pins to the analog core, DGND should be connected to
a dedicated ground domain that is separate from the analog
ground domains. If the application permits, the DGND should
share digital ground domain with the system FPGA or ASIC
that interfaces with the ADATE318 SPI. All CMOS inputs and
outputs are referenced between VCC and DGND, and their
valid levels should be guaranteed relative to these.
The ADATE318 should have ample supply decoupling of 0.1 μF
on each supply pin located as close to the device as possible,
ideally right up against the device. In addition, there should be
one 10 μF tantalum capacitor shared across each power domain.
The 0.1 μF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESL), such as the
common ceramic capacitors that provide a low impedance path
to ground at high frequencies to handle transient currents due
to internal logic switching.
The analog core of the product includes all analog ATE
functional blocks such as DACs, driver, comparator, load,
PPMU, VHH driver, and so on. The VPLUS, VDD, and VSS
supplies provide power for the analog core. The AGND and
PGND are analog ground and analog power ground references,
respectively. PGND is generally more noisy with analog
switching transients, and it may also have large static dc
currents. The AGND is generally more quiet and has relatively
small static dc currents. Ideally, these ground domains should
be separated, but it is not necessary. They can be connected
together outside the chip to a shared analog ground plane. VDD
and VSS should be adequately bypassed to the PGND ground
domain. Both PGND and AGND (whether separated or shared)
should be kept separate from the DGND ground plane as
discussed above.
Digital lines running under the device should be avoided
because these couple noise onto the device. The analog ground
plane should be allowed to run under the device to avoid noise
coupling. The power supply lines should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching digital
signals should be shielded with digital ground to avoid radiating
noise to other parts of the board and should never be run near
the reference inputs. It is essential to minimize noise on all
VREF lines. Avoid crossover of digital and analog signals.
Traces on opposite sides of the board should run at right angles
to each other. This reduces the effects of feedthrough
The VPLUS supply pin has the sole purpose to provide high
voltage power for the VHH drive capability (HVOUT pin). If
the VHH drive capability is used, the VPLUSsupply must be
provided as specified. If the VHH drive capability is not used,
the VPLUS supply can be connected directly to the VDD supply
domain to save power.
throughout the board. As is the case for all thin packages, care
must be taken to avoid flexing the package and to avoid a point
load on the surface of this package during the assembly process.
The ADATE318 also has a DUTGND input pin that can be used
to sense the remote DUT ground potential. All DAC functions
Rev. 0 | Page 70 of 80
ADATE318
USER INFORMATION AND TRUTH TABLES
Table 25. Driver Truth Table1
DCL Control Register Bits (0x19)
High Speed Inputs
DCL Enable
ADDR
0x19[0]
Force Load
ADDR
0x19[2]
Force Drive Force State
Load Enable
ADDR
0x19[5]
ADDR
0x19[1]
ADDR
0x19[4:3]
DRV_VT_HIZ
ADDR 0x19 [6]
Driver
Low leakage
VIL
VIH
High-Z
VIT
VIL
VIH
High-Z
VIT
RCVx
DATx
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
0
XX
00
01
10
11
XX
XX
XX
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
0
0
1
1
X
X
X
X
X
0
1
X
X
1 X = don’t care.
Table 26. Active Load Truth Table1
DCL Control Register Bits (0x19)
Force Drive Force State Load Enable
High Speed Inputs
DCL Enable
ADDR
Force Load
ADDR
ADDR
ADDR
ADDR
DRV_VT_HIZ
Load
0x19[0]
0x19[2]
0x19[1]
0x19[4:3]
0x19[5]
ADDR 0x19 [6]
RCVx
DATx
0
1
1
1
1
1
X
1
0
0
0
0
X
X
X
X
X
X
XX
XX
XX
XX
XX
XX
X
X
0
1
1
1
X
X
X
X
0
1
X
X
X
0
1
1
X
X
X
X
X
X
Low leakage
Active on
Low leakage
Active off
Active on
Active off
1 X = don’t care.
Table 27. VHH and VIH/VIL Driver Truth Table1
VHH_ENABLE ADDR 0x18[0]
CH0 RCV (RCV0) CH0 DAT (DAT0) Output of VHH Driver
1
1
1
0
0
0
1
X
0
1
X
X
VIL (Channel 0, VIL DAC)
VIH (Channel 0, VIH DAC)
VHH
Disabled (HVOUT pin set to 0.0 V, approximately 50 Ω impedance)
1 X = don’t care.
Table 28. Comparator Truth Table
DMC ENABLE
ADDR 0x1C[0] CMPH0
CMPL0
CMPH1
CMPL1
0
Normal window compare
mode
Normal window compare
mode
Normal window compare
mode
Normal window compare
mode
Logic high: VOH0 < VDUT0 Logic high: VOL0 < VDUT0
Logic low: VOH0 > VDUT0 Logic low: VOL0 > VDUT0
Logic high: VOH1 < VDUT1
Logic low: VOH1 > VDUT1
Logic high: VOL1 < VDUT1
Logic low: VOL1 > VDUT1
1
Differential compare mode Differential compare mode Normal window compare
Normal window compare
mode
mode
Logic high:
Logic high:
Logic high: VOH1 < VDUT1
Logic low: VOH1 > VDUT1
Logic high: VOL1 < VDUT1
Logic low: VOL1 > VDUT1
VOH0 < VDUT0 – VDUT1
Logic low:
VOL0 < VDUT0 − VDUT1
Logic low:
VOH0 > VDUT0 – VDUT1
VOL0 > VDUT0 − VDUT1
Rev. 0 | Page 71 of 80
ADATE318
ALARM FUNCTIONS
The ADATE318 contains per-channel overvoltage detectors
(OVD), PPMU voltage/current clamps, and a per-chip thermal
alarm to detect and signal fault conditions. The status of these
circuits may be interrogated via the SPI by reading the alarm
state register (SPI ADDR 0x1E; see Figure 124). This read-only
register is cleared by a read operation. In addition, the fault
conditions are combined in the fault alarm logic (see Figure 137)
The various alarm circuits are controlled through the alarm
mask register (ADDR 0x1D; see Figure 123). In the default
state, the thermal alarm is enabled, and both the overvoltage
alarm and the PPMU clamp alarms are masked off.
The only function of the alarm circuits is to detect and signal
the presence of a fault. The only actions taken upon detection of
a fault are setting of the appropriate register bit and activating
and drive the open drain
pin to signal that a fault has
ALARM
the
pin.
ALARM
occurred.
PPMU EXTERNAL CAPACITORS
Table 29. PPMU External Compensation and Feedforward Capacitors
External Components
Location
220 pF
220 pF
1000 pF
1000 pF
Between FFCAPB0 and FFCAPA0
Between FFCAPB1 and FFCAPA1
Between AGND and SCAP0
Between AGND and SCAP1
Table 30. Other External Components
External Components
Location
10 kΩ
1 kΩ
ALARM pull-up to VCC
BUSY pull-up to VCC
TEMPERATURE SENSOR
Table 31.
Temperature
0 K
Output
0.00 V
300 K
3.00 V
TKELVIN
0.00 V + (TKELVIN ) × 10 mV/K
Rev. 0 | Page 72 of 80
ADATE318
DEFAULT TEST CONDITIONS
Table 32.
Name
Default Test Condition
VIHx DAC Levels
VITx/VCOMx DAC Levels
VILx DAC Levels
VOHx DAC Levels
VOLx DAC Levels
VCHx DAC Levels
VCLxDAC Levels
VIOHxDAC Levels
VIOLx DAC Levels
PPMU_VINx DAC Levels
VHH DAC Level
OVDH DAC Levels
OVDL DAC Levels
DAC_CONTROL
VHH_CONTROL
DCL_CONTROL
PPMU_CONTROL
2.0 V
1.0 V
0.0 V
6.5 V
−1.5 V
7.5 V
−2.5 V
0.0 mA
0.0 mA
0.0 V
13.0 V
7.0 V
−2.0 V
0x0000: DAC calibration disabled, DAC load mode is immediate
0x0000: HVOUT (VHH) disabled
0x0001: DCL enabled, load disabled, high-Z for RCVx = 1, force drive = 0 (to VIL state)
0x0000: PPMU disabled, PPMU Range E, Force-V1/Measure-V2, input to VDUTGND, internal sense path,
clamps disabled, external PPMU_S open, PPMU_POWER_x off
PPMU_MEAS_CONTROL
COMPARATOR_CONTROL
ALARM_MASK
0x0000: PPMU_MEASx high-Z
0x0000: normal window comparator mode, comparator hysteresis disabled
0x0045: disable alarm functions
PRE_EMPHASIS_CONTROL
Calibration m-Coefficients
Calibration c-Coefficients
DATx, RCVx Inputs
0x0000: disable driver CLC, differential comparator CLC, and normal window comparator CLC
1.0 (0xFFFF)
0.0 (0x8000)
Logic low
DUTx Pins
CMPHx, CMPLx Outputs
VDUTGND
Unterminated
Unterminated
0.0 V
1 Force-V indicates force voltage.
2 Measure-V indicates measure voltage.
Rev. 0 | Page 73 of 80
ADATE318
DETAILED FUNCTIONAL BLOCK DIAGRAMS
DAC
VCHx
ADDR 0x06, CHx
DAC
PMU CLAMP LEVELS
SHARED WITH HIGH
SPEED DCL CLAMPS
HIGH-Z
VCLx
ADDR 0x07, CHx
(IDEAL CLAMP DIODES)
TERM
DRV_RCV_MODE
(SEE THE DRIVER LOGIC DIAGRAM)
0
1
DAC
VIT/VCCMx
ADDR 0x02, CHx
DAC
VIHx
1
0
50Ω
0
ADDR 0x01, CHx
DUTx
DAC
VILx
DRV
ADDR 0x03, CHx
DATx
DRV_RCV_SW
(SEE THE DRIVER LOGIC DIAGRAM)
DRV_LOW_LEAK
(SEE THE DRIVER LOGIC DIAGRAM)
Figure 127. Driver Block Diagram
DCL_ENABLE
ADDR 0x19[0]
DRV_LOW_LEAK
FORCE_DRV
ADDR 0x19[1]
DRV_LOW_LEAK = DCL_ENABLE
DRV_RCV_MODE = DRIVE_VT_HIZ + FORCE_DRV × FORCE_STATE[0]
DRV_RCV_SW = FORCE_DRV × FORCE_STATE[1] + FORCE_DRV × RCVx
FORCE_STATE[1]
ADDR 0x19[4]
FORCE_STATE[0]
ADDR 0x19[3]
DRV_VT_HIZ
ADDR 0x19[6]
RCVx
DRV_RCV_MODE
(SEE THE DRIVER BLOCK DIAGRAM)
DRV_RCV_SW
(SEE THE DRIVER BLOCK DIAGRAM)
Figure 128. Driver Logic Diagram
Rev. 0 | Page 74 of 80
ADATE318
ADATE318
DAT
100Ω
DAT
RCV
TO DRIVER,
LOAD, AND VHH
100Ω
RCV
0.0V ≤ V
CM
≤ 3.3V
≤ 1.0V
200mV ≤ V
DM
TYPICAL INPUT WAVEFORMS
DAT
DAT
1.30V
V
V
= 1.20V
= 200mV
CM
DM
V
DM
1.10V
V
CM
RCV
RCV
1.25V
0.95V
V
V
= 1.10V
= 300mV
CM
DM
V
DM
V
CM
Figure 129. Driver Input Stage Diagram
50Ω
FROM DRIVER
DUTx
LOAD_CONNECT
(SEE THE ACTIVE LOAD LOGIC DIAGRAM)
DAC
VIOL
ADDR 0x09
DAC
VIT/VCOM
ADDR 0x2
DAC
VIOH
ADDR 0x08
ACTIVE LOAD
LOAD_PWR_DOWN
(SEE THE ACTIVE LOAD LOGIC DIAGRAM)
Figure 130. Active Load Block Diagram
DCL_ENABLE
ADDR 0x19[0]
FORCE_LOAD
ADDR 0x19[2]
LOAD_CONNECT
(SEE THE ACTIVE LOAD BLOCK DIAGRAM)
LOAD_ENABLE
ADDR 0x19[5]
DRV_VT_HIZ
ADDR 0x19[6]
RCVn
LOAD_PWR_DOWN
(SEE THE ACTIVE LOAD BLOCK DIAGRAM)
LOAD_CONNECT = DCL_ENABLE × (FORCE_LOAD + RCVn × DRV_VT_HIZ × LOAD_ENABLE)
LOAD_PWR_DOWN = DCL_ENABLE + FORCE_LOAD × LOAD_ENABLE
Figure 131. Active Load Logic Diagram
Rev. 0 | Page 75 of 80
ADATE318
DAC
VHH
<5Ω
VHH (NOTE 1)
VHH DRIVER
VDUTGND
HVOUT
VIL (NOTE 2)
VIH (NOTE 2)
DAC
DAC
VIL
50Ω
50Ω
VL/VH
VIH
DRIVER
DAT0
RCV0
VHH_EN
NOTES
1. VHH = 2 × (DAC
+ (V
REF
– V
REFGND
)/5 + V
DUTGND
) – V
DUTGND
VHH
+ V
2. VIL = DAC
; VIH = DAC
DUTGND VIH
+ V
DUTGND
VIL
Figure 132. VHH and VIL/VIH Driver Block Diagram
DAC
VHH
DAC
VIH
HVOUT
DAC
VIL
0.0V
VHH_ENABLE
ADDR 0x18[0]
L
H
RCV0
DAT0
L
H
L
L
DON’T CARE
DON’T CARE
L
H
L
H
L
DON’T CARE
H
H
Figure 133. VHH and VIL/VIH Waveform Diagram
Rev. 0 | Page 76 of 80
ADATE318
DAC
VOH0
0
1
ADDR 0x04
COMPH
COMPH
DUT0
DAC
VOL0
ADDR 0x05
DMC_ENABLE
ADDR 0x1C[0]
DAC
VOH0
0
1
COMPL
COMPL
DAC
VOL0
DIFFERENTIAL
COMPARATOR ON
CHANNEL 0 ONLY
TO DUT1
Figure 134. Comparator Block Diagram
0.5V ≤ VTT_EXT ≤ VTTCx
VTTC
ADATE318
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
CMP
CMP
≥ 250mV
OUTPUT
WAVEFORM
VTTC
VHI = VTTC – 25mV
10mA
VLO = VTTC – 275mV
Figure 135. Comparator Output Stage Diagram
Rev. 0 | Page 77 of 80
ADATE318
PPMU_CLAMP_ENABLE_x
ADDR 0x1A[9], CHx
DAC
VCH
ADDR 0x06, CHx
DAC
PMU CLAMP LEVELS
SHARED WITH HIGH
SPEED DCL CLAMPS
PPMU_S_ENABLE_x
ADDR 0x1A[11], CHx
VCL
ADDR 0x07, CHx
PMU_Sx
1.2K
PPMU_INPUT_SEL_x
ADDR 0x1A[7:6], CHx
PPMU_ENABLE_x
ADDR 0x1A[0], CHx
VDUTGND
2.5V + VDUTGND
0
1
2
3
R
PPMU
DAC
F-AMP
I-AMP
DUTx
PPMU
ADDR 0x0A, CHx
PPMU_RANGE_x
ADDR 0x1A[3:1], CHx
CURRENT
VOLTAGE
VREF/2 + VDUTGND
A
= 5.0
V
PPMU_FORCE_E_VI_x
ADDR 0x1A[4], CHx
PPMU_MEAS_VI_x
ADDR 0x1A[5], CHx
A
= 1.0
PPMU_Sx
V
PPMU_SENSE_PATH_x
ADDR 0x1A[8], CHx
PPMU_MEAS_SEL_x
ADDR 0x1B[1], CHx
0
1
PPMU_MEASx
(RELATIVE TO VDUTGND)
RANGE
40mA
1mA
R
PPMU
×1
CH0: THERM OUT
CH1: THERM GND
12.5Ω
500Ω
5kΩ
PPMU_MEAS_ENABLE_x
100µA
10µA
2µA
ADDR 0x1B[0], CHx
PPMU_CMPHx
50kΩ
250kΩ
VOH x
ADDR 0x04, CHx
PPMU_CMPLx
PPMU GO/NO-GO COMPARATOR DAC LEVELS ARE
SHARED WITH THE HIGH SPEED PE COMPARATOR.
WHEN PPMU IS NOT IN ACTIVE MODE, PPMU
GO/NO-GO COMPARATORS ARE NOT USED AND
THEIR OUTPUTS ARE FORCED TO STATIC LOW.
VOL x
ADDR 0x05, CHx
PPMU_ENABLE_x
ADDR 0x1A[0], CHx
PPMU_POWER_x
ADDR 0x1A[15], CHx
0
1
X
0
PPMU IS POWERED DOWN.
PPMU IS IN FULL-POWER STANDBY MODE BUT NOT YET ENABLED TO
FORCE V/FORCE I. USE THIS MODE FOR FAST INTERNAL SETTLING OF
LEVELS PRIOR TO ENABLING ACTIVE MODE TO MINIMIZE PPMU GLITCHING.
1
1
PPMU IS IN FULL-POWER ACTIVE MODE.
Figure 136. PPMU Block Diagram
Rev. 0 | Page 78 of 80
ADATE318
NOTE: DEDICATED OVERVOLTAGE WINDOW COMPARATORS
ARE PROVIDED FOR EACH CHANNEL. ONLY ONE CHANNEL
IS SHOWN HERE. THE DAC
BETWEEN CHANNELS.
, LEVELS ARE SHARED
OVDx
DAC
OVDH
ADDR 0x0C, CH0
DUTx
V
CC
DAC
OVDL
ALARM
ADDR 0x0D, CH0
V
CC
OVD_ALARM_MASK_x
ADDR 0x1D[0], CHx
D
Q
Q
THERM_ALARM_MASK
ADDR 0x1D[3], CH0
THERM_THRESHOLD
ADDR 0x1D[6:4], CH0
RESET BY READING
FROM SPI ALARM
STATE REGISTER
ADDR 0x1E, CHx
THERM
(10mV/K)
TEMPERATURE
SENSOR
(10mV/K)
PPMU_ALARM_MASK_x
ADDR 0x1D[2], CHx
NOTE: DEDICATED PPMU CLAMP INDICATORS
ARE PROVIDED FOR EACH CHANNEL. ONLY
ONE CHANNEL IS SHOWN HERE.
FROM PPMUx
CLAMP INDICATOR
Figure 137. Fault Alarm Block Diagram
Rev. 0 | Page 79 of 80
ADATE318
OUTLINE DIMENSIONS
0.60
0.42
0.24
10.00
0.35
0.60
0.42
0.24
BSC SQ
(SEE NOTE 2)
0.25
(SEE NOTE 2)
1
63
84
64
PIN 1
INDICATOR
9.75
BSC SQ
0.40
BSC
EXPOSED PAD
(SEE NOTE 1)
6.85
6.75 SQ
6.65
0.93
0.83
0.73
0.60
0.50
0.40
21
22
42
43
TOP VIEW
BOTTOM VIEW
8.00 REF
0.70
0.60
0.50
0.70
0.65
0.60
12° MAX
0.90
0.85
0.80
0.05 MAX
0.01 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-262-VHHE.
NOTES:
1. FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
2. TIEBARS MUST BE SOLDERED TO THE BOARD.
Figure 138. 84-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-84-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADATE318BCPZ
TJ = +25°C to +70°C
84-Lead LFCSP_VQ with Exposed Pad
CP-84-2
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09530-0-4/11(0)
Rev. 0 | Page 80 of 80
相关型号：
ADAU1361BCPZ
SPECIALTY CONSUMER CIRCUIT, QCC32, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
ROCHESTER
ADAU1361BCPZ-R7
SPECIALTY CONSUMER CIRCUIT, QCC32, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
ROCHESTER
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