ADAU1513ASVZ-RL7 [ADI]
Class-D Audio Power Stage; D类音频功率级
| 型号： | ADAU1513ASVZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Class-D Audio Power Stage |
| 文件： | 总16页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Class-D Audio Power Stage
ADAU1513
FEATURES
GENERAL DESCRIPTION
Integrated stereo power stage
The ADAU1513 is a 2-channel bridge-tied load (BTL)
Class-D audio power stage. The power stage can drive the
speaker loads of 4 Ω at up to 15 W per channel at high
efficiency. The 4-channel audio system can be formed when
used with an ADAV4201 pulse-width modulator (PWM)
processor using two ADAU1513s. The power stage accepts a
3.3 V logic differential PWM as input from an ADAV4201
processor. The power stage comprises thermal and output
short-circuit protection with logic-level error flag outputs for
interfacing to a system microcontroller along with reset and
mute control of the power stage. The power stage operates from
a range of power supply voltages from 9 V up to 18 V. The low
power digital logic operates from a 3.3 V supply. The power
stage can be used with modulators other than the ADAV4201.
Contact your local sales department for application assistance.
R
DS-ON < 0.3 Ω (per transistor)
Efficiency > 90%
Short-circuit protection
Overtemperature protection
APPLICATIONS
Flat panel televisions
PC audio systems
Mini components
FUNCTIONAL BLOCK DIAGRAM
PVDD
INL+
INL–
A1
A2
OUTL+
PGND
PVDD
B1
B2
OUTL–
INR+
INR–
PGND
PVDD
LEVEL SHIFT
AND DEAD
TIME CONTROL
C1
C2
OUTR+
PGND
PVDD
AVDD
AGND
VOLTAGE
REFERENCE
D1
D2
OUTR–
PGND
TEMPERATURE/
OVERCURRENT
PROTECTION
MODE CONTROL
LOGIC
DVDD
ADAU1513
DGND
STDN MUTE ERR OTW
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADAU1513
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 12
Overview ..................................................................................... 12
Power Stage ................................................................................. 12
Protection Circuits ..................................................................... 12
Thermal Protection.................................................................... 12
Overcurrent Protection ............................................................. 12
Undervoltage Protection ........................................................... 12
Automatic Recovery from Protections.................................... 12
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Performance Summary................................................................ 3
Power Supplies .............................................................................. 3
Digital I/O ..................................................................................... 4
PWM Input Logic Table .............................................................. 4
Digital Timing............................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Description .............................. 6
Typical Performance Characteristics ............................................. 8
MUTE
STDN
...................................................................... 13
and
Power-Up/Power-Down Sequence .......................................... 13
Applications Information.............................................................. 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADAU1513
SPECIFICATIONS
DVDD = 3.3 V, AVDD = 3.3 V, PVDD = 15 V, ambient temperature = 25°C, load impedance = 8 Ω, measurement bandwidth = 20 Hz to
20 kHz, unless otherwise noted. Audio performance test data measured with ADAV4201.
PERFORMANCE SUMMARY
Table 1.
Parameter
OUTPUT POWER1
Min Typ
Max Unit Test Conditions/Comments
1 kHz
11
14
14.5
17.5
19
W
W
W
W
W
W
%
1% THD + N, 8 Ω
10% THD + N, 8 Ω
1% THD + N, 6 Ω
10% THD + N, 6 Ω
1% THD + N, 4 Ω
10% THD + N, 4 Ω
POUT = 15 W
23
EFFICIENCY
90
RDS-ON
Per High-Side Transistor
Per Low-Side Transistor
280
250
mΩ
mΩ
ID = 100 mA
ID = 100 mA
THERMAL CHARACTERISTICS
Thermal Warning Active2
135
150
5
°C
°C
A
Die temperature
Die temperature
Thermal Shutdown Active
OVERCURRENT SHUTDOWN ACTIVE
TOTAL HARMONIC DISTORTION PLUS NOISE (THD + N)
SIGNAL-TO-NOISE RATIO (SNR)
DYNAMIC RANGE
peak
0.1
96
96
65
5
%
POUT = 1 W, 1 kHz
dB
dB
dB
V
A-weighted, referred to 1% THD + N output
A-weighted, measured with −60 dBFS input
@ 0 dBFS input 20 Hz to 20 kHz
CROSSTALK BETWEEN LEFT AND RIGHT CHANNELS
UNDERVOLTAGE TRIP THRESHOLD
MINIMUM OUTPUT PULSE WIDTH
50
ns
1 Output powers above 15 W at 4 Ω and above 18 W at 6 Ω may need extra heat-sinking for continuous operation.
2 Thermal warning flag is for indication of device TJ reaching close to shutdown temperature.
POWER SUPPLIES
Table 2.
Parameter
Min
3.0
3.0
9
Typ
3.3
3.3
15
Max
3.6
3.6
18
Unit
Test Conditions/Comments
STDN held low
DIGITAL SUPPLY VOLTAGE (DVDD)
V
V
V
ANALOG SUPPLY VOLTAGE (AVDD)
POWER TRANSISTOR SUPPLY VOLTAGE (PVDD)
POWER-DOWN CURRENT
AVDD
DVDD
PVDD
2
50
55
3
55
600
μA
μA
ꢀA
MUTE CURRENT
AVDD
DVDD
MUTE held low
0.5
0.9
0.3
0.6
1.2
0.9
mA
mA
mA
PVDD
OPERATING CURRENT
AVDD
DVDD
STDN and MUTE held high
0.5
1.1
34
0.6
2.5
40
mA
mA
mA
PVDD
Rev. 0 | Page 3 of 16
ADAU1513
DIGITAL I/O
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT VOLTAGE
Input Voltage High
Input Voltage Low
OUTPUT VOLTAGE
Output Voltage High
Output Voltage Low
LEAKAGE CURRENT ON DIGITAL INPUTS
2.0
V
V
0.8
2.4
V
V
@ 2 mA
@ 2 mA
0.4
10
μA
PWM INPUT LOGIC TABLE
Table 4.
MUTE
INL+/INR+
INL−/INR−
OUTL+/OUTR+
OUTL−/OUTR−
Mode
Low
Low/High
Low
High
Low
High
Low/High
Low
Low
High
High
Off
Off
High-Z
High
High
High
High
GND
PVDD
GND
PVDD
GND
GND
PVDD
PVDD
Output damped
Positive output
Negative output
Not used
DIGITAL TIMING
Table 5.
Parameter
Min
Typ
Unit
μs
μs
Description
tSET
tHOLD
tWAIT
10
10
100
Wait Time for Unmute
Wait Time for Shutdown
Wait Time for Applying Input
ns
tPDL-H
tPDH-L
13
13
ns
ns
Propagation Delay (Low to High)
Propagation Delay (High to Low)
tOUTx +/OUTx− MUTE
600
ns
Time Delay After MUTE Held Low Until Output Stops Switching
STDN
MUTE
tSET
tWAIT
INx+/INx–
tPDL-H
tPDH-L
OUTx+/OUTx–
Figure 2. Timing Diagram Unmute
STDN
tHOLD
MUTE
INx+/INx–
OUTx+/OUTx–
tOUTx+/OUTx– MUTE
Figure 3. Timing Diagram Mute
Rev. 0 | Page 4 of 16
ADAU1513
ABSOLUTE MAXIMUM RATINGS
Table 6.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
DVDD to DGND
AVDD to AGND
PVDD to PGND1
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +20.0 V
DGND − 0.3 V to DVDD + 0.3 V
DGND − 0.3 V to DVDD + 0.3 V
−40°C to +85°C
–65°C to +150°C
150°C
PWM Inputs
MUTE/STDN Inputs
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
θJA Thermal Resistance
ESD CAUTION
26.7°C/W
ΨJB Thermal Characterization
(Junction-Board)
13.3°C/W
ΨJT Thermal Characterization
(Junction-Package Top)
0.2°C/W
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
260°C
215°C
220°C
1 Includes any induced voltage due to inductive load.
Rev. 0 | Page 5 of 16
ADAU1513
PIN CONFIGURATION AND FUNCTION DESCRIPTION
OUTL–
OUTL–
OUTL–
OUTL+
OUTL+
OUTL+
INL–
1
2
3
4
5
6
7
8
9
36 OUTR–
35 OUTR–
34 OUTR–
33 OUTR+
32 OUTR+
31 OUTR+
30 TEST13
29 TEST12
28 TEST11
27 TEST10
26 TEST9
25 TEST8
PIN 1
INDICATOR
ADAU1513
TOP VIEW
(Not to Scale)
INL+
ERR
OTW 10
TEST2 11
TEST3 12
NOTES
1. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
PGND, DGND, AND AGND FOR TQFP-48.
2. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
PGND AND DGND FOR LFCSP-48.
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number
Mnemonic Type1
Description
1, 2, 3
4, 5, 6
7
OUTL−
OUTL+
INL−
O
O
I
Output of High Power Transistors, Left Channel Negative Polarity.
Output of High Power Transistors, Left Channel Positive Polarity.
Differential PWM Left Input (−).
8
INL+
I
Differential PWM Left Input (+).
9
ERR
O
O
I
I
I
Overtemperature Shutdown Error Indicator (Active Low Open-Drain Output).
Overtemperature Warning Indicator (Active Low Open-Drain Output).
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DVDD.
Differential PWM Right Input (−).
10
OTW
11
12
13
TEST2
TEST3
INR−
14
INR+
I
Differential PWM Right Input (+).
15
MUTE
STDN
TEST4
TEST5
DGND
DVDD
AVDD
AGND
TEST6
TEST7
TEST8
TEST9
TEST10
TEST11
TEST12
TEST13
OUTR+
I
Mute (Active Low Input).
16
I
Shutdown/Reset Input (Active Low Input).
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31, 32, 33
I
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Do not connect.
Digital Ground for Digital Circuitry. Internally connected to exposed pad (ePAD)2.
Positive Supply for Digital Circuitry.
Positive Supply for Analog Circuitry (Can be Tied to DVDD).
Analog Ground for Analog Circuitry. Internally connected to ePAD2. Can be tied to DGND.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Output of High Power Transistors, Right Channel Positive Polarity.
O
P
P
P
P
I
I
I
I
I
I
I
I
O
Rev. 0 | Page 6 of 16
ADAU1513
Pin Number
Mnemonic Type1
Description
34, 35, 36
37, 38, 47, 48
39, 40, 41, 42, 43, 44, 45, 46
OUTR−
PGND
PVDD
O
P
P
Output of High Power Transistors, Right Channel Negative Polarity.
Power Ground for High Power Transistors. Internally connected to ePAD2.
Positive Power Supply for High Power Transistors.
1 I = input, O = output, P = power.
2
ePAD is connected internally to PGND, DGND, and AGND.
Rev. 0 | Page 7 of 16
ADAU1513
TYPICAL PERFORMANCE CHARACTERISTICS
–20
–20
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
10m
100m
1
10
10m
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 5. THD + N vs. Output Power, 9 V, 4 Ω
Figure 8. THD + N vs. Output Power, 12 V, 4 Ω
–20
–20
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
10m
100m
1
10
10m
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 6. THD + N vs. Output Power, 9 V, 6 Ω
Figure 9. THD + N vs. Output Power, 12 V, 6 Ω
–20
–30
–40
–50
–60
–70
–80
–20
–30
–40
–50
–60
–70
–80
10m
100m
1
10
10m
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 10. THD + N vs. Output Power, 12 V, 8 Ω
Figure 7. THD + N vs. Output Power, 9 V, 8 Ω
Rev. 0 | Page 8 of 16
ADAU1513
–20
–30
–40
–50
–60
–70
–80
0
–10
0dBr = OUTPUT POWER AT 1% THD + N
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10m
100m
1
10
0
2
4
6
8
10
12
14
16
18
20
OUTPUT POWER (W)
FREQUENCY (kHz)
Figure 11. THD + N vs. Output Power, 15 V, 4 Ω
Figure 14. FFT, 1 W, 15 V, 8 Ω
0
–10
–20
–30
–40
–50
–60
–70
–80
0dBr = OUTPUT POWER AT 1% THD + N
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10m
100m
1
10
0
2
4
6
8
10
12
14
16
18
20
OUTPUT POWER (W)
FREQUENCY (kHz)
Figure 12. THD + N vs. Output Power, 15 V, 6 Ω
Figure 15. FFT, 60 dBFS, 15 V, 8 Ω
–20
–30
–40
–50
–60
–70
–80
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
10m
100m
1
10
0
2
4
6
8
10
12
14
16
18
20
OUTPUT POWER (W)
FREQUENCY (kHz)
Figure 13. THD + N vs. Output Power, 15 V, 8 Ω
Figure 16. FFT Dither, 15 V, 8 Ω
Rev. 0 | Page 9 of 16
ADAU1513
0
–5
90
80
70
60
50
40
30
20
10
0
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
20
100
1k
10k
0
5
10
15
20
25
30
FREQUENCY (Hz)
OUTPUT POWER (W)
Figure 17. THD + N vs. Frequency, 1 W, 15 V, 8 Ω
Figure 20. Efficiency vs .Output Power, 15 V, 4 Ω
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
90
80
70
60
50
40
30
20
10
0
LEFT TO RIGHT
RIGHT TO LEFT
20
100
1k
10k
0
5
10
15
20
25
FREQUENCY (Hz)
OUTPUT POWER (W)
Figure 21. Efficiency vs. Output Power, 15 V, 6 Ω
Figure 18. Crosstalk, 0 dBFS, 15 V, 8 Ω
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
(°C)
0
5
10
15
20
25
T
OUTPUT POWER (W)
AMBIENT
Figure 19. Power Dissipation vs. Ambient Temperature
Figure 22. Efficiency vs. Output Power, 15 V, 8 Ω
Rev. 0 | Page 10 of 16
ADAU1513
6
5
4
3
2
1
0
30
25
20
15
10
5
REQUIRES EXTRA HEAT-SINKING
4Ω
6Ω
8Ω
0
0
5
10
15
20
25
6
7
8
9
10 11 12 13 14 15 16 17 18
PVDD (V)
OUTPUT POWER PER CHANNEL, STEREO MODE (W)
Figure 26. Power Dissipation vs. Output Power, 6 Ω
Figure 23. Output Power vs. PVDD, 40 dB THD + N
40
35
30
25
20
15
10
5
3
2
1
0
4Ω
6Ω
8Ω
0
6
7
8
9
10 11 12 13 14 15 16 17 18
PVDD (V)
0
5
10
15
20
OUTPUT POWER PER CHANNEL, STEREO MODE (W)
Figure 27. Power Dissipation vs. Output Power, 8 Ω
Figure 24. Output Power vs. PVDD, 20 dB THD + N
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
OUTPUT POWER PER CHANNEL, STEREO MODE (W)
Figure 25. Power Dissipation vs. Output Power, 4 Ω
Rev. 0 | Page 11 of 16
ADAU1513
THEORY OF OPERATION
This error flag is latched type. To restore the normal operation,
MUTE
again. The error flag is useful for the microcontroller in the
system to indicate an abnormal operation and to initiate the
OVERVIEW
(Pin 16ꢀ needs to be toggled to low and then to high
The ADAU1513 is a 2-channel integrated power stage designed
to accept the logic level PWM inputs. The PWM inputs are
amplified, low-pass filtered using a simple passive LC network,
and then can be used to drive the speaker loads. The power
stage has built-in circuits for overtemperature, overcurrent,
short-circuit, and undervoltage protection.
MUTE
audio
sequence. The device senses the short-circuit
condition on the outputs after the LC filter. Typical short-circuit
conditions include shorting of the output load and shorting to
either PVDD or GND.
POWER STAGE
UNDERVOLTAGE PROTECTION
The 2-channel ADAU1513 power stage comprises a total of
eight half bridges. Each half bridge is made up of PMOS and
NMOS devices. The gate drive for the respective FETs is
generated internally and does not need a special gate drive
supply or bootstrap capacitor compared to all NMOS stages.
This simplifies the high-side driver design and requires less
external components.
The ADAU1513 has an undervoltage protection circuit that
senses the undervoltage on PVDD. When the PVDD supply
goes below the operating threshold, the output FETs are turned
to a high-Z condition. Also, the device issues an error flag by
ERR
the operation,
pulling the
pin low. This condition is latched. To restore
MUTE
(Pin 16ꢀ needs to be toggled to low and
then to high again.
PROTECTION CIRCUITS
AUTOMATIC RECOVERY FROM PROTECTIONS
The ADAU1513 includes comprehensive protection circuits.
It includes thermal warning, thermal overheat, and overcurrent
In certain applications, it is desired for the amplifier to recover
itself from thermal protection without the need for system
microcontroller intervention.
ERR
OTW
or short-circuit protection on the outputs. The
and
outputs are open drain, requiring external pull-up resistors.
The outputs are capable of sinking 10 mA. The open-drain
outputs are useful in multichannel applications where more
than one ADAU1513 are used. The error outputs of multiple
ADAU1513s can be OR’ed to simplify the system design. The
logic outputs of the error flags ease the system design using a
microcontroller.
The ADAU1513 thermal protection circuit issues two error
OTW
signals for this purpose: one thermal warning (
ERR
ꢀ and the
other thermal shutdown (
ꢀ.
With these two error signals, there are two options for using the
protections:
OTW
ERR
•
•
Option 1: Using
Option 2: Using
The power stage does not consist of protection in case PWM
input stays high continuously. In such a case, the output pro-
duces dc and it is possible to damage the speaker. To prevent
this, ensure that the modulator is switching whenever the power
stage is turned on.
The following sections provide further details of these two
options.
OTW
Option 1: Using
THERMAL PROTECTION
OTW
The
pin is pulled low when the die temperature reaches
130°C to 135°C This pin can be wired to the
an RC circuit as shown in Figure 28.
Thermal protection in the ADAU1513 is categorized into two
error flags: one as thermal warning and the other as thermal
shutdown. When the device junction temperature reaches near
135°C ( 5°Cꢀ the ADAU1513 outputs a thermal warning error
MUTE
pin using
DVDD
ADAU1513
OTW
R1
flag by pulling
(Pin 10ꢀ low. This flag can be used by the
100kΩ
D1
1N4148
microcontroller in the system as an indication to the user or can
be used to lower the input level to the amplifier to prevent the
thermal shutdown. The device continues operation until
shutdown temperature is reached.
10
TO MUTE
LOGIC INPUT
OTW
C1
47µF
15
MUTE
When the device junction temperature exceeds 150°C the
Figure 28. Option 1 Schematic for Autorecovery
ERR
device outputs an error flag by pulling the
(Pin 9ꢀ low. This
MUTE
OTW
MUTE
pin.
The low logic level on
also pulls down the
error flag is latched. To restore the operation,
(Pin 16ꢀ
The bridge is shut down and, therefore, starts cooling or the
die temperature starts reducing. When it reaches 120°C, the
needs to be toggled to low and then to high again.
OVERCURRENT PROTECTION
OTW
signal starts going high. While this pin is tied to a
The overcurrent protection in the ADAU1513 is set internally at
5 A peak output current. The device protects the output devices
capacitor with a resistor pulled to DVDD, the voltage on this
pin starts rising slowly towards DVDD. When it reaches the
ERR
against excessive output current by pulling the
(Pin 9ꢀ low.
MUTE
input logic high threshold, is deasserted and the
Rev. 0 | Page 12 of 16
ADAU1513
amplifier starts functioning again. This cycle repeats itself
depending on the input signal conditions and the temperature
of the die. This option allows part operation that is safely below
the shutdown temperature of 150°C and allows the amplifier to
recover itself without the need for microcontroller intervention.
POWER-UP/POWER-DOWN SEQUENCE
Figure 30 shows the recommended power-up sequence for the
ADAU1513.
AVDD/DVDD
ERR
Option 2: Using
PVDD
STDN
ERR
Option 2 is similar to Option 1 if the
pin can be tied to
MUTE
OTW
. See the circuit in Figure 29.
instead of
tSET
DVDD
ADAU1513
MUTE
tWAIT
R1
100kΩ
D1
INx+/INx–
1N4148
9
TO MUTE
LOGIC INPUT
ERR
OUTx+/OUTx–
C1
47µF
tPDL-H
15
MUTE
Figure 30. Recommended Power-Up Sequence
Figure 29. Option 2 Schematic for Autorecovery
The ADAU1513 does not have any pop-and-click suppression
circuits; therefore, care must be taken during the power-up. The
power stage stays in Hi-Z on power-up. However, it is recom-
In this case, the part goes into shutdown mode due to any of the
error-generating events like output overcurrent, overtemperature,
missing PVDD or DVDD, or clock loss. The part recovers itself
based on the same circuit operation in Figure 28.
STDN
MUTE
mended to ensure that
initial power-up. First,
and
should be pulled high followed by
are held low during
STDN
MUTE
after the
to turn on the power stage. The power stage turns on
However, if the part goes into error mode due to overtempera-
ture, then the device would have reached its maximum limit of
150°C (15°C to 20°C higher than Option 1). If it goes into error
mode due to an overcurrent from a short circuit on the speaker
outputs, then the part will keep itself recycling on and off until
the short circuit is removed.
MUTE
signal is pulled high and responds to PWM
inputs after a small propagation delay of 200 μs.
The special turn-on sequence may be necessary depending on
the PWM used to prevent the turn-on pop or click. However, if
the ADAV4201 processor is used, the processor has a built-in
special turn-on PWM sequence. The processor sends a unique
PWM input start sequence that ensures soft turn-on.
It is possible that, with this operation, the part is subjected to a
much higher temperature and current stress continuously. This,
in turn, reduces the part’s reliability in the long term. Therefore,
using Option 1 for autorecovery from the thermal protection
and using the system microcontroller to indicate to the user of
an error condition is recommended.
If another modulator is used, care must be taken to ensure that
the modulator has built-in pop-and-click suppression. Also,
because the power stage does not track the PWM inputs, it is
recommended to use the system microcontroller to ensure that
the modulator is ready to send the PWM sequence before
turning on the power stage.
MUTE AND STDN
MUTE
STDN
are 3.3 V logic-compatible inputs used
The
to control the turn-on/turn-off for ADAU1513.
STDN
and
Similarly, for muting the amplifier, it may be necessary to
supply a special muting PWM sequence for minimum pop and
click. The ADAV4201 processor has a built-in feature that takes
care of this need. If any other modulator is used, care must be
taken during muting of the power stage.
The
input is active low when the
pin is pulled low
and the device is in its energy-saving mode. The power stage is
STDN
STDN
in high-Z state. The high logic level input on the
pin will
wake up the device. The logic circuits are running internally but
the power stage is still in high-Z state.
The system microcontroller can be used to handle the
mute/unmute of the power stage as well as a modulator.
MUTE
When the
and starts responding to PWM inputs. The low level on the
MUTE
pin is pulled high, the power stage is active
The error outputs of the power stage should be connected to
the microcontroller port. This error flag can be used to inform
the modulator that the power stage is shut down and to mute
the PWM inputs. On removal of the error condition, the
microcontroller should initiate an unmute sequence to mini-
mize pop and click while power stage is turning on/turning off.
pin disables the power stage and is recommended to be
used to mute the audio output. See the Power-Up/Power-Down
Sequence section for more details.
The ADAU1513 uses three separate supplies: AVDD (3.3 V
analog for internal reference), DVDD (3.3 V digital for control
logic and clock oscillator), and PVDD (9 V to 18 V power stage
and level shifter). Separate pins are provided for the AVDD,
Rev. 0 | Page 13 of 16
ADAU1513
DVDD, and PVDD supply connections, as well AGND, DGND,
and PGND.
When using separate AVDD and DVDD supplies, ensure that
both supplies are stable before unmuting or turning on the
power stage.
In addition, the ADAU1513 incorporates a built-in undervoltage
lockout logic on DVDD as well as PVDD. This helps detect
undervoltage operation and eliminates the need to have an
external mechanism to sense the supplies.
STDN
MUTE
and
During power-up, it is recommended to keep
low to ensure that the power stage stays in high-Z mode.
MUTE
Similarly, during shutdown, pulling
to logic low before
down is recommended. However, where a fault
The ADAU1513 monitors the DVDD and PVDD supply
voltages and prevents the power stage from turning on if either
of the supplies are not present or below the operating threshold.
Therefore, if DVDD is missing or below the operating thresh-
old, for example, the power stage will not turn on, even if the
PVDD is present or vice versa.
STDN
pulling
event occurs, the power stage will shut down to protect the part.
In this case, depending on the signal level, there is some pop at
the speaker.
During shutdown of the power supplies to reduce power
consumption, it is highly recommended to mute the amplifier
Because this protection is only present on DVDD and PVDD
and not on AVDD, shorting both AVDD and DVDD externally
or generating AVDD and DVDD from one power source is
recommended. This ensures both AVDD and DVDD supplies
are tracking each other and avoids the need to monitor the
sequence with respect to PVDD. This also ensures minimal
pop and click during power-up.
STDN
first, followed by pulling
low before shutting down any of
the supplies. After MUTE is pulled low, the power supplies can
be shut down in the following order: PVDD, DVDD, then
AVDD. Where AVDD and DVDD are generated from a single
source, ensure that PVDD is tuned off before DVDD and
MUTE
STDN
AVDD, and after issuing
and
.
Rev. 0 | Page 14 of 16
ADAU1513
APPLICATIONS INFORMATION
Refer to the application schematic in Figure 31 for details on connections and component values. For details on the PWM modulator part,
refer to the ADAV4201 data sheet.
For applications with PVDD > 15 V, add components R1 and R2 = 10 Ω typical, C5 and C6 = 680 pF typical, and D1 through D8 = CRS01/02.
3.3V
PVDD
100nF
100nF
100nF
470µF
1µF
100nF
PVDD
L1
L2
D1
D2
OUTL+
R1
C1
C2
10Ω
INL+
PULSE-WIDTH
MODULATOR
ADAV4201
PVDD
INL–
INR+
C5
680pF
D3
D4
OUTL–
INR–
SDA SCL
PVDD
D5
D6
PVDD
L3
L4
OUTR+
OUTR–
R2
C3
C4
10Ω
ADAU1513
C6
680pF
2
I C CONTROL
D7
D8
STDN
SYSTEM LOGIC
CONTROL
MUTE
ERR
OR
MICROCONTROLLER
OTW
Figure 31. Application Schematic
Table 8. Suggested Low-Pass Filter Values
Load Impedance (Ω)
Inductance L1 to L4 (μH)
Capacitance C1 to C4 (μF)
4
6
8
10
15
22
1.5
1
0.68
Rev. 0 | Page 15 of 16
ADAU1513
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 32. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.20
MAX
BOTTOM VIEW
(PINS UP)
37
36
48
37
36
48
1
1
1.00 REF
PIN 1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
5.10
SQ
7.20
7.00 SQ
6.80
EXPOSED
PAD
1.05
1.00
0.95
0.20
0.09
12
25
24
25
24
12
13
13
VIEW A
7°
3.5°
0°
0.27
0.22
0.17
0.50 BSC
LEAD PITCH
0.15
0.05
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ABC
Figure 33. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-48-5)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model
Package Description
ADAU1513ACPZ1
ADAU1513ACPZ-RL1
ADAU1513ACPZ-RL71
ADAU1513ASVZ1
ADAU1513ASVZ-RL1
ADAU1513ASVZ-RL71
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-48-1
CP-48-1
CP-48-1
SV-48-5
SV-48-5
SV-48-5
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13”Tape and Reel
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Tape and Reel
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 13”Tape and Reel
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 7”Tape and Reel
1 Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06750-0-5/07(0)
Rev. 0 | Page 16 of 16
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