ADAV803AST_技术文档

Audio Codec for Recordable DVD

ADAV803

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Stereo analog-to-digital converter (ADC)

Supports 48 kHz/96 kHz sample rates

102 dB dynamic range

Single-ended input

Automatic level control

Stereo digital-to-analog converter (DAC)

Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz

sample rates

PLL

CONTROL

REGISTERS

OLRCLK

VINL

VINR

RECORD

DATA

OUTPUT

ANALOG-TO-DIGITAL

CONVERTER

OBCLK

OSDATA

DIGITAL

INPUT/OUTPUT

REFERENCE

SRC

VREF

OAUXLRCLK

OAUXBCLK

OAUXSDATA

AUX DATA

OUTPUT

SWITCHING MATRIX

(DATA PATH)

101 dB dynamic range

Single-ended output

VOUTL

VOUTR

DIGITAL-TO-ANALOG

CONVERTER

DIT

DITOUT

Asynchronous operation of ADC and DAC

Stereo sample rate converter (SRC)

Input/output range: 8 kHz to 192 kHz

140 dB dynamic range

FILTD

ZEROL/INT

ZEROR

PLAYBACK

DATA INPUT

AUX DATA

INPUT

DIR

ADAV803

Digital interfaces

Record

Playback

Figure 1.

Auxiliary record

Auxiliary playback

APPLICATIONS

S/PDIF (IEC 60958) input and output

Digital interface receiver (DIR)

Digital interface transmitter (DIT)

PLL-based audio MCLK generators

Generates required DVDR system MCLKs

Device control via I²C-compatible serial port

64-lead LQFP package

DVD-recordable

All formats

CD-R/W

GENERAL DESCRIPTION

The ADAV803 is a stereo audio codec intended for applications

such as DVD or CD recorders that require high performance

and flexible, cost-effective playback and record functionality.

The ADAV803 features Analog Devices, Inc. proprietary, high

performance converter cores to provide record (ADC),

playback (DAC), and format conversion (SRC) on a single chip.

The ADAV803 record channel features variable input gain to

allow for adjustment of recorded input levels and automatic

level control, followed by a high performance stereo ADC

whose digital output is sent to the record interface. The record

channel also features level detectors that can be used in

feedback loops to adjust input levels for optimum recording.

The playback channel features a high performance stereo DAC

with independent digital volume control.

The sample rate converter (SRC) provides high performance

sample rate conversion to allow inputs and outputs that require

different sample rates to be matched. The SRC input can be

selected from playback, auxiliary, DIR, or ADC (record). The

SRC output can be applied to the playback DAC, both main and

auxiliary record channels, and a DIT. Operation of the ADAV803

is controlled via an I²C®-compatible serial interface, which

allows the programming of individual control register settings.

The ADAV803 operates from a single analog 3.3 V power

supply and a digital power supply of 3.3 V with an optional

digital interface range of 3.0 V to 3.6 V.

The part is housed in a 64-lead LQFP package and is character-

ized for operation over the commercial temperature range of

−40°C to +85°C.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADAV803

TABLE OF CONTENTS

Features .............................................................................................. 1

DAC Section................................................................................ 18

Sample Rate Converter (SRC) Functional Overview ............ 19

PLL Section ................................................................................. 22

S/PDIF Transmitter and Receiver ............................................ 23

Serial Data Ports......................................................................... 27

Interface Control ............................................................................ 30

I²C Interface ................................................................................ 30

Block Reads and Writes............................................................. 31

Register Descriptions..................................................................... 32

Layout Considerations................................................................... 59

ADC ............................................................................................. 59

DAC.............................................................................................. 59

PLL ............................................................................................... 59

Reset and Power-Down Considerations ................................. 59

Outline Dimensions....................................................................... 60

Ordering Guide .......................................................................... 60

Functional Block Diagram .............................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Conditions............................................................................. 3

ADAV803 Specifications ............................................................. 3

Timing Specifications .................................................................. 7

Temperature Range ...................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Functional Description.................................................................. 15

ADC Section ............................................................................... 15

REVISION HISTORY

7/07—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to ADC Section............................................................... 15

Changes to Figure 25...................................................................... 15

Changes to Figure 33...................................................................... 21

Changes to SRC Architecture Section ......................................... 21

Changes to Table 7.......................................................................... 22

Changes to Figure 36...................................................................... 22

Changes to Figure 39, Figure 40, Figure 41, Figure 42 .............. 23

Changes to Transmitter Operation Section ................................ 27

Changes to Interrupts Section ...................................................... 27

Changes to Figure 50...................................................................... 28

Changes to Table 97........................................................................ 47

Changes to Table 101...................................................................... 48

Changes to Table 136 and Table 137 ............................................ 56

Updated Outline Dimensions....................................................... 60

Changes to Ordering Guide .......................................................... 60

7/04—Revision 0: Initial Version

Rev. A | Page 2 of 60

ADAV803

SPECIFICATIONS

TEST CONDITIONS

Test conditions, unless otherwise noted.

Table 1.

Test Parameter

Condition

Supply Voltage

Analog

3.3 V

Digital

3.3 V

Ambient Temperature

Master Clock (MCLKI)

Measurement Bandwidth

Word Width (All Converters)

Load Capacitance on Digital Outputs

ADC Input Frequency

DAC Output Frequency

Digital Input

25°C

12.288 MHz

20 Hz to 20 kHz

24 bits

100 pF

1007.8125 Hz at −1 dBFS

960.9673 Hz at 0 dBFS

Slave Mode, I²S Justified Format

Digital Output

ADAV803 SPECIFICATIONS

Table 2.

Parameter

Min

Typ

Max

Unit

Comments

PGA SECTION

Input Impedance

Minimum Gain

Maximum Gain

Gain Step

4

0

24

0.5

kΩ

dB

REFERENCE SECTION

Absolute Voltage, V_REF

V_REFTemperature Coefficient

ADC SECTION

1.5

80

V

ppm/°C

Number of Channels

Resolution

2

24

Bits

Dynamic Range

Unweighted

−60 dB input

f_S= 48 kHz

f_S= 96 kHz

f_S= 48 kHz

f_S= 96 kHz

99

98

102

101

dB

A-Weighted

98

Total Harmonic Distortion + Noise

Input = −1.0 dBFS

f_S= 48 kHz

f_S= 96 kHz

−88

−87

dB

Analog Input

Input Range ( Full Scale)

DC Accuracy

1.0

V rms

Gain Error

Interchannel Gain Mismatch

Gain Drift

−1.5

−0.8

0.05

1

dB

mdB/°C

mV

Offset

−10

Rev. A | Page 3 of 60

ADAV803

Parameter

Min

Typ

−110

0.39

−48

∞

Max

Unit

Comments

Crosstalk (EIAJ Method)

Volume Control Step Size (256 Steps)

Maximum Volume Attenuation

Mute Attenuation

Group Delay

dB

% per step

dB

ADC outputs all zero codes

f_S= 48 kHz

f_S= 96 kHz

910

460

μs

ADC LOW-PASS DIGITAL DECIMATION FILTER

CHARACTERISTICS¹

Pass-Band Frequency

Stop-Band Frequency

Stop-Band Attenuation

Pass-Band Ripple

22

44

26

52

120

0.01

kHz

dB

f_S= 48 kHz

f_S= 96 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 48 kHz

f_S= 96 kHz

ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS

Cutoff Frequency

SRC SECTION

Resolution

0.9

24

Hz

f_S= 48 kHz

Bits

Sample Rate

SRC MCLK

8

192

33

kHz

MHz

XIN = 27 MHz

f_S-MAXis the greater of the input or

output sample rate

138 × f_S-

MAX

Maximum Sample Rate Ratios

Upsampling

1:8

Downsampling

7.75:1

Dynamic Range

140

120

20 Hz to f_S/2, 1 kHz, −60 dBFS input,

f_IN= 44.1 kHz, f_OUT= 48 kHz

20 Hz to f_S/2, 1 kHz, 0 dBFS input,

f_IN= 44.1 kHz, f_OUT= 48 kHz

Total Harmonic Distortion + Noise

dB

DAC SECTION

Number of Channels

Resolution

2

24

Bits

Dynamic Range

Unweighted

20 Hz to 20 kHz, −60 dB input

f_S= 48 kHz

f_S= 96 kHz

f_S= 48 kHz

f_S= 96 kHz

99

98

101

100

dB

A-Weighted

97

Total Harmonic Distortion + Noise

Referenced to 1V rms

f_S= 48 kHz

f_S= 96 kHz

−91

−90

dB

Analog Outputs

Output Range ( Full Scale)

Output Resistance

Common-Mode Output Voltage

DC Accuracy

1.0

60

1.5

V rms

Ω

V

Gain Error

Interchannel Gain Mismatch

Gain Drift

−2

−0.8

0.05

1

dB

mdB/°C

mV

+30

DC Offset

−30

Rev. A | Page 4 of 60

ADAV803

Parameter

Min

Typ

Max

Unit

dB

Degrees

dB

Comments

Crosstalk (EIAJ Method)

Phase Deviation

Mute Attenuation

Volume Control Step Size (256 Steps)

Group Delay

−110

0.05

−95.625

0.375

dB

48 kHz

96 kHz

192 kHz

630

155

66

μs

DAC LOW-PASS DIGITAL INTERPOLATION FILTER

CHARACTERISTICS

Pass-Band Frequency

Stop-Band Frequency

Stop-Band Attenuation

Pass-Band Ripple

20

22

42

24

26

60

70

kHz

dB

f_S= 44.1 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 44.1 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 44.1 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 44.1 kHz

f_S= 48 kHz

f_S= 96 kHz

70

0.002

0.005

dB

PLL SECTION

Master Clock Input Frequency

Generated System Clocks

MCLKO

27/54

MHz

× f_S

SYSCLK1

256

768

256/384/512/768 ×

32 kHz/44.1 kHz/48 kHz

256/384/512/768 ×

32 kHz/44.1 kHz/48 kHz

SYSCLK2

× f_S

SYSCLK3

512

256/512 × 32 kHz/44.1 kHz/48 kHz

Jitter

SYSCLK1

SYSCLK2

SYSCLK3

65

75

ps rms

DIR SECTION

Input Sample Frequency

Differential Input Voltage

DIT SECTION

Output Sample Frequency

DIGITAL I/O

Input Voltage High, V_IH

Input Voltage Low, V_IL

Input Leakage, I_IH@ V_IH= 3.3 V

Input Leakage, I_IL@ V_IL= 0 V

Output Voltage High, V_OH@ I_OH= 0.4 mA

Output Voltage Low, V_OL@ I_OL= −2 mA

Input Capacitance

27.2

200

kHz

mV

27.2

2.0

kHz

DVDD

0.8

10

V

μA

V

10

2.4

0.4

15

V

pF

Rev. A | Page 5 of 60

ADAV803

Parameter

POWER

Min

Typ

Max

Unit

Comments

Supplies

Voltage, AVDD

Voltage, DVDD

Voltage, ODVDD

3.0

3.3

3.6

V

Operating Current

Analog Current

Digital Current

Digital Interface Current

DIRIN/DIROUT Current

PLL Current

Power-Down Current

Analog Current

All supplies at 3.3 V

RESET low, no MCLK

60

38

13

mA

5

18

mA

μA

mA

μA

Digital Current

2.5

700

3.5

900

Digital Interface Current

DIRIN/DIROUT Current

PLL Current

Power Supply Rejection

Signal at Analog Supply Pins

−70

dB

1 kHz, 300 mV p-p

20 kHz, 300 mV p-p

¹Guaranteed by design.

Rev. A | Page 6 of 60

ADAV803

TIMING SPECIFICATIONS

Timing specifications are guaranteed over the full temperature and supply range.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Comments

MASTER CLOCK AND RESET

MCLKI Frequency

XIN Frequency

f_MCLK

f_XIN

t_RESET

12.288

27

54

MHz

ns

RESET Low

20

I²C PORT

SCL Clock Frequency

SCL High

SCL Low

f_SCL

t_SCLH

t_SCLL

400

kHz

μs

0.6

1.3

Start Condition

Setup Time

Hold Time

Data Setup Time

SCL Rise Time

SCL Fall Time

SDA Rise Time

SDA Fall Time

Stop Condition

Setup Time

t_SCS

t_SCH

t_DS

t_SCR

t_SCF

t_SDR

t_SDF

0.6

100

μs

ns

Relevant for repeated start condition

After this period, the first clock is generated

300

t_SCS

0.6

μs

SERIAL PORTS¹

Slave Mode

xBCLK High

xBCLK Low

t_SBH

t_SBL

f_SBF

t_SLS

t_SLH

t_SDS

t_SDH

t_SDD

40

64 × f_S

10

ns

xBCLK Frequency

xLRCLK Setup

xLRCLK Hold

xSDATA Setup

xSDATA Hold

xSDATA Delay

Master Mode

xLRCLK Delay

xSDATA Delay

xSDATA Setup

xSDATA Hold

ns

To xBCLK rising edge

From xBCLK rising edge

To xBCLK rising edge

From xBCLK rising edge

From xBCLK falling edge

t_MLD

t_MDD

t_MDS

t_MDH

5

10

ns

From xBCLK falling edge

From xBCLK rising edge

10

¹The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.

TEMPERATURE RANGE

Table 4.

Parameter

Min

Typ

Max

Unit

°C

Specifications Guaranteed

Functionality Guaranteed

Storage

25

−40

−65

+85

+150

°C

Rev. A | Page 7 of 60

ADAV803

ABSOLUTE MAXIMUM RATINGS

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

DVDD to DGND and ODVDD

to DGND

0 V to 4.6 V

AVDD to AGND

Digital Inputs

Analog Inputs

AGND to DGND

Reference Voltage

0 V to 4.6 V

DGND − 0.3 V to DVDD + 0.3 V

AGND − 0.3 V to AVDD + 0.3 V

−0.3 V to +0.3 V

Indefinite short circuit to

ground

ESD CAUTION

Soldering (10 sec)

300°C

Rev. A | Page 8 of 60

ADAV803

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VINR

VINL

ADVDD

ADGND

PLL_LF2

PLL_LF1

PLL_GND

PLL_VDD

DGND

PIN 1

INDICATOR

3

AGND

AVDD

4

5

DIR_LF

DIR_GND

DIR_VDD

RESET

AD0

6

7

ADAV803

TOP VIEW

(Not to Scale)

8

SYSCLK1

SYSCLK2

SYSCLK3

XIN

9

10

11

12

13

14

15

16

SDA

SCL

AD1

XOUT

ZEROL/INT

ZEROR

DVDD

MCLKO

MCLKI

DVDD

DGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

NC = NO CONNECT

Figure 2. ADAV803 Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

I/O

Description

1

2

3

4

VINR

VINL

AGND

AVDD

I

Analog Audio Input, Right Channel.

Analog Audio Input, Left Channel.

Analog Ground.

Analog Voltage Supply.

5

6

7

8

DIR_LF

DIR_GND

DIR_VDD

RESET

AD0

DIR Phase-Locked Loop (PLL) Filter Pin.

Supply Ground for DIR Analog Section. This pin should be connected to AGND.

Supply for DIR Analog Section. This pin should be connected to AVDD.

Asynchronous Reset Input (Active Low).

I

9

I

I²C Address LSB.

10

11

12

13

SDA

SCL

AD1

ZEROL/INT

I/O

I

O

Data Input/Output of I²C-Compatible Control Interface.

Clock Input of I²C Compatible Control Interface.

I²C Address MSB.

Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined by

the INTRPT bit in DAC Control Register 4.

14

15

16

17

18

19

20

21

22

23

24

25

26

ZEROR

DVDD

DGND

ILRCLK

IBCLK

ISDATA

OLRCLK

OBCLK

OSDATA

DIRIN

ODVDD

ODGND

DITOUT

O

Right Channel (Output) Zero Flag.

Digital Voltage Supply.

Digital Ground.

I/O

I

I/O

O

Sampling Clock (LRCLK) of Playback Digital Input Port.

Serial Clock (BCLK) of Playback Digital Input Port.

Data Input of Playback Digital Input Port.

Sampling Clock (LRCLK) of Record Digital Output Port.

Serial Clock (BCLK) of Record Digital Output Port.

Data Output of Record Digital Output Port.

Input to Digital Input Receiver (S/PDIF).

Interface Digital Voltage Supply.

I

Interface Digital Ground.

S/PDIF Output from DIT.

O

Rev. A | Page 9 of 60

ADAV803

Pin No.

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

Mnemonic

I/O

O

I/O

I

Description

OAUXLRCLK

OAUXBCLK

OAUXSDATA

IAUXLRCLK

IAUXBCLK

IAUXSDATA

DGND

DVDD

MCLKI

MCLKO

XOUT

XIN

SYSCLK3

SYSCLK2

SYSCLK1

DGND

PLL_VDD

PLL_GND

PLL_LF1

PLL_LF2

ADGND

ADVDD

VOUTR

NC

VOUTL

NC

AVDD

AGND

FILTD

Sampling Clock (LRCLK) of Auxiliary Digital Output Port.

Serial Clock (BCLK) of Auxiliary Digital Output Port.

Data Output of Auxiliary Digital Output Port.

Sampling Clock (LRCLK) of Auxiliary Digital Input Port.

Serial Clock (BCLK) of Auxiliary Digital Input Port.

Data Input of Auxiliary Digital Input Port.

Digital Ground.

Digital Supply Voltage.

External MCLK Input.

Oscillator Output.

Crystal Input.

I

O

I

Crystal or External MCLK Input.

System Clock 3 (from PLL2).

System Clock 2 (from PLL2).

System Clock 1 (from PLL1).

O

Digital Ground.

Supply for PLL Analog Section. This pin should be connected to AVDD.

Ground for PLL Analog Section. This pin should be connected to AGND.

Loop Filter for PLL1.

Loop Filter for PLL2.

Analog Ground (Mixed Signal). This pin should be connected to AGND.

Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD.

Right Channel Analog Output.

No Connect.

Left Channel Analog Output.

No Connect.

Analog Voltage Supply.

Analog Ground.

Output DAC Reference Decoupling.

Analog Ground.

Voltage Reference Voltage.

Analog Ground.

Analog Voltage Supply.

ADC Modulator Input Filter Capacitor (Right Channel, Negative).

ADC Modulator Input Filter Capacitor (Right Channel, Positive).

Analog Ground.

ADC Modulator Input Filter Capacitor (Left Channel, Positive).

ADC Modulator Input Filter Capacitor (Left Channel, Negative).

O

AGND

VREF

AGND

AVDD

CAPRN

CAPRP

AGND

CAPLP

CAPLN

Rev. A | Page 10 of 60

ADAV803

TYPICAL PERFORMANCE CHARACTERISTICS

0

–50

–100

–150

–50

–100

–150

0

96

192

288

384

0

0.5

1.0

1.5

2.0

FREQUENCY (kHz)

FREQUENCY (Normalized to f )

S

Figure 3. ADC Composite Filter Response

Figure 6. DAC Composite Filter Response, 48 kHz

5

0

–5

–50

–10

–15

–20

–100

–150

–25

–30

12

24

36

48

0

5

10

15

20

FREQUENCY (kHz)

FREQUENCY (Hz)

Figure 7. DAC Pass-Band Filter Response, 48 kHz

Figure 4. ADC High-Pass Filter Response, f_S= 48 kHz

0.06

0.04

0.02

0

5

0

–5

–10

–15

–20

–0.02

–0.04

–0.06

–25

–30

8

16

FREQUENCY (kHz)

24

0

5

10

15

20

FREQUENCY (Hz)

Figure 8. DAC Filter Ripple, 48 kHz

Figure 5. ADC High-Pass Filter Response, f_S= 96 kHz

Rev. A | Page 11 of 60

ADAV803

0

–50

–100

–150

–200

–150

0

384

768

1152

1536

192

384

576

768

FREQUENCY (kHz)

Figure 9. DAC Composite Filter Response, 96 kHz

Figure 12. DAC Composite Filter Response, 192 kHz

0

–2

–4

–50

–6

–100

–150

–8

–10

48

0

24

48

72

96

64

80

FREQUENCY (kHz)

96

FREQUENCY (kHz)

Figure 10. DAC Pass-Band Filter Response, 96 kHz

Figure 13. DAC Pass-Band Filter Response, 192 kHz

0.10

0.05

0

0.50

0.40

0.30

0.20

0.10

0

–0.10

–0.20

–0.30

–0.40

–0.50

–0.05

–0.10

0

24

48

72

96

0

8

16

32

64

FREQUENCY (kHz)

Figure 11. DAC Filter Ripple, 96 kHz

Figure 14. DAC Filter Ripple, 192 kHz

Rev. A | Page 12 of 60

ADAV803

0

DNR = 102dB

THD+N = 95dB

(A-WEIGHTED)

–20

–40

–60

–80

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

0

2

4

6

8

10

12

14

16

18

20

0

5

10

15

20

25

30

35

40

45 48

FREQUENCY (kHz)

Figure 15. DAC Dynamic Range, f_S= 48 kHz

Figure 18. DAC THD + N, f_S= 96 kHz

0

DNR = 102dB

(A-WEIGHTED)

THD+N = 96dB

–20

–40

–60

–80

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

2

4

6

8

10

12

14

16

18

20

5

10

15

20

FREQUENCY (kHz)

Figure 16. DAC THD + N, f_S= 48 kHz

Figure 19. ADC Dynamic Range, f_S= 48 kHz

0

THD+N = 92dB

(V = –3dB)

DNR = 102dB

(A-WEIGHTED)

IN

–20

–40

–60

–80

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

5

10

15

20

25

30

35

40

45 48

5

10

15

20

FREQUENCY (kHz)

Figure 17. DAC Dynamic Range, f_S= 96 kHz

Figure 20. DAC THD + N, f_S= 48 kHz

Rev. A | Page 13 of 60

ADAV803

0

DNR = 102dB

THD+N = 92dB

(A-WEIGHTED)

(V = –3dB)

IN

–20

–40

–60

–80

–20

–40

–60

–80

–100

–120

–140

–100

–120

–140

–160

0

8

16

24

32

40

48

0

8

16

24

32

40

48

FREQUENCY (kHz)

Figure 21. ADC Dynamic Range, f_S= 96 kHz

Figure 22. ADC THD + N, f_S= 96 kHz

Rev. A | Page 14 of 60

ADAV803

FUNCTIONAL DESCRIPTION

Programmable Gain Amplifier (PGA)

ADC SECTION

The input of the record channel features a PGA that converts

the single-ended signal to a differential signal, which is applied

to the analog Σ-Δ modulator of the ADC. The PGA can be

programmed to amplify a signal by up to 24 dB in 0.5 dB

increments. Figure 24 shows the structure of the PGA circuit.

4kΩ TO 64kΩ

The ADAV803’s ADC section is implemented using a second-

order multibit (5 bits) Σ-Δ modulator. The modulator is

sampled at either half of the ADC MCLK rate (modulator clock

= 128 × f_S) or one-quarter of the ADC MCLK rate (modulator

clock = 64 × f_S). The digital decimator consists of a Sinc^5 filter

followed by a cascade of three half-band FIR filters. The Sinc

decimates by a factor of 16 at 48 kHz and by a factor of 8 at

96 kHz. Each of the half-band filters decimates by a factor of 2.

EXTERNAL

CAPACITOR

(1nF NPO)

4kΩ

CAPxN

Figure 23 shows the details of the ADC section. By default, the

ADC assumes that the MCLK rate is 256 times the sample rate.

The ADC can be clocked by a number of different clock sources

to control the sample rate. MCLK selection for the ADC is set

by Internal Clocking Control Register 1 (Address 0x76). The

ADC provides an output word of up to 24 bits of resolution in

twos complement format. The output word can be routed to the

output ports, the sample rate converter, or the S/PDIF digital

transmitter.

125Ω

VREF

EXTERNAL

CAPACITOR

MODULATOR

(1nF NPO)

TO

125Ω

8kΩ

CAPxP

EXTERNAL

CAPACITOR

(1nF NPO)

8kΩ

Figure 24. PGA Block Diagram

Analog Σ-Δ Modulator

The ADC features a second-order, multibit, Σ-Δ modulator. The

input features two integrators in cascade followed by a flash

converter. This multibit output is directed to a scrambler,

followed by a DAC for loop feedback. The flash ADC output is

also converted from thermometer coding to binary coding for

input as a 5-bit word to the decimator. Figure 25 shows the

ADC block diagram.

REG 0x76

BITS[4:2]

The ADC also features independent digital volume control for

the left and right channels. The volume control consists of

256 linear steps, with each step reducing the digital output

codes by 0.39%. Each channel also has a peak detector that

records the peak level of the input signal. The peak detector

register is cleared by reading it.

ADC MCLK REG 0x6F

DIVIDER

BITS[1:0]

ADC

MCLK

ADC

Figure 23. Clock Path Control on the ADC

PEAK

DETECT

HPF

MULTIBIT

VOLUME

CONTROL

Σ-Δ

DECIMATOR

MODULATOR

÷2

÷4

384kHz

768kHz

192kHz

384kHz

96kHz

48kHz

96kHz

HALF-BAND

FILTER

SINC

COMPENSATION

HALF-BAND

FILTER

ADC MCLK

SINC^5

192kHz

MODULATOR

CLOCK

(6.144MHz MAX)

AMC

(REG 0x6E

BIT 7)

Figure 25. ADC Block Diagram

Rev. A | Page 15 of 60

ADAV803

Automatic Level Control (ALC)

No Recovery Mode

The ADC record channel features a programmable automatic

level control block. This block monitors the level of the ADC

output signal and automatically reduces the gain, if the signal at

the input pins causes the ADC output to exceed a preset limit.

This function can be useful to maximize the signal dynamic

range when the input level is not well defined. The PGA can be

used to amplify the unknown signal, and the ALC reduces the

gain until the ADC output is within the preset limits. This

results in maximum front end gain.

By default, there is no gain recovery. Once the gain has been

reduced, it is not recovered until the ALC is reset, either by

toggling the ALCEN bit in ALC Control Register 1 or by

writing any value to ALC Control Register 3. The latter option

is more efficient because it requires only one write operation to

reset the ALC function. No recovery mode prevents volume

modulation of the signal caused by adjusting the gain, which

can create undesirable artifacts in the signal. The gain can be

reduced but not recovered. Therefore, care should be taken that

spurious signals do not interfere with the input signal because

these might trigger a gain reduction unnecessarily.

Because the ALC block monitors the output of the ADC, the

volume control function should not be used. The ADC volume

control scales the results from the ADC, and any distortion

caused by the input signal exceeding the input range of the

ADC is still present at the output of the ADC, but scaled by a

value determined by the volume control register.

Normal Recovery Mode

Normal recovery mode allows for the PGA gain to be recovered,

provided that the input signal meets certain criteria. First, the

ALC must not be in attack mode, that is, the PGA gain has been

reduced sufficiently such that the input signal is below the level

set by the attack threshold bits. Second, the output result from

the ADC must be below the level set by the recovery threshold

bits in the ALC control register. If both of these criteria are met,

the gain is recovered by one step (0.5 dB). The gain is

The ALC block has two functions, attack mode and recovery

mode. Recovery mode consists of three settings: no recovery,

normal recovery, and limited recovery. These modes are

discussed in the following sections. Figure 26 is a flow diagram

of the ALC block. When the ALC has been enabled, any

changes made to the PGA or ALC settings are ignored. To

change the functionality of the ALC, it must first be disabled.

The settings can then be changed and the ALC re-enabled.

incrementally restored to its original value, assuming that the

ADC output level is below the recovery threshold at intervals

determined by the recovery time bits.

If the ADC output level exceeds the recovery threshold while

the PGA gain is being restored, the PGA gain value is held and

does not continue restoration until the ADC output level is

again below the recovery threshold. Once the PGA gain is

restored to its original value, it is not changed again unless the

ADC output value exceeds the attack threshold and the ALC

then enters attack mode. Care should be taken when using this

mode to choose values for the attack and recovery thresholds

that prevent excessive volume modulation caused by continuous

gain adjustments.

Attack Mode

When the absolute value of the ADC output exceeds the level

set by the attack threshold bits in ALC Control Register 2, attack

mode is initiated. The PGA gain for both channels is reduced by

one step (0.5 dB). The ALC then waits for a time determined by

the attack timer bits before sampling the ADC output value

again. If the ADC output is still above the threshold, the PGA

gain is reduced by a further step. This procedure continues until

the ADC output is below the limit set by the attack threshold

bits. The initial gains of the PGAs are defined by the ADC left

PGA gain register and the ADC right PGA gain register, and

they can have different values. The ALC subtracts a common

gain offset to these values. The ALC preserves any gain

difference in dB as defined by these registers. At no time do the

PGA gains exceed their initial values. The initial gain setting,

therefore, also serves as a maximum value.

Limited Recovery Mode

Limited recovery mode offers a compromise between no recov-

ery and normal recovery modes. If the output level of the ADC

exceeds the attack threshold, attack mode is initiated. When

attack mode has reduced the PGA gain to suitable levels, the

ALC attempts to recover the gain to its original level. If the

ADC output level exceeds the level set by the recovery threshold

bits, a counter is incremented (GAINCNTR). This counter is

incremented at intervals equal to the recovery time selection, if

the ADC has any excursion above the recovery threshold. If the

counter reaches its maximum value, determined by the

GAINCNTR bits in ALC Control Register 1, the PGA gain is

deemed suitable and no further gain recovery is attempted.

Whenever the ADC output level exceeds the attack threshold,

attack mode is reinitiated and the counter is reset.

The limit detection mode bit in ALC Control Register 1

determines how the ALC responds to an ADC output that

exceeds the set limits. If this bit is a 1, both channels must

exceed the threshold before the gain is reduced. This mode can

be used to prevent unnecessary gain reduction due to spurious

noise on a single channel. If the limit detection mode bit is a 0,

the gain is reduced when either channel exceeds the threshold.

Rev. A | Page 16 of 60

ADAV803

Selecting a Sample Rate

selecting the lower modulator rate reduces the amount of digital

noise, improving THD + N, but also reduces the oversampling

ratio, therefore reducing the dynamic range by a corresponding

amount.

The output sample rate of the ADC is always ADC MCLK/256,

as shown in Figure 23. By default, the ADC modulator runs at

ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz,

the ADC modulator should be set to run at ADC MCLK/4.

This is achieved by setting the AMC (ADC Modulator Clock)

bit in the ADC Control Register 1. To compensate for the

reduced modulator clock speed, a different set of filters is used

in the decimator section, ensuring that the sample rate remains

the same.

For best performance of the ADC, avoid using similar frequency

clocks from separate sources in the ADAV803. For example,

running the ADC from a 12.288 MHz clock connected to

MCLKI and using the PLL to generate a separate 12.288 MHz

clock for the DAC can reduce the performance of the ADC.

This is due to the interaction of the clocks, which generate beat

frequencies that can affect the charge on the switch capacitors of

the analog inputs.

The AMC bit can also be used to boost the THD + N perform-

ance of the ADC at the expense of dynamic range. The

improvement is typically 0.5 dB to 1.0 dB and works because

ATTACK MODE

WAIT FOR SAMPLE

NO

IS SAMPLE

GREATER THAN ATTACK

THRESHOLD?

NO

IS A RECOVERY

MODE ENABLED?

YES

DECREASE GAIN BY 0.5dB

AND WAIT ATTACK TIME

LIMITED RECOVERY

NORMAL RECOVERY

WAIT FOR SAMPLE

IS SAMPLE

ABOVE ATTACK

THRESHOLD?

IS SAMPLE

ABOVE ATTACK

THRESHOLD?

NO

HAS RECOVERY

TIME BEEN

HAS RECOVERY

TIME BEEN

REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

ARE ALL

SAMPLES BELOW

RECOVERY

NO

THRESHOLD?

YES

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

INCREMENT

GAINCNTR

HAS GAIN BEEN

FULLY RESTORED?

NO

HAS GAIN BEEN

FULLY RESTORED?

YES

NO

YES

IS GAINCNTR

AT MAXIMUM?

YES

NO

Figure 26. ALC Flow Diagram

Rev. A | Page 17 of 60

ADAV803

Selecting a Sample Rate

DAC SECTION

Correct operation of the DAC is dependent upon the data rate

provided to the DAC, the master clock applied to the DAC, and

the selected interpolation rate. By default, the DAC assumes

that the MCLK rate is 256 times the sample rate, which requires

an 8× oversampling rate. This combination is suitable for

sample rates of up to 48 kHz.

The ADAV803 has two DAC channels arranged as a stereo pair

with single-ended analog outputs. Each channel has its own

independently programmable attenuator, adjustable in 128 steps

of 0.375 dB per step. The DAC can receive data from the

playback or auxiliary input ports, the SRC, the ADC, or the

DIR. Each analog output pin sits at a dc level of VREF, and

swings 1.0 V rms for a 0 dB digital input signal. A single op amp

third-order external low-pass filter is recommended to remove

high frequency noise present on the output pins. Note that the

use of op amps with low slew rate or low bandwidth can cause

high frequency noise and tones to fold down into the audio

band. Care should be taken in selecting these components.

For a 96 kHz data rate that has a 24.576 MHz MCLK (256 × f_S)

associated with it, the DAC MCLK divider should be set to

divide the MCLK by 2. This prevents the DAC engine from

running too fast. To compensate for the reduced MCLK rate,

the interpolator should be selected to operate in 4 × (DAC

MCLK = 128 × f_S). Similar combinations can be selected for

different sample rates.

The FILTD and VREF pins should be bypassed by external

capacitors to AGND. The FILTD pin is used to reduce the noise

of the internal DAC bias circuitry, thereby reducing the DAC

output noise. The voltage at the VREF pin can be used to bias

external op amps used to filter the output signals. For

applications in which the VREF is required to drive external

op amps, which might draw more than 50 μA or have dynamic

load changes, extra buffering should be used to preserve the

quality of the ADAV803 reference.

REG 0x76

BITS[7:5]

MCLK

DIVIDER

REG 0x65

BITS[3:2]

The digital input data source for the DAC can be selected from

a number of available sources by programming the appropriate

bits in the datapath control register. Figure 27 shows how the

digital data source and the MCLK source for the DAC are

selected. Each DAC has an independent volume register giving

256 steps of control, with each step giving approximately

0.375 dB of attenuation. Note that the DACs are muted by

default to prevent unwanted pops, clicks, and other noises from

appearing on the outputs while the ADAV803 is being

configured. Each DAC also has a peak-level register that records

the peak value of the digital audio data. Reading the register

clears the peak.

DAC

MCLK

AUXILIARY IN

PLAYBACK

DIR

DAC

INPUT

DAC

ADC

REG 0x63

BITS[5:3]

Figure 27. Clock and Datapath Control on the DAC

PEAK

DETECTOR

TO CONTROL

REGISTERS

DAC

FROM DAC

DATA PATH

MULTIPLEXER

MULTI-BIT

ANALOG

VOLUME/MUTE

CONTROL

INTERPOLATOR

Σ-Δ

OUTPUT

MODULATOR

DAC

TO ZERO FLAG PINS

ZERO DETECT

Figure 28. DAC Block Diagram

Rev. A | Page 18 of 60

ADAV803

SAMPLE RATE CONVERTER (SRC) FUNCTIONAL

OVERVIEW

INTERPOLATE

BY N

LOW-PASS

FILTER

ZERO-ORDER

HOLD

IN

OUT

f_{S_IN}

f_{S_OUT}

During asynchronous sample rate conversion, data can be

converted at the same sample rate or at different sample rates.

The simplest approach to an asynchronous sample rate

conversion is to use a zero-order hold between the two

samplers, as shown in Figure 29. In an asynchronous system, T2

is never equal to T1, nor is the ratio between T2 and T1

rational. As a result, samples at f_{S_OUT}are repeated or dropped,

producing an error in the resampling process.

TIME DOMAIN OF f_{S_IN}SAMPLES

TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER

The frequency domain shows the wide side lobes that result

from this error when the sampling of f_{S_OUT}is convolved with

the attenuated images from the sin(x)/x nature of the zero-order

hold. The images at f_{S_IN}(dc signal images) of the zero-order

hold are infinitely attenuated. Because the ratio of T2 to T1 is an

irrational number, the error resulting from the resampling at

TIME DOMAIN OF f_{S_OUT}RESAMPLING

TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT

f

_{S_OUT}can never be eliminated. The error can be significantly

reduced, however, through interpolation of the input data at

_{S_IN}. Therefore, the sample rate converter in the ADAV803 is

conceptually interpolated by a factor of 2²⁰.

Figure 30. SRC Time Domain

f

In the frequency domain shown in Figure 31, the interpolation

expands the frequency axis of the zero-order hold. The images

from the interpolation can be sufficiently attenuated by a good

low-pass filter. The images from the zero-order hold are now

pushed by a factor of 2²⁰closer to the infinite attenuation point

of the zero-order hold, which is f_{S_IN}× 2²⁰. The images at the

zero-order hold are the determining factor for the fidelity of the

ZERO-ORDER

HOLD

IN

OUT

f_{S_IN}=1/T1

f_{S_OUT}= 1/T2

ORIGINAL SIGNAL

SAMPLED AT f_{S_IN}

output at f_{S_OUT}

.

INTERPOLATE

BY N

LOW-PASS

FILTER

ZERO-ORDER

HOLD

IN

OUT

SIN(X)/X OF ZERO-ORDER HOLD

f_{S_IN}

f_{S_OUT}

SPECTRUM OF ZERO-ORDER HOLD OUTPUT

FREQUENCY DOMAIN OF SAMPLES AT f_{S_IN}

FREQUENCY DOMAIN OF THE INTERPOLATION

f_{S_IN}

SPECTRUM OF f_{S_OUT}SAMPLING

f_{S_OUT}

2 × f_{S_OUT}

FREQUENCY RESPONSE OF f_{S_OUT}CONVOLVED

WITH ZERO-ORDER HOLD SPECTRUM

20

2

× f_{S_IN}

Figure 29. Zero-Order Hold Used by f_{S_ OUT}to Resample Data from f_{S_IN}

Conceptual High Interpolation Model

SIN(X)/X OF ZERO-ORDER HOLD

Interpolation of the input data by a factor of 2²⁰involves placing

(2²⁰− 1) samples between each f_{S_IN}sample. Figure 30 shows

both the time domain and the frequency domain of interpolation

by a factor of 2²⁰. Conceptually, interpolation by 2²⁰involves the

steps of zero-stuffing (2²⁰− 1) number of samples between each

FREQUENCY DOMAIN OF f_{S_OUT}RESAMPLING

20

2

× f_{S_IN}

FREQUENCY DOMAIN

AFTER RESAMPLING

20

× f_{S_IN}

f

_{S_IN}sample and convolving this interpolated signal with a

2

digital low-pass filter to suppress the images. In the time

domain, it can be seen that f_{S_OUT}selects the closest f_{S_IN}× 2²⁰

sample from the zero-order hold, as opposed to the nearest f_{S_IN}

sample in the case of no interpolation. This significantly

reduces the resampling error.

Figure 31. Frequency Domain of the Interpolation and Resampling

Rev. A | Page 19 of 60

ADAV803

The worst-case images can be computed from the zero-order

hold frequency response:

This technique is supported by the Fourier transform property

that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of

decimation is limited by the size of the RAM.

Maximum Image = sin(π × F/f_{S_INTERP})/(π × F/f_{S_INTERP}

where:

F is the frequency of the worst-case image that would be

2²⁰× f_{S_IN}

_{S_IN}/2.

_{S_INTERP}= f_{S_IN}× 2²⁰.

)

SRC Architecture

The architecture of the sample rate converter is shown in

Figure 32. The sample rate converter’s FIFO block adjusts the

left and right input samples and stores them for the FIR filter’s

convolution cycle. The f_{S_IN}counter provides the write address

to the FIFO block and the ramp input to the digital servo loop.

The ROM stores the coefficients for the FIR filter convolution

and performs a high order interpolation between the stored

coefficients. The sample rate ratio block measures the sample

rate for dynamically altering the ROM coefficients and scaling

of the FIR filter length as well as the input data. The digital

servo loop automatically tracks the f_{S_IN}and f_{S_OUT}sample rates

and provides the RAM and ROM start addresses for the start of

the FIR filter convolution.

f

The following worst-case images would appear for f_{S_IN}equal to

192 kHz:

Image at f_{S_INTERP}− 96 kHz = −125.1 dB

Image at f_{S_INTERP}+ 96 kHz = −125.1 dB

Hardware Model

The output rate of the low-pass filter in Figure 30 is the

interpolation rate:

2²⁰× 192,000 kHz = 201.3 GHz

RIGHT DATA IN

Sampling at a rate of 201.3 GHz is clearly impractical, in

addition to the number of taps required to calculate each

interpolated sample. However, because interpolation by 2²⁰

involves zero-stuffing 2²⁰− 1 samples between each f_{S_IN}sample,

most of the multiplies in the low-pass FIR filter are by zero. A

further reduction can be realized because only one interpolated

sample is taken at the output at the f_{S_OUT}rate, so only one

convolution needs to be performed per f_{S_OUT}period instead of

2²⁰convolutions. A 64-tap FIR filter for each f_{S_OUT}sample is

sufficient to suppress the images caused by the interpolation.

ROM A

LEFT DATA IN

FIFO

HIGH

ORDER

INTERP

ROM B

ROM C

ROM D

f_{S_IN}

COUNTER

DIGITAL

SERVO LOOP

FIR FILTER

SAMPLE RATE RATIO

L/R DATA OUT

f_{S_IN}

f_{S_OUT}

SAMPLE

RATE RATIO

EXTERNAL

RATIO

One difficulty with the preceding approach is that the correct

interpolated sample must be selected upon the arrival of f_{S_OUT}

.

Figure 32. Architecture of the Sample Rate Converter

Because there are 2²⁰possible convolutions per f_{S_OUT}period, the

arrival of the f_{S_OUT}clock must be measured with an accuracy of

1/201.3 GHz = 4.96 ps. Measuring the f_{S_OUT}period with a clock

of 201.3 GHz frequency is clearly impossible; instead, several

coarse measurements of the f_{S_OUT}clock period are made and

averaged over time.

The FIFO receives the left and right input data and adjusts the

amplitude of the data for both the soft muting of the sample rate

converter and the scaling of the input data by the sample rate

ratio before storing the samples in the RAM. The input data is

scaled by the sample rate ratio because, as the FIR filter length

of the convolution increases, so does the amplitude of the

convolution output. To keep the output of the FIR filter from

saturating, the input data is scaled down by multiplying it by

(f_{S_OUT}/f_{S_IN}) when f_{S_OUT}< f_{S_IN}. The FIFO also scales the input

data for muting and unmuting of the SRC.

Another difficulty with the preceding approach is the number

of coefficients required. Because there are 2²⁰possible convolu-

tions with a 64-tap FIR filter, there must be 2²⁰polyphase

coefficients for each tap, which requires a total of 2²⁶coeffi-

cients. To reduce the number of coefficients in ROM, the SRC

stores a small subset of coefficients and performs a high order

interpolation between the stored coefficients.

The RAM in the FIFO is 512 words deep for both left and right

channels. An offset to the write address provided by the f_{S_IN}

counter is added to prevent the RAM read pointer from

overlapping the write address. The minimum offset on the SRC

is 16 samples. However, the group delay and mute-in register

can be used to increase this offset.

The preceding approach works when f_{S_OUT}> f_{S_IN}. However,

when the output sample rate, f_{S_OUT}, is less than the input sample

rate, f_{S_IN}, the ROM starting address, input data, and length of

the convolution must be scaled. As the input sample rate rises

over the output sample rate, the antialiasing filter’s cutoff

frequency must be lowered because the Nyquist frequency of

the output samples is less than the Nyquist frequency of the

input samples. To move the cutoff frequency of the antialiasing

filter, the coefficients are dynamically altered and the length of

the convolution is increased by a factor of (f_{S_IN}/f_{S_OUT}).

The number of input samples added to the write pointer of the

FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay

register. This feature is useful in varispeed applications to

prevent the read pointer to the FIFO from running ahead of the

write pointer. When set, Bit 7 of the group delay and mute-in

register soft-mutes the sample rate. Increasing the offset of the

Rev. A | Page 20 of 60

ADAV803

write address pointer is useful for applications in which small

changes in the sample rate ratio between f_{S_IN}and f_{S_OUT}are

expected. The maximum decimation rate can be calculated

from the RAM word depth and the group delay as

output of the SRC can be muted by asserting Bit 7 of the Group

Delay and Mute register until the SRC has changed to slow

mode. The MUTE_IND bit can be set to generate an interrupt

when the SRC changes to slow mode, indicating that the data is

being sample rate converted accurately.

(512 − 16)/64 taps = 7.75

for short group delay and

(512 − 64)/64 taps = 7

The frequency responses of the digital servo loop for fast mode

and slow mode are shown in Figure 34. The FIR filter is a 64-tap

filter when f_{S_OUT}≥ f_{S_IN}and is (f_{S_IN}/f_{S_OUT}) × 64 taps when f_{S_IN}

>

for long group delay.

f

_{S_OUT}. The FIR filter performs its convolution by loading in the

starting address of the RAM address pointer and the ROM

address pointer from the digital servo loop at the start of the

The digital servo loop is essentially a ramp filter that provides

the initial pointer to the address in RAM and ROM for the start

of the FIR convolution. The RAM pointer is the integer output

of the ramp filter, and the ROM is the fractional part. The

digital servo loop must provide excellent rejection of jitter on

the f_{S_IN}and f_{S_OUT}clocks, as well as measure the arrival of the

f

_{S_OUT}period. The FIR filter then steps through the RAM by

decrementing its address by 1 for each tap, and the ROM

pointer increments its address by the (f_{S_OUT}/f_{S_IN}) × 2²⁰ratio for

_{S_IN}> f_{S_OUT}or 2²⁰for f_{S_OUT}≥ f_{S_IN}. Once the ROM address rolls

f

over, the convolution is completed.

f

_{S_OUT}clock within 4.97 ps. The digital servo loop also divides

the fractional part of the ramp output by the ratio of f_{S_IN}/f_{S_OUT}

to dynamically alter the ROM coefficients when f_{S_IN}> f_{S_OUT}

0

FAST MODE

.

–20

–40

SLOW MODE

–60

–80

–100

–120

–140

–160

–180

–200

REG 0x76

BIT[1:0]

REG 0x77

BIT[4:3]

–220

0.01

0.1

1

10

100

1k

10k

100k

REG 0x00

BITS[1:0]

FREQUENCY (Hz)

Figure 34. Frequency Response of the Digital Servo Loop;

f_{S_IN}is the X-Axis, f_{S_OUT}= 192 kHz, Master Clock is 30 MHz

SRC

MCLK

AUXILIARY IN

PLAYBACK

DIR

The convolution is performed for both the left and right

channels, and the multiply accumulate circuit used for the

convolution is shared between the channels. The f_{S_IN}/f_{S_OUT}

sample rate ratio circuit is used to dynamically alter the

coefficients in the ROM when f_{S_IN}> f_{S_OUT}. The ratio is

calculated by comparing the output of an f_{S_OUT}counter to the

output of an f_{S_IN}counter. If f_{S_OUT}> f_{S_IN}, the ratio is held at one.

If f_{S_IN}> f_{S_OUT}, the sample rate ratio is updated, if it is different

by more than two f_{S_OUT}periods from the previous f_{S_OUT}to f_{S_IN}

comparison. This is done to provide some hysteresis to prevent

the filter length from oscillating and causing distortion.

SRC

INPUT

SRC

OUTPUT

ADC

REG 0x62

BITS[7:6]

Figure 33. Clock and Datapath Control on the SRC

The digital servo loop is implemented with a multirate filter. To

settle the digital servo loop filter more quickly upon startup or a

change in the sample rate, a fast mode has been added to the

filter. When the digital servo loop starts up or the sample rate is

changed, the digital servo loop enters fast mode to adjust and

settle on the new sample rate. Upon sensing that the digital

servo loop is settling down to a reasonable value, the digital

servo loop returns to normal (or slow) mode.

Figure 33 shows the detail of the SRC section. The SRC master

clock is expected to be equal to 256 times the output sample

rate. This master clock can be provided by four different clock

sources. The selection is set by the SRC and Clock Control

register (Address 0x00), and the selected clock source can be

divided using the same register.

During fast mode, the MUTE_IND bit in the s Sample Rate

Converter Error register is asserted to let the user know that

clicks or pops might be present in the digital audio data. The

Rev. A | Page 21 of 60

ADAV803

Table 7. PLL Frequency Selection Options

MCLK Selection

PLL SECTION

Sample Rate, f_S

PLL (kHz)

The ADAV803 features a dual PLL configuration to generate

independent system clocks for asynchronous operation.

Figure 37 shows the block diagram of the PLL section. The PLL

generates the internal and system clocks from a 27 MHz clock.

This clock is generated either by a crystal connected between

XIN and XOUT, as shown in Figure 35, or from an external

clock source connected directly to XIN. A 54 MHz clock can

also be used, if the internal clock divider is used.

XTAL

Normal f_S

Double f_S

1

32/44.1/48

64/88.2/96

32/44.1/48

64/88.2/96

Same as f_Sselected

for PLL 2A

256/384 × f_S

512/768 × f_S

256/384 × f_S

512/768 × f_S

256/384 × f_S

2A

2B

256/384 × f_S

256/512 × f_S

C

The PLLs require some external components to operate

correctly. These components, shown in Figure 36, form a loop

filter that integrates the current pulses from a charge pump and

produces a voltage that is used to tune the VCO. Good quality

capacitors, such as PPS film, are recommended. Figure 37

shows a block diagram of the PLL section, including the master

clock selection. Figure 38 shows how the clock frequencies at

the clock output pins, SYSCLK1 to SYSCLK3, and the internal

PLL clock values, PLL1 and PLL2, are selected.

Figure 35. Crystal Connection

Both PLLs (PLL1 and PLL2) can be programmed independently

and can accommodate a range of sampling rates (32 kHz

/44.1 kHz/48 kHz) with selectable system clock oversampling

rates of 256 and 384. Higher oversampling rates can also be

selected by enabling the doubling of the sampling rate to give

512 or 768 × f_Sratios. Note that this option also allows

oversampling ratios of 256 or 384 at double sample rates of

64 kHz /88.2 kHz/96 kHz.

The clock nodes, PLL1 and PLL2, can be used as master clocks

for the other blocks in the ADAV803, such as the DAC or ADC.

The PLL has separate supply and ground pins, which should be

as clean as possible to prevent electrical noise from being

converted into clock jitter by coupling onto the loop filter pins.

AVDD

The PLL outputs can be routed internally to act as clock sources

for the other component blocks such as the ADC and DAC. The

outputs of the PLLs are also available on the three SYSCLK pins.

Figure 38 shows how the PLLs can be configured to provide the

sampling clocks.

732Ω

PLL BLOCK

1.2µF

10nF

PLL_LFx

Figure 36. PLL Loop Filter

PLL_LF1

REG 0x78

BIT 6

PHASE

XIN

OUTPUT

SCALER N1

DETECTOR

AND LOOP

FILTER

SYSCLK1

VCO

÷2

PLL1

REG 0x74

BIT 4

XOUT

÷N

REG 0x74

BIT 5

MCLKO

PHASE

DETECTOR

AND LOOP

FILTER

OUTPUT

SCALER N2

÷2

SYSCLK2

SYSCLK3

VCO

MCLKI

REG 0x78

BIT 7

PLL2

OUTPUT

SCALER N3

÷N

PLL_LF2

Figure 37. PLL Section Block Diagram

Rev. A | Page 22 of 60

ADAV803

PLL1 MCLK

PLL2 MCLK

PLL1

REG 0x75

BITS[3:2]

REG 0x75

BIT 0

48kHz

32kHz

44.1kHz

×2

FS1

SYSCLK1

REG 0x77

BIT 0

REG 0x75

BIT 1

256

384

÷2

PLLINT1

PLL2

REG 0x75

BIT 4

REG 0x75

BIT 5

256

384

×2

FS2

SYSCLK2

REG 0x77

BITS[2:1]

REG 0x75

BITS[7:6]

48kHz

32kHz

÷2

44.1kHz

PLLINT2

REG 0x74

BIT 0

÷2

FS3

256

512

SYSCLK3

Figure 38. PLL Clocking Scheme

CHANNEL STATUS

AND USER BITS

ADC

S/PDIF TRANSMITTER AND RECEIVER

The ADAV803 contains an integrated S/PDIF transmitter and

receiver. The transmitter consists of a single output pin,

DITOUT, on which the biphase encoded data appears. The

S/PDIF transmitter source can be selected from the different

blocks making up the ADAV803. Additionally, the clock source

for the S/PDIF transmitter can be selected from the various

clock sources available in the ADAV803.

DIR

PLAYBACK

AUXILIARY IN

SRC

DIT

INPUT

DIT

DITOUT

REG 0x63

BITS[2:0]

Figure 40. Digital Output Transmitter Block Diagram

The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts

the S/PDIF input data stream. The DIRIN pin can be configured

to accept a digital input level, as defined in the Specifications

section, or an input signal with a peak-to-peak level of 200 mV

minimum, as defined by the IEC 60958-3 specification. DIR_LF

is a loop filter pin, required by the internal PLL, which is used

to recover the clock from the S/PDIF data stream.

AUDIO

DIRIN

DATA

RECOVERED

CLOCK

DIR

CHANNEL STATUS/

USER BITS

The components shown in Figure 42 form a loop filter, which

integrates the current pulses from a charge pump and produces

a voltage that is used to tune the VCO of the clock recovery

PLL. The recovered audio data and audio clock can be routed to

the different blocks of the ADAV803, as required. Figure 39

shows a conceptual diagram of the DIRIN block.

Figure 41. Digital Input Receiver Block Diagram

AVDD

3.3kΩ

DIR BLOCK

100nF

6.8nF

REG 0x7A

BIT 4

DIR_LF

DIRIN

C*

SPDIF

Figure 42. DIR Loop Filter Components

SPDIF

RECEIVER

COMPARATOR

DC

LEVEL

*EXTERNAL CAPACITOR IS ONLY REQUIRED

FOR VARIABLE LEVEL SPDIF INPUTS.

Figure 39. DIRIN Block

Rev. A | Page 23 of 60

ADAV803

Serial Digital Audio Transmission Standards

Ordinarily, the biphase-mark encoding method results in a

polarity transition between bit boundaries.

The ADAV803 can receive and transmit S/PDIF, AES/EBU, and

IEC-958 serial streams. S/PDIF is a consumer audio standard,

and AES/EBU is a professional audio standard. IEC-958 has

both consumer and professional definitions. This data sheet is

not intended to fully define or to provide a tutorial for these

standards. Contact the international standards-setting bodies

for the full specifications.

1

0

1

0

1

0

1

0

PREAMBLE X

PREAMBLE Y

PREAMBLE Z

All these digital audio communication schemes encode audio

data and audio control information using the biphase-mark

method. This encoding method minimizes the dc content of the

transmitted signal. As can be seen from Figure 43, 1s in the

original data end up with midcell transitions in the biphase-

mark encoded data, while 0s in the original data do not. Note

that the biphase-mark encoded data always has a transition

between bit boundaries.

Figure 45. Preambles

The serial digital audio communication scheme is organized

using a frame and subframe construction. There are two

subframes per frame (ordinarily the left and right channel).

Each subframe includes the appropriate 4-bit preamble, up to

24 bits of audio data, a validity (V) bit, a user (U) bit, a channel

status (C) bit, and an even parity (P) bit. The channel status bits

and the user bits accumulate over many frames to convey

control information. The channel status bits accumulate over a

192 frame period (called a channel status block). The user bits

accumulate over 1176 frames when the interconnect is imple-

menting the so-called subcode scheme (EIAJ CP-2401). The

organization of the channel status block, frames, and subframes

is shown in Table 9 and Table 10. Note that the ADAV803

supports the professional audio standard from a software

point of view only. The digital interface supports only

consumer mode.

CLOCK

(2 TIMES BIT RATE)

0

1

0

DATA

BIPHASE-MARK

DATA

Figure 43. Biphase-Mark Encoding

Digital audio-communication schemes use preambles to

distinguish among channels (called subframes) and among

longer-term control information blocks (called frames). Pream-

bles are particular biphase-mark patterns, which contain encoding

violations that allow the receiver to uniquely recognize them.

These patterns and their relationship to frames and subframes

are shown in Table 8 and Figure 44.

Table 9. Consumer Audio Standard

Data Bits

Table 8. Biphase-Mark Encode Preamble

Address¹

7

6

5

4

3

2

1

0

Biphase Patterns

Channel

N

Channel

Status

Emphasis

Copy- Non-

Pro/

X

Y

Z

11100010 or 00011101

11100100 or 00011011

11101000 or 00010111

Left

Right

right

Audio Con

= 0

N + 1

N + 2

N + 3

Category Code

Channel Number Source Number

Left and CS block start

Reserved

Clock

Sampling Frequency

PREAMBLES

Accuracy

N + 4

Reserved

Word Length

X LEFT CH Y RIGHT CH Z LEFT CH Y RIGHT CH X LEFT CH Y RIGHT CH

SUBFRAME SUBFRAME

N + 5 to

(N + 23)

Reserved

¹N = 0x20 for receiver channel status buffer.

N = 0x38 for transmitter channel status buffer.

FRAME 191

FRAME 0

FRAME 1

Figure 44. Preambles, Frames, and Subframes

The biphase-mark encoding violations are shown in Figure 45.

Note that all three preambles include encoding violations.

Rev. A | Page 24 of 60

ADAV803

bits are available as a memory buffer, taking up 24 consecutive

register locations. The user bits are read using an indirect

memory addressing scheme, where the receiver user bit

indirect-address register is programmed with an offset to the

user bit buffer, and the receiver user bit data register can be read

to determine the user bits at that location. Reading the receiver

user bit data register automatically updates the indirect address

register to the next location in the buffer. Typically, the receiver

user bit indirect-address register is programmed to zero (the

start of the buffer), and the receiver user bit data register is read

repeatedly until all the buffer’s data has been read. Figure 46

and Figure 47 show how receiving the channel status bits and

user bits is implemented.

Table 10. Professional Audio Standard

Data Bits

Address¹

7

6

5

4

3

2

1

0

N

Sample

Frequency

User Bit Management

Lock

Emphasis

Non-

Audio = 1

Pro/Con

N + 1

N + 2

Channel Mode

Alignment

Level

Source Word

Length

Use of Auxiliary Mode

Sample Bits

N + 3

N + 4

Channel Identification

f_S

Scaling

Sample

Frequency (f_S)

Reserved Digital Audio

Reference

Signal

N + 5

Reserved

N + 6

Alphanumeric Channel Origin Data—First Character

Alphanumeric Channel Origin Data

Alphanumeric Channel Origin Data—Last Character

Alphanumeric Channel Destination Data—First Character

Alphanumeric Channel Destination Data

Alphanumeric Channel Destination Data—Last Character

Local Sample Address Code—LSW

Local Sample Address Code

CHANNEL

STATUS A

SECOND BUFFER

N + 7

DIRIN

RECEIVE

CS BUFFER

(0x20 TO 0x37)

(24 × 8 BITS)

N + 8

N + 9

S/PDIF

RECEIVE

BUFFER

CHANNEL

STATUS B

(24 × 8 BITS)

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 16

N + 17

N + 18

N + 19

N + 20

N + 21

N + 22

N + 23

RxCSSWITCH

FIRST BUFFER

Figure 46. Channel Status Buffer

S/PDIF

Local Sample Address Code

0.....7

8.....15

16.....23

0.....7

Local Sample Address Code—MSW

Time of Day Code—LSW

8.....15

ADDRESS = 0x50

16.....23

Time of Day Code

RECEIVER USER BIT

INDIRECT ADDRESS

REGISTER

Time of Day Code

Time of Day Code—MSW

Reliability Flags

Reserved

FIRST

BUFFER

USER-BIT

BUFFER

ADDRESS = 0x51

Cyclic Redundancy Check Character (CRCC)

RECEIVER USER BIT

DATA REGISTER

¹N = 0x20 for receiver channel status buffer.

N = 0x38 for transmitter channel status buffer

The standards allow the channel status bits in each subframe to

be independent, but ordinarily the channel status bits in the two

subframes of each frame are the same. The channel status bits

are defined differently for the consumer audio standards and

the professional audio standards. The 192 channel status bits are

organized into 24 bytes and have the interpretations shown in

Table 9 and Table 10.

Figure 47. Receiver User Bit Buffer

The S/PDIF receive buffer is updated continuously by the

incoming S/PDIF stream. Once all the channel status bits for

the block (192 for Channel A and 192 for Channel B) are

received, the bits are copied into the receiver channel status

buffer. This buffer stores all 384 bits of channel status

information, and the RxCSSWITCH bit in the channel status

switch buffer register determines whether the Channel A or the

Channel B status bits are required to be read. The receive

channel status bit buffer is 24 bytes long and spans the address

range from 0x20 to 0x37.

The S/PDIF transmitter and receiver have a comprehensive

register set. The registers give the user full access to the

functions of the S/PDIF block, such as detecting nonaudio and

validity bits, Q subcodes, and preambles. The channel status bits

as defined by the IEC60958 and AES3 specifications are stored

in register buffers for ease of use. An autobuffering function

allows channel status bits and user bits read by the receiver to be

copied directly to the transmitter block, removing the need for

user intervention.

Because the channel status bits of an S/PDIF stream rarely

change, a software interrupt/flag bit, RxCSBINT, is provided to

notify the host control either that a new block of channel status

bits is available or that the first five bytes of channel status

information have changed from a previous block. The function

of the RxCSBINT is controlled by the RxBCONF3 bit in the

Receiver Buffer Configuration register.

Receiver Section

The ADAV803 uses a double-buffering scheme to handle read-

ing channel status and user bit information. The channel status

Rev. A | Page 25 of 60

ADAV803

The size of the user bit buffer can be set by programming the

RxBCONF0 bit in the receiver buffer configuration register, as

shown in Table 11.

bit is set. This is a sticky bit that remains high until the register

is read.

Transmitter Operation

The S/PDIF transmitter has a similar buffer structure to the

receive section. The transmitter channel status buffer occupies

24 bytes of the register map. This buffer is long enough to store

the 192 bits required for one channel of channel status informa-

tion. Setting the TxCSSWITCH bit determines if the data

loaded to the transmitter channel status buffer is intended for

Channel A or Channel B. In most cases, the channel status bits

for Channel A and Channel B are the same, in which case

setting the Tx_A/B_Same bit reads the data from the trans-

mitter channel status buffer and transmits it on both channels.

Table 11. RxBCONF3 Functionality

RxBCONF0 Receiver User Bit Buffer Size

0

1

384 bits with Preamble Z as the start of the block.

768 bits with Preamble Z as the start of the block.

The updating of the user bit buffer is controlled by Bits

RxBCONF[2:1] and Bit 7 to Bit 4 of the channel status register,

as shown in Table 12 and Table 13.

Table 12. RxBCONF[2:1] Functionality

RxBCONF

Because the channel status information is rarely changed during

transmission, the information contained in the buffer is

transmitted repeatedly. The Disable_Tx_Copy bit can be used

to prevent the channel status bits from being copied from the

transmitter CS buffer into the S/PDIF transmitter buffer until

the user has finished loading the buffers. This feature is

typically used, if the Channel A data and Channel B data are

different. Setting the bit prevents the data from being copied.

Clearing the bit allows the data to be copied and then

Bit 2

Bit 1

Receiver User Bit Buffer Configuration

User bits are ignored.

Update second buffer when first buffer is full.

Format according to Byte 1, Bit 4 to Bit 7, if

PRO bit is set. Format according to IEC60958-3,

if PRO bit is clear.

0

1

0

1

0

Table 13. Automatic User Bit Configuration

Bits

Automatic Receiver User Bit Buffer

Configuration

transmitted. Figure 48 shows how the buffers are organized.

7

0

6

5

0

4

0

1

User bits are ignored.

AES-18 format: the user bit buffer is treated in

the same way as when RxBCONF[2:1] = 0b01.

User bit buffer is updated in the same way as

when RxBCONF[2:1] = 0b01 and RxBCONF0 =

0b00.

User-defined format: the user bit buffer is

treated in the same way as when

RxBCONF[2:1] = 0b01.

DITOUT

CHANNEL

STATUS A

(24 × 8 BITS)

1

0

1

0

S/PDIF

TRANSMIT

BUFFER

TRANSMIT

CS BUFFER

(0x38 TO 0x4F)

CHANNEL

STATUS B

(24 × 8 BITS)

TxCSSWITCH

Figure 48. Transmitter Channel Status Buffer

As with the receiver section, the transmitted user bits are also

double-buffered. This is required because, unlike the channel

status bits, the user bits do not necessarily repeat themselves.

The user bits can be buffered in various configurations, as listed

in Table 14. Transmission of the user bits is determined by the

state of the BCONF3 bit. If the bit is 0, the user bits begin

transmitting right away without alignment to the Z preamble. If

this bit is 1, the user bits do not start transmitting until a

Z preamble occurs when the TxBCONF[2:1] bits are 01.

When the user bit buffer has been filled, the RxUBINT

interrupt bit in the interrupt status register is set, provided that

the RxUBINT mask bit is set, to indicate that the buffer has new

information and can be read.

For the special case when the user data is formatted according

to the IEC 60958-3 standard into messages made of information

units, called IUs, the zeros stuffed between each IU and each

message are removed and only the IUs are stored. Once the end

of the message is sensed by more that eight zeros between IUs,

the user bit buffer is updated with the complete message and

the first buffer begins looking for the start of the next message.

Table 14. Transmitter User Bit Buffer Configurations

TxBCONF2-1

Bit 2

Bit 1

Transmitter User Bit Buffer Configuration

Zeros are transmitted for the user bits.

Host writes user bits to the buffer until it is full.

Writes the user bits to the buffer in IUs

specified by IEC60958-3 and transmits them

according to the standard.

Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and

W bits (see the IEC 60958-3 specification for more

0

1

0

1

0

information). When 96 IUs are received, the Q subcode of the

IUs is stored in the Q subcode buffer, consisting of 10 bytes. The

Q subcode is the Q bits taken from each of the 96 IUs. The first

10 bytes (80 bits) of the Q subcode contain information sent by

CD, MD, and DAT systems. The last 16 bits of the Q subcode

are used to perform a CRC check of the Q subcode. If an error

occurs in the CRC check of the Q subcode, the QCRCERROR

1

First 10 bytes of the user-bit buffer are

configured to store a Q subcode.

Rev. A | Page 26 of 60

ADAV803

When the user bits are transmitted according to the IEC 60958-3

format, the messages contained in the user bits can still be sent

without dropping or repeating messages. Because zero-stuffing

is allowed between IUs and messages, zeros can be added or

subtracted to preserve the messages. When the transmitter

sample rate is greater than the receiver sample rate, extra zeros

are stuffed between the messages. When the sample rate of the

transmitter is less than the sample rate of the receiver, the zeros

stuffed between the messages are subtracted. If there are not

enough zeros between the messages to be subtracted, the zeros

between IUs are subtracted as well. The Zero_Stuff_IU bit in

the Autobuffer register enables the adding or subtracting of

zeros between messages.

Table 15. Transmitter User Bit Buffer Size

TxBCONF0 Buffer Size

0

1

384 bits with Preamble Z as the start of the block.

768 bits with Preamble Z as the start of the block.

By using sticky bits and interrupts, the transmit buffers can

notify the host or microcontroller about their status. The sticky

bit, TxUBINT, is set when the transmit user bit buffer has been

updated and the second transmit user bit buffer is empty and

ready to accept new user bits. This bit is located in the interrupt

status register. When the host reads the interrupt status register,

this bit is cleared. Interrupts for the TxUBINT sticky bit can be

enabled by setting the TxUBINT Mask bit in the interrupt

status mask register

Interrupts

The ADAV803 provides interrupt bits to indicate the presence

of certain conditions that require attention. Reading the

interrupt status register (Register 0x1C) allows the user to

determine if any of the interrupts have been asserted. The bits

of the Interrupt Status register remain high, if set, until the

register is read. Two bits, SRCError and RxError, indicate

interrupt conditions in the sample rate converter and an S/PDIF

receiver error, respectively. Both these conditions require a read

of the appropriate error register (Register 0x1A and Register

0x18, respectively) to determine the exact cause of the interrupt.

S/PDIF 0

0.....7

8.....15

16.....23

0.....7

8.....15

16.....23

ADDRESS = 0x52

TRANSMITTER USER BIT

INDIRECT ADDRESS

REGISTER

USER-BIT

BUFFER

SECOND

BUFFER

ADDRESS = 0x53

TRANSMITTER USER BIT

DATA REGISTER

Each interrupt in the interrupt status register has an associated

mask bit in the interrupt status mask register. The interrupt

mask bit must be set for the corresponding interrupt to be

generated. This feature allows the user to determine which

functions should be responded to.

Figure 49. Transmitter User Bit Buffer

Autobuffering

The dual function pin ZEROL/INT can be set to indicate the

presence of no audio data on the left channel or the presence of

an interrupt set in the interrupt status register. As shown in

Table 16, the function of this pin is selected by the INTRPT bit

in DAC Control Register 4.

The ADAV803 S/PDIF receiver and transmitter sections have

an autobuffering mode allowing the channel status and user bits

to be copied automatically from the receiver to the transmitter

without user intervention. The channel status and user bits

can be independently selected for autobuffering using the

Auto_CSBits and Auto_UBits bits, respectively, in the Auto-

buffer register. When the receiver and transmitter are running

at the same sample rate, the transmitted channel status and user

bits are the same as the received channel-status and user bits.

Table 16. ZEROL/INT Pin Functionality

INTRPT

Pin Functionality

0

1

Pin functions as a ZEROL flag pin.

Pin functions as an interrupt pin.

In many systems, however, it is likely that the receiver and

transmitter are not running at the same frequency. When the

transmitter sample rate is higher than the receiver sample rate,

the channel status and user bit blocks are sometimes repeated.

When the transmitter sample rate is lower than the receiver

sample rate, the channel status and user bit blocks might be

dropped. Because the first five bytes of the channel status are

typically constant, they can be repeated or dropped with no

information loss. However, if the PRO bit in the channel status

is set and the local sample address code and time-of-day code

bytes contain information, these bytes might be repeated or

dropped, in which case information can be lost. It is up to the

user to determine how to handle this case.

SERIAL DATA PORTS

The ADAV803 contains four flexible serial ports (SPORTs) to

allow data transfer to and from the codec. All four SPORTs are

independent and can be configured as master or slave ports. In

slave mode, the xLRCLK and xBCLK signals are inputs to the

serial ports. In master mode, the serial port generates the

xLRCLK and xBCLK signals. The master clock for the SPORT

can be selected from a number of sources, as shown in

Figure 50.

Rev. A | Page 27 of 60

ADAV803

Care should be taken to ensure that the clock rate is appropriate

for whatever block is connected to the serial port. For example,

if the ADC is running from the MCLKI input at 256 × f_S, then

the master clock for the SPORT should also run from the

MCLKI input to ensure that the ADC and serial port are

synchronized.

REG 0x76

BITS[4:2]

OLRCLK

OBCLK

OSDATA

ADC

OUTPUT

PORT

DIR PLL(512 × f_S

)

MCLK

DIR PLL(256 × f_S

PLLINT1

PLLINT2

MCLKI

XIN

ICLK1

ICLK2

PLL CLOCK

REG 0x06

BITS[5:4]

REG 0x76

The SPORTs can be set to transmit or receive data in I²S, left-

justified or right-justified formats with different word lengths

by programming the appropriate bits in the playback register,

auxiliary input port register, record register, and auxiliary

output port-control register. Figure 51 is a timing diagram of

the serial data port formats.

BITS[7:5]

ILRCLK

IBCLK

ISDATA

DAC

INPUT

PORT

DIR PLL(512 × f_S

)

MCLK

DIR PLL(256 × f_S

PLLINT1

PLLINT2

MCLKI

XIN

ICLK1

ICLK2

PLL CLOCK

REG 0x04

BITS[4:3]

REG 0x77

BITS[4:3]

REG 0x00

BITS[1:0]

SRC

MCLK

REG 0x00

BITS[3:2]

Clocking Scheme

MCLKI

ICLK1

XIN

PLLINT1

PLLINT2

The ADAV803 provides a flexible choice of on-chip and off-

chip clocking sources. The on-chip oscillator with dual PLLs is

intended to offer complete system clocking requirements for

use with available MPEG encoders, decoders, or a combination

of codecs. The oscillator function is designed for generation of a

27 MHz video clock from a 27 MHz crystal connected between

the XIN and XOUT pins. Capacitors must also be connected

between these pins and DGND, as shown in Figure 35. The

capacitor values should be specified by the crystal manufacturer.

A square wave version of the crystal clock is output on the

MCLKO pin. If the system has a 27 MHz clock available, this

clock can be connected directly to the XIN pin.

DIVIDER

DIR PLL(512 × f_S

DIR PLL(256 × f_S

)

DIVIDER

REG 0x00

BITS[7:6]

MCLKI

XIN

PLLINT1

PLLINT2

DIVIDER

ICLK2

REG 0x00

BITS[4:5]

REG 0x76

BITS[1:0]

Figure 50. SPORT Clocking Scheme

LEFT CHANNEL

RIGHT CHANNEL

LRCLK

BCLK

SDATA

MSB

LSB

MSB

LSB

LEFT-JUSTIFIED MODE — 16 BITS TO 24 BITS PER CHANNEL

LEFT CHANNEL

LRCLK

RIGHT CHANNEL

BCLK

MSB

I S MODE — 16 BITS TO 24 BITS PER CHANNEL

LSB

SDATA

MSB

LSB

2

LEFT CHANNEL

RIGHT CHANNEL

LRCLK

BCLK

SDATA

MSB

LSB

MSB

LSB

RIGHT-JUSTIFIED MODE — SELECT NUMBER OF BITS PER CHANNEL

Figure 51. Serial Data Modes

Rev. A | Page 28 of 60

ADAV803

Datapath

PLL

OSCILLATOR

RECORD

DATA

The ADAV803 features a digital input/output switching/

multiplexing matrix that gives flexibility to the range of possible

input and output connections. Digital input ports include

playback and auxiliary input (both 3-wire digital), and S/PDIF

(single-wire to the on-chip receiver). Output ports include the

record and auxiliary output ports (both 3-wire digital) and the

S/PDIF port (single-wire from the on-chip transmitter).

Internally, the DIR and DIT are interfaced via 3-wire interfaces.

The datapath for each input and output port is selected by

programming Datapath Control Register 1 and Datapath

Control Register 2. Figure 52 shows the internal datapath

structure of the ADAV803.

OUTPUT

ADC

AUX

DATA

OUTPUT

REFERENCE

DAC

SRC

DIT

CONTROL

REGISTERS

PLAYBACK

DATA

INPUT

AUX

DATA

INPUT

DIR

Figure 52. Datapath

Rev. A | Page 29 of 60

ADAV803

INTERFACE CONTROL

The ADAV803 has a dedicated control port to allow the internal

registers of the ADAV803 to be accessed. Each of the internal

registers is eight bits wide. Where bits are described as reserved

(RES), these bits should be programmed as zero.

Initiating a write operation to the ADAV803 involves sending a

start condition and then sending the device address with the

R/W set low. The ADAV803 responds by issuing an ACK to

indicate that it has been addressed. The user then sends a

second frame telling the ADAV803 which register is required to

be written to. The 7-bit register address is left-shifted to make

the eight bits that the frame requires. Another ACK is issued by

the ADAV803. Finally, the user can send another frame with the

eight data bits required to be written to the register. A third

ACK is issued by the ADAV803, after which the user can send a

stop condition to complete the data transfer.

I²C INTERFACE

The I²C interface of the ADAV803 is a 2-wire interface

consisting of a clock line, SCL, and a data line, SDA. SDA is

bidirectional; the ADAV803 drives SDA to either acknowledge

the master, ACK, or send data during a read operation. The

SDA pin for the I²C port is an open-drain collector that requires

a 1 kΩ pull-up resistor. A write or read access occurs when the

SDA line is pulled low while the SCL line is high, indicated by

START in the timing diagrams. SDA is allowed to change only

when SCL is low, except when a start or stop condition occurs,

as shown in Figure 53 and Figure 54. The I²C interface supports

both standard (100 kbps) and fast (400 kbps) modes as defined

by the I²C standards.

A read operation requires that the user first write to the

ADAV803 to point to the correct register and then read the

data. This is achieved by sending a start condition followed by

the device address frame, with R/W low, and then the register

address frame. Following the ACK from the ADAV803, the user

must issue a repeated start condition. This is identical to a start

condition. The next frame is the device address with R/W set

high. On the next frame, the ADAV803 outputs the register data

on the SDA line. A stop condition completes the read operation.

Figure 53 and Figure 54 show examples of writing to and read-

ing from the DAC left volume register (Address 0b1101000).

The first eight bits of the access consist of the device address

and the R/W bit. The device address consists of an internal

built-in address (0b00100) and two address pins, AD1 and

AD0. The two address pins allow up to four ADAV803s to be

used in a system.

SCK

0

1

0

1

0

1

0

SDA

START BY

AD1

AD0 R/W

X

ACK. BY

ADAV803

ACK. BY

ADAV803

MASTER

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

SCK

(CONTINUED)

SDA

(CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY STOP BY

ADAV803 MASTER

FRAME 3

DATA BYTE TO

ADAV803

Figure 53. Writing to the DAC Left Volume Register in I²C

Rev. A | Page 30 of 60

ADAV803

SCL

SDA

0

1

0

1

0

AD1 AD0 R/W

1

0

X

START BY

MASTER

ACK. BY

ADAV803

ACK. BY

ADAV803

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

SCL

(CONTINUED)

SDA

(CONTINUED)

0

1

0

AD1 AD0 R/W

D7

D6

D5

D4

D3

D2

D1

D0

REPEATED START

BY MASTER

ACK. BY

ADAV803

ACK. BY

ADAV803 MASTER

STOP BY

FRAME 3

CHIP ADDRESS BYTE

FRAME 4

REGISTER DATA

Figure 54. Reading from the DAC Left Volume Register in I²C

Care should be exercised when using the block read or block

write modes. For most cases, block reading or writing to a

register automatically increments the register address to point

to the next register. The exceptions to this case are the indirect

memory address registers, transmitter user bit and receiver user

bit data buffers. Using a block read or write to access these

registers does not update the absolute register address, but

instead updates the buffer address to provide the next value in

the buffer.

BLOCK READS AND WRITES

The ADAV803 provides the user with the ability to write to or

read from a block of registers in one continuous operation. To

use this feature, the user has to continue providing data frames

before the stop condition. For a write operation, the register

address is automatically incremented with each additional

frame and the register data is written to that register address.

For a read operation, the register address is automatically

incremented with each additional frame, and the register data is

clocked out on that frame.

Rev. A | Page 31 of 60

ADAV803

REGISTER DESCRIPTIONS

SRC and Clock Control—Address 0000000 (0x00)

Table 17. SRC and Clock Control Register Bit Map

7

6

5

4

3

2

1

0

SRCDIV1

SRCDIV0

CLK2DIV1

CLK2DIV0

CLK1DIV1

CLK1DIV0

MCLKSEL1

MCLKSEL0

Table 18. SRC and Clock Control Register Bit Descriptions

Bit Name

Description

SRCDIV[1:0]

Divides the SRC master clock.

00 = SRC master clock is not divided.

01 = SRC master clock is divided by 1.5.

10 = SRC master clock is divided by 2.

11 = SRC master clock is divided by 3.

Clock divider for Internal Clock 2 (ICLK2).

00 = Divide by 1.

01 = Divide by 1.5.

10 = Divide by 2.

11 = Divide by 3.

CLK2DIV[1:0]

CLK1DIV[1:0]

MCLKSEL[1:0]

Clock divider for Internal Clock 1 (ICLK1).

00 = Divide by 1.

01 = Divide by 1.5.

10 = Divide by 2.

11 = Divide by 3.

Clock selection for the SRC master clock.

00 = Internal Clock 1.

01 = Internal Clock 2.

10 = PLL recovered clock (512 × f_S).

11 = PLL recovered clock (256 × f_S).

S/PDIF Loopback Control—Address 0000011 (0x03)

Table 19. S/PDIF Loopback Control Register Bit Map

7

6

5

4

3

2

1

0

Reserved

TxMUX

Table 20. S/PDIF Loopback Control Register Bit Descriptions

Bit Name

Description

TxMUX

Selects the source for S/PDIF output (DITOUT).

0 = S/PDIF transmitter, normal mode.

1 = DIRIN, loopback mode.

Rev. A | Page 32 of 60

ADAV803

Playback Port Control—Address 0000100 (0x04)

Table 21. Playback Port Control Register Bit Map

7

6

5

4

3

2

1

0

Reserved

CLKSRC1

CLKSRC0

SPMODE2

SPMODE1

SPMODE0

Table 22. Playback Port Control Register Bit Descriptions

Bit Name

Description

CLKSRC[1:0]

Selects the clock source for generating the ILRCLK and IBCLK.

00 = Input port is a slave.

01 = Recovered PLL clock.

10 = Internal Clock 1.

11 = Internal Clock 2.

SPMODE[2:0]

Selects the serial format of the playback port.

000 = Left-justified.

001 = I²S.

100 = 24-bit, right-justified.

101 = 20-bit, right-justified.

110 = 18-bit, right-justified.

111 = 16-bit, right-justified.

Auxiliary Input Port—Address 0000101 (0x05)

Table 23. Auxiliary Input Port Register Bit Map

7

6

5

4

3

2

1

0

Reserved

CLKSRC1

CLKSRC0

SPMODE2

SPMODE1

SPMODE0

Table 24. Auxiliary Input Port Register Bit Descriptions

Bit Name

Description

CLKSRC[1:0]

Selects the clock source for generating the IAUXLRCLK and IAUXBCLK.

00 = Input port is a slave.

01 = Recovered PLL cock.

10 = Internal Clock 1.

11 = Internal Clock 2.

SPMODE[2:0]

Selects the serial format of auxiliary input port.

000 = Left-justified.

001 = I²S.

100 = 24-bit, right-justified.

101 = 20-bit, right-justified.

110 = 18-bit, right-justified.

111 = 16-bit, right-justified.

Rev. A | Page 33 of 60

ADAV803

Record Port Control—Address 0000110 (0x06)

Table 25. Record Port Control Register Bit Map

7

6

5

4

3

2

1

0

Reserved

CLKSRC1

CLKSRC0

WLEN1

WLEN0

SPMODE1

SPMODE0

Table 26. Record Port Control Register Bit Descriptions

Bit Name

Description

CLKSRC[1:0]

Selects the clock source for generating the OLRCLK and OBCLK.

00 = Record port is a slave.

01 = Recovered PLL clock.

10 = Internal Clock 1.

11 = Internal Clock 2.

Selects the serial output word length.

00 = 24 bits.

WLEN[1:0]

01 = 20 bits.

10 = 18 bits.

11 = 16 bits.

SPMODE[1:0]

Selects the serial format of the record port.

00 = Left-justified.

01 = I²S.

10 = Reserved.

11 = Right-justified.

Auxiliary Output Port—Address 0000111 (0x07)

Table 27. Auxiliary Output Port Register Bit Map

7

6

5

4

3

2

1

0

Reserved

CLKSRC1

CLKSRC0

WLEN1

WLEN0

SPMODE1

SPMODE0

Table 28. Auxiliary Output Port Register Bit Descriptions

Bit Name

Description

CLKSRC[1:0]

Selects the clock source for generating the OAUXLRCLK and OAUXBCLK.

00 = Auxiliary record port is a slave.

01 = Recovered PLL clock.

10 = Internal Clock 1.

11 = Internal Clock 2.

Selects the serial output word length.

00 = 24 bits.

WLEN[1:0]

01 = 20 bits.

10 = 18 bits.

11 = 16 bits.

SPMODE[1:0]

Selects the serial format of the auxiliary record port.

00 = Left-justified.

01 = I²S.

10 = Reserved.

11 = Right-justified.

Rev. A | Page 34 of 60

ADAV803

Group Delay and Mute—Address 0001000 (0x08)

Table 29. Group Delay and Mute Register Bit Map

7

6

5

4

3

2

1

0

MUTE_SRC

GRPDLY6

GRPDLY5

GRPDLY4

GRPDLY3

GRPDLY2

GRPDLY1

GRPDLY0

Table 30. Group Delay and Mute Register Bit Descriptions

Bit Name

Description

MUTE_SRC

Soft-mutes the output of the sample rate converter.

0 = No mute.

1 = Soft mute.

GRPDLY[6:0]

Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples.

0000000 = No delay.

0000001 = 1 sample delay.

0000010 = 2 sample delay.

1111110 = 126 sample delay.

1111111 = 127 sample delay.

Receiver Configuration 1—Address 0001001 (0x09)

Table 31. Receiver Configuration 1 Register Bit Map

7

6

5

4

3

2

1

0

NOCLOCK

RxCLK1

RxCLK0

AUTO_DEEMPH ERR1

ERR0

LOCK1

LOCK0

Table 32. Receiver Configuration 1 Register Bit Descriptions

Bit Name

Description

NOCLOCK

Selects the source of the receiver clock when the PLL is not locked.

0 = Recovered PLL clock is used.

1 = ICLK1 is used.

RxCLK[1:0]

Determines the oversampling ratio of the recovered receiver clock.

00 = RxCLK is a 128 × f_Srecovered clock.

01 = RxCLK is a 256 × f_Srecovered clock.

10 = RxCLK is a 512 × f_Srecovered clock.

11 = Reserved.

AUTO_DEEMPH

ERR[1:0]

Automatically de-emphasizes the data from the receiver based on the channel status information.

0 = Automatic de-emphasis is disabled.

1 = Automatic de-emphasis is enabled.

Defines what action the receiver should take, if the receiver detects a parity or biphase error.

00 = No action is taken.

01 = Last valid sample is held.

10 = Invalid sample is replaced with zeros.

11 = Reserved.

LOCK[1:0]

Defines what action the receiver should take, if the PLL loses lock.

00 = No action is taken.

01 = Last valid sample is held.

10 = Zeros are sent out after the last valid sample.

11 = Soft-mute of the last valid audio sample.

Rev. A | Page 35 of 60

ADAV803

Receiver Configuration 2—Address 0001010 (0x0A)

Table 33. Receiver Configuration 2 Register Bit Map

7

6

5

4

3

2

1

0

RxMUTE

SP_PLL

SP_PLL_ SEL1

SP_PLL_ SEL0

Reserved

Reserved NO NONAUDIO

NO_VALIDITY

Table 34. Receiver Configuration 2 Register Bit Descriptions

Bit Name

Description

RxMUTE

Hard-mutes the audio output for the AES3/S/PDIF receiver.

0 = AES3/S/PDIF receiver is not muted.

1 = AES3/S/PDIF receiver is muted.

SP_PLL

AES3/S/PDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.

0 = Left/right clock generated from the AES3/S/PDIF preambles is the reference clock to the PLL.

1 = Left/right clock from one of the serial ports is the reference clock to the PLL.

Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set.

00 = Playback port is selected.

SP_PLL_SEL[1:0]

01 = Auxiliary input port is selected.

10 = Record port is selected.

11 = Auxiliary output port is selected.

NO NONAUDIO

NO_VALIDITY

When the NO NONAUDIO bit is set, data from the AES3/S/PDIF receiver is not allowed into the sample rate converter

(SRC). If the NO NONAUDIO data is due to DTS, AAC, and so on, as defined by the IEC61937 standard, then the data

from the AES3/S/PDIF receiver is not allowed into the SRC regardless of the state of this bit.

0 = AES3/S/PDIF receiver data is sent to the SRC.

1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO NONAUDIO bit is set.

When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC.

0 = AES3/S/PDIF receiver data is sent to the SRC.

1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set.

Rev. A | Page 36 of 60

ADAV803

Receiver Buffer Configuration—Address 0001011 (0x0B)

Table 35. Receiver Buffer Configuration Register Bit Map

7

6

5

4

3

2

1

0

Reserved

RxBCONF5

RxBCONF4

RxBCONF3

RxBCONF2

RxBCONF1

RxBCONF0

Table 36. Receiver Buffer Configuration Register Bit Descriptions

Bit Name

Description

RxBCONF5

If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit

interrupt is enabled only when there is a change in the start (ID) bit.

0 = User bit interrupt is enabled in normal mode.

1 = If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.

RxBCONF4

RxBCONF3

RxBCONF[2:1]

This bit determines whether Channel A and Channel B user bits are stored in the buffer together or separated

between A and B.

0 = User bits are stored together.

1 = User bits are stored separately.

Defines the function of RxCSBINT.

0 = RxCSBINT are set when a new block of receiver channel status is read, which is 192 audio frames.

1 = RxCSBINT is set only if the first five bytes of the receiver channel status block changes from the previous

channel status block.

Defines the user bit buffer.

00 = User bits are ignored.

01 = Updates the second user bit buffer when the first user bit buffer is full.

10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If

the PRO bit is not set, formats the user bits according to the IEC60958-3 standard.

11 = Reserved.

RxBCONF0

Defines the user bit buffer size, if RxBCONF[2:1] = 01.

0 = 384 bits with Preamble Z as the start of the buffer.

1 = 768 bits with Preamble Z as the start of the buffer.

Transmitter Control—Address 0001100 (0x0C)

Table 37. Transmitter Control Register Bit Map

7

6

5

4

3

2

1

0

Reserved

TxVALIDITY

TxRATIO2

TxRATIO1

TxRATIO0

TxCLKSEL1

TxCLKSEL0

TxENABLE

Table 38. Transmitter Control Register Bit Descriptions

Bit Name

Description

TxVALIDITY

This bit is used to set or clear the VALIDITY bit in the AES3/S/PDIF transmit stream.

0 = Audio is suitable for digital-to-analog conversion.

1 = Audio is not suitable for digital-to-analog conversion.

Determines the AES3/S/PDIF transmitter to AES3/S/PDIF receiver ratio.

000 = Transmitter to receiver ratio is 1:1.

TxRATIO[2:0]

001 = Transmitter to receiver ratio is 1:2.

010 = Transmitter to receiver ratio is 1:4.

101 = Transmitter to receiver ratio is 2:1.

110 = Transmitter to receiver ratio is 4:1.

TxCLKSEL[1:0]

TxENABLE

Selects the clock source for the AES3/S/PDIF transmitter.

00 = Internal Clock 1 is the clock source for the transmitter.

01 = Internal Clock 2 is the clock source for the transmitter.

10 = Recovered PLL clock is the clock source for the transmitter.

11 = Reserved.

Enables the AES3/S/PDIF transmitter.

0 = AES3/S/PDIF transmitter is disabled.

1 = AES3/S/PDIF transmitter is enabled.

Rev. A | Page 37 of 60

ADAV803

Transmitter Buffer Configuration—Address 0001101 (0x0D)

Table 39. Transmitter Buffer Configuration Register Bit Map

7

6

5

4

3

2

1

0

IU_Zeros3

IU_Zeros2

IU_Zeros1

IU_Zeros0

TxBCONF3

TxBCONF2

TxBCONF1

TxBCONF0

Table 40. Transmitter Buffer Configuration Register Bit Descriptions

Bit Name

Description

IU_Zeros[3:0]

Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8.

0000 = 0.

0001 = 1.

…

0111 = 7.

1000 = 8.

TxBCONF3

Transmitter user bits can be stored in separate buffers or stored together.

0 = User bits are stored together.

1 = User bits are stored separately.

TxBCONF[2:1]

Configures the transmitter user bit buffer.

00 = Zeros are transmitted for the user bits.

01 = Transmitter user bit buffer size is configured according to TxBCONF0.

10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard.

11 = Reserved.

TxBCONF0

Determines the buffer size of the transmitter user bits when TxBCONF[2:1] is 01.

0 = 384 bits with Preamble Z as the start of the buffer.

1 = 768 bits with Preamble Z as the start of the buffer.

Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E)

Table 41. Channel Status Switch Buffer and Transmitter Register Bit Map

7

6

5

4

3

2

1

0

Reserved

Tx_A/B_Same

Disable_Tx_Copy Reserved

Reserved

TxCSSWITCH

RxCSSWITCH

Table 42. Channel Status Switch Buffer and Transmitter Register Bit Description

Bit Name

Description

Tx_A/B_Same

Transmitter Channel Status A and B are the same. The transmitter reads only from the Channel Status A buffer and

places the data into the Channel Status B buffer.

0 = Channel status for A and B are separate.

1 = Channel status for A and B are the same.

Disable_Tx_Copy

Disables the copying of the channel status bits from the transmitter channel status buffer to the S/PDIF transmitter

buffer.

0 = Copying transmitter channel status is enabled.

1 = Copying transmitter channel status is disabled.

TxCSSWITCH

RxCSSWITCH

Toggle switch for the transmit channel status buffer.

0 = 24-byte Transmitter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F.

1 = 24-byte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F.

Toggle switch for the receive channel status buffer.

0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37.

1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.

Rev. A | Page 38 of 60

ADAV803

Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F)

Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map

7

6

5

4

3

2

1

0

MSBZeros7

MSBZeros6

MSBZeros5

MSBZeros4

MSBZeros3

MSBZeros2

MSBZeros1

MSBZeros0

Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description

Bit Name

Description

MSBZeros[7:0]

Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets).

Default = 0x00.

Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10)

Table 45. Transmitter Message Zeros Least Significant Byte Register Bit Map

7

6

5

4

3

2

1

0

LSBZeros7

LSBZeros6

LSBZeros5

LSBZeros4

LSBZeros3

LSBZeros2

LSBZeros1

LSBZeros0

Table 46. Transmitter Message Zeros Least Significant Byte Register Bit Descriptions

Bit Name

Description

LSBZeros[7:0]

Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09.

Autobuffer—Address 0010001 (0x11)

Table 47. Autobuffer Register Bit Map

7

6

5

4

3

2

1

0

Reserved

Zero_Stuff_IU

Auto_UBits

Auto_CSBits

IU_Zeros3

IU_Zeros2

IU_Zeros1

IU_Zeros0

Table 48. Autobuffer Register Bit Descriptions

Bit Name

Description

Zero_Stuff_IU

Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format.

0 = No zeros added or subtracted.

1 = Zeros can be added or subtracted between IUs.

Auto_UBits

Auto_CSBits

IU_Zeros[3:0]

Enables the user bits to be autobuffered between the AES3/S/PDIF receiver and transmitter.

0 = User bits are not autobuffered.

1 = User bits are autobuffered.

Enables the channel status bits to be autobuffered between the AES3/S/PDIF receiver and transmitter.

0 = Channel status bits are not autobuffered.

1 = Channel status bits are autobuffered.

Sets the maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8.

0000 = 0.

0001 = 1.

…

0111 = 7.

1000 = 8.

Sample Rate Ratio MSB—Address 0010010 (0x12)

Table 49. Sample Rate Ratio MSB Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

Reserved

SRCRATIO14

SRCRATIO13

SRCRATIO12

SRCRATIO11

SRCRATIO10

SRCRATIO09

SRCRATIO08

Table 50. Sample Rate Ratio MSB Register (Read-Only) Bit Descriptions

Bit Name

Description

SRCRATIO[14:8]

Seven most significant bits of the15-bit sample rate ratio.

Rev. A | Page 39 of 60

ADAV803

Sample Rate Ratio LSB—Address 0010011 (0x13)

Table 51. Sample Rate Ratio LSB Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

SRCRATIO07

SRCRATIO06

SRCRATIO05

SRCRATIO04

SRCRATIO03

SRCRATIO02

SRCRATIO01

SRCRATIO00

Table 52. Sample Rate Ratio LSB Register (Read-Only) Bit Descriptions

Bit Name

Description

SRCRATIO[7:0]

Eight least significant bits of the15-bit sample rate ratio.

Preamble-C MSB—Address 0010100 (0x14)

Table 53. Preamble-C MSB Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

PRE_C15

PRE_C14

PRE_C13

PRE_C12

PRE_C11

PRE_C10

PRE_C9

PRE_C8

Table 54. Preamble-C MSB Register (Read-Only) Bit Descriptions

Bit Name

Description

PRE_C[15:8]

Eight most significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937

standard; otherwise, bits show zeros.

Preamble-C LSB—Address 0010101 (0x15)

Table 55. Preamble-C LSB Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

PRE_C07

PRE_C06

PRE_C05

PRE_C04

PRE_C03

PRE_C02

PRE_C01

PRE_C00

Table 56. Preamble-C LSB Register (Read-Only) Bit Descriptions

Bit Name

Description

PRE_C[7:0]

Eight least significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937

standard; otherwise, bits show zeros.

Preamble-D MSB—Address 0010110 (0x16)

Table 57. Preamble-D MSB Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

PRE_D15

PRE_D14

PRE_D13

PRE_D12

PRE_D11

PRE_D10

PRE_D9

PRE_D8

Table 58. Preamble-D MSB Register (Read-Only) Bit Descriptions

Bit Name

Description

PRE_D[15:8]

Eight most significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937

standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits

of the 16-bit Preamble-C of Channel B.

Preamble-D LSB—Address 0010111 (0x17)

Table 59. Preamble-D LSB Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

PRE_D07

PRE_D06

PRE_D05

PRE_D04

PRE_D03

PRE_D02

PRE_D01

PRE_D00

Table 60. Preamble-D LSB Register (Read-Only) Bit Descriptions

Bit Name

Description

PRE_D[7:0]

Eight least significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937

standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits

of the 16-bit Preamble-C of Channel B.

Rev. A | Page 40 of 60

ADAV803

Receiver Error—Address 0011000 (0x18)

Table 61. Receiver Error Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

RxValidity

Emphasis

NonAudio

NonAudio Preamble

CRCError

NoStream

BiPhase/Parity

Lock

Table 62. Receiver Error Register (Read-Only) Bit Descriptions

Bit Name

RxValidity

Emphasis

Description

This is the VALIDITY bit in the AES3 received stream.

This bit is set if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an

interrupt unless it changes state.

NonAudio

This bit is set when Channel Status Bit 1 (nonaudio) is set. Once it has been read, it does not generate another interrupt

unless the data becomes audio or the type of nonaudio data changes.

NonAudio

Preamble

This bit is set if the audio data is nonaudio due to the detection of a preamble. The nonaudio preamble type register

indicates what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt

unless it changes state.

CRCError

This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error register is read.

NoStream

This bit is set if there is no AES3/S/PDIF stream present at the AES3/S/PDIF receiver. Once read, it remains high and does

not generate an interrupt unless it changes state.

BiPhase/Parity

Lock

This bit is set if a biphase or parity error occurred in the AES3/S/PDIF stream. This bit is not cleared until the register is read.

This bit is set if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not

generate an interrupt unless it changes state.

Receiver Error Mask—Address 0011001 (0x19)

Table 63. Receiver Error Mask Register Bit Map

7

6

5

4

3

2

1

0

RxValidity

Mask

Emphasis

Mask

NonAudio

Mask

NonAudio Preamble

Mask

CRCError

Mask

NoStream

Mask

BiPhase/Parity

Mask

Lock

Mask

Table 64. Receiver Error Mask Register Bit Descriptions

Bit Name

Description

RxValidity Mask

Masks the RxValidity bit from generating an interrupt.

0 = RxValidity bit does not generate an interrupt.

1 = RxValidity bit generates an interrupt.

Emphasis Mask

Masks the Emphasis bit from generating an interrupt.

0 = Emphasis bit does not generate an interrupt.

1 = Emphasis bit generates an interrupt.

NonAudio Mask

NonAudio Preamble Mask

CRCError Mask

Masks the NonAudio bit from generating an interrupt.

0 = NonAudio bit does not generate an interrupt.

1 = NonAudio bit generates an interrupt.

Masks the NonAudio preamble bit from generating an interrupt.

0 = NonAudio preamble bit does not generate an interrupt.

1 = NonAudio preamble bit generates an interrupt.

Masks the CRCError bit from generating an interrupt.

0 = CRCError bit does not generate an interrupt.

1 = CRCError bit generates an interrupt.

NoStream Mask

BiPhase/Parity Mask

Lock Mask

Masks the NoStream bit from generating an interrupt.

0 = NoStream bit does not generate an interrupt.

1 = NoStream bit generates an interrupt.

Masks the BiPhase/Parity bit from generating an interrupt.

0 = BiPhase/Parity bit does not generate an interrupt.

1 = BiPhase/Parity bit generates an interrupt.

Masks the Lock bit from generating an interrupt.

0 = Lock bit does not generate an interrupt.

1 = Lock bit generates an interrupt.

Rev. A | Page 41 of 60

ADAV803

Sample Rate Converter Error—Address 0011010 (0x1A)

Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

Reserved

TOO_SLOW

OVRL

OVRR

MUTE_IND

Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions

Bit Name

Description

TOO_SLOW

This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the

internal convolution.

OVRL

This bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been

clipped. This bit is not cleared until the register is read.

OVRR

This bit is set when the right output data of the sample rate converter has gone over the full-scale range and has

been clipped. This bit is not cleared until the register is read.

MUTE_IND

Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.

The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state

and does not generate an interrupt until it has changed state.

Sample Rate Converter Error Mask—Address 0011011 (0x1B)

Table 67. Sample Rate Converter Error Mask Register Bit Map

7

6

5

4

3

2

1

0

Reserved

OVRL Mask

OVRR Mask

MUTE_IND MASK

Table 68. Sample Rate Converter Error Mask Register Bit Descriptions

Bit Name

Description

OVRL Mask

Masks the OVRL from generating an interrupt.

0 = OVRL bit does not generate an interrupt.

1 = OVRL bit generates an interrupt.

OVRR Mask

Masks the OVRR from generating an interrupt.

0 = OVRR bit does not generate an interrupt.

1 = OVRR bit generates an interrupt. Reserved.

Masks the MUTE_IND from generating an interrupt.

0 = MUTE_IND bit does not generate an interrupt.

1 = MUTE_IND bit generates an interrupt.

MUTE_IND MASK

Rev. A | Page 42 of 60

ADAV803

Interrupt Status—Address 0011100 (0x1C)

Table 69. Interrupt Status Register Bit Map

7

6

5

4

3

2

1

0

SRCError

TxCSTINT

TxUBINT

TxCSBINT

RxCSDIFF

RxUBINT

RxCSBINT

RxERROR

Table 70. Interrupt Status Register Bit Descriptions

Bit Name

Description

SRCError

This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample

rate converter error register. This bit remains high until the interrupt status register is read.

TxCSTINT

This bit is set if a write to the transmitter channel status buffer was made while transmitter channel status bits were being

copied from the transmitter CS buffer to the S/PDIF transmit buffer.

TxUBINT

This bit is set if the S/PDIF transmit buffer is empty. This bit remains high until the interrupt status register is read.

TxCSBINT

This bit is set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit remains high

until the interrupt status register is read.

RxCSDIFF

RxUBINT

RxCSBINT

RxERROR

This bit is set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit remains

high until read, but does not generate an interrupt.

This bit is set if the receiver user bit buffer has a new block or message. This bit remains high until the interrupt status

register is read.

This bit is set if a new block of channel status is read when RxBCONF3 = 0, or if the channel status has changed when

RxBCONF3 = 1. This bit remains high until the interrupt status register is read.

This bit is set if one of the AES3/S/PDIF receiver interrupts is asserted, and the host should immediately read the receiver

error register. This bit remains high until the interrupt status register is read.

Interrupt Status Mask—Address 0011101 (0x1D)

Table 71. Interrupt Status Mask Register Bit Map

7

6

5

4

3

2

1

0

SRCError Mask

TxCSTINT Mask

TxUBINT Mask

TxCSBINT Mask

Reserved

RxUBINT Mask

RxCSBINT Mask

RxError Mask

Table 72. Interrupt Status Mask Register Bit Descriptions

Bit Name

Description

SRCError Mask

Masks the SRCError bit from generating an interrupt.

0 = SRCError bit does not generate an interrupt.

1 = SRCError bit generates an interrupt.

TxCSTINT Mask

TxUBINT Mask

TxCSBINT Mask

RxUBINT Mask

RxCSBINT Mask

RxError Mask

Masks the TxCSTINT bit from generating an interrupt.

0 = TxCSTINT bit does not generate an interrupt.

1 = TxCSTINT bit generates an interrupt.

Masks the TxUBINT bit from generating an interrupt.

0 = TxUBINT bit does not generate an interrupt.

1 = TxUBINT bit generates an interrupt.

Masks the TxCSBINT bit from generating an interrupt.

0 = TxCSBINT bit does not generate an interrupt.

1 = TxCSBINT bit generates an interrupt.

Masks the RxUBINT bit from generating an interrupt.

0 = RxUBINT bit does not generate an interrupt.

1 = RxUBINT bit generates an interrupt.

Masks the RxCSBINT bit from generating an interrupt.

0 = RxCSBINT bit does not generate an interrupt.

1 = RxCSBINT bit generates an interrupt.

Masks the RxError bit from generating an interrupt.

0 = RxError bit does not generate an interrupt.

1 = RxError bit generates an interrupt.

Rev. A | Page 43 of 60

ADAV803

Mute and De-Emphasis—Address 0011110 (0x1E)

Table 73. Mute and De-Emphasis Register Bit Map

7

6

5

4

3

2

1

0

Reserved

TxMUTE

Reserved

SRC_DEEM1

SRC_DEEM0

Reserved

Table 74. Mute and De-Emphasis Register Bit Descriptions

Bit Name

Description

TxMUTE

Mutes the AES3/S/PDIF transmitter.

0 = Transmitter is not muted.

1 = Transmitter is muted.

SRC_DEEM[1:0]

Selects the de-emphasis filter for the input data to the sample rate converter.

00 = No de-emphasis.

01 = 32 kHz de-emphasis.

10 = 44.1 kHz de-emphasis.

11 = 48 kHz de-emphasis.

NonAudio Preamble Type—Address 0011111 (0x1F)

Table 75. NonAudio Preamble Type Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

Reserved

DTS-CD

Preamble

NonAudio

Frame

NonAudio

Subframe_A

NonAudio

Subframe_B

Table 76. NonAudio Preamble Type Register (Read-Only) Bit Descriptions

Bit Name

Description

DTS-CD Preamble

NonAudio Frame

This bit is set if the DTS-CD preamble is detected.

This bit is set if the data received through the AES3/S/PDIF receiver is nonaudio data according to the IEC61937

standard or nonaudio data according to SMPTE337M.

NonAudio Subframe_A This bit is set if the data received through Channel A of the AES3/S/PDIF receiver is subframe nonaudio data

according to SMPTE337M.

NonAudio Subframe_B This bit is set if the data received through Channel B of the AES3/S/PDIF receiver is subframe nonaudio data

according to SMPTE337M.

Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37)

Table 77. Receiver Channel Status Buffer Register Bit Map

7

6

5

4

3

2

1

0

RCSB7

RCSB6

RCSB5

RCSB4

RCSB3

RCSB2

RCSB1

RCSB0

Table 78. Receiver Channel Status Buffer Register Bit Descriptions

Bit Name

Description

RCSB[7:0]

The 24-byte receiver channel status buffer. The PRO bit is stored at address location 0x20, Bit 0. This buffer is read-

only if the channel status is not autobuffered between the receiver and transmitter.

Transmitter Channel Status Buffer—Address 0111000 to Address 1001111 (0x38 to 0x4F)

Table 79. Transmitter Channel Status Buffer Register Bit Map

7

6

5

4

3

2

1

0

TCSB7

TCSB6

TCSB5

TCSB4

TCSB3

TCSB2

TCSB1

TCSB0

Table 80. Transmitter Channel Status Buffer Register Bit Descriptions

Bit Name

Description

TCSB[7:0]

The 24-byte transmitter channel status buffer. The PRO bit is stored at address location 0x38, Bit 0. This buffer is

disabled when autobuffering between the receiver and transmitter is enabled.

Rev. A | Page 44 of 60

ADAV803

Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50)

Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map

7

6

5

4

3

2

1

0

RxUBADDR7

RxUBADDR6

RxUBADDR5

RxUBADDR4

RxUBADDR3

RxUBADDR2

RxUBADDR1

RxUBADDR0

Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions

Bit Name

Description

RxUBADDR[7:0]

Indirect address pointing to the address location in the receiver user bit buffer.

Receiver User Bit Buffer Data—Address 1010001 (0x51)

Table 83. Receiver User Bit Buffer Data Register Bit Map

7

6

5

4

3

2

1

0

RxUBDATA7

RxUBDATA6

RxUBDATA5

RxUBDATA4

RxUBDATA3

RxUBDATA2

RxUBDATA1

RxUBDATA0

Table 84. Receiver User Bit Buffer Data Register Bit Descriptions

Bit Name

Description

RxUBDATA[7:0]

A read from this register reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR0[7:0].

This buffer can be written to when autobuffering of the user bits is enabled; otherwise, it is a read-only buffer.

Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52)

Table 85. Transmitter User Bit Buffer Indirect Address Register Bit Map

7

6

5

4

3

2

1

0

TxUBADDR7

TxUBADDR6

TxUBADDR5

TxUBADDR4

TxUBADDR3

TxUBADDR2

TxUBADDR1

TxUBADDR0

Table 86. Transmitter User Bit Buffer Indirect Address Register Bit Descriptions

Bit Name

Description

TxUBADDR[7:0]

Indirect address pointing to the address location in the transmitter user bit buffer.

Transmitter User Bit Buffer Data—Address 1010011 (0x53)

Table 87. Transmitter User Bit Buffer Data Register Bit Map

7

6

5

4

3

2

1

0

TxUBDATA7

TxUBDATA6

TxUBDATA5

TxUBDATA4

TxUBDATA3

TxUBDATA2

TxUBDATA1

TxUBDATA0

Table 88. Transmitter User Bit Buffer Data Register Bit Descriptions

Bit Name

Description

TxUBDATA[7:0]

A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR0[7:0].

When user bit autobuffering is enabled, this buffer is disabled.

Q Subcode CRCError Status—Address 1010100 (0x54)

Table 89. Q Subcode CRCError Status Register (Read-Only) Bit Map

7

6

5

4

3

2

1

0

Reserved

QCRCERROR

QSUB

Table 90. Q Subcode CRCError Status Register (Read-Only) Bit Descriptions

Bit Name

Description

QCRCERROR

This bit is set if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This

bit is cleared once the register is read.

QSUB

This bit is set if a Q subcode has been read into the Q subcode buffer (see Table 91).

Rev. A | Page 45 of 60

ADAV803

Q Subcode Buffer—Address 0x55 to Address 0x5E

Table 91. Q Subcode Buffer Bit Map

Address Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x55

0x56

Address

Control

Track

number

0x57

0x58

0x59

0x5A

0x5B

0x5C

Index

Minute

Second

Frame

Zero

Minute

Second

Frame

Zero

Minute

Second

Frame

Zero

Minute

Second

Frame

Zero

Minute

Second

Frame

Zero

Minute

Second

Frame

Zero

Minute

Second

Frame

Zero

Minute

Second

Frame

Zero

Absolute

minute

Absolute

minute

Absolute

minute

Absolute

minute

Absolute

minute

Absolute

minute

Absolute

minute

Absolute

minute

0x5D

0x5E

Absolute

second

Absolute

second

Absolute

second

Absolute

second

Absolute

second

Absolute

second

Absolute

second

Absolute

second

Absolute

frame

Absolute

frame

Absolute

frame

Absolute

frame

Absolute

frame

Absolute

frame

Absolute

frame

Absolute

frame

Datapath Control Register 1—Address 1100010 (0x62)

Table 92. Datapath Control Register 1 Bit Map

7

6

5

4

3

2

1

0

SRC1

SRC0

REC2

REC1

REC0

AUXO2

AUXO1

AUXO0

Table 93. Datapath Control Register 1 Bit Descriptions

Bit Name

Description

SRC[1:0]

Datapath source select for sample rate converter (SRC).

00 = ADC.

01 = DIR.

10 = Playback.

11 = Auxiliary in.

REC[2:0]

Datapath source select for record output port.

000 = ADC.

001 = DIR.

010 = Playback.

011 = Auxiliary in.

100 = SRC.

AUXO[2:0]

Datapath source select for auxiliary output port.

000 = ADC.

001 = DIR.

010 = Playback.

011 = Auxiliary in.

100 = SRC.

Rev. A | Page 46 of 60

ADAV803

Datapath Control Register 2—Address 1100011 (0x63)

Table 94. Datapath Control Register 2 Bit Map

7

6

5

4

3

2

1

0

Reserved

DAC2

DAC1

DAC0

DIT2

DIT1

DIT0

Table 95. Datapath Control Register 2 Bit Descriptions

Bit Name

Description

DAC[2:0]

Datapath source select for DAC.

00 = ADC.

01 = DIR.

10 = Playback.

11 = Auxiliary in.

100 = SRC.

DIT[2:0]

Datapath source select for DIT.

000 = ADC.

001 = DIR.

010 = Playback.

011 = Auxiliary in.

100 = SRC.

DAC Control Register 1—Address 1100100 (0x64)

Table 96. DAC Control Register 1 Bit Map

7

6

5

4

3

2

1

0

DR_ALL

DR_DIG

CHSEL1

CHSEL0

POL1

POL0

MUTER

MUTEL

Table 97. DAC Control Register 1 Bit Descriptions

Bit Name

Description

DR_ALL

Hard reset and power-down.

0 = Normal, output pins go to V_REFlevel.

1 = Hard reset and low power, output pins go to AGND.

DAC digital reset.

DR_DIG

0 = Normal.

1 = Reset all except registers.

DAC channel select.

00 = Normal, left-right.

01 = Both right.

CHSEL[1:0]

10 = Both left.

11 = Swapped, right-left.

DAC channel polarity.

00 = Both positive.

01 = Left negative.

10 = Right negative.

11 = Both negative.

Mute right channel.

0 = Mute.

POL[1:0]

MUTER

MUTEL

1 = Normal.

Mute left channel.

0 = Mute.

1 = Normal.

Rev. A | Page 47 of 60

ADAV803

DAC Control Register 2—Address 1100101 (0x65)

Table 98. DAC Control Register 2 Bit Map

7

6

5

4

3

2

1

0

Reserved

DMCLK1

DMCLK0

DFS1

DFS0

DEEM1

DEEM0

Table 99. DAC Control Register 2 Bit Descriptions

Bit Name

Description

DMCLK[1:0]

DAC MCLK divider.

00 = MCLK.

01 = MCLK/1.5.

10 = MCLK/2.

11 = MCLK/3.

DFS[1:0]

DAC interpolator select.

00 = 8 × (MCLK = 256 × f_S).

01 = 4 × (MCLK = 128 × f_S).

10 = 2 × (MCLK = 64 × f_S).

11 = Reserved.

DEEM[1:0]

DAC de-emphasis select.

00 = None.

01 = 44.1 kHz.

10 = 32 kHz.

11 = 48 kHz.

DAC Control Register 3—Address 1100110 (0x66)

Table 100. DAC Control Register 3 Bit Map

7

6

5

4

3

2

1

0

Reserved

ZFVOL

ZFDATA

ZFPOL

Table 101. DAC Control Register 3 Bit Descriptions

Bit Name

Description

ZFVOL

DAC zero flag on mute and zero volume.

0 = Enabled.

1 = Disabled.

ZFDATA

ZFPOL

DAC zero flag on zero data disable.

0 = Enabled.

1 = Disabled.

DAC zero flag polarity.

0 = Active low.

1 = Active high.

Rev. A | Page 48 of 60

ADAV803

DAC Control Register 4—Address 1100111 (0x67)

Table 102. DAC Control Register 4 Bit Map

7

6

5

4

3

2

1

0

Reserved

INTRPT

ZEROSEL1

ZEROSEL0

Reserved

Table 103. DAC Control Register 4 Bit Descriptions

Bit Name

Description

INTRPT

This bit selects the functionality of the ZEROL/INT pin.

0 = Pin functions as a ZEROL flag pin.

1 = Pin functions as an interrupt pin.

ZEROSEL[1:0]

These bits control the functionality of the ZEROR pin when the ZEROL/INT pin is used as an interrupt.

00 = Pin functions as a ZEROR flag pin.

01 = Pin functions as a ZEROL flag pin.

10 = Pin is asserted when either the left or right channel is zero.

11 = Pin is asserted when both the left and right channels are zero.

DAC Left Volume—Address 1101000 (0x68)

Table 104. DAC Left Volume Register Bit Map

7

6

5

4

3

2

1

0

DVOLL7

DVOLL6

DVOLL5

DVOLL4

DVOLL3

DVOLL2

DVOLL1

DVOLL0

Table 105. DAC Left Volume Register Bit Descriptions

Bit Name

Description

DVOLL[7:0]

DAC left channel volume control.

1111111 = 0 dBFS.

1111110 = −0.375 dBFS.

0000000 = −95.625 dBFS.

DAC Right Volume—Address 1101001 (0x69)

Table 106. DAC Right Volume Register Bit Map

7

6

5

4

3

2

1

0

DVOLR7

DVOLR6

DVOLR5

DVOLR4

DVOLR3

DVOLR2

DVOLR1

DVOLR0

Table 107. DAC Right Volume Register Bit Descriptions

Bit Name

Description

DVOLR[7:0]

DAC right channel volume control.

1111111 = 0 dBFS.

1111110 = −0.375 dBFS.

0000000 = −95.625 dBFS.

DAC Left Peak Volume—Address 1101010 (0x6A)

Table 108. DAC Left Peak Volume Register Bit Map

7

6

5

4

3

2

1

0

Reserved

DLP5

DLP4

DLP3

DLP2

DLP1

DLP0

Table 109. DAC Left Peak Volume Register Bit Descriptions

Bit Name

Description

DLP[5:0]

DAC left channel peak volume detection.

000000 = 0 dBFS.

000001 = −1 dBFS.

111111 = −63 dBFS.

Rev. A | Page 49 of 60

ADAV803

DAC Right Peak Volume—Address 1101011 (0x6B)

Table 110. DAC Right Peak Volume Register Bit Map

7

6

5

4

3

2

1

0

Reserved

DRP5

DRP4

DRP3

DRP2

DRP1

DRP0

Table 111. DAC Right Peak Volume Register Bit Descriptions

Bit Name

Description

DRP[5:0]

DAC right channel peak volume detection.

000000 = 0 dBFS.

000001 = −1 dBFS.

111111 = −63 dBFS.

ADC Left Channel PGA Gain—Address 1101100 (0x6C)

Table 112. ADC Left Channel PGA Gain Register Bit Map

7

6

5

4

3

2

1

0

Reserved

AGL5

AGL4

AGL3

AGL2

AGL1

AGL0

Table 113. ADC Left Channel PGA Gain Register Bit Descriptions

Bit Name

Description

AGL[5:0]

PGA left channel gain control.

000000 = 0 dB.

000001 = 0.5 dB.

…

101111 = 23.5 dB.

110000 = 24 dB.

…

111111 = 24 dB.

ADC Right Channel PGA Gain—Address 1101101 (0x6D)

Table 114. ADC Right Channel PGA Gain Register Bit Map

7

6

5

4

3

2

1

0

Reserved

AGR5

AGR4

AGR3

AGR2

AGR1

AGR0

Table 115. ADC Right Channel PGA Gain Register Bit Descriptions

Bit Name

Description

AGR[5:0]

PGA right channel gain control.

000000 = 0 dB.

000001 = 0.5 dB.

…

101111 = 23.5 dB.

110000 = 24 dB.

…

111111 = 24 dB.

Rev. A | Page 50 of 60

ADAV803

ADC Control Register 1—Address 1101110 (0x6E)

Table 116. ADC Control Register 1 Bit Map

7

6

5

4

3

2

1

0

AMC

HPF

PWRDWN

ANA_PD

MUTER

MUTEL

PLPD

PRPD

Table 117. ADC Control Register 1 Bit Descriptions

Bit Name

Description

AMC

ADC modulator clock.

0 = ADC MCLK/2 (128 × f_S).

1 = ADC MCLK/4 (64 × f_S).

High-pass filter enable.

0 = Normal.

HPF

1 = HPF enabled.

ADC power-down.

0 = Normal.

1 = Power-down.

ADC analog section power-down.

0 = Normal.

1 = Power-down.

Mute ADC right channel.

0 = Normal.

PWRDWN

ANA_PD

MUTER

MUTEL

PLPD

1 = Muted.

Mute ADC left channel.

0 = Normal.

1 = Muted.

PGA left power-down.

0 = Normal.

1 = Power-down.

PGA right power-down.

0 = Normal.

PRPD

1 = Power-down.

ADC Control Register 2—Address 1101111 (0x6F)

Table 118. ADC Control Register 2 Bit Map

7

6

5

4

3

2

1

0

Reserved

BUF_PD

Reserved

MCD1

MCD0

Table 119. ADC Control Register 2 Bit Descriptions

Bit Name

Description

BUF_PD

Reference buffer power-down control.

0 = Normal.

1 = Power-down.

MCD[1:0]

ADC master clock divider.

00 = Divide by 1.

01 = Divide by 2.

10 = Divide by 3.

11 = Divide by 1.

Rev. A | Page 51 of 60

ADAV803

ADC Left Volume—Address 1110000 (0x70)

Table 120. ADC Left Volume Register Bit Map

7

6

5

4

3

2

1

0

AVOLL7

AVOLL6

AVOLL5

AVOLL4

AVOLL3

AVOLL2

AVOLL1

AVOLL0

Table 121. ADC Left Volume Register Bit Descriptions

Bit Name

Description

AVOLL[7:0]

ADC left channel volume control.

1111111 = 1.0 (0 dBFS).

1111110 = 0.996 (−0.00348 dBFS).

1000000 = 0.5 (−6 dBFS).

0111111 = 0.496 (−6.09 dBFS).

0000000 = 0.0039 (−48.18 dBFS).

ADC Right Volume—Address 1110001 (0x71)

Table 122. ADC Right Volume Register Bit Map

7

6

5

4

3

2

1

0

AVOLR7

AVOLR6

AVOLR5

AVOLR4

AVOLR3

AVOLR2

AVOLR1

AVOLR0

Table 123. ADC Right Volume Register Bit Descriptions

Bit Name

Description

AVOLR[7:0]

ADC right channel volume control.

1111111 = 1.0 (0 dBFS).

1111110 = 0.996 (−0.00348 dBFS).

1000000 = 0.5 (−6 dBFS).

0111111 = 0.496 (−6.09 dBFS).

0000000 = 0.0039 (−48.18 dBFS).

ADC Left Peak Volume—Address 1110010 (0x72)

Table 124. ADC Left Peak Volume Register Bit Map

7

6

5

4

3

2

1

0

Reserved

ALP5

ALP4

ALP3

ALP2

ALP1

ALP0

Table 125. ADC Left Peak Volume Register Bit Descriptions

Bit Name

Description

ALP[5:0]

ADC left channel peak volume detection.

000000 = 0 dBFS.

000001 = −1 dBFS.

111111 = −63 dBFS.

ADC Right Peak Volume—Address 1110011 (0x73)

Table 126. ADC Right Peak Volume Register Bit Map

7

6

5

4

3

2

1

0

Reserved

ARP5

ARP4

ARP3

ARP2

ARP1

ARP0

Table 127. ADC Right Peak Volume Register Bit Descriptions

Bit Name

Description

ARP[5:0]

ADC right channel peak volume detection.

000000 = 0 dBFS.

000001 = −1 dBFS.

111111 = −63 dBFS.

Rev. A | Page 52 of 60

ADAV803

PLL Control Register 1—Address 1110100 (0x74)

Table 128. PLL Control Register 1 Bit Map

7

6

5

4

3

2

1

0

DIRIN_CLK1

DIRIN_CLK0

MCLKODIV

PLLDIV

PLL2PD

PLL1PD

XTLPD

SYSCLK3

Table 129. PLL Control Register 1 Bit Descriptions

Bit Name

Description

DIRIN_CLK[1:0]

Recovered S/PDIF clock sent to SYSCLK3.

00 = SYSCLK3 comes from PLL block.

01 = Reserved.

10 = Reserved.

11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN.

Divide input MCLK by 2 to generate MCLKO.

0 = Disabled.

MCLKODIV

PLLDIV

1 = Enabled.

Divide XIN by 2 to generate the PLL master clock.

0 = Disabled.

1 = Enabled.

PLL2PD

PLL1PD

XTLPD

Power-down PLL2.

0 = Normal.

1 = Power-down.

Power-down PLL1.

0 = Normal.

1 = Power-down.

Power-down XTAL oscillator.

0 = Normal.

1 = Power-down.

SYSCLK3

Clock output for SYSCLK3.

0 = 512 × f_S.

1 = 256 × f_S.

Rev. A | Page 53 of 60

ADAV803

PLL Control Register 2—Address 1110101 (0x75)

Table 130. PLL Control Register 2 Bit Map

7

6

5

4

3

2

1

0

FS2_1

FS2_0

SEL2

DOUB2

FS1

FS0

SEL1

DOUB1

Table 131. PLL Control Register 2 Bit Descriptions

Bit Name

Description

FS2_[1:0]

Sample rate select for PLL2.

00 = 48 kHz.

01 = Reserved.

10 = 32 kHz.

11 = 44.1 kHz.

SEL2

Oversample ratio select for PLL2.

0 = 256 × f_S.

1 = 384 × f_S.

DOUB2

FS[1:0]

Double-selected sample rate on PLL2.

0 = Disabled.

1 = Enabled.

Sample rate select for PLL1.

00 = 48 kHz.

01 = Reserved.

10 = 32 kHz.

11 = 44.1 kHz.

SEL1

Oversample ratio select for PLL1.

0 = 256 × f_S.

1 = 384 × f_S.

DOUB1

Double-selected sample rate on PLL1.

0 = Disabled.

1 = Enabled.

Rev. A | Page 54 of 60

ADAV803

Internal Clocking Control Register 1—Address 1110110 (0x76)

Table 132. Internal Clocking Control Register 1 Bit Map

7

6

5

4

3

2

1

0

DCLK2

DCLK1

DCLK0

ACLK2

ACLK1

ACLK0

ICLK2_1

ICLK2_0

Table 133. Internal Clocking Control Register 1 Bit Descriptions

Bit Name

Description

DCLK[2:0]

DAC clock source select.

000 = XIN.

001 = MCLKI.

010 = PLLINT1.

011 = PLLINT2.

100 = DIR PLL (512 × f_S).

101 = DIR PLL (256 × f_S).

110 = XIN.

111 = XIN.

ACLK[2:0]

ADC clock source select.

000 = XIN.

001 = MCLKI.

010 = PLLINT1.

011 = PLLINT2.

100 = DIR PLL (512 × f_S).

101 = DIR PLL (256 × f_S).

110 = XIN.

111 = XIN.

ICLK2_[1:0]

Source selector for internal clock ICLK2.

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

Internal Clocking Control Register 2—Address 1110111 (0x77)

Table 134. Internal Clocking Control Register 2 Bit Map

7

6

5

4

3

2

1

0

Reserved

ICLK1_1

ICLK1_0

PLL2INT1

PLL2INT0

PLL1INT

Table 135. Internal Clocking Control Register 2 Bit Descriptions

Bit Name

Description

ICLK1_[1:0]

Source selector for internal clock ICLK1.

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

PLL2INT[1:0]

PLL1INT

PLL2 internal selector (see Figure 38).

00 = FS2.

01 = FS2/2.

10 = FS3.

11 = FS3/2.

PLL1 internal selector.

0 = FS1.

1 = FS1/2.

Rev. A | Page 55 of 60

ADAV803

PLL Clock Source Register—Address 1111000 (0x78)

Table 136. PLL Clock Source Register Bit Map

7

6

5

4

3

2

1

0

PLL2_Source

PLL1_Source

Reserved

Table 137. PLL Clock Source Register Bit Descriptions

Bit Name

Description

PLL2_Source

Selects the clock source for PLL2.

0 = XIN.

1 = MCLKI.

PLL1_Source

Selects the clock source for PLL1.

0 = XIN.

1 = MCLKI

PLL Output Enable—Address 1111010 (0x7A)

Table 138. PLL Output Enable Register Bit Map

7

6

5

4

3

2

1

0

Reserved

DIRINPD

DIRIN_PIN

Reserved

SYSCLK1

SYSCLK2

SYSCLK3

Table 139. PLL Output Enable Register Bit Descriptions

Bit Name

Description

DIRINPD

This bit powers down the S/PDIF receiver.

0 = Normal.

1 = Power-down.

DIRIN_PIN

SYSCLK1

SYSCLK2

SYSCLK3

This bit determines the input levels of the DIRIN pin.

0 = DIRIN accepts input signals down to 200 mV according to AES3 requirements.

1 = DIRIN accepts input signals as defined in the Specifications section.

Enables the SYSCLK1 output.

0 = Enabled.

1 = Disabled.

Enables the SYSCLK2 output.

0 = Enabled.

1 = Disabled.

Enables the SYSCLK3 output.

0 = Enabled.

1 = Disabled.

Rev. A | Page 56 of 60

ADAV803

ALC Control Register 1—Address 1111011 (0x7B)

Table 140. ALC Control Register 1 Bit Map

7

6

5

4

3

2

1

0

FSSEL1

FSSEL0

GAINCNTR1

GAINCNTR0

RECMODE1

RECMODE0

LIMDET

ALCEN

Table 141. ALC Control Register 1 Bit Descriptions

Bit Name

Description

FSSEL[1:0]

These bits should equal the sample rate of the ADC.

00 = 96 kHz.

01 = 48 kHz.

10 = 32 kHz.

11 = Reserved.

GAINCNTR[1:0]

RECMODE[1:0]

These bits determine the limit of the counter used in limited recovery mode.

00 = 3.

01 = 7.

10 = 15.

11 = 31.

These bits determine which recovery mode is used by the ALC section.

00 = No recovery.

01 = Normal recovery.

10 = Limited recovery.

11 = Reserved.

LIMDET

ALCEN

These bits limit detect mode.

0 = ALC is used when either channel exceeds the set limit.

1 = ALC is used only when both channels exceed the set limit.

These bits enable ALC.

0 = Disable ALC.

1 = Enable ALC.

Rev. A | Page 57 of 60

ADAV803

ALC Control Register 2— Address = 1111100 (0x7C)

Table 142. ALC Control Register 2 Bit Map

7

6

5

4

3

2

1

0

Reserved

RECTH1

RECTH0

ATKTH1

ATKTH0

RECTIME1

RECTIME0

ATKTIME

Table 143. ALC Control Register 2 Bit Descriptions

Bit Name

Description

Recovery threshold.

00 = −2 dB.

RECTH[1:0]

01 = −3 dB.

10 = −4 dB.

11 = −6 dB.

ATKTH[1:0]

RECTIME[1:0]

ATKTIME

Attack threshold.

00 = 0 dB.

01 = −1 dB.

10 = −2 dB.

11 = −4 dB.

Recovery time selection.

00 = 32 ms.

01 = 64 ms.

10 = 128 ms.

11 = 256 ms.

Attack timer selection.

0 = 1 ms.

1 = 4 ms.

ALC Control Register 3—Address 1111101 (0x7D)

Table 144. ALC Control Register 3 Bit Map

7

6

5

4

3

2

1

0

ALC RESET

Table 145. ALC Control Register 3 Bit Description

Bit Name

Description

ALC RESET

A write to this register restarts the ALC operation. The value written to this register is irrelevant. A read from this

register gives the gain reduction factor.

Rev. A | Page 58 of 60

ADAV803

LAYOUT CONSIDERATIONS

Getting the best performance from the ADAV803 requires a

careful layout of the printed circuit board (PCB). Using separate

analog and digital ground planes is recommended, because

these give the currents a low resistance path back to the power

supplies. The ground planes should be connected in only one

place, usually under the ADAV803, to prevent ground loops.

The PLL has its own power supply pins. To get the best

performance from the PLL and from the rest of the ADAV803,

it is recommended that a separate analog supply be used. Where

this is not possible, the user must decide whether to connect the

PLL supply to the analog (AVDD) or digital (DVDD) supply.

Connecting the PLL supply to AVDD gives the best jitter

performance, but can degrade the performance of the ADC and

DAC sections slightly due to the increased digital noise created

on the AVDD by the PLL. Connecting the PLL supply to DVDD

keeps digital noise away from the analog supply, but the jitter

specifications might be reduced depending on the quality of the

digital supply. Using the layout recommendations described in

this section helps to reduce these effects.

The analog and digital supply pins should be decoupled to their

respective ground pins with a 10 μF to 47 μF tantalum capacitor

and a 0.1 μF ceramic capacitor. These capacitors should be

placed as close as possible to the supply pins.

ADC

The ADC uses a switch capacitor input stage and is, therefore,

particularly sensitive to digital noise. Sources of noise, such as

PLLs or clocks, should not be routed close to the ADC section.

The CAPxN and CAPxP pins form a charge reservoir for the

switched capacitor section of the ADC, so keeping these nodes

electrically quiet is a key factor in ensuring good performance.

The capacitors connected to these pins should be of good

quality, either NPO or COG, and should be placed as close as

possible to CAPxN and CAPxP.

RESET AND POWER-DOWN CONSIDERATIONS

RESET

When the ADAV803 is held in reset by bringing the

pin low, a number of circuit blocks remain powered up. For

example, the crystal oscillator circuit based around the XIN

and XOUT pins is still active, so that a stable clock source

is available when the ADAV803 is taken out of reset. In addi-

tion, the VCO associated with the S/PDIF receiver is active so

that the receiver locks to the incoming S/PDIF stream in the

shortest possible time. Where power consumption is a concern,

the individual blocks of the ADAV803 can be powered down via

the control registers to gain significant power savings. Table 146

shows typical power savings when using the power-down bits

in the control registers.

DAC

The DAC requires an analog filter to filter out-of-band noise

from the analog output. A third-order Bessel filter is

recommended, although the filter to use depends on the

requirements of the application.

PLL

Table 146. Typical Power Requirements

The PLL can be used to generate digital clocks, either for use

internally or to clock external circuitry. Because every clock is a

potential source of noise, care should be taken when using the

PLL. The ADAV803’s PLL outputs can be enabled or disabled,

as required. If the PLL clocks are not required by external

circuitry, it is recommended that the outputs be disabled. To

reduce cross-coupling between clocks, a digital ground trace

can be routed on either side of the PLL clock signal, if required.

Operating

Mode

AV_DD

(mA)

DV_DD

(mA)

ODV_DD

(mA)

DIR_V_DD

(mA)

Power

(mW)

Normal

Reset low

Power-

down bits

50

30

12

25

4

0.1

5

2.5

1.3

5

1

0.7

280.5

123.75

46.53

Rev. A | Page 59 of 60

ADAV803

OUTLINE DIMENSIONS

12.20

12.00 SQ

11.80

0.75

0.60

0.45

1.60

MAX

64

49

1

48

PIN 1

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.08

COPLANARITY

16

33

0.15

0.05

SEATING

17

32

PLANE

VIEW A

0.27

0.22

0.17

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 55. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

Control

Interface DAC Outputs

Package

Option

Model

Package Description

ADAV803ASTZ¹

ADAV803ASTZ-REEL¹

EVAL-ADAV803EBZ¹

−40°C to +85°C

I²C

Single-Ended

64-Lead Low Profile Quad Flat Package [LQFP]

Evaluation Board

ST-64-2

¹Z = RoHS Compliant Part.

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C

Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D04756-0-7/07(A)

Rev. A | Page 60 of 60


型号：	ADAV803AST
厂家：	ADI
描述：	IC SPECIALTY CONSUMER CIRCUIT, PQFP64, PLASTIC, LQFP-64, Consumer IC:Other 商用集成电路
文件：	总60页 (文件大小：811K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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