ADC0838VVWM [ADI]
ADC0838VVWM PDF 杰鸿顺电子; ADC0838VVWM PDF杰鸿顺电子
| 型号： | ADC0838VVWM |
| 厂家： | 
ADI |
| 描述： | ADC0838VVWM PDF 杰鸿顺电子 |
| 文件： | 总32页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 1999
ADC0831/ADC0832/ADC0834/ADC0838
8-Bit Serial I/O A/D Converters with Multiplexer Options
n Operates ratiometrically or with 5 VDC voltage
reference
General Description
The ADC0831 series are 8-bit successive approximation A/D
n No zero or full-scale adjust required
converters with a serial I/O and configurable input multiplex-
n 2-, 4- or 8-channel multiplexer options with address logic
ers with up to 8 channels. The serial I/O is configured to
n Shunt regulator allows operation with high voltage
™
comply with the NSC MICROWIRE serial data exchange
standard for easy interface to the COPS family of proces-
supplies
™
n 0V to 5V input range with single 5V power supply
n Remote operation with serial digital data link
n TTL/MOS input/output compatible
n 0.3" standard width, 8-, 14- or 20-pin DIP package
n 20 Pin Molded Chip Carrier Package (ADC0838 only)
n Surface-Mount Package
sors, and can interface with standard shift registers or µPs.
The 2-, 4- or 8-channel multiplexers are software configured
for single-ended or differential inputs as well as channel as-
signment.
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Key Specifications
n Resolution
8 Bits
1
±
±
n Total Unadjusted Error
n Single Supply
n Low Power
⁄2
LSB and 1 LSB
Features
n NSC MICROWIRE compatible — direct interface to
COPS family processors
n Easy interface to all microprocessors, or operates
“stand-alone”
5 VDC
15 mW
32 µs
n Conversion Time
Typical Application
DS005583-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
COPS and MICROWIRE are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS005583
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Connection Diagrams
ADC0838 8-Channel Mux
Small Outline/Dual-In-Line Package
(WM and N)
ADC0834 4-Channel MUX
Small Outline/Dual-In-Line Package
(WM and N)
ADC0832 2-Channel MUX
Dual-In-Line Package (N)
DS005583-31
COM internally connected to GND.
internally connected to V
V
.
CC
REF
Top View
DS005583-30
Top View
COM internally connected to A GND
Top View
DS005583-8
Top View
Top View
ADC0832 2-Channel MUX
Small Outline Package (WM)
ADC0831 Single
Differential Input
ADC0831 Single Differential Input
Small Outline Package (WM)
Dual-In-Line Package (N)
DS005583-32
Top View
DS005583-41
DS005583-42
Top View
Top View
ADC0838 8-Channel MUX
Molded Chip Carrier (PCC)
Package (V)
DS005583-33
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Ordering Information
Part Number
Analog Input
Total
Unadjusted Error
Package
Temperature
Range
Channels
±
ADC0831CCN
ADC0831CCWM
ADC0832CIWM
ADC0832CCN
ADC0832CCWM
ADC0834BCN
ADC0834CCN
ADC0834CCWM
ADC0838BCV
ADC0838CCV
ADC0838CCN
ADC0838CIWM
ADC0838CCWM
1
1
Molded (N)
SO(M)
0˚C to +70˚C
0˚C to +70˚C
−40˚C to +85˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
−40˚C to +85˚C
0˚C to +70˚C
±
2
4
8
1
SO(M)
Molded (N)
SO(M)
1
±
⁄
2
Molded (N)
Molded (N)
SO(M)
±
1
1
±
⁄
2
PCC (V)
PCC (V)
Molded (N)
SO(M)
±
1
SO(M)
See NS Package Number M14B, M20B, N08E, N14A, N20A or V20A
3
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Lead Temperature (Soldering 10 sec.)
Dual-In-Line Package (Plastic)
260˚C
Molded Chip Carrier Package
Vapor Phase (60 sec.)
215˚C
220˚C
2000V
Infrared (15 sec.)
Current into V+ (Note 3)
Supply Voltage, VCC (Note 3)
Voltage
15 mA
6.5V
ESD Susceptibility (Note 5)
Operating Ratings (Notes 1, 2)
Logic Inputs
−0.3V to VCC + 0.3V
−0.3V to VCC + 0.3V
Supply Voltage, VCC
Temperature Range
ADC0832/8CIWM
ADC0834BCN,
4.5 VDC to 6.3 VDC
MIN≤TA≤TMAX
Analog Inputs
T
±
Input Current per Pin (Note 4)
Package
5 mA
−40˚C to +85˚C
±
20 mA
Storage Temperature
Package Dissipation
−65˚C to +150˚C
ADC0838BCV,
ADC0831/2/4/8CCN,
ADC0838CCV,
=
at TA 25˚C (Board Mount)
0.8W
ADC0831/2/4/8CCWM
0˚C to +70˚C
Converter and Multiplexer Electrical Characteristics The following specifications apply for
=
=
=
=
=
=
VCC V+ VREF 5V, VREF ≤ VCC +0.1V, TA Tj 25˚C, and fCLK 250 kHz unless otherwise specified. Boldface limits
apply from TMIN to TMAX
.
Conditions
CIWM Devices
BCV, CCV, CCWM, BCN
and CCN Devices
Parameter
Typ
Tested
Limit
Design
Limit
Typ
Tested
Limit
Design
Units
(Note 12)
(Note 12)
Limit
(Note 13)
(Note 14)
(Note 13)
(Note 14)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
=
Total Unadjusted Error
ADC0838BCV
VREF 5.00 V
1
1
±
±
±
±
(Note 6)
⁄
⁄
2
2
⁄
⁄
2
2
1
1
ADC0834BCN
LSB
(Max)
±
±
ADC0838CCV
1
1
1
1
1
1
±
±
±
±
ADC0831/2/4/8CCN
ADC0831/2/4/8CCWM
ADC0832/8CIWM
±
1
Minimum Reference
Input Resistance (Note 7)
Maximum Reference
Input Resistance (Note 7)
3.5
3.5
1.3
3.5
3.5
1.3
5.4
1.3
5.9
kΩ
kΩ
5.9
Maximum Common-Mode
Input Range (Note 8)
VCC +0.05
VCC +0.05
VCC+0.05
V
V
Minimum Common-Mode
Input Range (Note 8)
GND −0.05
GND −0.05 GND−0.05
1
1
1
±
⁄4
±
±
±
±
DC Common-Mode Error
Change in zero
1/16
⁄
4
1/16
⁄
4
LSB
15 mA into V+
=
=
VCC N.C.
error from VCC 5V
=
to internal zener
VREF 5V
operation (Note 3)
VZ, internal
1
1
1
LSB
V
MIN 15 mA into V+
MAX
6.3
8.5
6.3
8.5
6.3
8.5
diode breakdown
(at V+) (Note 3)
1
1
1
1
=
±
±
±
±
±
±
±
Power Supply Sensitivity
IOFF, Off Channel Leakage
Current (Note 9)
VCC 5V 5%
1/16
⁄
4
⁄
4
1/16
⁄
4
⁄
4
LSB
µA
=
On Channel 5V,
−0.2
−1
−0.2
−1
=
Off Channel 0V
=
On Channel 0V,
+0.2
+1
+0.2
+1
µA
=
Off Channel 5V
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Converter and Multiplexer Electrical Characteristics The following specifications apply for
=
=
=
=
=
=
VCC V+ VREF 5V, VREF ≤ VCC +0.1V, TA Tj 25˚C, and fCLK 250 kHz unless otherwise specified. Boldface limits
apply from TMIN to TMAX. (Continued)
Conditions
CIWM Devices
BCV, CCV, CCWM, BCN
and CCN Devices
Parameter
Typ
Tested
Limit
Design
Limit
Typ
Tested
Limit
Design
Units
(Note 12)
(Note 12)
Limit
(Note 13)
(Note 14)
(Note 13)
(Note 14)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
=
ION, On Channel Leakage
Current (Note 9)
On Channel 0V,
−0.2
−1
−0.2
+0.2
−1
+1
µA
µA
=
Off Channel 5V
=
On Channel 5V,
+0.2
+1
=
Off Channel 0V
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical “1” Input
Voltage (Min)
=
VCC 5.25V
2.0
0.8
1
2.0
0.8
1
2.0
0.8
1
V
V
=
VCC 4.75V
VIN(0), Logical “0” Input
Voltage (Max)
=
IIN(1), Logical “1” Input
Current (Max)
VIN 5.0V
0.005
0.005
µA
µA
=
IIN(0), Logical “0” Input
Current (Max)
VIN 0V
−0.005
−1
−0.005
−1
−1
=
VCC 4.75V
VOUT(1), Logical “1” Output
Voltage (Min)
=
IOUT −360 µA
2.4
4.5
0.4
2.4
4.5
0.4
2.4
4.5
0.4
V
V
V
=
IOUT −10 µA
=
VCC 4.75V
VOUT(0), Logical “0” Output
Voltage (Max)
=
IOUT 1.6 mA
=
IOUT, TRI-STATE Output
Current (Max)
VOUT 0V
−0.1
0.1
−3
3
−0.1
0.1
−3
+3
−3
+3
µA
µA
=
VOUT 5V
=
ISOURCE, Output Source
Current (Min)
VOUT 0V
−14
−6.5
−14
−7.5
−6.5
mA
=
ISINK, Output Sink Current (Min)
ICC, Supply Current (Max)
ADC0831, ADC0834,
ADC0838
VOUT VCC
16
0.9
2.3
8.0
2.5
6.5
16
0.9
2.3
9.0
2.5
6.5
8.0
2.5
6.5
mA
mA
mA
ADC0832
Includes Ladder
Current
AC Characteristics
=
=
=
The following specifications apply for VCC 5V, tr tf 20 ns and 25˚C unless otherwise specified.
Typ
Tested
Design
Limit
Limit
Units
Parameter
Conditions
(Note 12)
Limit
(Note 13)
10
(Note 14)
fCLK, Clock Frequency
Min
kHz
kHz
1/fCLK
%
Max
400
tC, Conversion Time
Clock Duty Cycle
(Note 10)
Not including MUX Addressing Time
8
Min
40
60
Max
%
t
SET-UP, CS Falling Edge or
250
ns
Data Input Valid to CLK
Rising Edge
t
HOLD, Data Input Valid
90
ns
after CLK Rising Edge
5
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AC Characteristics (Continued)
=
=
=
The following specifications apply for VCC 5V, tr tf 20 ns and 25˚C unless otherwise specified.
Typ
Tested
Design
Limit
Limit
Units
Parameter
Conditions
(Note 12)
Limit
(Note 13)
(Note 14)
=
CL 100 pF
tpd1, tpd0 — CLK Falling
Edge to Output Data Valid
(Note 11)
Data MSB First
Data LSB First
650
250
125
1500
600
ns
ns
ns
=
=
t
1H, t0H, — Rising Edge of
CL 10 pF, RL 10k
250
CS to Data Output and
SARS Hi–Z
(see TRI-STATE® Test Circuits)
=
=
CL 100 pf, RL 2k
500
ns
C
IN, Capacitance of Logic
5
5
pF
Input
C
OUT, Capacitance of Logic
pF
Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground plugs.
Note 3: Internal zener diodes (6.3 to 8.5V) are connected from V+ to GND and V
CC
to GND. The zener at V+ can operate as a shunt regulator and is connected
to V via a conventional diode. Since the zener voltage equals the A/D’s breakdown voltage, the diode insures that V will be below breakdown when the device
CC CC
is powered from V+. Functionality is therefore guaranteed for V+ operation even though the resultant voltage at V may exceed the specified Absolute Max of 6.5V.
CC
It is recommended that a resistor be used to limit the max current into V+. (See Figure 3 in Functional Description Section 6.0)
−
+
<
>
V ) the absolute value of current at that pin should be limited
Note 4: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
V
or V
IN
IN
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
Note 7: Cannot be tested for ADC0832.
Note 8: For V (−)≥V (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct
IN IN
for analog input voltages one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V levels (4.5V), as high
CC
level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec
allows 50 mV forward bias of either diode. This means that as long as the analog V or V does not exceed the supply voltage by more than 50 mV, the output
IN
REF
code will be correct. To achieve an absolute 0 V to 5 V input voltage range will therefore require a minimum supply voltage of 4.950 V over temperature varia-
D
C
D
C
D
C
tions, initial tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1 µs. The maximum time the clock can be high is 60 µs. The clock
can be stopped when low so long as the analog input voltage remains stable.
Note 11: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow
for comparator response time.
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 14: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Typical Performance Characteristics
Unadjusted Offset Error
vs VREF Voltage
Linearity Error vs VREF
Voltage
Linearity Error vs
Temperature
DS005583-44
DS005583-43
DS005583-45
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Typical Performance Characteristics (Continued)
Linearity Error vs fCLK
Power Supply Current vs
Temperature (ADC0838,
ADC0831, ADC0834)
Output Current vs
Temperature
DS005583-46
DS005583-48
DS005583-47
Note: For ADC0832 add I
.
REF
Power Supply Current
vs fCLK
DS005583-29
Leakage Current Test Circuit
DS005583-3
7
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TRI-STATE Test Circuits and Waveforms
t1H
t0H
DS005583-49
DS005583-50
t1H
t0H
DS005583-51
DS005583-52
Timing Diagrams
Data Input Timing
Data Output Timing
DS005583-24
DS005583-25
ADC0831 Start Conversion Timing
DS005583-26
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Timing Diagrams (Continued)
ADC0831 Timing
DS005583-27
*LSB first output not available on ADC0831.
ADC0832 Timing
DS005583-28
ADC0834 Timing
DS005583-5
9
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Timing Diagrams (Continued)
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ADC0838 Functional Block Diagram
11
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Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample-data com-
parator structure which provides for a differential analog in-
put to be converted by a successive approximation routine.
In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent chan-
nel pairs. For example channel 0 and channel 1 may be se-
lected as a different pair but channel 0 or 1 cannot act differ-
entially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is best il-
lustrated by the MUX addressing codes shown in the follow-
ing tables for the various product options.
The actual voltage converted is always the difference be-
tween an assigned “+” input terminal and a “−” input terminal.
The polarity of each input terminal of the pair being con-
verted indicates which line the converter expects to be the
most positive. If the assigned “+” input is less than the “−” in-
put the converter responds with an all zeros output code.
A unique input multiplexing scheme has been utilized to pro-
vide multiple analog channels with software-configurable
single-ended, differential, or a new pseudo-differential option
which will convert the difference between the voltage at any
analog input and a common terminal. The analog signal con-
ditioning required in transducer-based data acquisition sys-
tems is significantly simplified with this type of input flexibility.
One converter package can now handle ground referenced
inputs and true differential inputs as well as signals with
some arbitrary reference voltage.
The MUX address is shifted into the converter via the DI line.
Because the ADC0831 contains only one differential input
channel with a fixed polarity assignment, it does not require
addressing.
The common input line on the ADC0838 can be used as a
pseudo-differential input. In this mode, the voltage on this pin
is treated as the “−” input for any of the other input channels.
This voltage does not have to be analog ground; it can be
any reference potential which is common to all of the inputs.
This feature is most useful in single-supply application where
the analog circuitry may be biased up to a potential other
than ground and the output signals are all referred to this
potential.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential.
TABLE 1. Multiplexer/Package Options
Number of Analog Channels
Part
Number of
Number
ADC0831
ADC0832
ADC0834
ADC0838
Single-Ended
Differential
Package Pins
1
2
4
8
1
1
2
4
8
8
14
20
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Functional Description (Continued)
TABLE 2. MUX Addressing: ADC0838
Single-Ended MUX Mode
MUX Address
Analog Single-Ended Channel #
SGL/
ODD/
SELECT
0
1
2
3
4
5
6
7
COM
DIF
1
SIGN
1
0
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
+
−
−
−
−
−
−
−
−
1
0
1
1
0
0
1
1
+
1
+
1
+
1
+
1
+
1
+
1
+
TABLE 3. MUX Addressing: ADC0838
Differential MUX Mode
MUX Address
Analog Differential Channel-Pair #
SGL/
ODD/
SELECT
0
1
2
3
DIF
0
SIGN
1
0
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
+
−
7
−
+
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
−
0
+
−
0
+
−
0
0
−
+
0
−
+
0
−
+
0
TABLE 4. MUX Addressing: ADC0834
Single-Ended MUX Mode
MUX Address
Channel #
SGL/
ODD/
SELECT
DIF
1
SIGN
1
0
1
0
1
0
1
2
3
0
0
1
1
+
1
+
1
+
1
+
COM is internally tied to A GND
TABLE 5. MUX Addressing: ADC0834
Differential MUX Mode
MUX Address
Channel #
SGL/
ODD/
SELECT
DIF
0
SIGN
1
0
1
0
1
0
1
2
+
−
3
−
+
0
0
1
1
+
−
0
0
−
+
0
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Functional Description (Continued)
TABLE 6. MUX Addressing: ADC0832
Single-Ended MUX Mode
MUX Address
Channel #
SGL/
DIF
1
ODD/
SIGN
0
0
1
+
1
1
+
COM is internally tied to A GND
TABLE 7. MUX Addressing: ADC0832
Differential MUX Mode
MUX Address
Channel #
SGL/
DIF
0
ODD/
SIGN
0
0
1
+
−
−
+
0
1
Since the input configuration is under software control, it can
be modified, as required, at each conversion. A channel can
be treated as a single-ended, ground referenced input for
one conversion; then it can be reconfigured as part of a dif-
ferential channel for another conversion. Figure 1 illustrates
the input flexibility which can be achieved.
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmitting
highly noise immune digital data back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate diagram is shown of each device.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above VCC (typically 5V) with-
out degrading conversion accuracy.
1. A conversion is initiated by first pulling the CS (chip select)
line low. This line must be held low for the entire conversion.
The converter is now waiting for a start bit and its MUX as-
signment word.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im-
provements; it allows more function to be included in the
2. A clock is then generated by the processor (if not provided
continuously) and output to the A/D clock input.
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Functional Description (Continued)
8 Single-Ended
8 Pseudo-Differential
DS005583-53
DS005583-54
Mixed Mode
4 Differential
DS005583-55
DS005583-56
FIGURE 1. Analog Input Multiplexer Options for the ADC0838
3. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register. The
start bit is the first logic “1” that appears on this line (all lead-
ing zeros are ignored). Following the start bit the converter
expects the next 2 to 4 bits to be the MUX assignment word.
7. After 8 clock periods the conversion is completed. The
1
SAR status line returns low to indicate this
later.
⁄2 clock cycle
8. If the programmer prefers, the data can be provided in an
LSB first format [this makes use of the shift enable (SE) con-
trol line]. All 8 bits of the result are stored in an output shift
register. On devices which do not include the SE control line,
the data, LSB first, is automatically shifted out the DO line,
after the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. On the ADC0838 the
SE line is brought out and if held high, the value of the LSB
remains valid on the DO line. When SE is forced low, the
data is then clocked out LSB first. The ADC0831 is an excep-
tion in that its data is only output in MSB first format.
4. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1
⁄ clock pe-
2
riod (where nothing happens) is automatically inserted to al-
low the selected MUX channel to settle. The SAR status line
goes high at this time to signal that a conversion is now in
progress and the DI line is disabled (it no longer accepts
data).
5. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX set-
tling time.
9. All internal registers are cleared when the CS line is high.
If another conversion is desired, CS must make a high to low
transition followed by address information.
6. When the conversion begins, the output of the SAR com-
parator, which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder, appears at the DO line on each
falling edge of the clock. This data is the result of the conver-
sion being shifted out (with the MSB coming first) and can be
read by the processor immediately.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire. This is
possible because the DI input is only “looked-at” during the
MUX addressing interval while the DO line is still in a high
impedance state.
15
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For absolute accuracy, where the analog input varies be-
tween very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
The LM385 and LM336 reference diodes are good low cur-
rent devices to use with these converters.
Functional Description (Continued)
3.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input to these convert-
ers defines the voltage span of the analog input (the differ-
ence between VIN(MAX) and VIN(MIN)) over which the 256
possible output codes apply. The devices can be used in ei-
ther ratiometric applications or in systems requiring absolute
accuracy. The reference pin must be connected to a voltage
source capable of driving the reference input resistance of
typically 3.5 kΩ. This pin is the top of a resistor divider string
used for the successive approximation conversion.
The maximum value of the reference is limited to the VCC
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow di-
rect conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter (1 LSB equals VREF/256).
In a ratiometric system, the analog input voltage is propor-
tional to the voltage used for the A/D reference. This voltage
is typically the system power supply, so the VREF pin can be
tied to VCC (done internally on the ADC0832). This technique
relaxes the stability requirements of the system reference as
the analog input and A/D reference move together maintain-
ing the same output code for a given input condition.
DS005583-57
DS005583-58
a) Ratiometric
b) Absolute with a reduced Span
FIGURE 2. Reference Examples
4.0 THE ANALOG INPUTS
VPEAK is its peak voltage value
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces-
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accu-
racy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
and fCLK, is the A/D clock frequency.
For a 60 Hz common-mode signal to generate a 1
⁄ LSB error
(≈5 mV) with the converter running at 250 kHz, its peak value
would have to be 6.63V which would be larger than allowed
as it exceeds the maximum analog input limits.
4
Due to the sampling nature of the analog inputs short spikes
of current enter the “+” input and exit the “−” input at the
clock edges during the actual conversion. These currents
decay rapidly and do not cause errors as the internal com-
parator is strobed at the end of a clock period. Bypass ca-
pacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resistance
of the analog signal source. Bypass capacitors should not be
used if the source resistance is greater than 1 kΩ.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+” in-
put and then the “−” input is 1
in the common-mode voltage during this short time interval
⁄
2
of a clock period. The change
This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well. The
can cause conversion errors. For
common-mode signal this error is:
a
sinusoidal
±
worst-case leakage current of 1 µA over temperature will
create a 1 mV input error with a 1 kΩ source resistance. An
op amp RC active low pass filter can provide both imped-
ance buffering and noise filtering should a high impedance
signal source be required.
where fCM is the frequency of the common-mode signal,
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Functional Description (Continued)
5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error
The zero of the A/D does not require adjustment. If the mini-
mum analog input voltage value, VIN(MIN), is not ground a
zero offset can be done. The converter can be made to out-
put 0000 0000 digital code for this minimum input voltage by
biasing any VIN (−) input at this VIN(MIN) value. This utilizes
the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the VIN(−) input and applying a small magnitude
positive voltage to the VIN(+) input. Zero error is the differ-
ence between the actual DC input voltage which is neces-
DS005583-11
FIGURE 3. An On-Chip Shunt Regulator Diode
sary to just cause an output digital code transition from 0000
This zener is intended for use as a shunt voltage regulator to
eliminate the need for any additional regulating components.
This is most desirable if the converter is to be remotely lo-
cated from the system power source.Figure 4 and Figure 5 il-
lustrate two useful applications of this on-board zener when
an external transistor can be afforded.
An important use of the interconnecting diode between V+
and VCC is shown in Figure 6 and Figure 7. Here, this diode
is used as a rectifier to allow the VCC supply for the converter
to be derived from the clock. The low current requirements of
the A/D and the relatively high clock frequencies used (typi-
cally in the range of 10k–400 kHz) allows using the small
1
0000 to 0000 0001 and the ideal
⁄
2
LSB value (1⁄
LSB 9.8
=
2
=
mV for VREF 5.000 VDC).
5.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1 1
LSB down from the desired
⁄
2
analog full-scale voltage range and then adjusting the mag-
nitude of the VREF input (or VCC for the ADC0832) for a digi-
tal output code which is just changing from 1111 1110 to 1111
1111.
5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
value filter capacitor shown to keep the ripple on the VCC line
1
to well under
⁄4 of an LSB. The shunt zener regulator can
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
also be used in this mode. This requires a clock voltage
swing which is in excess of VZ. A current limit for the zener is
needed, either built into the clock generator or a resistor can
be used from the CLK pin to the V+ pin.
should be properly adjusted first. A VIN (+) voltage which
1
equals this desired zero reference plus
⁄2 LSB (where the
=
LSB is calculated for the desired analog span, using 1 LSB
analog span/256) is applied to selected “+” input and the
zero reference voltage at the corresponding “−” input should
then be adjusted to just obtain the 00HEX to 01HEX code tran-
sition.
The full-scale adjustment should be made [with the proper
V
IN(−) voltage applied] by forcing a voltage to the VIN(+) in-
put which is given by:
where:
VMAX the high end of the analog input range
=
and
=
VMIN
the low end (the offset zero) of the analog
range.
(Both are ground referenced.)
The VREF (or VCC) voltage is then adjusted to provide a code
change from FEHEX to FFHEX. This completes the adjust-
ment procedure.
6.0 POWER SUPPLY
A unique feature of the ADC0838 and ADC0834 is the inclu-
sion of a zener diode connected from the V+ terminal to
ground which also connects to the VCC terminal (which is the
actual converter supply) through a silicon diode, as shown in
Figure 3. (Note 3)
17
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Applications
DS005583-12
FIGURE 4. Operating with a Temperature
Compensated Reference
DS005583-35
*4.5V ≤ V
CC
≤ 6.3V
FIGURE 6. Generating VCC from the Converter Clock
DS005583-34
DS005583-36
FIGURE 5. Using the A/D as
the System Supply Regulator
*4.5V ≤ V
CC
≤ 6.3V
FIGURE 7. Remote Sensing —
Clock and Power on 1 Wire
Digital Link and Sample Controlling Software for the
Serially Oriented COP420 and the Bit Programmable I/O INS8048
DS005583-13
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8048 CODING EXAMPLE
Applications (Continued)
Mnemonic
Instruction
COP CODING EXAMPLE
=
;SELECT A/D (CS 0)
START:
ANL
P1,
#0F7H
Mnemonic
LEI
Instruction
ENABLES SIO’s INPUT AND OUTPUT
←
5
MOV
MOV
B, #5
;BIT COUNTER
=
1
SC
C
←
;A MUX ADDRESS
A,
#ADDR
=
=
OGI
G0 0 (CS 0)
CLR A
AISC 1
XAS
CLEARS ACCUMULATOR
LOADS ACCUMULATOR WITH 1
←
LOOP 1:
ZERO:
RRC
JC
A
;CY ADDRESS BIT
ONE
;TEST BIT
EXCHANGES SIO WITH
ACCUMULATOR
=
;BIT
0
←
0
ANL
JMP
P1,
#0FEH
;DI
AND STARTS SK CLOCK
LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR
—
LDD
CONT
;CONTINUE
=
;BIT
1
NOP
XAS
←
1
ONE:
ORL
P1, #1
;DI
LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER
↑
→ →
1 0
CONT:
CALL PULSE
;PULSE SK 0
DJNZ B, LOOP
1
;CONTINUE UNTIL
DONE
CALL PULSE
;EXTRA CLOCK FOR
SYNC
8 INSTRUCTIONS
↓
←
8
MOV
B, #8
;BIT COUNTER
→ →
0
XAS
READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
PUTS HIGH ORDER NIBBLE INTO RAM
CLEARS ACCUMULATOR
LOOP 2:
CALL PULSE
;PULSE SK 0
1
←
;CY DO
IN
A, P1
A
XIS
RRC
RRC
MOV
RLC
MOV
CLR A
RC
A
=
C
0
←
;A RESULT
A, C
A
XAS
READS LOW ORDER NIBBLE INTO
ACCUMULATOR AND STOPS SK
PUTS LOW ORDER NIBBLE INTO RAM
←
;A(0) BIT AND SHIFT
←
C, A
;C RESULT
XIS
OGI
LEI
DJNZ B, LOOP
2
;CONTINUE UNTIL
DONE
=
=
G0 1 (CS 1)
DISABLES SIO’s INPUT AND OUTPUT
RETR
;PULSE SUBROUTINE
←
1
PULSE:
ORL
NOP
ANL
P1, #04
;SK
;DELAY
←
0
P1,
;SK
#0FBH
RET
19
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Applications (Continued)
A “Stand-Alone” Hook-Up for ADC0838 Evaluation
DS005583-59
*
Pinouts shown for ADC0838.
For all other products tie to
pin functions as shown.
Low-Cost Remote Temperature Sensor
DS005583-60
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Applications (Continued)
Digitizing a Current Flow
DS005583-15
Operating with Ratiometric Transducers
DS005583-37
=
*V (−) 0.15 V
IN
CC
15% of V
CC
≤ V
XDR
≤ 85% of V
CC
21
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Applications (Continued)
Span Adjust: 0V≤VIN≤3V
DS005583-61
Zero-Shift and Span Adjust: 2V≤VIN≤5V
DS005583-62
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Applications (Continued)
Obtaining Higher Resolution
DS005583-63
a) 9-Bit A/D
DS005583-64
Controller performs a routine to determine which input polarity (9-bit example) or which channel pair (10-bit example) provides a non-zero output code. This
information provides the extra bits.
b) 10-Bit A/D
23
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Applications (Continued)
Protecting the Input
DS005583-18
Diodes are 1N914
High Accuracy Comparators
DS005583-38
=
>
<
DO all 1s if +V
−V
−V
IN
IN
=
DO all 0s if +V
IN
IN
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Applications (Continued)
Digital Load Cell
DS005583-19
•Uses one more wire than load cell itself
•Two mini-DIPs could be mounted inside load cell for digital output transducer
•Electronic offset and gain trims relax mechanical specs for gauge factor and offset
•Low level cell output is converted immediately for high noise immunity
4 mA-20 mA Current Loop Converter
DS005583-20
•All power supplied by loop
•1500V isolation at output
25
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Applications (Continued)
Isolated Data Converter
DS005583-39
•No power required remotely
•1500V isolation
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Applications (Continued)
Two Wire Interface for 8 Channels
DS005583-21
27
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Applications (Continued)
Two Wire 1-Channels Interface
DS005583-22
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Physical Dimensions inches (millimeters) unless otherwise noted
Hermetic Dual-In-Line Package (WM)
NS Package Number M14B
29
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Hermetic Dual-In-Line Package (WM)
NS Package Number M20B
Molded Dual-In-Line Package (N)
NS Package Number N08E
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
NS Package Number N14A
Molded-Dual-In-Line Package (N)
NS Package Number N20A
31
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Chip Carrier Package (V)
Order Number ADC0838BCV or ADC0838CCV
NS Package Number V20A
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2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
the life support device or system, or to affect its
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