ADCA3270ACEZ-R7 [ADI]
DOCSIS 3.1 Power Doubler Amplifier, 45 MHz to 1218 MHz;
| 型号： | ADCA3270ACEZ-R7 |
| 厂家： | 
ADI |
| 描述： | DOCSIS 3.1 Power Doubler Amplifier, 45 MHz to 1218 MHz |
| 文件： | 总14页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DOCSIS 3.1 Power Doubler Amplifier,
45 MHz to 1218 MHz
ADCA3270
Data Sheet
FEATURES
GENERAL DESCRIPTION
Drop-in replacement for RFCM3327 and RFCM3328
Total composite power: 73 dBmV
High power gain: 25 dB at 1218 MHz
Excellent linearity
The Analog Devices, Inc., ADCA3270 is a 24 V power doubler,
monolithic microwave IC (MMIC) with 25 dB of power gain.
The device achieves high RF output up to 73 dBmV composite
power under 18 dB tilt conditions by using advanced circuit
design techniques with gallium arsenide (GaAs), pseudomorphic
high electron transistor (pHEMT), and gallium nitride (GaN)
HEMT technologies. The dc current and supply voltage can be
adjusted externally for optimum distortion performance vs.
power consumption over a range of output levels. The
Very low distortion
Composite triple beat: −80 dBc typical
Composite second-order: −80 dBc typical
Carrier to intermodulation noise: 59 dB typical
Low noise figure: 3 dB typical at 45 MHz and 4 dB typical at
1218 MHz
Unconditionally stable
Configurable current: 350 mA to 480 mA at 24 V
Temperature monitor
ADCA3270 provides high gain, simplifying the design and
manufacturing of DOCSIS 3.1 infrastructure equipment.
The ADCA3270 is packaged in a 9-terminal thermally
enhanced chip array small outline no lead cavity [LGA_CAV]
with an industry-standard footprint.
9-terminal thermally enhanced chip array small outline no
lead cavity [LGA_CAV]
APPLICATIONS
45 MHz to 1218 MHz community access television (CATV)
infrastructure amplifier systems
Remote physical layer (PHY)
DOCSIS 3.1 compliant
FUNCTIONAL BLOCK DIAGRAM
ADCA3270
RFIP
RFOP
1
4
9
5
VCC
OUTPUT
INPUT
RFIN
RFON
NTC
DNC
VCC TSEN
2
3
6
7
8
TEMPERATURE
MONITOR
GND
Figure 1.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
ADCA3270
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
S-Parameters ..................................................................................7
9 dB Tilt Performance...................................................................8
18 dB Tilt Performance.................................................................9
Theory of Operation ...................................................................... 10
Applications Information.............................................................. 11
ADCA3270 Temperature Sense Monitor................................ 11
Thermal Considerations............................................................ 11
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Performance ................................................................... 3
Distortion Data (All Digital Channel Plan).............................. 3
Distortion Data (Mixed Signal Channel Plan)......................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Electrostatic Discharge (ESD) Ratings ...................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Soldering Information and Recommended PCB Land Pattern
....................................................................................................... 11
ADCA3270 Bias Current........................................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
7/2021—Revision 0: Initial Version
Rev. 0 | Page 2 of 14
Data Sheet
ADCA3270
SPECIFICATIONS
GENERAL PERFORMANCE
Supply voltage (VCC) = 24 V, exposed paddle temperature (TPADDLE) = 35°C, source impedance (ZS) = load impedance (ZL) = 75 Ω, and dc
current (ICC) = 480 mA, unless otherwise noted.
Table 1.
Parameter
POWER GAIN
Symbol Min
Typ
23.6
25
Max
25.0
26.5
Unit Test Conditions/Comments
S21
22.0
23.0
dB
dB
dB
dB
dB
Frequency = 45 MHz, see Figure 4
Frequency = 1218 MHz, see Figure 4
Frequency = 45 MHz to 1218 MHz
Frequency = 45 MHz to 1218 MHz
Frequency = 45 MHz to 1218 MHz, see Figure 5
See Figure 3 and Figure 6
SLOPE STRAIGHT LINE1
FLATNESS OF FREQUENCY RESPONSE2
REVERSE ISOLATION
RETURN LOSS
2.0
0.75
28
S12
S11
Input
−20
−15
−12
−12
−12
−20
−20
−20
−20
−18
3
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Frequency = 45 MHz to 320 MHz
Frequency = 320 MHz to 640 MHz
Frequency = 640 MHz to 870 MHz
Frequency = 870 MHz to 1000 MHz
Frequency = 1000 MHz to 1218 MHz
Frequency = 45 MHz to 320 MHz
Frequency = 320 MHz to 640 MHz
Frequency = 640 MHz to 870 MHz
Frequency = 870 MHz to 1000 MHz
Frequency = 1000 MHz to 1218 MHz
Frequency = 45 MHz
Output
S22
NOISE FIGURE
4
Frequency = 1218 MHz
SUPPLY
Voltage
VCC
18
24
26
V
Supply voltage can be adjusted for different applications,
see the Applications Information section
DC Current (Total)
ICC (TOTAL)
VBIAS
350
480
1.08
500
mA
V
Can be biased between 350 mA and 480 mA (see the
Applications Information section)
RF Input Bias Voltage
1 Slope straight line is defined as the delta between the gain at the start frequency and the gain at the stop frequency.
2 Flatness of frequency response is defined as the delta between the gain at any frequency between the start and stop frequencies and a straight line reference drawn
between the gain at the start frequency and the gain at the stop frequency.
DISTORTION DATA (ALL DIGITAL CHANNEL PLAN)
VCC = 24 V, TPADDLE = 35°C, and ZS = ZL = 75 Ω, unless otherwise noted.
Table 2.
Parameter
Symbol
Min Typ
Max
Unit
Test Conditions/Comments
TOTAL COMPOSITE POWER TCP
73
dBmV 18 dB tilt, 190 digital (256 QAMs) channels from 57 MHz to
1215 MHz
73
dBmV 9 dB tilt, 190 digital (256 QAMs) channels from 57 MHz to
1215 MHz
ERROR RATES
Modulation Error Rate
Bit Error Rate
MER
BER
47
dB
<1 × 10−10
<1 × 10−9
PostViterbi, 18 dB tilt, 190 digital (256 QAMs) channels from
57 MHz to 1215 MHz
PreViterbi, 9 dB tilt, 190 digital (256 QAMs) channels from
57 MHz to 1215 MHz
Rev. 0 | Page 3 of 14
ADCA3270
Data Sheet
DISTORTION DATA (MIXED SIGNAL CHANNEL PLAN)
VCC = 24 V, T FLANGE = 35°C, and ZS = ZL = 75 Ω, unless otherwise noted.
Table 3.
Parameter
Symbol
Min Typ
Max
Unit
Test Conditions/Comments
DISTORTION
TCP = 72.4 dBmV, the analog and digital channel plan
consists of 18 dB extrapolated tilt, 79 continuous wave
channels plus 111 digital channels, a National Television
System Committee (NTSC) frequency raster range of
55.25 MHz to 547.25 MHz, and −6 dB offset
Composite Triple Beat
CTB
CSO
−80
dBc
Defined by the National Cable and Telecommunications
Association (NCTA)
Defined by NCTA
Defined by American National Standard/Society of
Cable Telecommunications Engineers (ANSI/SCTE) 17
(test procedure for carrier to noise)
Composite Second-Order
Carrier to Intermodulation Noise
−80
59
dBc
dB
Rev. 0 | Page 4 of 14
Data Sheet
ADCA3270
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
VCC
DC Supply over Voltage (5 minute)
RF Input Voltage (RFINPUT), Single Tone
Temperature
Operating Range, TPADDLE
Peak Reflow (Moisture Sensitivity Level
(MSL) 3
Junction (TJ) to Maintain 1 Million Hour
Mean Time to Failure (MTTF)
Nominal Junction (TJ)
Rating
30 V
75 dBmV
θJC is the thermal resistance from the operating portion of the
PHEMT device to the outside surface of the package closest to
the device mounting area (the exposed paddle on the bottom of
the case). See the Thermal Considerations section for additional
information.
−30°C to +110°C
260°C
170°C
Table 5. Thermal Resistance
Package Type
1
θJC
Unit
TPADDLE = 110°C, ICC = 480 mA, VCC = 24 V
Storage (TS) Range
144°C
−40°C to +150°C
CE-9-2
2.9
°C/W
1 Thermal resistance (θJC) is defined as between the TPADDLE and the internal
device junction (TJ).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADCA3270
Table 6. ADCA3270, 6-Terminal LGA_CAV
ESD Model
Withstand Threshold (V)
Class
HBM
500
Class 1B, passed
ESD CAUTION
Rev. 0 | Page 5 of 14
ADCA3270
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RFIP
GND
GND
RFIN
1
2
3
4
9
8
7
6
5
RFOP
TSEN
VCC
ADCA3270
TOP VIEW
(Not to Scale)
GND
RFON
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED
PADDLE TO A LOW IMPEDANCE ELECTRICAL
AND THERMAL GROUND PLANE.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 4
2, 3, 6
5, 9
7
Mnemonic
RFIP, RFIN
GND
RFON, RFOP
VCC
Description
RF Differential Inputs.
Ground.
RF Differential Outputs.
Positive Supply Voltage, 24 V Typical.
Temperature Sensing Pin.
8
TSEN
Exposed Pad. Solder the exposed paddle to a low impedance electrical and thermal ground plane.
Rev. 0 | Page 6 of 14
Data Sheet
ADCA3270
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 24 V, TPADDLE = 35°C, and ZS = ZL = 75 Ω, unless otherwise noted.
S-PARAMETERS
0
0
–5
+85°C
+35°C
–30°C
+85°C
+35°C
–30°C
–5
–10
–15
–20
–25
–30
–35
–40
–10
–15
–20
–25
–30
–35
–40
45
200
400
600
800
1000
1218
45
200
400
600
800
1000
1218
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3. S11 vs. Frequency at Various Temperatures
Figure 5. S12 vs. Frequency at Various Temperatures
30
28
26
24
22
20
0
–5
+85°C
+35°C
–30°C
+85°C
+35°C
–30°C
–10
–15
–20
–25
–30
–35
–40
45
200
400
600
800
1000
1218
45
200
400
600
800
1000
1218
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. S21 vs. Frequency at Various Temperatures
Figure 6. S22 vs. Frequency at Various Temperatures
Rev. 0 | Page 7 of 14
ADCA3270
Data Sheet
9 dB TILT PERFORMANCE
9 dB extrapolated tilt and 190 digital channels (QAM256, ITU-T J.83, Annex B).
70
65
60
55
50
45
40
35
30
–2
–3
–4
–5
–6
–7
–8
–9
1×10
1×10
1×10
1×10
1×10
1×10
1×10
1×10
57MHz
57MHz
111MHz
501MHz
999MHz
1215MHz
111MHz
501MHz
999MHz
1215MHz
–10
1×10
69
70
71
72
73
74
75
76
69
70
71
72
73
74
75
76
77
78
TOTAL COMPOSITE OUTPUT POWER (dBmV)
TOTAL COMPOSITE OUTPUT POWER (dBmV)
Figure 7. MER RMS vs. Total Composite Output Power at Various Frequencies,
35°C, 9 dB Tilt
Figure 9. PreViterbi BER vs. Total Composite Output Power at
Various Frequencies, 35°C, 9 dB Tilt
70
–2
1×10
–30°C
+35°C
+85°C
+85°C
65
60
55
50
45
40
35
30
+35°C
–30°C
–3
–4
–5
–6
–7
–8
–9
1×10
1×10
1×10
1×10
1×10
1×10
1×10
–10
1×10
69
70
71
72
73
74
75
76
69
70
71
72
73
74
75
76
77
78
TOTAL COMPOSITE OUTPUT POWER (dBmV)
TOTAL COMPOSITE OUTPUT POWER (dBmV)
Figure 8. MER RMS vs. Total Composite Output Power at
Various Temperatures, 57 MHz, 9 dB Tilt
Figure 10. PreViterbi BER vs. Total Composite Output Power at
Various Temperatures, 57 MHz, 9 dB Tilt
Rev. 0 | Page 8 of 14
Data Sheet
ADCA3270
18 dB TILT PERFORMANCE
18 dB extrapolated tilt and 190 digital channels (QAM256, ITU-T J.83, Annex B).
70
65
60
55
50
45
40
35
30
–2
–3
–4
–5
–6
–7
–8
–9
1×10
1×10
1×10
1×10
1×10
1×10
1×10
1×10
57MHz
57MHz
111MHz
501MHz
999MHz
1215MHz
111MHz
501MHz
999MHz
1215MHz
–10
1×10
69
70
71
72
73
74
75
76
69
70
71
72
73
74
75
76
TOTAL COMPOSITE OUTPUT POWER (dBmV)
TOTAL COMPOSITE OUTPUT POWER (dBmV)
Figure 11. MER RMS vs. Total Composite Output Power at
Various Frequencies, 35°C, 18 dB Tilt
Figure 13. PostViterbi BER vs. Total Composite Output Power at
Various Frequencies, 35°C, 18 dB Tilt
70
–2
1×10
+85°C
+35°C
–30°C
+85°C
+35°C
–30°C
65
60
55
50
45
40
35
30
–3
–4
–5
–6
–7
–8
–9
1×10
1×10
1×10
1×10
1×10
1×10
1×10
–10
1×10
69
70
71
72
73
74
75
76
69
70
71
72
73
74
75
76
TOTAL COMPOSITE OUTPUT POWER (dBmV)
TOTAL COMPOSITE OUTPUT POWER (dBmV)
Figure 12. MER RMS vs. Total Composite Output Power at
Various Temperatures, 57 MHz, 18 dB Tilt
Figure 14. PostViterbi BER vs. Total Composite Output Power at
Various Temperatures, 57 MHz, 18 dB Tilt
Rev. 0 | Page 9 of 14
ADCA3270
Data Sheet
THEORY OF OPERATION
The ADCA3270 is a balanced amplifier packaged in a LGA_CAV.
The application circuit interfaces the ADCA3270 to a 75 Ω input
and output matched impedance consistent with a matched
module designed for CATV applications. The ADCA3270
uses cascode field effect transistor (FET) feedback amplifiers
in a Class A push pull configuration. The bottom half of the
cascode stages are implemented in a single die, linear FET process
that minimizes parasitics, thereby enabling higher gain. The
top devices in the cascodes are implemented using a linear
GaN process that is able to swing high RF voltages. The
frequency of operation is from 45 MHz to 1218 MHz.
ADCA3270
75Ω
75Ω
Figure 15. Simplified Schematic
The ADCA3270 is unconditionally stable for robust operation in
systems targeting DOCSIS 3.1 and legacy DOCSIS standards.
Rev. 0 | Page 10 of 14
Data Sheet
ADCA3270
APPLICATIONS INFORMATION
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
ADCA3270 TEMPERATURE SENSE MONITOR
The ADCA3270 has an internally mounted, negative temperature
coefficient (NTC) thermistor that, when used as the bottom of a
resistive voltage divider, provides an output voltage that is
correlated to the ground temperature at the TPADDLE of the
LGA_CAV package. When configured as shown in Figure 16,
the typical relationship between VTSEN and TPADDLE results in
what is shown in Figure 17.
Figure 18 shows the recommended land pattern for the
ADCA3270. To minimize thermal impedance, the exposed
paddle on the 9.00 mm × 8.00 mm LGA_CAV is soldered to a
ground plane along with Pin 2, Pin 3, and Pin 6. To improve
thermal dissipation, 188 thermal vias are arranged in an array
under the exposed paddle. The array consists of alternating
rows of 13 vias and 12 vias, maximizing the number of vias
within the area. The area under the paddle is also tied to ground
on the bottom layer of the PCB. If multiple ground layers exist,
tie these layers together by the vias. The external layer of the
PCB must be a minimum of 2 oz. copper. The minimum
average plated hole wall thickness of the vias must not be less
than 0.001 inch, and it is recommended that the vias be filled
with a conductive paste, such as Tatsuta AE3030, and plated
over. The full recommended PCB footprint design is shown in
Figure 19.
5V
REFERENCE
3.3kΩ
V
ADCA3270
8
TSEN
NTC
Figure 16. Recommended NTC Configuration
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
0.6
0.8
1.0
1.2
1.4
1.6
(V)
1.8
2.0
2.2
2.4
V
TSEN
Figure 17. TPADDLE vs. VTSEN
Figure 18. Recommended Land Pattern
THERMAL CONSIDERATIONS
For further information on optimizing the thermal performance
while using the ADCA3270, refer to the AN-1604 Application
Note, Thermal Management Calculations for RF Amplifiers in
LFCSP and Flange Packages.
The ADCA3270 is packaged in a thermally efficient, 9-terminal
chip array small outline no lead cavity [LGA_CAV]. The
thermal resistance from θJC is 2.9°C/W, where the case is defined
by the exposed paddle on the bottom of the package. For the
best thermal performance, it is recommended that as many
thermal vias as possible be added under the exposed paddle of
the LGA_CAV package. For optimal performance, it is
recommended that these vias be filled with a paste that has high
thermal conductivity. It is also recommended that the array of
vias under the ADCA3270 interface to an external heat sink
such as a pedestal on the system chassis.
Rev. 0 | Page 11 of 14
ADCA3270
Data Sheet
Figure 19. Recommended PCB Layout (Dimensions Shown in Millimeters)
Figure 21 provides the typical transfer function of ICC to VBIAS
which allows the user to adjust ICC from 380 mA to 480 mA.
,
ADCA3270 BIAS CURRENT
The ADCA3270 employs a versatile circuit design, allowing
system designers to configure the supply voltage at the VCC
connection (Pin 7) and the bias control voltage (VBIAS) at the
RFIP (Pin 1) and RFIN (Pin 4) connections to optimize the
power dissipation in any given application. It is recommended
that the ICC be controlled by employing a precision 5 V reference
and a resistor divider (R1 and R2) to set ICC as illustrated in
Figure 20. The voltage is connected to each input through a ferrite
bead (FB1 and FB2). The dc output of the balun used to feed the
RF into the power amplifier must be blocked using a capacitor.
480
470
460
450
440
430
420
410
400
390
380
370
360
350
5V
REFERENCE
FB1
RFIP
0.6
0.7
0.8
0.9
1.0
(V)
1.1
1.2
1.3
R1
V
BIAS
Figure 21. ICC vs. VBIAS
V
BIAS
R2
RFIN
FB2
Figure 20. Setting the Bias Control Voltage
Rev. 0 | Page 12 of 14
Data Sheet
ADCA3270
60
55
50
45
40
35
Figure 22 and Figure 23 illustrates the MER performance trade-
off for different supply voltage configurations. Figure 24 and
Figure 25 illustrates the modulation error ratio performance
trade-off for different bias current configurations.
60
350mA
375mA
400mA
425mA
450mA
475mA
18V
19V
20V
21V
55
22V
23V
24V
50
45
40
35
71.5
72.0
72.5
73.0
73.5
74.0
74.5
75.0
75.5
TOTAL COMPOSITE OUTPUT POWER (dBmV)
Figure 24. MER RMS vs. Total Composite Output Power, VCC = 24 V,
25 mA Steps from 350 mA to 475 mA, 9 dB Tilt
60
350mA
71.5
72.0
72.5
73.0
73.5
74.0
74.5
75.0
75.5
375mA
400mA
425mA
TOTAL COMPOSITE OUTPUT POWER (dBmV)
55
50
45
40
35
450mA
475mA
Figure 22. MER RMS vs. Total Composite Output Power, ICC = 475 mA,
VCC = 18 V to 24 V, 1 V Steps, 9 dB Tilt
60
18V
19V
20V
21V
55
22V
23V
24V
50
45
40
35
71.5
72.0
72.5
73.0
73.5
74.0
74.5
75.0
75.5
TOTAL COMPOSITE OUTPUT POWER (dBmV)
Figure 25. MER RMS vs. Total Composite Output Power, VCC = 24 V,
25 mA Steps from 350 mA to 475 mA, 22 dB Tilt
71.5
72.0
72.5
73.0
73.5
74.0
74.5
75.0
75.5
TOTAL COMPOSITE OUTPUT POWER (dBmV)
Figure 23. MER RMS vs. Total Composite Output Power, ICC = 475 mA,
CC = 18 V to 24 V, 1 V Steps, 22 dB Tilt
V
Rev. 0 | Page 13 of 14
ADCA3270
Data Sheet
OUTLINE DIMENSIONS
9.10
9.00
8.90
6.80 BSC
0.18
0.15
0.12
Ø
PIN 1
INDICATOR
VENT HOLE
9
1
4.00
BSC
8.10
8.00
7.90
4.00
BSC
EXPOSED
PAD
1.35
BSC
7.40 BSC
5
4
1.00
BSC
1.40
REF
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.65
0.60 SQ
0.55
0.10
REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.95 REF
2.50 MAX
SECTION OF THIS DATA SHEET.
0.452
0.412
0.372
SEATING
PLANE
Figure 26. 9-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
9.00 mm × 8.00 mm Body and 2.50 mm Package Height
(CE-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−30°C to +110°C
−30°C to +110°C
Package Description
Package Option
CE-9-2
CE-9-2
ADCA3270ACEZ
ADCA3270ACEZ-R7
ADCA3270-EVALZ
9-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
9-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
Evaluation Board
1 Z = RoHS Compliant Part.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D24276-7/21(0)
Rev. 0 | Page 14 of 14
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