ADCMP394ARZ [ADI]
Single Comparator with Accurate Reference Output;
| 型号： | ADCMP394ARZ |
| 厂家： | 
ADI |
| 描述： | Single Comparator with Accurate Reference Output 放大器 光电二极管 |
| 文件： | 总18页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single/Dual/Quad Comparators with
Accurate Reference Output
Data Sheet
ADCMP394/ADCMP395/ADCMP396
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VCC
High accuracy reference output voltage: 1 V 0.9%
Single-supply voltage operation: 2.3 V to 5.5 V
Rail-to-rail common-mode input voltage range
Low input offset voltage across VCMR: 1 mV typical
Guarantees comparator output logic low from VCC = 0.9 V to
undervoltage lockout (UVLO)
ADCMP394
REF
REF
IN+
IN–
OUT
GND
Operating temperature range: −40°C to +125°C
Package types:
Figure 1.
8-lead, narrow body SOIC (ADCMP394)
10-lead MSOP (ADCMP395)
16-lead, narrow body SOIC (ADCMP396)
VCC
ADCMP395
REF
REF
APPLICATIONS
INA+
INA–
OUTA
OUTB
Battery management/monitoring
Power supply detection
Window comparators
INB+
INB–
Threshold detectors/discriminators
Microprocessor systems
GND
Figure 2.
VCC
GENERAL DESCRIPTION
The ADCMP394/ADCMP395/ADCMP396 are single/dual/quad
rail-to-rail input, low power comparator ideal for use in general-
purpose applications. These comparators operate from a supply
voltage of 2.3 V to 5.5 V and draw a minimal amount of
current. The single ADCMP394 consumes only 33.9 μA of
supply current. The dual ADCMP395 and quad ADCMP396
consumes 37.2 μA and 41.6 μA of supply current respectively.
The low voltage and low current operation of these devices
makes it ideal for battery-powered systems.
ADCMP396
REF
REF
INA+
INA–
OUTA
OUTB
OUTC
OUTD
INB+
INB–
INC+
INC–
IND+
IND–
The comparators features a common-mode input voltage range
of 200 mV beyond rails, an offset voltage of 1 mV typical across
the full common-mode range, and a UVLO monitor. In addition,
the design of the comparator allows a defined output state upon
power-up. The comparator generates a logic low output if the
supply voltage is less than the UVLO threshold.
GND
Figure 3.
The ADCMP394/ADCMP395/ADCMP396 incorporates a 1 V
0.9% buffered reference voltage. The reference voltage output
can directly connect to the comparator input to serve as the trip
value for precise monitoring and detection of positive voltage. It
can also act as an offset when monitoring the negative voltage.
The ADCMP394 and ADCMP396 are available in 8-pin and 16-
lead, narrow body SOIC package, respectively. The ADCMP395
is available in a 10-lead MSOP package. The comparators are
specified to operate over the −40°C to +125°C extended
temperature range.
Rev. B
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ADCMP394/ADCMP395/ADCMP396
Data Sheet
TABLE OF CONTENT
Open-Drain Output................................................................... 11
Power-Up Behavior.................................................................... 11
Crossover Bias Point .................................................................. 11
Comparator Hysteresis .............................................................. 11
Typical Applications....................................................................... 12
Adding Hysteresis....................................................................... 12
Window Comparator for Positive Voltage Monitoring......... 12
Window Comparator for Negative Voltage Monitoring....... 13
Programmable Sequencing Control Circuit............................... 13
Mirrored Voltage Sequencer Example..................................... 15
Threshold and Timeout Programmable Voltage Supervisor 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Basic Comparator....................................................................... 11
Rail-to-Rail Input (RRI) ............................................................ 11
REVISION HISTORY
5/16—Rev. A to Rev. B
Changes to Equation 4 ................................................................... 12
Changes to Figure 39...................................................................... 14
3/15—Rev. 0 to Rev. A
Added ADCMP395/ADCMP396 (Throughout) ......................... 1
11/14—Revision 0: Initial Version
Rev. B | Page 2 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
SPECIFICATIONS
VCC = 2.3 V to 5.5 V, TA = −40°C to +125°C, VCMR = −200 mV to VCC + 200 mV, unless otherwise noted. Typical values are at TA = 25°C.
Table 1.
Parameter
Symbol
VCC
Min
Typ
Max
Unit
Test Conditions/Comments1
POWER SUPPLY
Supply Voltage Range
2.3
0.9
5.5
UVLORISE
V
V
Guarantees comparator output low
VCC Quiescent Current
ADCMP394
ICC
33.9
32.6
37.2
35.9
41.6
41.3
47.9
45.8
51.9
49.2
59.4
56.4
µA
µA
µA
µA
µA
µA
All outputs in high-Z state, VOD = 0.1 V
All outputs low, VOD = 0.1 V
All outputs in high-Z state, VOD = 0.1 V
All outputs low, VOD = 0.1 V
All outputs in high-Z state, VOD = 0.1 V
All outputs low, VOD = 0.1 V
ADCMP395
ADCMP396
UNDERVOLTAGE LOCKOUT
VCC Rising
Hysteresis
UVLORISE
UVLOHYS
2.062
5
2.162
25
2.262
50
V
mV
REFERENCE OUTPUT
Reference Output Voltage
VREF
0.991
0.991
1
1
1.008
1.008
V
V
IREF
IREF
=
=
1 mA, TA = −40°C to +85°C
1 mA
COMPARATOR INPUT
Common-Mode Input Range
Input Offset Voltage
VCMR
VOS
−200
VCC + 200
mV
mV
mV
mV
mV
nA
nA
nA
nA
mV
mV
0.5
0.5
1
2.5
2.5
5
IN+ = IN− = 1 V
IN+ = IN− = 1 V, TA = −40°C to +85°C
1
5
TA = −40°C to +85°C
VCMR = −50 mV to VCC + 50 mV
IN+ = IN− = 1 V
VCMR = −50 mV to VCC + 50 mV
VCMR = −50 mV to VCC + 50 mV, TA = −40°C to +85°C
VCM = 1 V
Input Offset Current
Input Bias Current
IOS
IBIAS
10
30
80
10
4
Input Hysteresis
VHYST
3
6
8
COMPARATOR OUTPUT
Output Low Voltage
VOL
0.1
0.01
0.3
0.15
150
V
V
nA
VCC = 2.3 V, ISINK = 2.5 mA
VCC = 0.9 V, ISINK = 100 µA
VOUT = 0 V to 5.5 V
Output Leakage Current
COMPARATOR CHARACTERISTICS
Power Supply Rejection Ratio
Common-Mode Rejection Ratio
Voltage Gain
Rise Time2
Fall Time2
ILEAK
PSRR
CMRR
AV
60
50
80
74
132
1.1
0.15
dB
dB
dB
µs
tR
VOUT = 10% to 90% of VCC
VOUT = 90% to 10% of VCC
tF
µs
Propagation Delay
Input Rising2
tPROP_R
4.7
4.9
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
VCM = 1 V, VCC = 2.3 V, 100 mV overdrive
VCM = 1 V, VCC = 5 V, 100 mV overdrive
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD= 10 mV
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
VCM = 1 V, VCC = 2.3 V, 100 mV overdrive
VCM = 1 V, VCC = 5 V, 100 mV overdrive
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
2.8
3.2
ADCMP395 Channel B
Input Falling2
4.9
9.7
4.5
9.5
tPROP_F
2
4.2
ADCMP395 Channel B
4.7
5
1 VOD is overdrive voltage.
2 RPULL-UP = 10 kΩ, and CL = 50 pF.
Rev. B | Page 3 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Rating
Table 3. Thermal Resistance
Package Type
VCC Pin
All INx+ and INx− Pins
All OUTx Pins
Reference Load Current, IREF
OUTx Pins Sink Current, ISINK
Storage Temperature Range
Operating Temperature Range
Lead Temperature (10 sec)
Junction Temperature
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
1 mA
θJA
121
130
80
Unit
°C/W
°C/W
°C/W
8-Lead Narrow-Body SOIC
10-Lead MSOP
16-Lead Narrow-Body SOIC
10 mA
−65°C to +150°C
−40°C to +125°C
300°C
ESD CAUTION
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 4 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND
NIC
IN+
1
2
3
4
8
7
6
5
OUT
VCC
REF
NIC
ADCMP394
TOP VIEW
(Not to Scale)
IN–
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
Figure 4. ADCMP394 Pin Configuration
Table 4. ADCMP394 Pin Function Descriptions
Pin No.
Mnemonic
GND
NIC
IN+
IN−
Description
1
2, 5
3
Device Ground.
Not Internally Connected.
Comparator Noninverting Input.
Comparator Inverting Input.
4
6
7
REF
VCC
Reference Output. This pin can be used to setup the comparator threshold.
Device Supply Input.
8
OUT
Comparator Output, Open-Drain.
OUTA
VCC
INA–
INA+
NIC
1
2
3
4
5
10 OUTB
9
8
7
6
GND
INB–
INB+
REF
ADCMP395
TOP VIEW
(Not to Scale)
NIC = NOT INTERNALLY CONNECTED.
Figure 5. ADCMP395 Pin Configuration
Table 5. ADCMP395 Pin Function Descriptions
Pin No.
Mnemonic
OUTA
VCC
INA−
INA+
NIC
Description
1
2
3
4
5
6
7
8
9
10
Comparator A Output, Open Drain.
Device Supply Input.
Comparator A Inverting Input.
Comparator A Noninverting Input.
Not Internally Connected.
Reference Output. This pin can be used to set up comparator threshold.
Comparator B Noninverting Input.
Comparator B Inverting Input.
REF
INB+
INB−
GND
Device Ground.
Comparator B Output, Open Drain.
OUTB
Rev. B | Page 5 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
OUTB
1
2
3
4
5
6
7
8
16 OUTC
15 OUTD
14 GND
13 IND+
12 IND–
11 INC+
10 INC–
OUTA
VCC
INA–
INA+
INB–
INB+
NIC
ADCMP396
TOP VIEW
(Not to Scale)
9
REF
NIC = NOT INTERNALLY CONNECTED.
Figure 6. ADCMP396 Pin Configuration
Table 6. ADCMP396 Pin Function Descriptions
Pin No.
Mnemonic
OUTB
OUTA
VCC
Description
1
2
3
Comparator B Output, Open Drain.
Comparator A Output, Open Drain.
Device Supply Input.
4
5
6
7
INA−
INA+
INB−
INB+
NIC
Comparator A Inverting Input.
Comparator A Noninverting Input.
Comparator B Inverting Input.
Comparator B Noninverting Input.
Not Internally Connected.
8
9
REF
Reference Output. This pin can be used to set up the comparator threshold.
Comparator C Inverting Input.
Comparator C Noninverting Input.
Comparator D Inverting Input.
Comparator D Noninverting Input.
Device Ground.
Comparator D Output, Open Drain.
Comparator C Output, Open Drain.
10
11
12
13
14
15
16
INC−
INC+
IND−
IND+
GND
OUTD
OUTC
Rev. B | Page 6 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.5
2.0
SAMPLE 1
SAMPLE 2
SAMPLE 3
T
T
T
T
= +25°C
= +85°C
= +125°C
= –40°C
A
A
A
A
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
COMMON-MODE VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 7. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VCC = 3.3 V
Figure 10. Input Offset Voltage (VOS) vs. Supply Voltage (VCC), VCM = 1 V
for Various Temperatures
2.5
2.4
V
V
V
= 2.3V
= 3.3V
= 5.5V
CC
CC
CC
IN+ = IN– + 10mV
2.2
2.0
1.5
V
= IN– = 1V
CM
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 8. Input Offset Voltage (VOS) vs. Temperature for
Various Supply Voltages, VCM = 1 V
Figure 11. Output Voltage (VOUT) vs. Supply Voltage (VCC), RPULLUP = 10 kΩ
70
70
65
60
55
50
45
40
35
30
25
ADCMP394
ADCMP395
ADCMP396
ADCMP394
ADCMP395
65
ADCMP396
60
55
50
45
40
35
30
25
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 9. Supply Current (ICC) vs. Supply Voltage (VCC) at Output Low Voltage
Figure 12. Supply Current (ICC) vs. Supply Voltage (VCC) at Output High
Voltage
Rev. B | Page 7 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
ADCMP394
ADCMP395
ADCMP396
ADCMP394
ADCMP395
65
55
45
35
25
15
65
ADCMP396
55
45
35
25
15
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE(°C)
Figure 16. Supply Current (ICC) vs. Temperature at Output Low Voltage (VOL)
Figure 13. Supply Current (ICC) vs. Temperature at Output High Voltage (VOH
)
3.8
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
2.3
V
V
V
= 2.3V
= 3.3V
= 5.5V
CC
CC
CC
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
T
T
T
T
= +25°C
= +85°C
= +125°C
= –40°C
A
A
A
A
2.1
1.9
1.7
–50
–25
0
25
50
75
100
125
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 17. Input Hysteresis vs. Temperature, VCM = 1 V
for Various Supply Voltages (VCC)
Figure 14. Input Hysteresis vs. Supply Voltage (VCC), VCM = 1 V
for Various Temperatures
14
12
10
8
8
V
V
V
= 2.3V
= 3.3V
= 5.5V
CC
CC
CC
V
V
V
= 2.3V
= 3.3V
= 5.5V
CC
CC
CC
7
6
5
4
3
2
6
4
2
0
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Propagation Delay vs. Temperature, High to Low,
OD = 10 mV
Figure 15. Propagation Delay vs. Temperature, Low to High,
OD = 10 mV
V
V
Rev. B | Page 8 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
10
9
8
7
6
5
4
3
2
1
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
C
V
= 10kΩ
= 50pF
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
C
V
= 10kΩ
= 50pF
CC
CC
CC
PULLUP
CC
CC
CC
PULL-UP
L
L
= 1V
= 1V
CM
CM
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
INPUT OVERDRIVE VOLTAGE (mV)
INPUT OVERDRIVE VOLTAGE (mV)
Figure 19. Propagation Delay vs. Input Overdrive Voltage, Low to High
Figure 22. Propagation Delay vs. Input Overdrive Voltage, High to Low
12
5.0
R
C
V
= 10kΩ
= 50pF
= 1V
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
C
V
= 10kΩ
= 50pF
V
V
V
= 2.3V
= 3.3V
= 5.5V
PULL-UP
CC
CC
CC
PULL-UP
CC
CC
CC
L
L
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 1V
CM
CM
10
8
6
4
2
0
10
30
50
70
90
10
30
50
70
90
INPUT OVERDRIVE VOLTAGE (mV)
INPUT OVERDRIVE VOLTAGE (mV)
Figure 20. Propagation Delay vs. Input Overdrive Voltage, Low to High,
Channel B
Figure 23. Propagation Delay vs. Input Overdrive Voltage, High to Low,
Channel B
200
18
V
C
= 3.3V
= 50pF
V
C
= 3.3V
= 50pF
CC
CC
L
L
190
180
170
160
150
140
130
120
110
100
16
14
12
10
8
6
4
2
0
1
10
100
1
10
100
PULL-UP RESISTANCE (kΩ)
PULL-UP RESISTANCE (kΩ)
Figure 21. Output Voltage Rise Time (tR) vs. Pull-Up Resistance (RPULLUP
)
Figure 24. Output Voltage Fall Time (tF) vs. Pull-Up Resistance (RPULLUP)
Rev. B | Page 9 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
I
(mA)
I
(mA)
SINK
SOURCE
Figure 25. Reference Voltage (VREF) vs. Source Current (ISOURCE) of the REF Pin,
CC = 3.3 V
Figure 28. Reference Voltage (VREF) vs. Sink Current (ISINK) of the REF Pin,
V
V
CC = 3.3 V
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
–40 –25 –10
5
20
35
50
65
80
95 110 125
2.3
2.8
3.3
3.8
4.3
4.8
5.3
TEMPERATURE (°C)
V
(V)
CC
Figure 26. Reference Voltage (VREF) vs. Temperature, VCC = 3.3 V
Figure 29. Reference Voltage (VREF) vs. Supply Voltage (VCC)
700
16
V
V
V
= 2.3V
= 3.3V
= 5.5V
CC
CC
CC
14
12
10
8
600
500
400
300
200
100
0
6
4
2
0
0
1
2
3
4
5
6
7
8
9
10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
(mA)
I
(mA)
SINK
I
SINK
Figure 27. Output Voltage (VOUT) Low vs. Sink Current (ISINK) for
Various Supply Voltages
Figure 30. Output Voltage (VOUT) Low vs. Sink Current (ISINK), VCC = 0.9 V
Rev. B | Page 10 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
THEORY OF OPERATION
BASIC COMPARATOR
POWER-UP BEHAVIOR
In its most basic configuration, a comparator can be used to
convert an analog input signal to a digital output signal (see
Figure 31). The analog signal on INx+ is compared to the
voltage on INx−, and the voltage at OUTx is either high or low,
depending on whether INx+ is at a higher or lower potential
than INx−, respectively.
On power-up, when VCC reaches 0.9 V, the ADCMP394/
ADCMP395/ADCMP396 is guaranteed to assert an output low
logic. When the voltage on the VCC pin exceeds UVLO, the
comparator inputs take control.
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type of architecture in both op amps
and comparators, have a dual front-end design. PMOS devices
are inactive near the VCC rail, and NMOS devices are inactive near
GND. At some predetermined point in the common-mode range,
a crossover occurs. At this point, normally 0.8 V and VCC − 0.8 V,
the measured offset voltages change.
V
CC
V+
INx+
INx–
V
IN
OUTx
V
REF
COMPARATOR HYSTERESIS
In noisy environments, or when the differential input amplitudes
are relatively small or slow moving, adding hysteresis (VHYST) to
the comparator is often desirable. The transfer function for a
comparator with hysteresis is shown in Figure 32. As the input
voltage approaches the threshold (0 V in Figure 32) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +VHYST/2.
The new switch threshold becomes −VHYST/2. The comparator
remains in the high state until the −VHYST/2 threshold is crossed
from below the threshold region in a negative direction. In this
manner, noise or feedback output signals centered on the 0 V
input cannot cause the comparator to switch states unless it
exceeds the region bounded by VHYST/2.
V
OUT
V+
V
REF
0V
t
V
IN
Figure 31. Basic Comparator and Input and Output Signals
RAIL-TO-RAIL INPUT (RRI)
Using a CMOS nonRRI stage (that is, a single differential pair)
limits the input voltage to approximately one gate-to-source
voltage (VGS) away from one of the supply lines. Because VGS
for normal operation is commonly more than 1 V, a single
differential pair input stage comparator greatly restricts the
allowable input voltage. This restriction can be quite limiting
with low voltage supplies. To resolve this issue, RRI stages allow
the input signal range to extend up to the supply voltage range.
In the case of the ADCMP394/ADCMP395/ADCMP396, the
inputs continue to operate 200 mV beyond the supply rails.
OUTPUT
V
OH
OPEN-DRAIN OUTPUT
V
OL
0V
The ADCMP394/ADCMP395/ADCMP396 have an open-drain
output stage that requires an external resistor to pull up to the
logic high voltage level when the output transistor is switched off.
The pull-up resistor must be large enough to avoid excessive
power dissipation, but small enough to switch logic levels
reasonably quickly when the comparator output is connected to
other digital circuitry. The rise time of the open-drain output
depends on the pull-up resistor (RPULLUP) and load capacitor (CL)
used.
INPUT
–V
+V
HYST
2
HYST
2
Figure 32. Comparator Hysteresis Transfer Function
The rise time can be calculated by
tR = 2.2 RPULLUP CL
(1)
Rev. B | Page 11 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
TYPICAL APPLICATIONS
ADDING HYSTERESIS
WINDOW COMPARATOR FOR POSITIVE VOLTAGE
MONITORING
To add hysteresis, see Figure 33; two resistors are used to create
different switching thresholds, depending on whether the input
signal is increasing or decreasing in magnitude. When the input
voltage increases, the threshold is above VREF, and when the
When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by VM, IM is the
nominal current through the resistor divider, VOV is the
overvoltage trip point, and VUV is the undervoltage trip point.
input voltage decreases, the threshold is below VREF
.
V
= 5V
V
CC
M
R
X
R
PULL-UP
INA+
INA–
V
OUTx
PH
INx–
INx+
V
= 2.5V
IN
REF
OUTA
OUTB
R
LOAD
V
R1
R
REF
Y
INB+
R2
INB–
V
PL
R
V
Z
OUT
Figure 34. Positive Undervoltage/Overvoltage Monitoring Configuration
Figure 34 illustrates the positive voltage monitoring input
connection. Three external resistors, RX, RY, and RZ, divide the
positive voltage for monitoring, VM, into the high-side voltage,
VPH, and the low-side voltage, VPL. The high-side voltage is
connected to the INA+ pin and the low-side voltage is
connected to the INB− pin.
V
IN
V
V
IN_HIGH
IN_LOW
Figure 33. Noninverting Comparator Configuration with Hysteresis
The upper input threshold level is given by
To trigger an overvoltage condition, the low-side voltage (in
this case, VPL) must exceed the VREF threshold on the INB+ pin.
Calculate the low-side voltage, VPL, by the following:
V
REF (R1 R2)
VIN_HI
(2)
R2
Assuming RLOAD >> R2, RPULLUP
The lower input threshold level is given by
VREF R1 R2 RPULLUP VCC R1
R2 RPULLUP
The hysteresis is the difference between these voltages levels.
REF (R1RPULLUP )VCC (R1R2)
.
RZ
VPL VREF VOV
(5)
RX RY RZ
In addition,
RX + RY + RZ = VM/IM
VIN _ LO
(3)
(4)
(6)
Therefore, RZ, which sets the desired trip point for the
overvoltage monitor, is calculated as
V
VHYS
R2(R2 RPULLUP
)
VREF
VM
RZ
(7)
VOV
IM
To trigger the undervoltage condition, the high-side voltage,
VPH, must be less than the VREF threshold on the INA− pin. The
high-side voltage, VPH, is calculated by
RY RZ
RX RY RZ
VPH VREF VUV
(8)
Because RZ is already known, RY can be expressed as
VREF VM
RZ
RY
(9)
VUV
IM
When RY and RZ are known, RX can be calculated by
RX = (VM/IM) – RY − RZ
(10)
If VM, IM, VOV, or VUV changes, each step must be recalculated.
Rev. B | Page 12 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
Because RZ is already known, RY can be expressed as follows:
WINDOW COMPARATOR FOR NEGATIVE
VOLTAGE MONITORING
VREF
VM VREF
RZ
RY
(15)
Figure 35 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a reference
voltage is required to connect to the end node of the voltage
divider circuit, in this case, REF.
IM
When RY and RZ are known, RX is then calculated by
VM VREF
VREF VUV
RY RZ
RX
(16)
IM
REF
PROGRAMMABLE SEQUENCING CONTROL CIRCUIT
R
Z
INA+
INA–
V
NH
The circuit shown in Figure 36 is used to control power supply
sequencing. The delay is set by the combination of the pull-up
resistor (RPULLUP), the load capacitor (CL), and the resistor
divider network.
OUTA
OUTB
R
Y
INB+
INB–
V
/V
REF CC
V
NL
R
X
R
R5
R4
PULL-UP
U1
INA+
INA–
V
M
SEQ
OUTA
Figure 35. Negative Undervoltage/Overvoltage Monitoring Configuration
V4
V3
C
L
INB+
INB–
Equation 7, Equation 9, and Equation 10 need some minor
modifications. The reference voltage, VREF, is added to the
overall voltage drop; therefore, it must be subtracted from VM,
VUV, and VOV before using each of them in Equation 7, Equation 9,
and Equation 10.
OUTB
R3
INC+
INC–
OUTC
OUTD
V2
V1
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between VREF and the
negative supply voltage into the high-side voltage, VNH, and the
low-side voltage, VNL. The high-side voltage, VNH, is connected
to INA+, and the low-side voltage, VNL, is connected to INB−.
R2
R1
IND+
IND–
Figure 36. Programmable Sequencing Control Circuit
To trigger an overvoltage condition, the monitored voltage must
exceed the nominal voltage in terms of magnitude, and the
high-side voltage (in this case, VNH) on the INA+ pin must be
more negative than ground. Calculate the high-side voltage,
VNH, by using the following formula:
Figure 37 shows a simple block diagram for a programmable
sequencing control circuit. The application delays the enable signal,
EN, of the external regulators (LDO x) in a linear order when
the open-drain signal (SEQ) changes from low to high impedance.
The ADCMP394/ADCMP395/ADCMP396 have a defined output
state during startup, which prevents any regulator from turning
on if VCC is still below the UVLO threshold.
RX RY
RX RY RZ
VNH GND
V
VOV
V
(11)
REF
OV
3.3V
IN
OUT
LDO 1
3.0V
1.8V
2.5V
1.2V
In addition,
EN
VM VREF
RX RY RZ
(12)
GND
IM
IN
OUT
LDO 2
Therefore, RZ, which sets the desired trip point for the
overvoltage monitor, is calculated by
V
/V
EN
REF CC
GND
t1
VREF
IM
VM VREF
VREF VOV
RZ
(13)
t2
t3
t4
SEQ
IN
OUT
LDO 3
To trigger an undervoltage condition, the monitored voltage
GND
EN
must be less than the nominal voltage in terms of magnitude,
and the low-side voltage (in this case, VNL) on the INB− pin
must be more positive than ground. Calculate the low-side
voltage, VNL, by the following:
GND
IN
OUT
LDO 4
EN
GND
RX
VNL GND
V
VUV
V
(14)
REF
UV
RX RY RZ
Figure 37. Simplified Block Diagram of a Programmable
Sequencing Control Circuit
Rev. B | Page 13 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
First, determine the allowable current, IDIV, flowing through the
resistor divider. After the value for IDIV is determined, calculate
R1, R2, R3, R4, and R5 using the following formulas:
SEQ
V4
V3
V2
V1
V
C
L
t4
t3
VREF
IDIV
OUT4
OUT3
OUT2
OUT1
RDIV
R1
R2
R3
R4
R1 R2 R3 R4 R5
(22)
(23)
(24)
(25)
V1RDIV
VREF
t2
t1
V2RDIV
VREF
Figure 38. Programmable Sequencing Control Circuit Timing Diagram
R1
When the SEQ signal changes from low to high impedance, the
load capacitor, CL, starts to charge. The time it takes to charge the
load capacitor to the pull-up voltage (in this case, VREF or VCC) is the
maximum delay programmable in the circuit. It is recommended
to have the threshold within 10% to 90% of the pull-up voltage.
Calculate the maximum allowable delay by
V3RDIV
VREF
R1 R2
R1 R2 R3
V4RDIV
VREF
(26)
(27)
R5 = RDIV − R1 − R2 − R3 − R4
t
MAX = 2.2RPULLUPCLOAD
(17)
To create a mirrored voltage sequence, add a resistor (RMIRROR
between the pull-up resistor (RPULLUP) and the load capacitor
(CL) as shown in Figure 39.
)
The delay of each output is changed by changing the threshold
voltage, V1 to V4, when the comparator changes its output state.
To calculate the voltage thresholds for the comparator, use the
following formulas:
V
/V
REF CC
t1
RPULLUPCL
R
R5
R4
PULL-UP
R
MIRROR
U1
INA+
INA–
(18)
(19)
(20)
(21)
V1 V
V2 V
V3 V
V4 V
1 e
1 e
1 e
1 e
SEQ
REF
OUT4
V4
C
L
t2
RPULLUPCL
INB+
INB–
OUT3
REF
V3
R3
t3
RPULLUPCL
INA+
INA–
U2
OUT2
REF
V2
V1
R2
R1
INB+
INB–
t4
RPULLUPCL
OUT1
REF
The threshold voltages can come from a voltage reference or a
voltage divider circuit, as shown in Figure 36.
Figure 39. Circuit Configuration for a Mirrored Voltage Sequencer
Figure 39 shows the circuit configuration for a mirrored voltage
sequencer. When SEQ changes from low to high impedance, the
response is similar to Figure 38. When SEQ changes from high
to low impedance, the load capacitor (CL) starts to discharge at
a rate set by RMIRROR. The delay of each comparator is dependent
on the threshold voltage previously set for t1 to t4. The result is a
mirrored power-down sequence.
Rev. B | Page 14 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
SEQ
V4
V3
V2
V1
V1
V
C
L
V4
V3
V2
t4
t3
t5
t6
OUT4
OUT3
t2
t7
OUT2
OUT1
t1
t8
Figure 40. Mirrored Voltage Sequencer Timing Diagram
The timing diagram for the mirrored voltage sequencer is
shown in Figure 40.
MIRRORED VOLTAGE SEQUENCER EXAMPLE
To illustrate how the mirrored voltage sequencer works, see
Figure 37 and then consider a system that uses a VREF of 1 V and
requires a delay of 50 ms when SEQ changes from low to high
impedance, and between each regulator when turning on. These
considerations require a rise time of at least 200 ms for the pull-up
resistor (RPULLUP) and the load capacitor (CL). The sum of the
resistance of RMIRROR and RPULLUP must be large enough to charge the
capacitor longer than the minimum required delay. For a
symmetrical mirrored power-down sequence, the value of RMIRROR
must be much larger than RPULLUP. A 10 kΩ RPULLUP value limits the
pull-down current to 100 μA while giving a reasonable value for
Equation 18 through Equation 21 must account for the additional
resistance, RMIRROR, in the calculations of the voltage thresholds.
To calculate these new thresholds, see Equation 28 through
Equation 31.
t1
RPULLUP RMIRROR CL
V1 V
1 e
(28)
(29)
(30)
(31)
REF
t2
RPULLUP RMIRROR
CL
REF
V2 V
V3 V
V4 V
1 e
RMIRROR. A typical 1 μF capacitor together with a 150 kΩ RMIRROR
t3
value gives a value of
RPULLUP RMIRROR CL
1 e
1 e
REF
t
MAX = 2.2((160 × 103) × (1 × 10−6)) = 351 ms
(36)
The threshold voltage required by each comparator is set by
Equation 28 to Equation 31. For example,
t4
RPULLUP RMIRROR CL
REF
50 103
3 6
10 1 10
160
V1 V
1 e
RMIRROR provides the mirrored delay by prolonging the discharge
time of the capacitor. The mirrored voltage sequencer uses the
same threshold in Equation 28 to Equation 31 in a decreasing
order. To calculate the exact value of the mirrored delay time,
see Equation 32 through Equation 35.
REF
where V1 = 268.38 mV.
Therefore, V2 = 464.74 mV, V3 = 608.39 mV, and V4 =
713.5 mV.
V4
VREF
Next, consider 10 μA as the maximum current (IDIV) flowing
t5 RMIRRORCLln
(32)
(33)
(34)
(35)
through the resistor divider network. This current gives the total
resistance of the divider network (RDIV) and the individual
resistor values using Equation 22 to Equation 27, resulting in
the following:
V3
VREF
t6 RMIRRORCLln
RDIV = 100 kΩ
V2
VREF
t7 RMIRRORCLln
R1 = 26.84 kΩ ≈ 26.7 kΩ
R2 = 19.64 kΩ ≈ 19.6 kΩ
R3 = 14.37 kΩ ≈ 14.3 kΩ
R4 = 10.51 kΩ ≈ 10.5 kΩ
R5 = 28.65 kΩ ≈ 28.7 kΩ
V1
VREF
t8 RMIRRORCLln
Rev. B | Page 15 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
Resistor values from the calculation are nonindustry standard,
using industry standard resistor values resulted in a new RDIV
value of 99.8 kΩ. Due to the discrepancy of the calculated resistor
value to the industry standard value, the threshold of each
comparator also changed. Calculate the new threshold values
by using a simple voltage divider formula:
THRESHOLD AND TIMEOUT PROGRAMMABLE
VOLTAGE SUPERVISOR
Figure 41 shows a circuit configuration for a programmable
threshold and timeout circuit. The timeout, tRESET, defines the
duration that the input voltage (VIN) must be kept above the
RESET
threshold voltage to toggle the
device from operating when VIN is not stable. If VIN falls below
RESET
signal, preventing the
V1 = VREFR1/RDIV
1V 26.7 kΩ
(37)
the threshold voltage, the
signal toggles quickly.
= 267.54 mV.
where V1 =
V
V
CC
IN
99.8 kΩ
R1
R
Therefore, V2 = 463.93 mV, V3 = 607.21 mV, and V4 = 712.42 mV.
PULL-UP
OUTA
Because the threshold of each comparator has changed, the time
when each comparator changes its output has also changed.
Calculate the new delay values for each comparator by using the
following equation:
R2
OUTB
C
RESET
T
V
REF
Figure 41. Programmable Threshold and Timeout Circuit
V1
t1 CL
R
PULLUP RMIRROR
ln 1
(38)
VREF
V
TH
V
IN
267.54mV
1
where t1 = −1 μF(10 kΩ + 150 kΩ)ln
= 49.81 ms.
tRESET
tRESET
1
RESET
Therefore, t2 = 99.78 ms, t3 = 149.52 ms, and t4 = 199.4 ms.
To calculate t5 through t8, use Equation 32 to Equation 35:
Figure 42. Threshold and Timeout Programmable Voltage Supervisor
Timing Diagram
During startup, the ADCMP394/ADCMP395/ADCMP396
guarantee a low output state when VCC is still below the UVLO
threshold, preventing the voltage supervisor from toggling.
V4
VREF
t5 RMIRRORCLln
712.42 mV
1
When VIN reaches the threshold set by the resistor divider (R1
and R2) and VREF, OUT1 changes from low to high and starts to
charge the timeout capacitor (CT). If VIN is kept above the threshold
voltage and the voltage in CT reaches VREF, OUT2 toggles. If VIN
falls below the threshold voltage while CT is charging, the timeout
capacitor quickly discharges, preventing OUT2 from toggling
while VIN is not stable.
where t5 = −150 kΩ × 1 μF × ln
= 50.86 ms.
Therefore, t6 = 74.83 ms, t7 = 115.2 ms, and t8 = 197.78 ms.
In the condition that VIN is tied to VCC, the circuit operates
when VCC is more than the minimum operating voltage.
The threshold voltage (VTH) is configured by changing the
resistor divider or VREF. Calculate the threshold voltage by
R1
R2
REF
VTH V
1
(39)
Timeout is adjusted by changing the values of the pull-up
resistor or the timeout capacitor. To set the timeout value,
determine the allowable current flowing through RPULLUP, IPULLUP
.
When IPULLUP is known, calculate RPULLUP and CT by the following
formulas:
R
PULLUP = VCC/IPULLUP
tRESET
(40)
(41)
CT
VREF
VCC
RPULLUP ln 1
Rev. B | Page 16 of 18
Data Sheet
ADCMP394/ADCMP395/ADCMP396
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
45°
1.27 (0.0500)
BSC
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0099)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 43. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 44. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. B | Page 17 of 18
ADCMP394/ADCMP395/ADCMP396
Data Sheet
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 45. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Branding
ADCMP394ARZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
R-8
R-8
ADCMP394ARZ-RL7
ADCMP395ARMZ
ADCMP395ARMZ-RL7
ADCMP396ARZ
RM-10
RM-10
R-16
R-16
LQ4
LQ4
ADCMP396ARZ-RL7
1 Z = RoHS Compliant Part.
©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12209-0-5/16(B)
Rev. B | Page 18 of 18
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