ADCMP561BRQ [ADI]
Dual High Speed PECL Comparators; 双路高速PECL比较器
| 型号： | ADCMP561BRQ |
| 厂家： | 
ADI |
| 描述： | Dual High Speed PECL Comparators |
| 文件： | 总16页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual High Speed PECL Comparators
ADCMP561/ADCMP562
FEATURES
FUNCTIONAL BLOCK DIAGRAM
HYS*
Differential PECL compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
NONINVERTING
Q OUTPUT
INPUT
ADCMP561/
ADCMP562
INVERTING
Q OUTPUT
INPUT
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
LATCH ENABLE
LATCH ENABLE
INPUT
INPUT
*ADCMP562 ONLY
Figure 1.
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
V
V
DD
1
2
20
19
18
17
16
15
14
13
12
11
DD
QA
QA
QB
1
2
3
4
5
6
7
8
16
QB
QA
QA
QB
3
APPLICATIONS
15 QB
ADCMP562
TOP VIEW
(Not to Scale)
V
GND
LEB
LEB
4
DD
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
14 GND
13 LEB
12 LEB
V
LEA
5
DD
ADCMP561
TOP VIEW
(Not to Scale)
LEA
LEA
6
LEA
V
V
7
EE
CC
11
V
V
–INA
+INA
–INB
+INB
HYSB
CC
10 –INB
+INB
8
EE
–INA
+INA
9
9
HYSA
10
Peak detection
High speed triggers
Figure 2. ADCMP561 16-Lead QSOP
Figure 3. ADCMP562 20-Lead QSOP
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Line receivers and signal restoration
Clock drivers
GENERAL DESCRIPTION
The ADCMP561/ADCMP562 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of comparators. A separate
programmable hysteresis pin is available on the ADCMP562.
are fully compatible with PECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to VDD − 2 V. A latch
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals that
The ADCMP561/ADCMP562 are specified over the industrial
temperature range (−40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADCMP561/ADCMP562
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Timing Information ....................................................................... 10
Application Information................................................................ 11
Clock Timing Recovery............................................................. 11
Optimizing High Speed Performance ..................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 12
Minimum Input Slew Rate Requirement................................ 12
Typical Application Circuits.......................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Specification Table ....................................................... 4
Changes to Figure 14........................................................................ 9
Changes to Figure 21...................................................................... 12
Changes to Figure 23...................................................................... 13
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADCMP561/ADCMP562
SPECIFICATIONS
VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = −40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Input Voltage Range
Input Differential Voltage
Input Offset Voltage
Input Offset Voltage Channel Matching
Offset Voltage Tempco
Input Bias Current
−2.0
−5
−10.0
3.0
+5
+10.0
V
V
VOS
VCM = 0 V
2.0
2.0
2.0
3
mV
mV
µV/°C
µA
∆VOS/dT
IIN
−IN = −2 V, +IN = +3 V
−10.0
+10.0
Input Bias Current Tempco
Input Offset Current
Input Capacitance
Input Resistance, Differential Mode
Input Resistance, Common Mode
Active Gain
0.5
1.0
0.75
750
1800
63
nA/°C
µA
pF
kΩ
kΩ
dB
CIN
AV
Common-Mode Rejection Ratio
Hysteresis
CMRR
VCM = −2.0 V to +3.0 V
RHYS = ∞
80
1.0
dB
mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Voltage Range
Latch Enable Differential Voltage Range
Latch Enable Input High Current
Latch Enable Input Low Current
LE Voltage, Open
VDD − 2.0
0.4
−300
−300
VDD − 0.2
VDD
2.0
+300
+300
VDD + 0.1
V
V
µA
µA
V
@ VDD
@ VDD −2.0 V
Latch inputs not connected
Latch inputs not connected
VOD = 250 mV
VDD
LE Voltage, Open
VDD/2 − 0.2 VDD/2 VDD/2 + 0.2
V
Latch Setup Time
Latch Hold Time
tS
tH
250
250
600
500
ps
ps
ps
ps
VOD = 250 mV
Latch-to-Output Delay
Latch Minimum Pulse Width
DC OUTPUT CHARACTERISTICS
Output Voltage—High Level
Output Voltage—Low Level
Rise Time
tPLOH, tPLOL VOD = 250 mV
tPL
VOD = 250 mV
VOH
VOL
tR
PECL 50 Ω to VDD − 2.0 V
PECL 50 Ω to VDD − 2.0 V
10% to 90%
VDD − 1.15
VDD − 1.95
VDD − 0.81
VDD − 1.54
V
V
ps
ps
550
470
Fall Time
tF
10% to 90%
AC PERFORMANCE
Propagation Delay
tPD
VOD = 1 V
VOD = 20 mV
VOD = 1 V
700
830
0.25
ps
ps
ps/°C
Propagation Delay Tempco
∆tPD /dT
Prop Delay Skew—Rising Transition to
Falling Transition
VOD = 1 V
50
ps
Within Device Propagation Delay Skew—
Channel-to-Channel
Overdrive Dispersion
Overdrive Dispersion
Slew Rate Dispersion
Pulse Width Dispersion
Duty Cycle Dispersion
Common-Mode Voltage Dispersion
V
OD = 1 V
50
75
75
50
25
15
10
ps
ps
ps
ps
ps
ps
ps
20 mV ≤ VOD ≤ 100 mV
100 mV ≤ VOD ≤ 1.5 V
0.4 V/ns ≤ SR ≤ 1.33 V/ns
700 ps ≤ PW ≤ 10 ns
33 MHz, 1 V/ns, 0.5 V
1 V swing, −1.5 V ≤ VCM ≤ +2.5 V
Rev. A | Page 3 of 16
ADCMP561/ADCMP562
Parameter
Symbol
BWEQ
Conditions
Min
Typ
Max
Unit
AC PERFORMANCE (continued)
Equivalent Input Rise Time Bandwidth1
Maximum Toggle Rate
Minimum Pulse Width
RMS Random Jitter
0 V to 1 V swing, 2 V/ns
>50% output swing
∆tPD < 25 ps
VOD = 400 mV, 1.3 V/ns, 312 MHz,
50% duty cycle
1500
800
700
1.0
MHz
MHz
ps
PWMIN
ps
Unit-to-Unit Propagation Delay Skew
POWER SUPPLY
100
ps
Positive Supply Current
Negative Supply Current
Logic Supply Current
IVCC
IVEE
IVDD
@ +5.0 V
@ −5.2 V
@ 3.3 V without load
@ 3.3 V with load
Dual
Dual
Dual
Dual, without load
Dual, with load
2
10
6
45
4.75
−4.96
2.5
130
180
3.2
22
9
5
28
13
70
5.25
−5.45
5.0
190
250
mA
mA
mA
mA
V
Logic Supply Current
60
Positive Supply Voltage
Negative Supply Voltage
Logic Supply Voltage
Power Dissipation
Power Dissipation
DC Power Supply Rejection Ratio—VCC
DC Power Supply Rejection Ratio—VEE
DC Power Supply Rejection Ratio—VDD
HYSTERESIS (ADCMP562 Only)
Hysteresis
VCC
VEE
VDD
PD
5.0
−5.2
3.3
160
220
85
V
V
mW
mW
dB
dB
dB
PSRRVCC
PSRRVEE
PSRRVDD
85
85
RHYS = 19.5 kΩ
RHYS = 8.0 kΩ
20
70
mV
mV
1 Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√ (trCOMP2 – trIN2), where trIN is the
20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.
Rev. A | Page 4 of 16
ADCMP561/ADCMP562
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Parameter
Rating
Supply Voltages
Positive Supply Voltage (VCC to GND)
Negative Supply Voltage (VEE to GND)
Logic Supply Voltage (VDD to GND)
Ground Voltage Differential
Input Voltages
−0.5 V to +6.0 V
−6.0 V to +0.5 V
−0.5 V to +6.0 V
−0.5 V to +0.5 V
THERMAL CONSIDERATIONS
Input Common-Mode Voltage
Differential Input Voltage
Input Voltage, Latch Controls
Output
−3.0 V to +4.0 V
−7.0 V to +7.0 V
−0.5 V to +5.5 V
The ADCMP561 QSOP 16-lead package option has a θJA
(junction-to-ambient thermal resistance) of 104°C/W in
still air.
Output Current
30 mA
The ADCMP562 QSOP 20-lead package option has a θJA
(junction-to-ambient thermal resistance) of 80°C/W in
still air.
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +85°C
125°C
−65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
ADCMP561/ADCMP562
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
V
DD
1
2
20
19
18
17
16
15
14
13
12
11
DD
QA
QA
QB
1
2
3
4
5
6
7
8
16
QB
QA
QA
QB
3
15 QB
ADCMP562
TOP VIEW
(Not to Scale)
V
GND
LEB
LEB
4
DD
14 GND
13 LEB
12 LEB
V
LEA
5
DD
ADCMP561
TOP VIEW
(Not to Scale)
LEA
LEA
6
LEA
V
V
7
EE
CC
11
V
V
–INA
+INA
–INB
+INB
HYSB
CC
10 –INB
+INB
8
EE
–INA
+INA
9
9
HYSA
10
Figure 4. ADCMP561 16-Lead QSOP Pin Configuration
Figure 5. ADCMP562 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP561 ADCMP562 Mnemonic Function
1
2
VDD
QA
Logic Supply Terminal.
1
2
One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
3
QA
3
4
4
5
VDD
LEA
Logic Supply Terminal.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In the latch mode (logic low), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
5
6
LEA
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
6
7
7
8
VEE
−INA
Negative Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must
be driven in conjunction with the noninverting A input.
8
9
+INA
Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting
A input must be driven in conjunction with the inverting A input.
10
11
12
HYSA
HYSB
+INB
Programmable Hysteresis Input.
Programmable Hysteresis Input.
Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting
B input must be driven in conjunction with the inverting B input.
9
10
13
−INB
Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must
be driven in conjunction with the noninverting B input.
11
12
14
15
VCC
LEB
Positive Supply Terminal.
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to placing the comparator in the latch mode. LEB
must be driven in conjunction with LEB. If left unconnected, the comparator defaults to
compare mode.
13
16
LEB
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In latch mode (logic low), the output
reflects the input state just prior to placing the comparator in the latch mode. LEB must be
driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode.
Rev. A | Page 6 of 16
ADCMP561/ADCMP562
Pin No.
ADCMP561 ADCMP562 Mnemonic Function
14
15
17
18
GND
QB
Analog Ground.
One of two complementary outputs for Channel B. QB is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of PIN LEB for more information.
16
19
20
QB
One of two complementary outputs for Channel B. QB is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEB for more information.
VDD
Logic Supply Terminal.
Rev. A | Page 7 of 16
ADCMP561/ADCMP562
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = +5.0 V, VEE = –5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted.
3.0
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
2.64
2.62
2.60
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–2.5
–1.5
–0.5
0.5
1.5
2.5
3.5
–40
–20
0
20
40
60
80
NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0V)
TEMPERATURE (°C)
Figure 6. Input Bias Current vs. Input Voltage
Figure 9. Input Bias Current vs. Temperature
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
2.6
2.4
2.2
2.0
1.8
1.6
1.4
–40
–20
0
20
40
60
80
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
TEMPERATURE (°C)
TIME (ns)
Figure 7. Input Offset Voltage vs. Temperature
Figure 10. Rise and Fall of Outputs vs. Time
575
570
565
560
555
550
545
540
535
530
525
500
495
490
485
480
475
470
465
460
455
450
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Rise Time vs. Temperature
Figure 11. Fall Time vs. Temperature
Rev. A | Page 8 of 16
ADCMP561/ADCMP562
715
710
705
700
695
690
685
680
708
706
704
702
700
698
696
694
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–2
–1
0
1
2
3
TEMPERATURE (°C)
INPUT COMMON-MODE VOLTAGE (V)
Figure 12. Propagation Delay vs. Temperature
Figure 15. Propagation Delay vs. Common-Mode Voltage
140
120
100
80
25
20
15
10
5
60
40
0
20
0
–5
0.7
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.7
2.7
3.7
4.7
5.7
6.7
7.7
8.7
9.7
OVERDRIVE VOLTAGE (V)
PULSE WIDTH (ns)
Figure 13. Propagation Delay vs. Overdrive Voltage
Figure 16. Propagation Delay Error vs. Pulse Width
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
20
0
0
0
50
100
(µA)
150
50
40
30
20
10
0
I
R
(kΩ)
HYS
HYS
Figure 17. Comparator Hysteresis vs. IHYS
Figure 14. Comparator Hysteresis vs. RHYS
Rev. A | Page 9 of 16
ADCMP561/ADCMP562
TIMING INFORMATION
LATCH ENABLE
50%
LATCH ENABLE
tS
tPL
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
REF
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 18. System Timing Diagram
Figure 18 shows the compare and latch features of the ADCMP561/ADCMP562. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol Timing
Description
tPDH
tPDL
tPLOH
tPLOL
tH
Input to Output High Delay
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Input to Output Low Delay
Latch Enable to Output High Delay
Latch Enable to Output Low Delay
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPL
tS
Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change.
Minimum Setup Time
Output Rise Time
Output Fall Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
tR
tF
VOD
Voltage Overdrive
Difference between the differential input and reference input voltages.
Rev. A | Page 10 of 16
ADCMP561/ADCMP562
APPLICATION INFORMATION
The ADCMP561/ADCMP562 comparators are very high speed
devices. Consequently, high speed design techniques must be
employed to achieve the best performance. The most critical
aspect of any ADCMP561/ADCMP562 design is the use of a
low impedance ground plane. A ground plane, as part of a
multilayer board, is recommended for proper high speed
performance. Using a continuous conductive plane over the
surface of the circuit board can create this, allowing breaks in
the plane only for necessary signal paths. The ground plane
provides a low inductance ground, eliminating any potential
differences at different ground points throughout the circuit
board caused by ground bounce. A proper ground plane also
minimizes the effects of stray capacitance on the circuit board.
CLOCK TIMING RECOVERY
Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed
comparator can be used to recover the distorted waveform
while maintaining a minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator amplifier, proper design and
layout techniques should be used to ensure optimal perform-
ance from the ADCMP561/ADCMP562. The performance
limits of high speed circuitry can be a result of stray capaci-
tance, improper ground impedance, or other layout issues.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible from the
power supply pins on the ADCMP561/ADCMP562 to ground.
These capacitors act as a charge reservoir for the device during
high frequency switching.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP561/ADCMP562. Source resistance in combination
with equivalent input capacitance could cause a lagged response
at the input, thus delaying the output. The input capacitance of
the ADCMP561/ADCMP562, in combination with stray
capacitance from an input pin to ground, could result in several
picofarads of equivalent capacitance. A combination of 3 kΩ
source resistance and 5 pF of input capacitance yields a time
constant of 15 ns, which is significantly slower than the 750 ps
capability of the ADCMP561/ADCMP562. Source impedances
should be significantly less than 100 Ω for best performance.
The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input may
be left open or may be attached to VDD (VDD is a PECL logic
high). The complementary input,
, may be left
LATCH ENABLE
open or may be tied to VDD − 2.0 V. Leaving the latch inputs
unconnected or providing the proper voltages disables the
latching function.
Sockets should be avoided due to stray capacitance and induc-
tance. If proper high speed techniques are used, the devices
should be free from oscillation when the comparator input
signal passes through the switching threshold.
Occasionally, one of the two comparator stages within the
ADCMP561/ADCMP562 is not used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
COMPARATOR PROPAGATION DELAY
DISPERSION
The ADCMP561/ADCMP562 have been specifically designed
to reduce propagation delay dispersion over an input overdrive
range of 100 mV to 1.5 V. Propagation delay overdrive
dispersion is the change in propagation delay that results from a
change in the degree of overdrive (how far the switching point
is exceeded by the input). The overall result is a higher degree of
timing accuracy because the ADCMP561/ADCMP562 are far
less sensitive to input variations than most comparator designs.
connecting the LATCH ENABLE and
inputs
LATCH ENABLE
as described previously.
The best performance is achieved with the use of proper PECL
terminations. The open emitter outputs of the ADCMP561/
ADCMP562 are designed to be terminated through 50 Ω
resistors to VDD − 2.0 V, or any other equivalent PECL termin-
ation. If high speed PECL signals must be routed more than a
centimeter, microstrip or stripline techniques may be required
to ensure proper transition times and prevent output ringing.
Rev. A | Page 11 of 16
ADCMP561/ADCMP562
Propagation delay dispersion is a specification that is important
in critical timing applications such as ATE, bench instruments,
and nuclear instrumentation. Overdrive dispersion is defined
as the variation in propagation delay as the input overdrive
conditions are changed (Figure 19). For the ADCMP561 and
ADCMP562, overdrive dispersion is typically 75 ps as the
overdrive is changed from 100 mV to 1.5 V. This specification
applies for both positive and negative overdrive because the
ADCMP561/ADCMP562 have equal delays for positive and
negative going inputs.
hysteresis versus resistance curve is shown in Figure 21.
A current source can also be used with the HYS pin. The
relationship between the current applied to the HYS pin and the
resulting hysteresis is shown in Figure 17.
–V
2
+V
2
H
H
0V
INPUT
1
1.5V OVERDRIVE
INPUT VOLTAGE
20mV OVERDRIVE
± V
0
V
REF
OS
OUTPUT
DISPERSION
Q OUTPUT
Figure 20. Comparator Hysteresis Transfer Function
Figure 19. Propagation Delay Dispersion
160
140
120
100
80
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often useful in a
noisy environment, or where it is not desirable for the
comparator to toggle between states when the input signal is at
the switching threshold. The transfer function for a comparator
with hysteresis is shown in Figure 20. If the input voltage
approaches the threshold from the negative direction, the
comparator switches from a 0 to a 1 when the input crosses
+VH/2. The new switching threshold becomes −VH/2. The
comparator remains in a 1 state until the threshold −VH/2 is
crossed, coming from the positive direction. In this manner,
noise centered on 0 V input does not cause the comparator to
switch states unless it exceeds the region bounded by VH/2.
60
40
20
0
50
40
30
20
10
0
R
(kΩ)
HYS
Figure 21. Comparator Hysteresis vs. RHYS
Positive feedback from the output to the input is often used to
produce hysteresis in a comparator (Figure 24). The major
problem with this approach is that the amount of hysteresis
varies with the output logic levels, resulting in a hysteresis that
is not symmetrical around zero.
MINIMUM INPUT SLEW RATE REQUIREMENT
As for all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate when the
input crosses the threshold. This oscillation is due in part to the
high input bandwidth of the comparator and the parasitics of
the package. Analog Devices recommends a slew rate of 1 V/µs
or faster to ensure a clean output transition. If slew rates less
than 1 V/µs are used, hysteresis should be added to reduce the
oscillation.
In the ADCMP562, hysteresis is generated through the
programmable hysteresis pin. A resistor from the HYS pin to
GND creates a current into the part that is used to generate
hysteresis. Hysteresis generated in this manner is independent
of output swing and is symmetrical around the trip point. The
Rev. A | Page 12 of 16
ADCMP561/ADCMP562
TYPICAL APPLICATION CIRCUITS
V
V
IN
IN
ADCMP561/
ADCMP562
OUTPUTS
OUTPUTS
ADCMP562
HYS
V
V
REF
REF
0Ω TO 80kΩ
LATCH
ENABLE
INPUTS
V
– 2.0V
V
– 2V
DD
DD
ALL RESISTORS 50Ω, UNLESS OTHERWISE NOTED
ALL RESISTORS 50Ω
Figure 22. High Speed Sampling Circuits
Figure 24. Adding Hysteresis Using the HYS Control Pin
50Ω
50Ω
50Ω
+V
REF
ADCMP561/
ADCMP562
ADCMP561/
ADCMP562
OUTPUTS
V
IN
V
50Ω
IN
100Ω
100Ω
(V – 2V)
DD
× 2
V
–2V
DD
Figure 25. How to Interface a PECL Output to an
Instrument with a 50 Ω to Ground Input
ADCMP561/
ADCMP562
OUTPUTS
–V
REF
V
–2V
DD
LATCH
ENABLE
INPUTS
ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED
Figure 23. High Speed Window Comparator
Rev. A | Page 13 of 16
ADCMP561/ADCMP562
OUTLINE DIMENSIONS
0.193
BSC
16
1
9
8
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AB
Figure 26. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
0.341
BSC
20
1
11
10
0.154
BSC
0.236
BSC
PIN 1
0.065
0.049
0.069
0.053
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
SEATING
PLANE
0.050
0.016
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AD
Figure 27. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Dimensions shown in inches
ORDERING GUIDE
Model
ADCMP561BRQ
ADCMP562BRQ
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
RQ-16
RQ-20
16-Lead QSOP
20-Lead QSOP
Rev. A | Page 14 of 16
ADCMP561/ADCMP562
NOTES
Rev. A | Page 15 of 16
ADCMP561/ADCMP562
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04687–0–7/04(A)
Rev. A | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明