ADDI9023BBCZ [ADI]
Vertical Driver for CCD Cameras; 垂直驱动器的CCD相机
| 型号： | ADDI9023BBCZ |
| 厂家： | 
ADI |
| 描述： | Vertical Driver for CCD Cameras |
| 文件： | 总12页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Vertical Driver for CCD Cameras
Data Sheet
ADDI9023
FEATURES
GENERAL DESCRIPTION
12-channel vertical driver
8 three-level drivers
4 two-level drivers
Substrate clock driver
Input logic supports a 1.6 V to 3.6 V range
Output drivers support a −9.5 V to +15.5 V range
6 mm × 6 mm CSP_BGA package with 0.65 mm pitch
The ADDI9023 is a 12-channel vertical driver for charge-coupled
device (CCD) imaging applications. It includes eight three-level
drivers and four two-level drivers. The input configuration can
support up to nine individual vertical timing phases and eight shift
gate signals. A separate substrate clock channel (SUBCK) is also
included. Typical load drive capability for each channel is 3 nF.
The ADDI9023 is specified over an operating temperature range
of −25°C to +85°C.
APPLICATIONS
Digital still cameras
Industrial cameras
Surveillance cameras
Medical imaging
FUNCTIONAL BLOCK DIAGRAM
VDD
VH VM VL
ADDI9023
XSG1
XV1
+
+
V1A
V1B
V2A
V2B
XSG2
XSG3
+
+
XV2
XSG4
THREE-LEVEL
OUTPUTS
XSG5
+
+
+
V3A
V3B
V4
XV3
XSG6
XSG7
XV4
XV5
+
V5
XSG8
XV6
XV7
V6
V7
TWO-LEVEL
OUTPUTS
XV8
XV9
V8
V9
SUBCK
XSUBCK
VLL
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
ADDI9023
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................6
Input/Output Logic States ................................................................8
Applications Information .............................................................. 10
Power-Up Sequence ................................................................... 10
Power-Down Sequence.............................................................. 10
Circuit Layout Information....................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Output Driver Specifications ...................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
ADDI9023
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
−25
−65
+85
+150
°C
°C
V-DRIVER POWER SUPPLY VOLTAGES
VDD
VH
VL
VM
VLL
VH to VL, VLL
Input logic supply
1.6
3.0
3.6
V
V
V
V
V
V
V-driver high supply
V-driver low supply
V-driver midsupply
SUBCK V-driver low supply
Maximum voltage from VH to VL, VLL
VH = +15 V, VM = 0 V, VL = VLL = −7.5 V
XVx = XSGx = 0 V
XVx = XSGx = VDD
XVx = XSGx = 0 V
XVx = XSGx = VDD
XVx = XSGx = 0 V
11.0
−9.5
−1.5
−9.5
15.0
−7.5
0.0
15.5
−5.5
+1.5
−5.5
24
−7.5
DC POWER SUPPLY CURRENTS
IVDD
0.5
0.5
0.4
3.3
2.1
0.1
0.3
0.2
0.3
0.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IVH
IVL
IVM
IVLL
XVx = XSGx = VDD
XVx = XSGx = 0 V
XVx = XSGx = VDD
XSUBCK = 0 V
XSUBCK = VDD
DIGITAL INPUTS
VDD = 1.6 V to 3.6 V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VDD − 0.6
V
V
µA
µA
pF
0.6
50
50
10
10
10
Rev. 0 | Page 3 of 12
ADDI9023
Data Sheet
OUTPUT DRIVER SPECIFICATIONS
VH = 15 V, VM = 0 V, VL, VLL = −7.5 V, TA = 25°C.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
V1A TO V5
Delay Time, VL to VM and VM to VL
Delay Time, VM to VH and VH to VM
Rise Time, VL to VM
Rise Time, VM to VH
Fall Time, VM to VL
tPLM, tPML
tPMH, tPHM
tRLM
tRMH
tFML
37
43
110
240
180
130
ns
ns
ns
ns
ns
ns
Load circuit: 20 Ω + 3 nF to GND
Load circuit: 20 Ω + 3 nF to GND
Load circuit: 20 Ω + 3 nF to GND
Load circuit: 20 Ω + 3 nF to GND
Fall Time, VH to VM
Output Currents
tFHM
V1A to V5 = −7.25 V
V1A to V5 = −0.25 V
V1A to V5 = +0.25 V
V1A to V5 = +14.75 V
14
−23
23
mA
mA
mA
mA
−10
On Resistance
RON
VH
VM
VL
23
11
17
35
20
25
Ω
Ω
Ω
V6 TO V9
Delay Time, VL to VM and VM to VL
Rise Time, VL to VM
Fall Time, VM to VL
Output Currents
tPLM, tPML
tRLM
tFML
37
110
180
ns
ns
ns
Load circuit: 20 Ω + 3 nF to GND
Load circuit: 20 Ω + 3 nF to GND
V6 to V9 = −7.25 V
V6 to V9 = −0.25 V
14
−23
mA
mA
On Resistance
VM
VL
RON
11
17
20
25
Ω
Ω
SUBCK OUTPUT
Delay Time, VLL to VH
Delay Time, VH to VLL
Rise Time, VLL to VH
Fall Time, VH to VLL
Output Currents
tPLH
tPHL
tRLH
tFHL
47
47
45
45
ns
ns
ns
ns
Load circuit: 1 nF to GND
Load circuit: 1 nF to GND
SUBCK = −7.25 V
SUBCK = +14.75 V
23
−22
10
mA
mA
Ω
VLL On Resistance
RON
17
V-DRIVER
50%
50%
INPUT
tRLM, tRMH, tRLH
tPML, tPHM, tPHL
90%
90%
V-DRIVER
OUTPUT
tPLM
,
tPMH, tPLH
tFML, tFHM, tFHL
10%
10%
Figure 2. Definition of V-Driver Timing Specifications
Rev. 0 | Page 4 of 12
Data Sheet
ADDI9023
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VDD to VSS
VH to VL, VLL
VH to VSS
VL to VSS
VM to VSS
VMM to VSS
VLL to VSS
V1A to V9 to VSS
VDREN to VSS
Junction Temperature
−0.3 V to +3.9 V
−0.3 V to +25.0 V
−0.3 V to +17.0 V
−17.0 V to +0.3 V
−6.0 V to +3.0 V
−6.0 V to +3.0 V
−17.0 V to +0.3 V
VL − 0.3 V to VH + 0.3 V
−0.3 V to VDD + 0.3 V
150°C
Table 4. Thermal Resistance
Package Type
θJA
Unit
40-Lead CSP_BGA
46
°C/W
ESD CAUTION
Lead Temperature
(Soldering, 10 sec)
350°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 12
ADDI9023
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
A
B
C
D
E
F
A
B
C
D
E
F
VM
VL
VDREN
XSG8
XSG5
XSG6
VH
XSG4
XSG1
V8
V6
V7
V5
V9
XSG7
XSG2
XSG3
XV8
ADDI9023
TOP VIEW
(Not to Scale)
V4
XV7
XV5
XV3
VSS
6
V3B
V3A
XV9
XV6
XV4
VSS
7
V2B
V1B
V1A
1
V2A
XSUBCK
XV1
VLL
4
XV2
VDD
5
G
G
SUBCK
VMM
3
2
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
Mnemonic
Type1
P
P
P
DI
DI
DI
DI
VO2
VO2
VO2
DI
DI
DI
Description
VM
VL
VH
VDREN
XSG8
XSG5
XSG6
V8
V-Driver Midsupply.
V-Driver Low Supply.
V-Driver High Supply.
V-Driver Enable. Active high.
Vertical Input.
Vertical Input.
Vertical Input.
CCD Vertical Transfer Clock.
CCD Vertical Transfer Clock.
CCD Vertical Transfer Clock.
Vertical Input.
Vertical Input.
Vertical Input.
Vertical Input.
CCD Vertical Transfer Clock.
CCD Vertical Transfer Clock (XV5 + XSG8).
Vertical Input.
Vertical Input.
CCD Vertical Transfer Clock (XV4 + XSG7).
CCD Vertical Transfer Clock (XV3 + XSG6).
Vertical Input.
V7
V9
XSG7
XSG2
XSG3
XSG4
V6
B6
B7
DI
C1
C2
C6
C7
D1
D2
D6
D7
E1
VO2
VO3
DI
V5
XV8
XSG1
V4
DI
VO3
VO3
DI
V3B
XV7
XV9
V2B
V3A
XV5
XV6
DI
Vertical Input.
VO3
VO3
DI
CCD Vertical Transfer Clock (XV2 + XSG4).
CCD Vertical Transfer Clock (XV3 + XSG5).
Vertical Input.
E2
E6
E7
DI
Vertical Input.
Rev. 0 | Page 6 of 12
Data Sheet
ADDI9023
Pin No.
F1
F2
F3
F4
Mnemonic
Type1
VO3
VO3
DI
Description
V1B
V2A
XSUBCK
XV1
CCD Vertical Transfer Clock (XV1 + XSG2).
CCD Vertical Transfer Clock (XV2 + XSG3).
XSUBCK Input to SUBCK Buffer.
Vertical Input.
DI
F5
XV2
DI
Vertical Input.
F6
XV3
DI
Vertical Input.
F7
XV4
DI
Vertical Input.
G1
G2
G3
G4
G5
G6
G7
V1A
VO3
VO2
P
P
P
CCD Vertical Transfer Clock (XV1 + XSG1).
CCD Substrate Clock Output.
SUBCK Output Driver Ground.
V-Driver Low Supply for SUBCK Output.
Digital Logic Supply.
SUBCK
VMM
VLL
VDD
VSS
P
P
Digital Logic Ground.
Digital Logic Ground.
VSS
1 DI = digital input; P = power; VO2 = vertical driver output, two-level; VO3 = vertical driver output, three-level.
Rev. 0 | Page 7 of 12
ADDI9023
Data Sheet
INPUT/OUTPUT LOGIC STATES
Table 6. V1A Output Polarity
Table 11. V3B Output Polarity
Vertical Driver Input
Vertical Driver Input
XV1
L
L
XSG1
V1A Output
XV3
L
L
XSG6
V3B Output
L
H
L
VH
VM
VL
L
H
L
VH
VM
VL
H
H
H
H
VL
H
H
VL
Table 7. V1B Output Polarity
Table 12. V4 Output Polarity
Vertical Driver Input
Vertical Driver Input
XV1
L
L
XSG2
V1B Output
XV4
L
L
XSG7
V4 Output
L
H
L
VH
VM
VL
L
H
L
VH
VM
VL
H
H
H
H
VL
H
H
VL
Table 8. V2A Output Polarity
Table 13. V5 Output Polarity
Vertical Driver Input
Vertical Driver Input
XV2
L
L
XSG3
V2A Output
XV5
L
L
XSG8
V5 Output
L
H
L
VH
VM
VL
L
H
L
VH
VM
VL
H
H
H
H
VL
H
H
VL
Table 9. V2B Output Polarity
Table 14. V6 to V9 Output Polarity
Vertical Driver Input
Vertical Driver Input
XV2
L
L
XSG4
V2B Output
XV6, XV7, XV8, or XV9
V6, V7, V8, or V9 Output
L
H
L
VH
VM
VL
L
H
VM
VL
H
H
H
VL
Table 15. SUBCK Output Polarity
Vertical Driver Input
Table 10. V3A Output Polarity
XSUBCK
SUBCK Output
Vertical Driver Input
L
VH
XV3
L
L
XSG5
V3A Output
H
VLL
L
H
L
VH
VM
VL
H
H
H
VL
Rev. 0 | Page 8 of 12
Data Sheet
ADDI9023
XV1, XV2,
XV3, XV4, XV5
XSG1, XSG2, XSG3, XSG4,
XSG5, XSG6, XSG7, XSG8
VH
V1A, V1B,
V2A, V2B,
V3A, V3B,
VM
V4, V5
VL
Figure 4. Three-Level V-Driver Output Polarities
XV6, XV7,
XV8, XV9
VM
V6, V7, V8, V9
VL
Figure 5. Two-Level V-Driver Output Polarities
XSUBCK
VH
SUBCK
VLL
Figure 6. SUBCK Output Polarity
Rev. 0 | Page 9 of 12
ADDI9023
Data Sheet
APPLICATIONS INFORMATION
3. Turn on the VL/VLL power supply, typically −6 V to −9 V.
4. Take the VDREN pin high to enable the V-driver outputs.
VDREN must remain high throughout normal vertical
timing operation.
POWER-UP SEQUENCE
When the ADDI9023 is powered up, the following sequence is
recommended (refer to Figure 7 for each step). Note that VH is
powered on before VL but, depending on CCD restrictions, VH
and VL can also be powered on simultaneously.
POWER-DOWN SEQUENCE
1. Turn on the VDD power supply, either 1.8 V or 3.3 V. After
VDD settles, the logic inputs from the timing generator (XV,
XSG, XSUBCK) can become active. Keep VDREN low during
this time.
When the ADDI9023 is powered down, reverse the procedure
shown in Figure 7.
1. Take the VDREN pin low to disable the V-driver outputs.
2. Turn off the VL/VLL and VH power supplies.
3. Turn off the VDD power supply.
2. Turn on the VH power supply, typically +12 V to +15 V.
1
2
3
4
VH SUPPLY
VDD
0V
0V
VM
POWER
SUPPLIES
VL, VLL SUPPLY
VDD
XV, XSG,
XSUBCK
(INPUT)
DON’T CARE
VDD
V-DRIVER OUTPUTS ACTIVE
WHEN VDREN IS HIGH
0V
0V
VDREN
VH
V1A TO V9
(OUTPUT)
VM
VL/VLL (SUBCK ONLY)
Figure 7. Recommended Power-Up Sequence
Rev. 0 | Page 10 of 12
Data Sheet
ADDI9023
additional bypass capacitor, such as a 1.0 µF to 22 µF capacitor,
depending on CCD and performance requirements. Connect the
ground pins (VSS, VM, and VMM) to a common ground plane.
CIRCUIT LAYOUT INFORMATION
The recommended circuit configuration is shown in Figure 8.
Each supply pin should have a high quality 0.1 µF capacitor
connected to ground. The VH and VL supplies should have an
VH SUPPLY
0.1µF
25V
1.0µF
25V
+3.3V SUPPLY
0.1µF
VL SUPPLY
0.1µF
10V
4.7µF
10V
+
XSG1
C7
V1A
XV1
G1
F1
F2
E1
E2
D2
D1
C2
C1
B2
B1
B3
G2
F4
V1B
V2A
V2B
V3A
V3B
V4
XSG2
B5
XSG3
B6
XV2
F5
XSG4
B7
XSG5
A6
XV3
F6
ADDI9023
V5
XSG6
A7
(Not to Scale)
V6
XV4
F7
V7
XSG7
B4
V8
XV5
E6
V9
SUBCK
XSG8
A5
XV6
E7
XV7
D6
13
XV8
V-DRIVER OUTPUTS
C6
XV9
D7
XSUBCK
(TO CCD)
F3
VDREN
A4
V-DRIVER OUTPUT ENABLE
ACTIVE HIGH (FROM
GENERAL-PURPOSE OUTPUT)
18
LOGIC INPUTS
(FROM
TIMING GENERATOR)
Figure 8. Typical Circuit Configuration
Rev. 0 | Page 11 of 12
ADDI9023
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
A1 BALL
CORNER
A1 BALL
CORNER
7
6
5
4
3
2
1
A
B
C
D
E
F
3.90
BSC SQ
0.65
BSC
G
BOTTOM VIEW
DETAIL A
1.05
TOP VIEW
REF
*
0.76
0.66
0.56
DETAIL A
*
1.04
0.96
0.81
0.30 NOM
0.25 MIN
0.45
0.40
0.35
COPLANARITY
0.10
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE
EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 9. 40-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
BC-40-1
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
40-Lead CSP_BGA
40-Lead CSP_BGA
Package Option
BC-40-1
BC-40-1
ADDI9023BBCZ
ADDI9023BBCZRL
−25°C to +85°C
−25°C to +85°C
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10693-0-4/12(0)
Rev. 0 | Page 12 of 12
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