ADE7762 [ADI]
Polyphase Energy Metering IC with Phase Drop Indication; 多相电能计量IC与相位落指示
| 型号： | ADE7762 |
| 厂家： | 
ADI |
| 描述： | Polyphase Energy Metering IC with Phase Drop Indication |
| 文件： | 总28页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Polyphase Energy Metering IC with Phase
Drop Indication
Preliminary Technical Data
ADE7762
FEATURES
The only analog circuitry used in the ADE7762 is in the
analog-to-digital converters (ADCs) and reference circuit. All
High accuracy supports 50 Hz/60 Hz IEC62053-21
Less than 0.1% error over a dynamic range of 500 to 1
Compatible with 3-phase 3-wire delta and 3-phase 4-wire Wye
configurations
Supplies average active power on the frequency outputs F1 and F2
High frequency output (CF) is intended for calibration and
supplies instantaneous active power
Logic output REVP indicates a potential miswiring or negative
power on the sum of all phases
Dropout indication for each phase on LED driver pins
Phase sequence error detection
Direct drive for electromechanical counters and 2-phase stepper
motors (F1 and F2)
other signal processing (for example, multiplication, filtering,
and summation) is carried out in the digital domain. This
approach provides superior stability and accuracy over
extremes in environmental conditions and over time.
The ADE7762 supplies average active power information on the
low frequency outputs, F1 and F2. These logic outputs can be
used to directly drive an electromechanical counter or to inter-
face with an MCU. The CF logic output gives instantaneous
active power information. This output is intended to be used for
calibration purposes.
The ADE7762 includes a power supply monitoring circuit on the
VDD pin. The ADE7762 remains inactive until the supply voltage
on VDD reaches 4 V. If the supply falls below 4 V, the ADE7762
also resets and no pulses are issued on F1, F2, and CF.
Proprietary ADCs and DSP provide high accuracy over large
variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.4 V 8% (25 ppm/°C typical) with external
overdrive capability
Single 5 V supply, low power (TBD mW typical)
Low cost CMOS process
A multiple multiplexed logic output provides phase dropout per
phase, reverse polarity per phase, and a phase sequence error.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no load
threshold ensures the ADE7762 does not exhibit any creep
when there is no load.
GENERAL DESCRIPTION
The ADE77621 is a high accuracy polyphase electrical energy
measurement IC. The ADE7762 specifications surpass the
accuracy requirements as quoted in the IEC62053-21 standard.
The ADE7762 is available in a 28-lead SOIC package.
1 Patent pending.
FUNCTIONAL BLOCK DIAGRAM
V
ABS
19
DD
5
7
8
IAP
IAN
VAP
ADC
ADC
X
X
POWER
SUPPLY
MONITOR
HPF
LPF
LPF
LPF
18
Φ
ADE7762
9
IBP
IBN
ADC
ADC
Σ
10
17
4
HPF
DGND
CLKIN
VBP
Φ
21
22 CLKOUT
ICP 11
ADC
ADC
X
12
16
15
ICN
HPF
VCP
Φ
VN
4kΩ
2.4V REF
PHASE AND REVP MONITOR
DIGITAL-TO-FREQUENCY CONVERTER
1
2
28
27
6
13
14
20
23
24
25
26
3
AGND
REF
LED_CTRL LED_A LED_B LED_C REVP SCF
S0
S1
F2
F1
CF
IN/OUT
Figure 1.
Rev. PrB
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
ADE7762
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Channels Connection.................................................. 16
Meter Connections..................................................................... 16
Power Supply Monitor ................................................................... 18
Phase Monitor................................................................................. 19
HPF and Offset Effects .................................................................. 20
Digital-to-Frequency Conversion ................................................ 21
Mode Selection of the Sum of the Three Active Energies..... 22
Power Measurement Considerations....................................... 22
Transfer Function........................................................................... 23
Frequency Outputs F1 and F2 .................................................. 23
Frequency Output CF................................................................ 24
Selecting a Frequency for an Energy Meter Application........... 25
Frequency Outputs..................................................................... 25
No Load Threshold .................................................................... 25
Negative Power Information..................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
General Description......................................................................... 1
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions ............................ 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 11
Test Circuit ...................................................................................... 12
Theory of Operation ...................................................................... 13
Power Factor Considerations.................................................... 13
Nonsinusoidal Voltage and Current ........................................ 14
Analog Inputs.................................................................................. 15
Current Channels ....................................................................... 15
Voltage Channels........................................................................ 15
Typical Connection Diagrams...................................................... 16
Current Channel Connection................................................... 16
Rev. PrB | Page 2 of 28
Preliminary Technical Data
SPECIFICATIONS
ADE7762
VDD = 5 V ± 5ꢀ, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
ACCURACY1, 2
Conditions
Min
Typ
Max
Unit
Measurement Error on
Current Channel
Voltage channel with full-scale signal (±±55 mV),
2±°C, over a dynamic range of ±55 to 1
5.1
% Reading
Phase Error Between
Channels
PF = 5.8 Capacitive
PF = 5.± Capacitive
±5.1
±5.1
Degrees
Degrees
AC Power Supply Rejection
SCF = 5, S5 = S1 = 1
Output Frequency
Variation (CF)
IA = IB = IC = 155 mV rms,
VA = VB = VC = 155 mV rms @ ±5 Hz,
Ripple on VDD of 255 mV rms @ 155 Hz
5.51
5.1
% Reading
DC Power Supply Rejection S1 = 1; S5 = SCF = 5
Output Frequency
Variation (CF)
V1 = 155 mV rms, V2 = 155 mV rms,
VDD = ± V ± 2±5 mV
% Reading
ANALOG INPUTS
See Analog Inputs section
Maximum Signal Levels
VAP – VN, VBP – VN, VCP – VN, IAP – IAN, IBP – IBN, ICP – ICN
±5.±
V peak
difference
Input Impedance (DC)
Bandwidth (−3 dB)
ADC Offset Error1, 2
Gain Error
CLKIN = 15 MHz
CLKIN/2±6, CLKIN = 15 MHz
375
415
14
kΩ
kHz
mV
% Ideal
±2±
2.6
External 2.± V reference, IA = IB = IC = ±55 mV dc
±ꢀ
REFERENCE INPUT
REFIN/OUT Input Voltage
Range
2.4 V + 8%
2.4 V − 8%
V
2.2
3.3
V
kΩ
pF
Input Impedance
Input Capacitance
ON-CHIP REFERENCE
Reference Error
15
Nominal 2.4 V
±255
mV
Temperature Coefficient
CLKIN
Input Clock Frequency
LOGIC INPUTS3
2±
15
ppm/°C
All specifications for CLKIN of 15 MHz
MHz
ACF, S5, S1, and ABS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS3
F1 and F2
VDD = ± V ± ±%
VDD = ± V ± ±%
Typically 15 nA, VIN = 5 V to VDD
2.4
V
V
μA
pF
5.8
±3
15
Output High Voltage, VOH ISOURCE = 15 mA, VDD = ± V
4.±
4.±
V
V
Output Low Voltage, VOL
CF and NEGP
ISINK = 15 mA, VDD = ± V
5.±
5.±
Output High Voltage, VOH VDD = ± V, ISOURCE = ± mA
V
V
Output Low Voltage, VOL
LED_CTRL
VDD = ± V, ISINK = ± mA
VDD = ± V, CLKIN = 15 MHz
Output Frequency
Output High Voltage
Output Low Voltage
17.3ꢀ
kHz
V
V
VDD = ± V, ISOURCE = 15 mA
VDD = ± V, ISINK = 15 mA
4.±
TBD
Rev. PrB | Page 3 of 28
ADE7762
Preliminary Technical Data
Parameter
Conditions
Min
Typ
Max
Unit
LED_A, LED_B, LED_C
Output Low ISINK
Output High Source
POWER SUPPLY
VDD
VDD = 4.7± V
VDD = 4.7± V
TBD
TBD
mA
mA
For specified performance
± V ± ±%
4.7±
±.2±
TBD
V
mA
IDD
TBD
1 See the Terminology section for explanation of specifications.
2 See the plots in the Typical Performance Characteristics section.
3 Sample tested during initial release and after any redesign or process changes that might affect this parameter.
Rev. PrB | Page 4 of 28
Preliminary Technical Data
ADE7762
TIMING CHARACTERISTICS
VDD = 5 V ± 5ꢀ, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter1,2
Conditions
Specification Unit
3
t1
t2
F1 and F2 pulse width (logic high)
Output pulse period (see the Transfer Function section)
125
ms
sec
See Figure 2
t3
Time between F1 falling edge and F2 falling edge
CF pulse width (logic high)
sec
ms
sec
sec
μs
1/2 t2
90
3, 4
t4
±
t±
CF pulse period (see the Transfer Function section)
Minimum time between F1 and F2 pulse
LED_CTRL pulse width
See Table 7
4/CLKIN
28.8
t6
t7
t8
tꢀ
LED_CTRL period
μs
57.5
LED pulse width
μs
7.2
1 Sample tested during initial release and after any redesign or process changes that might affect this parameter.
2 See Figure 2.
3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies (see the Frequency Outputs section).
4 CF is not synchronous to F1 or F2 frequency outputs.
± The CF pulse is always 1 μs in the high frequency mode (see the Frequency Outputs section).
t1
F1
t6
t2
t3
F2
t5
t4
CF
Figure 2. Timing Diagram for Frequency Outputs
t8
t7
t9
Figure 3: Timing Diagram for LED Drivers
Rev. PrB | Page ± of 28
ADE7762
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND
VDD to DGND
−5.3 V to +7 V
−5.3 V to +7 V
Analog Input Voltage to AGND
VA P, V B P, V C P, V N , I A P, I A N , I B P, I B N , I C P,
and ICN
−6 V to +6 V
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Industrial
−5.3 V to VDD + 5.3 V
−5.3 V to VDD + 5.3 V
−5.3 V to VDD + 5.3 V
−45°C to +8±°C
−6±°C to +1±5°C
1±5°C
Storage Temperature Range
Junction Temperature
28-Lead SOIC, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (65 sec)
63 mW
±±°C/W
21±°C
225°C
Infrared (1± sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4555 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 6 of 28
Preliminary Technical Data
ADE7762
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LED_CTRL
LED_A
CF
1
2
3
4
5
6
7
8
9
28 LED_B
27 LED_C
26 F1
DGND
25 F2
V
24 S1
DD
ADE7762
REVP
IAP
23 S0
TOP VIEW
22 CLKOUT
21 CLKIN
20 SCF
19 ABS
18 VAP
17 VBP
16 VCP
15 VN
(Not to Scale)
IAN
IBP
IBN 10
ICP 11
ICN 12
AGND 13
REF
14
IN/OUT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LED_CTRL
LED Control Output. The LED_CTRL signal multiplexes the indication of phase drop, phase sequence
error, and per phase reverse power on the LED_A, LED_B, and LED_C pins.
2
3
4
LED_A
CF
Phase A Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power
on phase A (see the Phase Monitor section).
Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information.
This output is intended to be used for calibration purposes.
This provides the ground reference for the digital circuitry in the ADE7762, that is, multiplier, filters, and
digital-to-frequency converter. Because the digital return currents in the ADE7762 are small, it is
acceptable to connect this pin to the analog ground plane of the whole system.
DGND
±
6
VDD
Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7762. The supply
voltage should be maintained at ± V ± ±% for specified operation. This pin should be decoupled to
DGND with a 15 μF capacitor in parallel with a 155 nF ceramic capacitor.
This logic output goes logic high when negative power is detected on the sum of the three phase
powers. This output is not latched and resets when positive power is once again detected (see the
Negative Power Information section).
REVP
7, 8;
ꢀ, 15;
11, 12
IAP, IAN;
IBP, IBN;
ICP, ICN
Analog Inputs for Current Channels. These channels are intended for use with current transducers and
are referenced in this document as current channels. These inputs are fully differential voltage inputs
with maximum differential input signal levels of ±5.± V (see the Analog Inputs section). Both inputs
have internal ESD protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these
inputs without risk of permanent damage.
13
14
AGND
This pin provides the ground reference for the analog circuitry in the ADE7762 (ADCs and reference).
This pin should be tied to the analog ground plane or the quietest ground reference in the system. This
quiet ground reference should be used for all analog circuitry, such as, anti-aliasing filters and current
and voltage transducers. To keep ground noise around the ADE7762 to a minimum, the quiet ground
plane should only connect to the digital ground plane at one point. It is acceptable to place the entire
device on the analog ground plane.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
2.4 V ±8% and a typical temperature coefficient of 2± ppm/°C. An external reference source can also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic
capacitor.
REFIN/OUT
1±, 16, 17, VN, VCP, VBP, VAP
18
Analog Inputs for the Voltage Channels. These channels are intended for use with voltage transducers
and are referenced in this document as voltage channels. These inputs are single-ended voltage inputs
with a maximum signal level of ±5.± V with respect to VN for specified operation. All inputs have
internal ESD protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these inputs
without risk of permanent damage.
1ꢀ
25
ABS
SCF
This logic input is used to select the method by which the three active energies from each phase are
summed. It selects between the arithmetical sum of the three energies (ABS logic high) or the sum of
the absolute values (ABS logic low). See the Mode Selection of the Sum of the Three Active Energies
section.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table 7 shows how the calibration frequencies are selected.
Rev. PrB | Page 7 of 28
ADE7762
Preliminary Technical Data
Pin No.
Mnemonic
Description
21
CLKIN
Master Clock for the ADCs and Digital Signal Processing. An external clock can be provided at this logic
input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to
provide a clock source for the ADE7762. The clock frequency for the specified operation is 15 MHz.
Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer
to the crystal manufacturer’s data sheet for the load capacitance requirements.
22
CLKOUT
A crystal can be connected across this pin and CLKIN as described previously to provide a clock source
for the ADE7762. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN
or when a crystal is being used.
23, 24
2±, 26
S5, S1
F2, F1
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion for design flexibility.
Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs
can be used to drive electromechanical counters and 2-phase stepper motors directly (see the Transfer
Function section).
27
28
LED_C
LED_B
Phase C Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power
on phase C (see the Phase Monitor section).
Phase B Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power
on phase B (see the Phase Monitor section).
Rev. PrB | Page 8 of 28
Preliminary Technical Data
ADE7762
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Error as a Percent of Reading
with Internal Reference (Wye Connection)
Figure 8. Error as a Percent of Reading over Temperature
with Internal Reference (Wye Connection)
Figure 6. Error as a Percent of Reading over Power Factor
with Internal Reference (Wye Connection)
Figure 9. Error as a Percent of Reading over Power Factor
with Internal Reference (Delta Connection)
Figure 7. Error as a Percent of Reading over Power Factor
with External Reference (Wye Connection)
Figure 10. Error as a Percent of Reading over Temperature
with External Reference (Wye Connection)
Rev. PrB | Page ꢀ of 28
ADE7762
Preliminary Technical Data
Figure 11. Error as a Percent of Reading over Frequency
Figure 13. Channel 1 Offset Distribution
with an Internal Reference (Wye Connection)
Figure 14. Error as a Percent of Reading over Power Supply
with Internal Reference (Wye Connection)
Figure 12. Error as a Percent of Reading over Power Supply
with External Reference (Wye Connection)
Rev. PrB | Page 15 of 28
Preliminary Technical Data
TERMINOLOGY
ADE7762
ADC Offset Error
Measurement Error
This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see an analog input signal offset.
However, because the HPF is always present, the offset is
removed from the current channel and the power calculation is
not affected by this offset.
The error associated with the energy measurement made by the
ADE7762 is defined by the following formula:
⎧
⎨
⎩
⎫
⎬
⎭
Energy Registered by ADE7762 – True Energy
PercentageError =
×100%
True Energy
Error between Channels
The high-pass filter (HPF) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
placed in the current channel. The phase correction network
ensures a phase match between the current channels and
voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz
and ±0.2° over a range of 40 Hz to 1 kHz (see Figure 28 and
Figure 29).
Gain Error
The gain error of the ADE7762 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7762 transfer function (see the Transfer
Function section).
Power Supply Rejection (PSR)
This quantifies the ADE7762 measurement error as a
percentage of reading when the power supplies are varied.
For the ac PSR measurement, a reading at a nominal supply
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supply and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading. See definition for Measurement Error.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supply is then varied ±5ꢀ and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.
Rev. PrB | Page 11 of 28
ADE7762
Preliminary Technical Data
TEST CIRCUIT
V
DD
100nF
10μF
5
19
I
LOAD
K7
26
25
3
V
IAP
F1
F2
CF
ABS
DD
1kΩ
4
3
1
2
7
8
TO FREQ.
COUNTER
33nF
ADE7762
820Ω
RB
1kΩ
IAN
22pF
10MHz
22pF
K8
33nF
22
21
CLKOUT
9
IBP
IBN
ICP
ICN
SAME AS
IAP, IAN
CLKIN
S0
10
23
24
20
11
12
V
S1
DD
SAME AS
IAP, IAN
1kΩ
SCF
1MΩ
1kΩ
18
REF
220V
AC
VAP
14
6
IN/OUT
REVP
33nF
0.1μF
10μF
1
SAME AS VAP
SAME AS VAP
17
16
LED_CTRL
VBP
VCP
2
LED_A
LED_B 28
15
27
VN
LED_C
33nF
AGND DGND
1kΩ
13
4
Figure 15. Test Circuit for Performance Curves
Rev. PrB | Page 12 of 28
Preliminary Technical Data
THEORY OF OPERATION
ADE7762
The six signals from the current and voltage transducers are
digitized with ADCs. These ADCs are 16-bit second-order ∑-Δ
with an oversampling rate of 833 kHz. This analog input
structure greatly simplifies transducer interface by providing a
wide dynamic range and bipolar input for direct connection to
the transducer. High-pass filters in the current channels remove
the dc component from the current signals. This eliminates any
inaccuracies in the active power calculation due to offsets in the
voltage or current signals (see the HPF and Offset Effects
section).
The low frequency output of the ADE7762 is generated by
accumulating the total active power information. This low
frequency inherently means a long accumulation time between
output pulses. The output frequency is therefore proportional to
the average active power. This average active power information
can, in turn, be accumulated (for example, by a counter) to
generate active energy information. Because of its high output
frequency and therefore shorter integration time, the CF output
is proportional to the instantaneous active power. This pulse is
useful for system calibration purposes that would take place
under steady load conditions.
The active power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals of each
phase. In order to extract the active power component, the dc
component, the instantaneous power signal is low-pass filtered
on each phase. Figure 16 illustrates the instantaneous active
power signal and shows how the active power information can
be extracted by low-pass filtering the instantaneous power
signal. This method is used to extract the active power
information on each phase of the polyphase system. The total
active power information is then obtained by adding the
individual phase active power. This scheme correctly calculates
active power for nonsinusoidal current and voltage waveforms
at all power factors. All signal processing is carried out in the
digital domain for superior stability over temperature and time.
POWER FACTOR CONSIDERATIONS
Low-pass filtering, the method used to extract the active power
information from the individual instantaneous power signal, is
still valid when the voltage and current signals of each phase are
not in phase. Figure 17 displays the unity power factor
condition and a displacement power factor (DPF) = 0.5, that is,
current signal lagging the voltage by 60°, for one phase of the
polyphase. Assuming that the voltage and current waveforms
are sinusoidal, the active power component of the instantaneous
power signal (the dc term) is given by
V ×1
2
⎛
⎜
⎝
⎞
⎟
⎠
×cos
(
60°
)
(1)
p(t) = i(t) × v(t)
WHERE:
V × I
V × I
2
v(t) = V × cos (ωt)
i(t) = I × cos (ωt)
p(t) = V × I
V × I
2
{1+ cos (2ωt)}
2
INSTANTANEOUS
POWER SIGNAL - p(t)
TIME
INSTANTANEOUS
ACTIVE POWER SIGNAL
VA × IA + VB × IB +
VC × IC
2
HPF
ADC
ABS
|X|
IAP
IAN
INSTANTANEOUS
TOTAL
POWER SIGNAL
LPF
LPF
LPF
MULTIPLIER
ADC
VAP
DIGITAL-TO-
FREQUENCY
HPF
ADC
F1
F2
IBP
IBN
Σ
Σ
Σ
|X|
MULTIPLIER
ADC
DIGITAL-TO-
FREQUENCY
VBP
CF
HPF
ADC
ICP
ICN
|X|
MULTIPLIER
ADC
VCP
VN
Figure 16. Signal Processing Block Diagram
Rev. PrB | Page 13 of 28
ADE7762
Preliminary Technical Data
∞
This is the correct active power calculation.
i
(
t
)
= IO + 2 ×
VnI × sin
(
nωt βn
)
(3)
∑
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS
ACTIVE POWER SIGNAL
n=0
where:
i(t) is the instantaneous current.
IO is the dc component.
V× I
2
In is the rms value of current harmonic n.
βn is the phase angle of the current harmonic.
0V
CURRENT
VOLTAGE
Using Equations 2 and 3, the active power, P, can be expressed
in terms of its fundamental active power (P1) and harmonic
active power (PH).
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS
ACTIVE POWER SIGNAL
P = P1 + PH
V× I
2
× cos(60°)
where:
0V
P = V1 × I1 cos φ1
1
(4)
φ1 = α1 − β1
VOLTAGE
CURRENT
60°
∞
Figure 17. DC Component of Instantaneous Power Signal
PH
=
Vn × In cos φn
∑
(5)
n=1
φn = αn −βn
NONSINUSOIDAL VOLTAGE AND CURRENT
The active power calculation method also holds true for non-
sinusoidal current and voltage waveforms. All voltage and
current waveforms in practical applications have some
harmonic content. Using the Fourier Transform, instantaneous
voltage and current waveforms can be expressed in terms of
their harmonic content
As can be seen from Equation 5, a harmonic active power
component is generated for every harmonic, provided that
harmonic is present in both the voltage and current waveforms.
The power factor calculation has been shown to be accurate in
the case of a pure sinusoid. Therefore, the harmonic active
power also correctly accounts for power factor since harmonics
are made up of a series of pure sinusoids. A limiting factor on
harmonic measurement is the bandwidth. On the ADE7762, the
bandwidth of the active power measurement is 14 kHz with a
master clock frequency of 10 MHz.
∞
v
(
t
)
= Vo + 2 ×
Vn × sin
(
nωt + αn
)
(2)
∑
n=0
where:
v(t) is the instantaneous voltage.
VO is the average value.
Vn is the rms value of voltage harmonic n.
and αn is the phase angle of the voltage harmonic.
Rev. PrB | Page 14 of 28
Preliminary Technical Data
ADE7762
ANALOG INPUTS
CURRENT CHANNELS
VOLTAGE CHANNELS
The voltage outputs from the current transducers are connected
to the ADE7762 current channels, which are fully differential
voltage inputs. IAP, IBP, and ICP are the positive inputs for IAN,
IBN, and ICN, respectively.
The output of the line voltage transducer is connected to the
ADE7762 at this analog input. Voltage channels are a pseudo-
differential voltage input. VAP, VBP, and VCP are the positive
inputs with respect to VN.
The maximum peak differential signal on the current channel
should be less than ±500 mV (353 mV rms for a pure sinusoidal
signal) for the specified operation.
The maximum peak differential signal on the voltage channel is
±500 mV (353 mV rms for a pure sinusoidal signal) for speci-
fied operation.
IAP–IAN
Figure 19 illustrates the maximum signal levels that can be
connected to the ADE7762 voltage channels.
+500mV
IAP
IAN
VAP–VN
DIFFERENTIAL INPUT
IA
±500mV MAX PEAK
+500mV
V
CM
VA P
VN
V
COMMON-MODE
CM
±25mV MAX
DIFFERENTIAL INPUT
VA
±500mV MAX PEAK
AGND
–500mV
V
CM
VCM
COMMON-MODE
±25mV MAX
Figure 18. Maximum Signal Levels, Current Channel
AGND
–500mV
The maximum signal levels on IAP and IAN are shown in
Figure 18. The maximum differential voltage between IAP and
IAN is ±500 mV. The differential voltage signal on the inputs
must be referenced to a common mode, for example, AGND.
The maximum common-mode signal shown in Figure 18 is
±25 mV.
Figure 19. Maximum Signal Levels, Voltage Channel
Voltage channels must be driven from a common-mode voltage,
that is, the differential voltage signal on the input must be refer-
enced to a common mode (usually AGND). The analog inputs
of the ADE7762 can be driven with common-mode voltages of
up to 25 mV with respect to AGND. However, best results are
achieved using a common mode equal to AGND.
Rev. PrB | Page 1± of 28
ADE7762
Preliminary Technical Data
TYPICAL CONNECTION DIAGRAMS
CURRENT CHANNEL CONNECTION
METER CONNECTIONS
Figure 20 shows a typical connection diagram for the current
channel (IA). A current transformer (CT) is the current trans-
ducer selected for this example. Notice the common-mode
voltage for the current channel is AGND and is derived by
center tapping the burden resistor to AGND. This provides the
complementary analog input signals for IAP and IAN. The CT
turns ratio and burden resistor Rb are selected to give a peak
differential voltage of ±500 mV at maximum load.
In 3-phase service, two main power distribution services exist:
3-phase 4-wire or 3-phase 3-wire. The additional wire in the
3-phase 4-wire arrangement is the neutral wire. The voltage
lines have a phase difference of ±120° (±2±/3 radians) between
each other (see Equation 6).
VA
VB
(
t
)
)
= 2 ×VA × cos
ωlt
)
2π
3
⎛
⎞
⎟
⎠
(
t
= 2 ×V × cos ω t +
(6)
⎜
B
l
⎝
In theory it is better to center tap Rb; however, this requires
very careful attention to the layout and matching of the resistors
to ensure that the channels have the same resistance. A single
resistor may be more practical and is a valid design choice.
4π
3
⎛
⎝
⎞
⎟
⎠
VC (t)
= 2 ×V × cos ω t +
⎜
C
l
where VA, VB, and VC represent the voltage rms values of the
different phases.
Rf
IAP
IAN
CT
The current inputs are represented by
Cf
Cf
±500mV
Rb
I A
IB
(
t
)
)
= 2 I A ×cos
ωlt + φA
)
2π
3
⎧
⎫
⎬
⎭
IP
PHASE NEUTRAL
Rf
(
t
= 2 IB ×cos ω t +
+ φB
(7)
⎨
l
⎩
4π
3
⎧
⎩
⎫
⎬
⎭
Figure 20. Typical Connection for Current Channels
IC
(
t
)
= 2 IC ×cos ω t +
+ φC
⎨
l
VOLTAGE CHANNELS CONNECTION
where:
Figure 21 shows two typical connections for the voltage chan-
nel. The first option uses a potential transformer (PT) to pro-
vide complete isolation from the main voltage. In the second
option, the ADE7762 is biased around the neutral wire, and a
resistor divider is used to provide a voltage signal proportional
to the line voltage. Adjusting the ratio of Ra, Rb, and VR is a
convenient way of carrying out a gain calibration on the meter.
VR can be implemented using either a potentiometer or a
binary weighted series of resistors. Either configuration works,
however, the potentiometer is subject to noise over time. Two
fixed value resistors can be used in place of VR to minimize the
noise.
IA, IB, and IC represent the rms value of the current of each
phase.
φA, φB, and φC represent the phase difference of the current and
voltage channel of each phase.
The instantaneous powers can then be calculated as follows:
PA(t) = VA(t) × IA(t)
PB(t) = VB(t) × IB(t)
PC(t) = VC(t) × IC(t)
Then:
PA
(
t
)
)
= VA × IA × cos
φA
)
− VA × IA ×cos
2ωlt + φA
4π
3
(8)
⎛
⎞
⎟
⎠
PB
(
t
= VB × IB × cos
(
φB
)
)
− VB × IB ×cos 2ω t +
+ φB
⎜
⎝
l
VAP
VN
Rf
PT
Cf
Cf
8π
3
⎛
⎞
⎟
⎠
PC
(
t
)
= VC × IC × cos
(
φC
− VC × IC ×cos 2ω t +
+ φC
±500mV
⎜
l
⎝
Rf
As shown in Equation 8, in the ADE7762, the active power
AGND
calculation per phase is made when current and voltage inputs
of one phase are connected to the same channel (A, B, or C).
Then the summation of each individual active power calcula-
tion gives the total active power information, P(t) = PA(t) +
PB(t) + PC(t).
PHASE NEUTRAL
Cf
Ra
*
Rb
*
VAP
VN
±500mV
VR
*
Rf
Cf
PHASE NEUTRAL
Ra >> Rf + VR; Rb + VR = Rf
*
*
Figure 21. Typical Connections for Voltage Channels
Rev. PrB | Page 16 of 28
Preliminary Technical Data
ADE7762
Figure 22 shows the connections of the ADE7762 analog inputs
with the power lines in a 3-phase 3-wire delta service.
Figure 23 shows the connections of the ADE7762 analog inputs
with the power lines in a 3-phase 4-wire Wye service.
Cf
Cf
Ra*
Ra*
Rb*
Rb*
VAP
IAP
VR*
VAP
VR*
IAP
IAN
Rb*
CT
IAN
Rb*
CT
ANTIALIASING
FILTERS
ANTIALIASING
FILTERS
CT
PHASE A
PHASE A
SOURCE
Cf
ANTIALIASING
FILTERS
Ra*
PHASE B
PHASE C
PHASE C
Rb*
Rb*
IBP
IBN
VBP
LOAD
SOURCE
PHASE B
VN
Rf
Cf
VR*
CT
CT
ANTIALIASING
FILTERS
ANTIALIASING
FILTERS
Cf
Ra*
Rb*
Rb*
Cf
IBP
IBN
Ra*
Rb*
ICP
LOAD
ICN
Rb*
VR*
VCP
VR*
VBP
Rf
Ra >> Rf + VR; Rb + VR = Rf
*
*
VN
Figure 22. 3-Phase 3-Wire Meter Connection with ADE7762
Ra >> Rf + VR; Rb + VR = Rf
*
*
CF
Figure 23. 3-Phase 4-Wire Meter Connection with ADE7762
Note that only two current inputs and two voltage inputs of the
ADE7762 are used in this case. The active power calculated by
the ADE7762 does not depend on the selected channels.
Rev. PrB | Page 17 of 28
ADE7762
Preliminary Technical Data
POWER SUPPLY MONITOR
The ADE7762 contains an on-chip power supply monitor. The
power supply (VDD) is monitored continuously by the ADE7762.
At power up, when the supply is less than 4V ±2ꢀ and VREF is less
than 1.9 V (typ), the outputs of the ADE7762 are inactive and the
data path is held in reset. Once VDD is greater than 4V ±2ꢀ and
VREF is greater than 1.9 V (typ), the chip is active and energy
accumulation begins. At power-down, when VDD falls below 4 V
or VREF falls below 1.9 V (typ), the data path is again held in reset.
This implementation ensures correct device operation at power-
up and at power-down. The power supply monitor has built-in
hysteresis and filtering. This gives a high degree of immunity to
false triggering due to noisy supplies.
V
DD
5V
4V
V
REF
2.4V
1.9V
0V
INTERNAL
RESET
INACTIVE
ACTIVE
INACTIVE
The power supply and decoupling for the part should be such
that the ripple at VDD does not exceed ±5ꢀ as specified for
normal operation.
Figure 24. On-Chip Power Supply Monitor
Rev. PrB | Page 18 of 28
Preliminary Technical Data
PHASE MONITOR
ADE7762
Phase Sequence Error
The ADE7762 has phase monitoring functions to detect phase
dropout, phase sequence error, and reverse polarity using four
pins. Phase dropout has the highest priority, and reverse
polarity has lowest priority. If a phase dropout occurs, phase
sequence error indication is disabled until all three phases are
above the phase dropout level (see the Phase Dropout Error
section). Because the dropout detection level is not set to zero, a
phase can have some small voltage during phase dropout
condition. Therefore, reverse polarity is still indicated on that
phase if the proper conditions occur.
The ADE7762 detects the zero crossing of each phase. A phase
sequence error occurs when the sequence A>B>C>A> … is vio-
lated. If a phase sequence error occurs, the Phase Seq/Drop LEDs
blink at 1 Hz (see Figure 26).
Phase sequence error and REVP can be displayed simultaneously.
The REVP LEDs continue to indicate reverse polarity if the proper
conditions exist. For example, if the phase sequence becomes
A>C>B>A… and phase B has negative active energy accumulated,
then the REVP LED for phase B is on solid and all of the Phase
Seq/Drop LEDs would be blinking at 1 Hz. The delay in indicating
the phase sequence error with blinking LEDs is approximately
150 ms from the time that a phase sequence error occurs.
The phase monitor circuit functions by multiplexing signals onto
the four pins. The four multiplexed pins are LED_CTRL, LED_A,
LED_B, and LED_C. Two LEDs can be connected to each pin as
shown in Figure 25. When LED_CTRL is high, LED_A would be
low to turn on an LED and indicate a phase drop condition on
Phase A. When LED_CTRL is low, LED_A is high to indicate a
reverse polarity (REVP) condition on phase A. Phase sequence
error is indicated by blinking the Phase Seq/Drop LEDs.
B = –120°
C = +120°
80% FS
A = 0°
VOLTAGE
WAVEFORMS
LED_CTRL switches at a rate of 131 kHz so that both the Phase
Seq/Drop LEDs and REVP LEDs can appear to be on simultane-
ously, which allows indication of phase dropout and REVP at the
same time. For the timing diagram, see Figure 3.
RISING EDGE
ZERO
A
B
A
B
C
C
CROSSINGS
PHASE SEQ/DROP LEDS ARE OFF.
C = –120°
B = +120°
80% FS
LED_CTRL
PHASE
SEQ/DROP
A = 0°
REVP
PHASE
SEQ/DROP
VOLTAGE
WAVEFORMS
LED_A
R
LOAD
REVP
PHASE
SEQ/DROP
LED_B
LED_C
R
LOAD
RISING EDGE
ZERO
CROSSINGS
A
C
A
C
B
B
REVP
PHASE SEQ/DROP LEDS ARE BLINKING AT 1Hz.
R
LOAD
C = –120°
Figure 25. Phase Monitor Circuit
80% FS
20% FS
A = 0°
Phase Dropout Error
B = +120°
The ADE7762 indicates a phase drop condition when there is
low voltage signal or no voltage signal on a phase. The phase
dropout condition occurs when the amplitude of the phase
drops below 20ꢀ of full-scale analog input voltage or when a
zero crossing is not followed by another zero crossing on that
phase for 150 ms. When this occurs, a phase dropout signal is
generated and the Phase Seq/Drop LED is turned on for the
missing phase. The delay between the phase drop condition
occurring at the analog inputs and indication of the condition
on the LED outputs is approximately 150 ms. During a phase
dropout condition, energy continues to accumulate on the
dropped channel, as well as the other channels, and phase
sequence error indication is disabled. The Phase Seq/Drop LED
for the dropped phase is turned off when the zero crossings
return for more than 150 ms and there is more than 20ꢀ of full-
scale input voltage on the voltage input of that phase.
VOLTAGE
WAVEFORMS
RISING EDGE
ZERO
CROSSINGS
A
B
A
B
C
C
PHASE SEQ/DROP LED FOR PHASE B IS ON.
Figure 26. Phase Sequence Detection
Reverse Polarity Error
When reverse power is detected on any phase, the
corresponding REVP LED turns on for that phase. For example,
if the power for phase A is negative, the REVP LED connected
to LED_A turns on. The indication of REVP on the LED_A,
LED_B, or LED_C pins is nearly instantaneous. As soon as the
input to the ADCs changes and the power is calculated such
that there is a reverse power condition on any phase, the
appropriate LED is turned on.
Rev. PrB | Page 1ꢀ of 28
ADE7762
Preliminary Technical Data
HPF AND OFFSET EFFECTS
Figure 27 shows the effect of offsets on the active power
calculation. An offset on the current channel and voltage
channel contributes a dc component after multiplication as
shown in Figure 27. Since this dc component is extracted by the
LPF and is used to generate the active power information for
each phase, the offsets can contribute a constant error to the
total active power calculation. The HPF in the current channels
avoids this problem easily. By removing the offset from at least
one channel, no error component can be generated at dc by the
multiplication. Error terms at cos(ωt) are removed by the LPF
and the digital-to-frequency conversion (see the Digital-to-
Frequency Conversion) section.
The ADE7762 is phase compensated up to 1 kHz as shown. This
ensures correct active harmonic power calculation even at low
power factors.
{
V cos
V × I
(
ωt
)
+VOS
}
×
{
I cos
(
ωt
)
+ IOS
ωt
}
=
(9)
+ IOS ×V cos ωt
) ( )
+ VOS × IOS + VOS × I cos
(
2
V × I
+
× cos 2ωt
( )
Figure 28. Phase Error between Channels (0 Hz to 1 kHz)
2
DC COMPONENT (INCLUDING ERRORTERM)
IS EXTRACTED BYTHE LPF FOR REAL
POWER CALCULATION
V
× I
OS
OS
V × I
2
I
× V
OS
V
× I
OS
2ω
FREQUENCY – RAD/S
ω
0
Figure 27. Effect of Channel Offset on the Active Power Calculation
The HPF in the current channels has an associated phase response
that is compensated for on-chip. Figure 28 and Figure 29 show the
phase error between channels with the compensation network.
Figure 29. Phase Error Between Channels (40 Hz to 70 Hz)
Rev. PrB | Page 25 of 28
Preliminary Technical Data
ADE7762
DIGITAL-TO-FREQUENCY CONVERSION
After multiplication, the digital output of the low-pass filter
contains the active power information of each phase. However,
since this LPF is not an ideal brick wall filter implementation, the
output signal also contains attenuated components at the line
frequency and its harmonics, that is, cos(hωt), where h = 1, 2, 3 ….
The average value of a sinusoidal signal is zero. Thus, the
frequency generated by the ADE7762 is proportional to the
average active power. Figure 30 shows the digital-to-frequency
conversion for steady load conditions, that is, constant voltage
and current.
The magnitude response of the filter is given by
1
The frequency output CF varies over time, even under steady load
conditions (see Figure 30). This frequency variation is primarily
due to the cos(2ωt) components in the instantaneous active power
signal. The output frequency on CF can be up to 160× higher than
the frequency on F1 and F2. The higher output frequency is
generated by accumulating the instantaneous active power signal
over a much shorter time, while converting it to a frequency. This
shorter accumulation period means less averaging of the cos(2ωt)
component. Therefore, some of this instantaneous power signal
passes through the digital-to-frequency conversion.
|H
(
)
f | =
(10)
2
f
⎧ ⎫
1 +
⎨ ⎬
8
⎩ ⎭
where the −3 dB cutoff frequency of the low-pass filter is 8 Hz.
For a line frequency of 50 Hz, this would give an attenuation of
the 2ω(100 Hz) component of approximately −22 dB. The
dominating harmonic is twice the line frequency, that is,
cos(2ωt), due to the instantaneous power signal. Figure 30
shows the instantaneous active power signal at the output of the
CF, which still contains a significant amount of instantaneous
power information, cos(2ωt).
Where CF is used for calibration purposes, the frequency counter
should average the frequency to remove the ripple and obtain a
stable frequency. If CF is being used to measure energy, for
example, in a microprocessor-based application, the CF output
should also be averaged to calculate power. Because the outputs F1
and F2 operate at a much lower frequency, significant averaging of
the instantaneous active power signal is carried out. The result is a
greatly attenuated sinusoidal content and a virtually ripple-free
frequency output on F1 and F2, which are used to measure energy
in a stepper-motor based meter.
This signal is then passed to the digital-to-frequency converter
where it is integrated (accumulated) over time to produce an
output frequency. This accumulation of the signal suppresses or
averages out any non-dc component in the instantaneous active
power signal.
ABS
VA
LPF
MULTIPLIER
IA
|X|
|X|
F1
DIGITAL-TO-
FREQUENCY
F1
Σ
Σ
VB
MULTIPLIER
F2
LPF
TIME
CF
Σ
DIGITAL-TO-
FREQUENCY
IB
CF
VC
TIME
LPF
MULTIPLIER
IC
|X|
V× I
2
LPF TO EXTRACT
REAL POWER
(DC TERM)
cos(2ωt)
ATTENUATED BY LPF
2ω
FREQUENCY – RAD/S
ω
0
INSTANTANEOUS REAL POWER SIGNAL
(FREQUENCY DOMAIN)
Figure 30. Active Power-to-Frequency Conversion
Rev. PrB | Page 21 of 28
ADE7762
Preliminary Technical Data
MODE SELECTION OF THE SUM OF THE THREE
ACTIVE ENERGIES
POWER MEASUREMENT CONSIDERATIONS
Calculating and displaying power information always have some
associated ripple that depends on the integration period used in the
MCU to determine average power as well as the load. For example,
at light loads, the output frequency can be 10 Hz. With an integra-
tion period of two seconds, only about 20 pulses are counted. The
possibility of missing one pulse always exists since the ADE7762
output frequency is running asynchronously to the MCU timer.
This would result in a 1-in-20 or 5ꢀ error in the power measure-
ment. To remedy this, an appropriate integration time should be
considered to achieve the desired accuracy.
The ADE7762 can be configured to execute the arithmetic sum
of the three active energies, Wh = WhΦA + Wh B + Wh , or the
C
Φ
Φ
sum of the absolute value of these energies, Wh = |Wh | +
A
Φ
|Wh | + |Wh |. The selection between the two modes can be
B
C
Φ
Φ
made by setting the
pin. Logic high and logic low applied
ABS
on the
pin correspond to the arithmetic sum and the sum
ABS
of absolute values, respectively.
When the sum of the absolute values is selected, the active
energy from each phase is always counted positive in the total
active energy. It is particularly useful in 3-phase 4-wire
instillation where the sign of the active power should always be
the same. If the meter is misconnected to the power lines, that
is, CT connected in the wrong direction then the total active
energy recorded without this solution can be reduced by two-
thirds.
The sum of the absolute values assures that the active energy
recorded represents the actual active energy delivered. In this
mode, the reverse power pin still detects when negative power is
present on any of the three phase inputs, but energy continues
to accumulate regardless of the sign.
Rev. PrB | Page 22 of 28
Preliminary Technical Data
ADE7762
TRANSFER FUNCTION
FREQUENCY OUTPUTS F1 AND F2
Example 1
Thus, if full-scale differential dc voltages of +500 mV are
applied to VA, VB, VC, IA, IB, and IC, respectively (500 mV is
the maximum differential voltage that can be connected to
current and voltage channels), then the expected output
frequency is calculated as follows:
The ADE7762 calculates the product of six voltage signals (on
current channel and voltage channel) and then low-pass filters
this product to extract active power information. This active
power information is then converted to a frequency. The
frequency information is output on F1 and F2 in the form of
active high pulses. The pulse rate at these outputs is relatively
low, for example, 2.01 Hz maximum for ac signals with SCF =
S0 = 0; S1 = 1 (see Table 6). This means that the frequency at
these outputs is generated from active power information
accumulated over a relatively long period. The result is an
output frequency that is proportional to the average active
power. The averaging of the active power signal is implicit to
the digital-to-frequency conversion. The output frequency or
pulse rate is related to the input voltage signals by the following
equation:
F1–7 = 0.58 Hz, SCF = S0 = S1 = 1
VAN = VBN = VCN = IA = IB = IC
= 500 mV dc = 0.5 V(rms of dc = dc)
VREF = 2.4 V (nominal reference value)
Note that if the on-chip reference is used, actual output
frequencies can vary from device to device due to reference
tolerance of ±8ꢀ.
6.181× 0.5× 0.5 × 0.58
Freq = 3×
= 0.467 Hz
(12)
2
2.4
6.181×
(V
× I + V × I + V × I
)
× F
AN
A
BN
B
CN
C 1−7
Example 2
Freq =
(11)
2
V
REF
In this example, with ac voltages of ±500 mV peak applied to
the voltage channels and current channels, the expected output
frequency is calculated as follows:
where:
Freq = output frequency on F1 and F2 (Hz).
VAN, BN, and VCN = differential rms voltage signal on voltage
channels (V).
IA, IB, and IC = differential rms voltage signal on current channels
(V).
F1−7 = 0.58 Hz, SCF = S0 = S1 =1
VAN = VBN = VCN = IA = IB = IC
V
(13)
0.5
2
= 500 mV peak AC =
VREF = 2.4 V
Vrms
V
REF = the reference voltage (2.4 V ±8ꢀ) (V).
(
nominal reference value
)
F1–7 = one of seven possible frequencies selected by using the
Note that if the on-chip reference is used, actual output fre-
quencies can vary from device to device due to reference
tolerance of ±8ꢀ.
logic inputs SCF, S0, and S1 (see Table 5).
Table 5. F1–7 Frequency Selection1
SCF
S1
S0
F1–7 (Hz)
2.35
6.181× 0.5× 0.5× 0.58
Freq = 3×
= 0.233 Hz
(14)
2
5
5
5
2 × 2 × 2.4
1
5
5
4.61
As can be seen from these two example calculations, the maximum
output frequency for ac inputs is always half of that for dc input
signals. The maximum frequency also depends on the number of
phases connected to the ADE7762. In a 3-phase 3-wire delta ser-
vice, the maximum output frequency is different from the maxi-
mum output frequency in a 3-phase 4-wire Wye service. The
reason is that there are only two phases connected to the analog
inputs, but also that in a delta service, the current channel input
and voltage channel input of the same phase are not in phase in
normal operation.
5
1
5
1
5
1
5
5
1
1
1
1
1
1
5
5
1
1
1.1±
4.61
±.22
1.1±
5.±8
5.±8
1 F1–7 is a fraction of the master clock and therefore varies if the specified
CLKIN frequency is altered.
Rev. PrB | Page 23 of 28
ADE7762
Preliminary Technical Data
Example 3
Note that if the on-chip reference is used, actual output
frequencies can vary from device to device due to reference
tolerance of ±8ꢀ.
In this example, the ADE7762 is connected to a 3-phase 3-wire
delta service as shown in Figure 22. The total active energy
calculation processed in the ADE7762 can be expressed as
6.181× 0.5 × 0.5 × 0.60
3
Freq = 2 ×
×
= 0.139 Hz
(20)
2
2
2 × 2 × 2.4
Total Active Power = (VA – VC) × IA + (VB – VC) × IB
Table 6 shows a complete listing of all maximum output
frequencies when using all three channel inputs.
where:
VA, VB, and VC represent the voltage on phase A, phase B, and
phase C, respectively.
IA and IB represent the current on phase A and phase B,
respectively.
Table 6: Maximum Output Frequency on F1 and F2
Maximum
Maximum
Frequency for AC
Inputs (Hz)
Frequency for DC
Inputs (Hz)
SCF
5
S1
5
S0
5
5.ꢀ3
1.86
5.46
1.86
2.15
5.46
5.23
5.23
1.8±
3.71
5.ꢀ3
3.71
4.25
5.ꢀ3
5.47
5.47
As the voltage and current inputs respect Equations 5 and 6, the
total active power (P) is
1
5
1
5
1
5
1
5
1
5
5
1
1
1
1
1
1
5
5
1
1
P =
(
VA −VC
)
IAP − IAN
+
VB −VC
×
⎛
IBP − IBN
4π
3
⎛
⎞
⎞
⎟
⎠
P = 2 ×VA × cos
(
ωlt
)
−
2 ×VC × cos ω t +
⎜
⎟
⎠
⎜
l
⎝
⎝
(15)
×
+
2 × I A ×cos
(
ωlt
)
2π
4π
3
⎛
⎜
⎞
⎟
⎛
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎟
⎠
2 ×VB ×cos ω t +
− v 2 ×V × cos ω t +
⎜
⎜
C
l
l
3
⎝
⎠
2π
3
⎛
⎝
⎞
×
2 × IB × cos ω t +
⎜
l
⎟
⎠
FREQUENCY OUTPUT CF
The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to 64×
the pulse rate on F1 and F2. Table 7 shows how the two
frequencies are related, depending on the states of the logic
inputs S0, S1, and SCF. Because of its relatively high pulse rate,
the frequency at this logic output is proportional to the
instantaneous active power. As is the case with F1 and F2, the
frequency is derived from the output of the low-pass filter after
multiplication. However, since the output frequency is high, this
active power information is accumulated over a much shorter
time. Thus, less averaging is carried out in the digital-to-
frequency conversion. The CF output is much more responsive
to power fluctuations with much less averaging of the active
power signal (see Figure 16).
For simplification, assume that ΦA = ΦB = ΦC = 0 and
VA = VB = VC = V. The preceding equation becomes
2π
3
2π
3
⎛
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎟
⎠
P = 2×V ×I A ×sin
×sin ω t +
×cos
(ωlt
)
⎜
⎜
l
(16)
(17)
π
3
2π
3
⎛
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎟
⎠
+2×V ×IB ×sin
×sin(ωl t + π
)
×cos ω t +
⎜
⎜
l
P then becomes
2π
3
2π
3
⎛
⎞
⎟
⎛
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎠
P = VAN × I A × sin
+ sin 2ω t +
⎜
l
⎜
⎜
⎟
⎝
⎠
π
⎞
π
3
⎛
⎞
⎟
⎛
⎝
⎛
⎝
⎞
⎟
⎠
+VBN × I B × sin
+ sin 2ω t +
⎜
l
⎜
⎜
⎟
3
⎠
⎝
⎠
where:
Table 7. Maximum Output Frequency on CF
VAN = V × sin(2±/3).
VBN = V × sin(±/3).
SCF
S1 S0 F1–7 (Hz)
CF Maximum for AC Signals (Hz)
16 × F1, F2 = 14.88
8 × F1, F2 = 14.88
5
1
5
5
5
5
1
1
1
1
5
5
1
1
5
5
1
1
2.3
As the LPF on each channel eliminates the 2ωl component of
the equation, the active power measured by the ADE7762 is
4.61
1.1±
4.61
±.22
1.1±
5.±8
5.±8
5
1
5
1
32 × F1, F2 = 14.88
16 × F1, F2 = 2ꢀ.76
165 × F1, F2 = 336
16 × F1, F2 = 7.36
3
2
3
2
P = VAN × IA
×
+VBN × IB ×
(18)
If full-scale ac voltage of ±500 mV peak is applied to the voltage
channels and current channels, the expected output frequency
is calculated as follows:
5
32 × F1, F2 = 7.36
1
16 × F1, F2 = 3.68
F
= 0.60Hz, SCF = S0 = S1 = 1
1−7
0.5
2
VAN = VBN = IA = IB = IC = 500 mVpeak ac =
Vrms
(19)
VCN = IC = 0
VREF = 2.4V nominal reference value
Rev. PrB | Page 24 of 28
Preliminary Technical Data
ADE7762
SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION
As shown in Table 5, the user can select one of seven
frequencies. This frequency selection determines the maximum
frequency on F1 and F2. These outputs are intended to be used
to drive the energy register (electromechanical or other). Since
seven different output frequencies can be selected, the available
frequency selection has been optimized for a 3-phase 4-wire
service with a meter constant of 100 imp/kWhr and a
maximum current of between 10 A and 100 A. Table 8 shows
the output frequency for several maximum currents (IMAX) with
a line voltage of 220 V (phase neutral). In all cases, the meter
constant is 100 imp/kWhr.
When selecting a suitable F1–7 frequency for a meter design, the
frequency output at IMAX (maximum load) with a 100 imp/kWhr
meter constant should be compared with Column 5 of Table 9. The
frequency that is closest in Table 9 determines the best choice of
frequency (F1–7). For example, if a 3-phase 4-wire Wye meter with a
25 A maximum current is being designed, the output frequency on
F1 and F2 with a 100 imp/kWhr meter constant is 0.46 Hz at 25 A
and 220 V (see Table 8). Looking at Table 9, the closest frequency to
0.46 Hz in Column 5 is 0.53 Hz. Therefore, F1–7 = 5.22 Hz is
selected for this design.
FREQUENCY OUTPUTS
Table 8. F1 and F2 Frequency at 100 imp/kWhr
Figure 2 shows a timing diagram for the various frequency
outputs. The outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or electro-
mechanical impulse counter. The F1 and F2 outputs provide
two alternating high going pulses. The pulse width (t1) is set at
120 ms, and the time between the rising edges of F1 and F2 (t3)
is approximately half the period of F1 (t2). If, however, the
period of F1 and F2 falls below 550 ms (1.81 Hz), the pulse
width of F1 and F2 is set to half of their period. The maximum
output frequencies for F1 and F2 are shown in Table 6.
IMAX (A)
F1 and F2 (Hz)
15
2±
45
65
85
155
5.18
5.46
5.73
1.15
1.47
1.83
The F1–7 frequencies allow complete coverage of this range of
output frequencies on F1 and F2. When designing an energy
meter, the nominal design voltage on the voltage channels
should be set to half scale to allow for calibration of the meter
constant. The current channel should also be no more than half
scale when the meter sees maximum load. This allows
overcurrent signals and signals with high crest factors to be
accommodated. Table 9 shows the output frequency on F1 and
F2 when all six analog inputs are half scale.
The high frequency CF output is intended to be used for
communications and calibration purposes. CF produces a 90 ms-
wide active high pulse (t4) at a frequency proportional to active
power. The CF output frequencies are given in Table 7. As in the
case of F1 and F2, if the period of CF (t5) falls below 190 ms, the CF
pulse width is set to half the period. For example, if the CF
frequency is 20 Hz, the CF pulse width is 25 ms.
Table 9. F1 and F2 Frequency with Half-Scale AC Inputs
Frequency on F1 and F2
F1–7 (Hz) (Half-Scale AC Inputs) (Hz)
NO LOAD THRESHOLD
SCF S1 S0
The ADE7762 includes no load threshold and start-up current
circuitry features that eliminate any creep effects in the meter.
The circuit is designed to issue a minimum output frequency.
Any load generating a frequency lower than this minimum
output frequency does not cause a pulse to be issued on F1, F2, or
CF. The no-load threshold is determined by the sum of all phases.
The minimum output frequency is given as 0.0075ꢀ of the full-
scale output frequency for each of the F1–7 frequency selections, or
approximately 0.0029ꢀ of the F1–7 frequency (see Table 10). For
example, for an energy meter with a 100 imp/kWhr meter
constant using F1–7 (4.61 Hz), the minimum output frequency at
F1 or F2 would be 13.35 × 10–5 Hz. This would be 2.13 × 10–3 Hz
at CF (16 × F1 Hz). In this example, the no load threshold would
be equivalent to 4.8 W of load or a start-up current of 20.03 mA
at 240 V.
5
1
5
1
5
1
5
1
5
5
5
5
1
1
1
1
5
5
1
1
5
5
1
1
2.3
5.23
5.46
5.12
5.46
5.±3
5.12
5.56
5.56
4.61
1.1±
4.61
±.22
1.1±
5.±8
5.±8
Rev. PrB | Page 2± of 28
ADE7762
Preliminary Technical Data
Table 10. CF, F1, and F2 Minimum Frequency at No Load
Threshold
SCF S1 S0 F1, F2 Minimum (Hz) CF Minimum (Hz)
NEGATIVE POWER INFORMATION
The ADE7762 detects when total power, calculated as the sum
of the three phases, is negative. This mechanism can detect an
incorrect connection of the meter or generation of negative
active energy. The REVP pin output goes active high when
negative power is detected on the sum of the three phase inputs.
If positive active power is detected on the sum of three phases,
then REVP pin output is low.
5
1
5
1
5
1
5
1
5
5
5
5
1
1
1
1
5
5
1
1
5
5
1
1
6.ꢀ4E − 5±
1.3ꢀE − 54
3.47E − 5±
1.3ꢀE − 54
1.±8E − 54
3.47E − 5±
1.7±E − 5±
1.7±E − 5±
1.11E − 53
1.11E − 53
1.11E − 53
2.23E − 53
2.±2E − 52
±.±±E − 54
±.65E − 54
2.85E − 54
The REVP pin output changes state at the same time as a pulse
is issued on CF. If the sum of the phases measure negative
power, then the REVP pin output stays high until the sum of the
phases measures positive power.
Rev. PrB | Page 26 of 28
Preliminary Technical Data
OUTLINE DIMENSIONS
ADE7762
18.10 (0.7126)
17.70 (0.6969)
28
1
15
14
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
0.25 (0.0098)
× 45°
0.30 (0.0118)
0.10 (0.0039)
8°
0°
1.27 (0.0500)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
BSC
COMPLIANT TO JEDEC STANDARDS MS-013-AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADE7762ARWZ1
ADE7762ARWZ-RL1
ADE7762ARW
Package Description
Package Option
28-Lead Standard Small Outline Package [SOIC_W]
28-Lead Standard Small Outline Package [SOIC_W]
28-Lead Standard Small Outline Package [SOIC_W]
28-Lead Standard Small Outline Package [SOIC_W]
ADE7762 Evaluation Board
RW-282
RW-28 on 13" Reels
RW-28
RW-28 on 13" Reels
ADE7762ARW-RL
EVAL-ADE7762EB
1 Z = Pb-free part.
2 RW = small outline wide body package in tubes.
Rev. PrB | Page 27 of 28
ADE7762
NOTES
Preliminary Technical Data
©
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05757-0-1/06(PrB)
Rev. PrB | Page 28 of 28
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