ADE7880_技术文档

Polyphase Multifunction Energy Metering IC

with Harmonic Monitoring

Data Sheet

ADE7880

FEATURES

GENERAL DESCRIPTION

Highly accurate; supports IEC 62053-21, IEC 62053-22,

IEC 62053-23, EN 50470-1, EN 50470-3, ANSI C12.20, and

IEEE1459 standards

Supports IEC 61000-4-7 Class I and Class II accuracy

specification

Compatible with 3-phase, 3- or 4-wire (delta or wye), and

other 3-phase services

Supplies rms, active, reactive and apparent powers, power

factor, THD, and harmonic distortion of all harmonics

within 2.8 kHz pass band on all phases

Supplies rms and harmonic distortions of all harmonics

within 2.8 kHz pass band on neutral current

Less than 1% error in harmonic current and voltage rms,

harmonic active and reactive powers over a dynamic

range of 2000 to 1 at T_A= 25°C

Supplies total (fundamental and harmonic) active and

apparent energy and fundamental active/reactive energy

on each phase and on the overall system

Less than 0.1% error in active and fundamental reactive

energy over a dynamic range of 1000 to 1 at T_A= 25°C

Less than 0.2% error in active and fundamental reactive

energy over a dynamic range of 5000 to 1 at T_A= 25°C

Less than 0.1% error in voltage and current rms over a

dynamic range of 1000 to 1 at T_A= 25°C

Battery supply input for missing neutral operation

Wide-supply voltage operation: 2.4 V to 3.7 V

Reference: 1.2 V (drift 10 ppm/°C typical) with external

overdrive capability

The ADE7880¹is high accuracy, 3-phase electrical energy

measurement IC with serial interfaces and three flexible pulse

outputs. The ADE7880 device incorporates second-order sigma-

delta (Σ-Δ) analog-to-digital converters (ADCs), a digital

integrator, reference circuitry, and all of the signal processing

required to perform the total (fundamental and harmonic) active,

and apparent energy measurements, rms calculations, as well as

fundamental-only active and reactive energy measurements. In

addition, the ADE7880 computes the rms of harmonics on the

phase and neutral currents and on the phase voltages, together

with the active, reactive and apparent powers, and the power

factor and harmonic distortion on each harmonic for all phases.

Total harmonic distortion (THD) is computed for all currents

and voltages. A fixed function digital signal processor (DSP)

executes this signal processing. The DSP program is stored in

the internal ROM memory.

The ADE7880 is suitable for measuring active, reactive, and

apparent energy in various 3-phase configurations, such as wye

or delta services with, both, three and four wires. The ADE7880

provides system calibration features for each phase, that is, rms

offset correction, phase calibration, and gain calibration. The

CF1, CF2, and CF3 logic outputs provide a wide choice of

power information: total active powers, apparent powers, or the

sum of the current rms values, and fundamental active and

reactive powers.

The ADE7880 contains waveform sample registers that allow

access to all ADC outputs. The devices also incorporate power

quality measurements, such as short duration low or high

voltage detections, short duration high current variations, line

voltage period measurement, and angles between phase voltages

and currents. Two serial interfaces, SPI and I²C, can be used to

communicate with the ADE7880. A dedicated high speed

interface, the high speed data capture (HSDC) port, can be used

in conjunction with I²C to provide access to the ADC outputs

and real-time power information. The ADE7880 also has two

40-lead lead frame chip scale package (LFCSP), Pb-free, pin-

for-pin compatible with ADE7854, ADE7858, ADE7868 and

ADE7878

APPLICATIONS

Energy metering systems

Power quality monitoring

Solar inverters

Process monitoring

Protective devices

IRQ0

IRQ1

interrupt request pins,

and , to indicate that an enabled

interrupt event has occurred. Three specially designed low power

modes ensure the continuity of energy accumulation when the

ADE7880 is in a tampering situation. The ADE7880 is available

in the 40-lead LFCSP, Pb-free package, pin-for-pin compatible

with ADE7854, ADE7858, ADE7868, and ADE7878 devices.

¹Patents Pending.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADE7880

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Changing Phase Voltage Data path.......................................... 30

Power Quality Measurements................................................... 31

Phase Compensation ................................................................. 36

Reference Circuit........................................................................ 38

Digital Signal Processor............................................................. 38

Root Mean Square Measurement............................................. 39

Active Power Calculation.......................................................... 43

Fundamental Reactive Power Calculation.............................. 49

Apparent Power Calculation..................................................... 53

Power Factor Calculation.......................................................... 55

Harmonics Calculations............................................................ 56

Waveform Sampling Mode ....................................................... 64

Energy-to-Frequency Conversion............................................ 64

No Load Condition.................................................................... 69

Checksum Register..................................................................... 71

Interrupts..................................................................................... 72

Serial Interfaces .......................................................................... 73

ADE7880 Quick Setup As Energy Meter................................ 80

ADE7880 Evaluation Board...................................................... 80

Die Version.................................................................................. 80

Silicon Anomaly ............................................................................. 81

ADE7880 Functionality Issues ................................................. 81

Functionality Issues.................................................................... 81

Section 1. ADE7880 Functionality Issues ............................... 82

Registers List ................................................................................... 83

Outline Dimensions..................................................................... 103

Ordering Guide ........................................................................ 103

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings.......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 13

Test Circuit ...................................................................................... 18

Terminology .................................................................................... 19

Power Management........................................................................ 20

PSM0—Normal Power Mode (All Parts)................................ 20

PSM1—Reduced Power Mode.................................................. 20

PSM2—Low Power Mode ......................................................... 20

PSM3—Sleep Mode (All Parts) ................................................ 21

Power-Up Procedure.................................................................. 23

Hardware Reset........................................................................... 24

Software Reset Functionality .................................................... 24

Theory of Operation ...................................................................... 25

Analog Inputs.............................................................................. 25

Analog-to-Digital Conversion.................................................. 25

Current Channel ADC............................................................... 26

di/dt Current Sensor and Digital Integrator............................... 28

Voltage Channel ADC ............................................................... 29

REVISION HISTORY

3/12—Rev. 0 to Rev. A

Changes to Figure 95...................................................................... 69

Changes to No Load Condition Section...................................... 69

Changes to Equation 53................................................................. 71

Changes to Figure 100 ................................................................... 74

Changes to Figure 101 and to Figure 102.................................... 75

Changes to SPI-Compatible Interface Section ........................... 76

Changes to HSDC Interface Section............................................ 78

Changes to Figure 109 and to Figure 110.................................... 80

Changes to Silicon Anomaly Section........................................... 81

Changes to Table 48 ....................................................................... 99

Changes to Table 52 ..................................................................... 101

Removed References to + N (Plus Noise) and changed VTHDN

to VTHD and ITHDN to ITHD.................................. Throughout

Changes to Reactive Energy Management Parameter in Table 1.... 4

Changes to Figure 6........................................................................ 11

Changes to Table 7.......................................................................... 12

Changes to Phase Compensation Section................................... 36

Changes to Equation 13................................................................. 39

Changes to Equation 33................................................................. 49

Changes to Fundamental Reactive Energy Calculation Section ... 51

Changes to Figure 80...................................................................... 55

Changes to Figure 85...................................................................... 62

Changes to Energy Registers and CF Outputs for Various

Accumulation Modes Section....................................................... 67

10/11—Revision 0: Initial Version

Rev. A | Page 2 of 104

Data Sheet

ADE7880

FUNCTIONAL BLOCK DIAGRAM

REF

RESET

4

IN/OUT VDD AGND

AVDD

24

DVDD DGND

17

26

25

5

6

AIRMSOS

POR

LDO

7

2

ADE7880

APGAIN

2

3

PM0

PM1

2

27

AIRMS

AVRMS

CLKIN

X

LPF

CLKOUT 28

1.2V

REF

X

HPFEN OF

CONFIG3

DIGITAL

INTEGRATOR

LPF

AIGAIN

CF1DEN

7

2

7

8

IAP

IAN

ADC

PGA1

HPF

AVRMSOS

33

34

35

CF1

DFC

:

HPFEN OF

CONFIG3

APGAIN

AWATTOS

APHCAL AVGAIN

CF2DEN

LPF

23

9

VAP

IBP

PHASE A,

PHASE B,

AND

PGA3

ADC

CF2/HREADY

CF3/HSCLK

:

AFWATTOS

AFVAROS

HPF

PHASE C

DATA

COMPUTATIONAL

BLOCK FOR

CF3DEN

PGA1

FUNDAMENTAL

ACTIVE AND

TOTAL/FUNDAMENTAL ACTIVE ENERGIES

FUNDAMENTAL REACTIVE ENERGY

APPARENT ENERGY

IBN 12

:

REACTIVE POWER

VOLTAGE CURRENT RMS

HARMONIC INFORMATION CALCULATION

FOR PHASE B

VBP 22

(SEE PHASE A FOR DETAILED DATA PATH)

ADC

COMPUTATIONAL

BLOCK FOR

29

32

36

IRQ0

2

HARMONIC

SPI/I C

13

14

ICP

ICN

INFORMATION ON

IRQ1

PGA1

ADC

TOTAL/FUNDAMENTAL ACTIVE ENERGIES

FUNDAMENTAL REACTIVE ENERGY

APPARENT ENERGY

PHASE A CURRENT

AND VOLTAGE

SCLK/SCL

VOLTAGE/CURRENT RMS

HARMONIC INFORMATION CALCULATION

FOR PHASE C

VCP 19

VN

(SEE PHASE A FOR DETAILED DATA PATH)

38 MOSI/SDA

37 MISO/HSD

39 SS/HSA

18

2

I C

COMPUTATIONAL BLOCK FOR HARMONIC

INFORMATION ON NEUTRAL CURRENT

HSDC

HPFEN OF

CONFIG3

DIGITAL

INTEGRATOR

NIRMSOS

NIGAIN

INP 15

INN

DIGITAL SIGNAL

PROCESSOR

2

ADC

PGA2

NIRMS

X

HPF

LPF

16

Figure 1. ADE7880 Functional Block Diagram

Rev. A | Page 3 of 104

ADE7880

Data Sheet

SPECIFICATIONS

VDD = 3.3 V 10ꢀ, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T_MINto T_MAX= −40°C to +85°C.

Table 1.

Parameter^{1, 2}

Min

Typ

Max

Unit

Test Conditions/Comments

ACTIVE ENERGY MEASUREMENT

Active Energy Measurement Error

(per Phase)

Total Active Energy

0.1

%

Over a dynamic range of 1000 to 1,

PGA = 1, 2, 4; integrator off, pf = 1, gain

compensation only

0.2

0.1

%

Over a dynamic range of 5000 to 1,

PGA = 1, 2, 4; integrator off, pf = 1

Over a dynamic range of 500 to 1,

PGA = 8, 16; integrator on, pf = 1, gain

compensation only

0.2

0.1

%

Over a dynamic range of 2000 to 1,

PGA = 8, 16; integrator on, pf = 1

Over a dynamic range of 1000 to 1,

PGA = 1, 2, 4; integrator off, pf = 1, gain

compensation only

Fundamental Active Energy

0.2

0.1

%

Over a dynamic range of 5000 to 1,

PGA = 1, 2, 4; integrator off, pf = 1

Over a dynamic range of 500 to 1,

PGA = 8, 16; integrator on, pf = 1, gain

compensation only

0.2

%

Over a dynamic range of 2000 to 1,

PGA = 8, 16; integrator on, pf = 1

Phase Error Between Channels

Power Factor (PF) = 0.8 Capacitive

PF = 0.5 Inductive

Line frequency = 45 Hz to 65 Hz, HPF on

Phase lead 37°

Phase lag 60°

0.05

Degrees

AC Power Supply Rejection

VDD = 3.3 V + 120 mV rms/120 Hz,

IPx = VPx = 100 mV rms

Output Frequency Variation

DC Power Supply Rejection

Output Frequency Variation

Total Active Energy Measurement

Bandwidth (−3 dB)

0.01

%

VDD = 3.3 V 330 mV dc

0.01

3.3

%

kHz

REACTIVE ENERGY MEASUREMENT

Reactive Energy Measurement Error

(per Phase)

Fundamental Reactive Energy

0.1

%

Over a dynamic range of 1000 to 1,

PGA = 1, 2, 4; integrator off, pf = 0, gain

compensation only

0.2

0.1

%

Over a dynamic range of 5000 to 1,

PGA = 1, 2, 4; integrator off, pf = 0

Over a dynamic range of 500 to 1,

PGA = 8, 16; integrator on, pf = 0, gain

compensation only

0.2

%

Over a dynamic range of 2000 to 1,

PGA = 8, 16; integrator on, pf = 0

Phase Error Between Channels

PF = 0.8 Capacitive

PF = 0.5 Inductive

Line frequency = 45 Hz to 65 Hz, HPF on

Phase lead 37°

Phase lag 60°

0.05

Degrees

AC Power Supply Rejection

VDD = 3.3 V + 120 mV rms/120 Hz,

IPx = VPx = 100 mV rms

Output Frequency Variation

DC Power Supply Rejection

0.01

%

VDD = 3.3 V 330 mV dc

Rev. A | Page 4 of 104

Data Sheet

ADE7880

Parameter^{1, 2}

Min

Typ

0.01

3.3

Max

Unit

%

kHz

Test Conditions/Comments

Output Frequency Variation

Fundamental Reactive Energy

Measurement Bandwidth (−3 dB)

RMS MEASUREMENTS

I RMS and V RMS Measurement

Bandwidth (−3 dB)

I RMS and V RMS Measurement Error

(PSM0 Mode)

3.3

0.1

kHz

%

Over a dynamic range of 1000 to 1,

PGA = 1

MEAN ABSOLUTE VALUE (MAV)

MEASUREMENT

I MAV Measurement Bandwidth

(PSM1 Mode)

I MAV Measurement Error (PSM1 Mode)

260

0.5

Hz

%

Over a dynamic range of 100 to 1,

PGA = 1, 2, 4, 8

HARMONIC MEASUREMENTS

Bandwidth (−3 dB)

No attenuation Pass Band

Fundamental Line Frequency f_L

3.3

2.8

kHz

Hz

45

66

Nominal voltages must have amplitudes

greater than 100 mV peak at voltage ADCs

Maximum Number of Harmonics³

⎡

⎢

⎣

⎤

⎥

⎦

2800

f_L

Absolute Maximum Number of

Harmonics

63

Harmonic RMS Measurement Error

1

%

Instantaneous reading accuracy over a

dynamic range of 1000 to 1 for harmonics

of frequencies within the pass band; after

the initial 750 ms settling time; PGA = 1

Accuracy over a dynamic range of 2000:1

for harmonics of frequencies within the

pass band; average of 10 readings at 128

ms update rate, after the initial 750 ms

setting time; PGA = 1

Harmonic Active/Reactive Power

Measurement Error

1

%

Instantaneous reading accuracy over a

dynamic range of 1000 to 1 for harmonics

of frequencies within the pass band; after

the initial 750 ms settling time; PGA = 1.

Accuracy over a dynamic range of 2000:1

for harmonics of frequencies within the

pass band; average of 5 readings at 128 ms

update rate, after the initial 750 ms setting

time; PGA = 1.

ANALOG INPUTS

Maximum Signal Levels

500

mV peak

Differential inputs between the following

pins: IAP and IAN, IBP and IBN, ICP and ICN;

single-ended inputs between the following

pins: VAP and VN, VBP and VN, VCP, and VN

Input Impedance (DC)

IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP,

and VCP Pins

VN Pin

490

170

kΩ

ADC Offset Error

−35

−2

mV

PGA = 1, uncalibrated error, see the

Terminology section. Scales inversely

proportional to the other PGA gains.

Gain Error

%

External 1.2 V reference

Rev. A | Page 5 of 104

ADE7880

Data Sheet

Parameter^{1, 2}

Min

Typ

Max

Unit

Test Conditions/Comments

WAVEFORM SAMPLING

Sampling CLKIN/2048, 16.384 MHz/2048 =

8 kSPS

Current and Voltage Channels

See the Waveform Sampling Mode

section

Signal-to-Noise Ratio, SNR

Signal-to-Noise-and-Distortion Ratio,

SINAD

72

dB

PGA = 1

Bandwidth (−3 dB)

3.3

0.3

kHz

TIME INTERVAL BETWEEN PHASES

Measurement Error

Degrees

Line frequency = 45 Hz to 65 Hz, HPF on

WTHR = VARTHR = VATHR = 3

If CF1, CF2, or CF3 frequency > 6.25 Hz and

CFDEN is even and > 1

CF1, CF2, CF3 PULSE OUTPUTS

Maximum Output Frequency

Duty Cycle

68.818

50

kHz

%

(1 + 1/CFDEN) ×

50

%

If CF1, CF2, or CF3 frequency > 6.25 Hz and

CFDEN is odd and > 1

Active Low Pulse Width

Jitter

80

0.04

ms

%

If CF1, CF2, or CF3 frequency < 6.25 Hz

For CF1, CF2, or CF3 frequency = 1 Hz and

nominal phase currents are larger than

10% of full scale

REFERENCE INPUT

REF_IN/OUTInput Voltage Range

1.1

1.3

10

V

Minimum = 1.2 V − 8%; maximum =

1.2 V + 8%

Input Capacitance

pF

ON-CHIP REFERENCE

Nominal 1.21 V at the REF_IN/OUTpin at

T_A= 25°C

PSM0 and PSM1 Modes

Reference Error

2

mV

Output Impedance

1

kΩ

Temperature Coefficient

CLKIN

10

50

ppm/°C

All specifications CLKIN of 16.384 MHz

Input Clock Frequency

Crystal Equivalent Series Resistance

CLKIN Load Capacitor⁴

CLKOUT Load Capacitor⁴

16.22

30

16.384

16.55

200

40

MHz

Ω

pF

20

40

pF

SS

,

LOGIC INPUTS—MOSI/SDA, SCLK/SCL,

RESET

, PM0, AND PM1

Input High Voltage, V_INH

Input Current, I_IN

Input Low Voltage, V_INL

Input Current, I_IN

2.4

V

nA

V

μA

pF

VDD = 3.3 V 10%

Input = VDD = 3.3 V

VDD = 3.3 V 10%

Input = 0, VDD = 3.3 V

82

0.8

−7.3

10

Input Capacitance, C_IN

IRQ0 IRQ1

, AND

VDD = 3.3 V 10%

LOGIC OUTPUTS—

MISO/HSD

,

Output High Voltage, V_OH

3.0

2.4

V

μA

V

I_SOURCE

800

0.4

2

Output Low Voltage, V_OL

I_SINK

CF1, CF2, CF3/HSCLK

Output High Voltage, V_OH

I_SOURCE

mA

V

μA

V

VDD = 3.3 V 10%

500

0.4

2

Output Low Voltage, V_OL

I_SINK

mA

Rev. A | Page 6 of 104

Data Sheet

ADE7880

Parameter^{1, 2}

POWER SUPPLY

PSM0 Mode

VDD Pin

Min

Typ

Max

Unit

Test Conditions/Comments

For specified performance

2.97

3.63

28

V

Minimum = 3.3 V − 10%; maximum =

3.3 V + 10%

I_DD

25

mA

PSM1 and PSM2 Modes

VDD Pin

I_DD

PSM1 Mode

PSM2 Mode

PSM3 Mode

VDD Pin

2.4

3.7

V

5.3

0.2

5.8

0.27

mA

For specified performance

3.7

6

V

ꢀA

I_DDin PSM3 Mode

1.8

¹See the Typical Performance Characteristics section.

²See the Terminology section for a definition of the parameters.

⎡

⎢

⎣

⎤

⎥

⎦

2800

3

means the whole number of the division.

f_L

⁴The CLKIN/CLKOUT load capacitors refer to the capacitors that are mounted between the CLKIN and CLKOUT pins of the ADE7880 and AGND. The capacitors should

be chosen based on the crystal manufacturer’s data sheet specification, and they must not have more than the maximum value specified in the table.

TIMING CHARACTERISTICS

VDD = 3.3 V 10ꢀ, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T_MINto T_MAX= −40°C to +85°C. Note that dual

function pin names are referenced by the relevant function only within the timing tables and diagrams (see the Pin Configuration and

Function Descriptions section for full pin mnemonics and descriptions).

Table 2. I²C-Compatible Interface Timing Parameter

Standard Mode

Fast Mode

Parameter

Symbol

f_SCL

t_HD;STA

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_R

Min

Max

Min

Max

Unit

kHz

ꢀs

μs

ns

μs

ns

SCL Clock Frequency

Hold Time (Repeated) Start Condition

Low Period of SCL Clock

High Period of SCL Clock

Set-Up Time for Repeated Start Condition

Data Hold Time

0

100

0

400

4.0

4.7

4.0

4.7

0

0.6

1.3

0.6

0

100

20

0.6

1.3

3.45

0.9

Data Setup Time

250

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

Setup Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

Pulse Width of Suppressed Spikes

1000

300

t_F

t_SU;STO

t_BUF

4.0

4.7

N/A¹

t_SP

50

¹N/A means not applicable.

Rev. A | Page 7 of 104

ADE7880

Data Sheet

SDA

t_BUF

t_SU;DAT

t_F

t_HD;STA

t_F

t_SP

t_F

t_LOW

SCLK

t_HD;STA

t_SU;STO

t_SU;STA

t_HD;DAT

t_HIGH

START

CONDITION

REPEATED START

CONDITION

STOP

START

CONDITION CONDITION

Figure 2. I²C-Compatible Interface Timing

Table 3. SPI Interface Timing Parameters

Parameter

Symbol

Min

Max

Unit

ns

ꢀs

ns

SS to SCLK Edge

t_SS

50

SCLK Period

SCLK Low Pulse Width

0.4

175

4000¹

t_SL

t_SH

SCLK High Pulse Width

Data Output Valid After SCLK Edge

Data Input Setup Time Before SCLK Edge

Data Input Hold Time After SCLK Edge

Data Output Fall Time

Data Output Rise Time

SCLK Rise Time

SCLK Fall Time

MISO Disable After SS Rising Edge

SS High After SCLK Edge

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

t_SF

t_DIS

t_SFS

100

5

20

200

0

¹Guaranteed by design.

SS

t_SS

t_SFS

SCLK

t_SL

t_SH

t_SF

t_SR

t_DAV

t_DIS

MSB

INTERMEDIATE BITS

LSB

MISO

t_DF

t_DR

INTERMEDIATE BITS

MSB IN

LSB IN

MOSI

t_DSU

t_DHD

Figure 3. SPI Interface Timing

Rev. A | Page 8 of 104

Data Sheet

ADE7880

Table 4. HSDC Interface Timing Parameter

Parameter

Symbol

Min

0

125

50

Max

Unit

ns

HSA to HSCLK Edge

HSCLK Period

t_SS

HSCLK Low Pulse Width

HSCLK High Pulse Width

Data Output Valid After HSCLK Edge

Data Output Fall Time

Data Output Rise Time

HSCLK Rise Time

HSCLK Fall Time

HSD Disable After HSA Rising Edge

HSA High After HSCLK Edge

t_SL

t_SH

t_DAV

t_DF

t_DR

t_SR

t_SF

t_DIS

t_SFS

50

40

20

10

5

0

HSA

t_SS

t_SFS

HSCLK

t_SL

t_SH

t_SF

t_SR

t_DAV

t_DIS

MSB

INTERMEDIATE BITS

t_DF

LSB

HSD

t_DR

Figure 4. HSDC Interface Timing

2mA

I

OL

TO OUTPUT

1.6V

C

L

50pF

800µA

I

OH

Figure 5. Load Circuit for Timing Specifications

Rev. A | Page 9 of 104

ADE7880

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter¹

Rating

VDD to AGND

VDD to DGND

Analog Input Voltage to AGND, IAP, IAN,

IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN

−0.3 V to +3.7 V

−2 V to +2 V

Analog Input Voltage to INP and INN

Reference Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Operating Temperature

−2 V to +2 V

−0.3 V to VDD + 0.3 V

THERMAL RESISTANCE

θ_JAis specified equal to 29.3°C/W; θ_JCis specified equal to

1.8°C/W.

Industrial Range

Storage Temperature Range

Junction Temperature

−40°C to +85°C

−65°C to +150°C

150°C

Table 6. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

40-Lead LFCSP

29.3

1.8

°C/W

Lead Temperature (Soldering, 10 sec)

300°C

¹Regarding the temperature profile used in soldering RoHS Compliant Parts,

Analog Devices, Inc. advises that reflow profiles should conform to J-STD 20

from JEDEC. Refer to JEDEC website for the latest revision.

ESD CAUTION

Rev. A | Page 10 of 104

Data Sheet

ADE7880

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC

PM0

PM1

RESET

DVDD

DGND

IAP

IAN

IBP

NC 10

1

2

3

4

5

6

7

8

9

30

29

28

27

NC

IRQ0

CLKOUT

CLKIN

ADE7880

TOP VIEW

(Not to Scale)

26 VDD

25 AGND

24 AVDD

23 VAP

22

21

VBP

NC

NOTES

1. NC = NO CONNECT.

2. CREATE A SIMILAR PAD ON THE PCB UNDER THE

EXPOSED PAD. SOLDER THE EXPOSED PAD TO

THE PAD ON THE PCB TO CONFER MECHANICAL

STRENGTH TO THE PACKAGE. DO NOT CONNECT

THE PADS TO AGND OR DGND.

Figure 6. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

No Connect. Do not connect to these pins. These pins are not connected internally.

1, 10, 11, 20,

21, 30, 31, 40

NC

2

3

4

5

PM0

Power Mode Pin 0. This pin, combined with PM1, defines the power mode of the ADE7880, as

described in Table 8.

Power Mode Pin 1. This pin defines the power mode of the ADE7880 when combined with PM0, as

described in Table 8.

Reset Input, Active Low. In PSM0 mode, this pin should stay low for at least 10 μs to trigger a

hardware reset.

This pin provides access to the on-chip 2.5 V digital LDO. Do not connect any external active

circuitry to this pin. Decouple this pin with a 4.7 μF capacitor in parallel with a ceramic 220 nF

capacitor.

PM1

RESET

DVDD

6

DGND

Ground Reference. This pin provides the ground reference for the digital circuitry.

7, 8

IAP, IAN

Analog Inputs for Current Channel A. This channel is used with the current transducers and is

referenced in this data sheet as Current Channel A. These inputs are fully differential voltage inputs

with a maximum differential level of 0.5 V. This channel also has an internal PGA equal to the ones

on Channel B and Channel C.

9, 12

13, 14

15, 16

17

IBP, IBN

ICP, ICN

INP, INN

REF_IN/OUT

Analog Inputs for Current Channel B. This channel is used with the current transducers and is

referenced in this data sheet as Current Channel B. These inputs are fully differential voltage inputs

with a maximum differential level of 0.5 V. This channel also has an internal PGA equal to the ones

on Channel C and Channel A.

Analog Inputs for Current Channel C. This channel is used with the current transducers and is

referenced in this data sheet as Current Channel C. These inputs are fully differential voltage inputs

with a maximum differential level of 0.5 V. This channel also has an internal PGA equal to the ones

on Channel A and Channel B.

Analog Inputs for Neutral Current Channel N. This channel is used with the current transducers and

is referenced in this data sheet as Current Channel N. These inputs are fully differential voltage

inputs with a maximum differential level of 0.5 V. This channel also has an internal PGA, different

from the ones found on the A, B, and C channels.

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal

value of 1.2 V. An external reference source with 1.2 V 8% can also be connected at this pin. In

either case, decouple this pin to AGND with a 4.7 μF capacitor in parallel with a ceramic 100 nF

capacitor. After reset, the on-chip reference is enabled.

Rev. A | Page 11 of 104

ADE7880

Data Sheet

Pin No.

Mnemonic

Description

18, 19, 22, 23

VN, VCP, VBP, VAP

Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is

referenced as the voltage channel in this data sheet. These inputs are single-ended voltage inputs

with a maximum signal level of 0.5 V with respect to VN for specified operation. This channel also

has an internal PGA.

24

25

26

AVDD

AGND

VDD

This pin provides access to the on-chip 2.5 V analog low dropout regulator (LDO). Do not connect

external active circuitry to this pin. Decouple this pin with a 4.7 μF capacitor in parallel with a

ceramic 220 nF capacitor.

Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the

analog ground plane or to the quietest ground reference in the system. Use this quiet ground

reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers.

Supply Voltage. This pin provides the supply voltage. In PSM0 (normal power mode), maintain the

supply voltage at 3.3 V 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low

power mode), and PSM3 (sleep mode), when the ADE7880 is supplied from a battery, maintain the

supply voltage between 2.4 V and 3.7 V. Decouple this pin to DGND with a 10 μF capacitor in parallel with

a ceramic 100 nF capacitor.

27

CLKIN

Master Clock. An external clock can be provided at this logic input. Alternatively, a parallel resonant

AT-cut crystal can be connected across CLKIN and CLKOUT to provide a clock source for the

ADE7880. The clock frequency for specified operation is 16.384 MHz. Use ceramic load capacitors of

a few tens of picofarad with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet

for load capacitance requirements.

28

CLKOUT

A crystal can be connected across this pin and CLKIN (as previously described with Pin 27 in this

table) to provide a clock source for the ADE7880.

29, 32

33, 34, 35

IRQ0, IRQ1

Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a

detailed presentation of the events that can trigger interrupts.

CF1, CF2/HREADY,

CF3/HSCLK

Calibration Frequency (CF) Logic Outputs. These outputs provide power information based on the

CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the CFMODE register. These outputs are used for

operational and calibration purposes. The full-scale output frequency can be scaled by writing to the

CF1DEN, CF2DEN, and CF3DEN registers, respectively (see the Energy-to-Frequency Conversion

section). CF2 is multiplexed with the HREADY signal generated by the harmonic calculations block.

CF3 is multiplexed with the serial clock output of the HSDC port.

36

SCLK/SCL

Serial Clock Input for SPI Port/Serial Clock Input for I²C Port. All serial data transfers are synchronized

to this clock (see the Serial Interfaces section). This pin has a Schmidt trigger input for use with a

clock source that has a slow edge transition time, for example, opto-isolator outputs.

37

38

39

EP

MISO/HSD

MOSI/SDA

SS/HSA

Data Out for SPI Port/Data Out for HSDC Port.

Data In for SPI Port/Data Out for I²C Port.

Slave Select for SPI Port/HSDC Port Active.

Exposed Pad

Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the

PCB to confer mechanical strength to the package. Do not connect the pads to AGND or DGND.

Rev. A | Page 12 of 104

Data Sheet

ADE7880

TYPICAL PERFORMANCE CHARACTERISTICS

0.5

0.3

V

= 2.97V

= 3.30V

= 3.63V

DD

0.3

0.1

–0.1

–0.3

–0.5

–0.3

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

–0.5

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 7. Total Active Energy Error as Percentage of Reading (Gain = +1,

Power Factor = 1) over Temperature with Internal Reference and

Integrator Off

Figure 10. Total Active Energy Error as Percentage of Reading (Gain = +1)

over Power Supply with Internal Reference and Integrator Off

0.5

0.3

0.5

GAIN = +1

GAIN = +2

GAIN = +4

GAIN = +8

GAIN = +16

0.3

0.1

–0.1

–0.3

–0.5

–0.1

–0.3

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

–0.5

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 11. Total Active Energy Error as Percentage of Reading (Gain = +16)

over Temperature with Internal Reference and Integrator On

Figure 8. Total Active Energy Error as Percentage of Reading over Gain with

Internal Reference and Integrator Off

0.5

PF = +1.0

PF = +0.5

PF = –0.5

0.3

0.1

–0.1

–0.3

–0.1

–0.3

–0.5

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

–0.5

0.01

0.1

1

10

100

45

47

49

51

53

55

57

59

61

63

65

PERCENTAGE OF FULL-SCALE CURRENT (%)

LINE FREQUENCY (Hz)

Figure 9. Total Active Energy Error as Percentage of Reading (Gain = +1) over

Frequency with Internal Reference and Integrator Off

Figure 12. Fundamental Active Energy Error as Percentage of Reading

(Gain = +1, Power Factor = 1) over Temperature with Internal Reference and

Integrator Off

Rev. A | Page 13 of 104

ADE7880

Data Sheet

0.5

0.3

GAIN = +1

GAIN = +2

GAIN = +4

GAIN = +8

GAIN = +16

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

0.3

0.1

–0.1

–0.3

–0.1

–0.3

–0.5

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 13. Fundamental Active Energy Error as Percentage of Reading over

Gain with Internal Reference and Integrator Off

Figure 16. Fundamental Reactive Energy Error as Percentage of Reading

(Gain = +1, Power Factor = 0) over Temperature with Internal Reference and

Integrator Off

0.5

V

= 2.97V

= 3.30V

= 3.63V

GAIN = +1

GAIN = +2

GAIN = +4

GAIN = +8

GAIN = +16

DD

0.3

0.1

0.3

0.1

–0.1

–0.3

–0.5

–0.1

–0.3

–0.5

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 14. Fundamental Active Energy Error as Percentage of Reading

(Gain = +1) over Power Supply with Internal Reference and Integrator Off

Figure 17. Fundamental Reactive Energy Error as Percentage of Reading over

Gain with Internal Reference and Integrator Off

0.5

PF = +1.0

PF = +0.5

PF = –0.5

0.3

0.1

–0.1

–0.3

–0.5

–0.3

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

–0.5

45

47

49

51

53

55

57

59

61

63

65

0.01

0.1

1

10

100

LINE FREQUENCY (Hz)

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 18. Fundamental Reactive Energy Error as Percentage of Reading

(Gain = +1) over Frequency with Internal Reference and Integrator Off

Figure 15. Fundamental Active Energy Error as Percentage of Reading

(Gain = +1) over Temperature with Internal Reference and Integrator On

Rev. A | Page 14 of 104

Data Sheet

ADE7880

0.5

0.3

V

= 2.97V

= 3.30V

= 3.63V

DD

0.3

0.1

–0.1

–0.3

–0.5

–0.1

–0.3

–0.5

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 19. Fundamental Reactive Energy Error as Percentage of Reading

(Gain = +1) over Power Supply with Internal Reference and Integrator Off

Figure 22. V RMS Error as a Percentage of Reading (Gain = +1) over

Temperature with Internal Reference

0.5

5

0

–5

0.3

–10

–15

–20

–25

–30

–35

–40

–45

0.1

–0.1

–0.3

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

–0.5

0

3

6

9

12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63

HARMONIC ORDER (55Hz FUNDAMENTAL)

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 23. Harmonic I RMS Error as a Percentage of Reading over Harmonic

Order, 63 Harmonics, 55 Hz Fundamental, 30 Averages per Reading, 750 ms

Settling time, 125 μs Update Rate

Figure 20. Fundamental Reactive Energy Error as Percentage of Reading

(Gain = +16) over Temperature with Internal Reference and Integrator On

6

0.5

0.3

4

2

0.1

0

–0.1

–2

–4

–6

–0.3

+85°C, PF = 1.0

+25°C, PF = 1.0

–40°C, PF = 1.0

–0.5

0.01

0.1

1

10

100

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 24. Harmonic I RMS Error as a Percentage of Reading (Gain = +1),

51 Harmonics, 55 Hz Fundamental, Single Reading, 750 ms Settling Time

Figure 21. I RMS Error as Percentage of Reading (Gain = +1) over

Temperature with Internal Reference and Integrator Off

Rev. A | Page 15 of 104

ADE7880

Data Sheet

6

4

2

0

–2

–4

–2

–4

–6

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 25. Harmonic I RMS Error as Percentage of Reading (Gain = +1),

51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading, 750 ms

Settling Time, 125 μs Update Rate

Figure 28. Harmonic Reactive Power Error as Percentage of Reading

(Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading, 750 ms

Settling Time, 125 μs Update Rate

6

4

2

0

–2

–4

–6

–2

–4

–6

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 26. Harmonic Active Power Error as Percentage of Reading

(Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading,

750 ms Settling Time, 125 μs Update Rate

Figure 29. Harmonic Reactive Power Error as Percentage of Reading

(Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,

750 ms Settling Time, 125 μs Update Rate

6

4

2

0

–2

–4

–6

–2

–4

–6

0.01

0.1

1

10

100

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 27. Harmonic Active Power Error as Percentage of Reading

(Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,

750 ms Settling Time, 125 μs Update Rate

Figure 30. Harmonic Apparent Power Error as Percentage of Reading

(Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading,

750 ms Settling Time, 125 μs Update Rate

Rev. A | Page 16 of 104

Data Sheet

ADE7880

6

4

2

0

–2

–4

–6

0.01

0.1

1

10

100

PERCENTAGE OF FULL-SCALE CURRENT (%)

Figure 31. Harmonic Apparent Power Error as Percentage of Reading

(Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,

750 ms Settling Time, 125 μs Update Rate

Rev. A | Page 17 of 104

ADE7880

Data Sheet

TEST CIRCUIT

3.3V

26

+

0.22µF

4.7µF

24

5

3.3V

2

3

PM0

39

38

SS/HSA

MOSI/SDA

PM1

RESET

IAP

10kΩ

1µF

1kΩ

4

MISO/HSD 37

7

10nF

3.3V

36

35

34

33

32

29

17

SCLK/SCL

CF3/HSCLK

CF2/HREADY

8

IAN

10kΩ

9

IBP

SAME AS

IAP, IAN

12

13

14

18

19

22

23

IBN

SAME AS

ADE7880

1.5kΩ

CF1

CF2

ICP

SAME AS

IAP, IAN

IRQ1

IRQ0

ICN

10nF

1kΩ

VN

REF

IN/OUT

+

VCP

VBP

VAP

20pF

0.1µF

4.7µF

10nF

28

27

CLKOUT

CLKIN

1kΩ

SAME AS

VCP

SAME AS

VCP

16.384MHz

20pF

6

25

Figure 32. Test Circuit

Rev. A | Page 18 of 104

Data Sheet

ADE7880

TERMINOLOGY

Measurement Error

the HPF removes the offset from the current and voltage channels

and the power calculation remains unaffected by this offset.

The error associated with the energy measurement made by the

ADE7880 is defined by

Gain Error

Measurement Error =

Energy Registered by ADE7880− TrueEnergy

The gain error in the ADCs of the ADE7880 is defined as the

difference between the measured ADC output code (minus the

offset) and the ideal output code (see the Current Channel ADC

section and the Voltage Channel ADC section). The difference

is expressed as a percentage of the ideal code.

×100%

(1)

TrueEnergy

Phase Error Between Channels

The high-pass filter (HPF) and digital integrator introduce a

slight phase mismatch between the current and the voltage

CF Jitter

The period of pulses at one of the CF1, CF2, or CF3 pins is

continuously measured. The maximum, minimum, and average

values of four consecutive pulses are computed as follows:

channel. The all digital design ensures that the phase matching

between the current channels and voltage channels in all three

phases is within 0.1° over a range of 45 Hz to 65 Hz and 0.2°

over a range of 40 Hz to 1 kHz. This internal phase mismatch

can be combined with the external phase error (from current

sensor or component tolerance) and calibrated with the phase

calibration registers.

Maximum = max(Period₀, Period₁, Period₂, Period₃)

Minimum = min(Period₀, Period₁, Period₂, Period₃)

Period₀+ Period₁+ Period₂+ Period₃

Average =

4

Power Supply Rejection (PSR)

This quantifies the ADE7880 measurement error as a percen-

tage of reading when the power supplies are varied. For the ac

PSR measurement, a reading at nominal supplies (3.3 V) is

taken. A second reading is obtained with the same input signal

levels when an ac signal (120 mV rms at 100 Hz) is introduced

onto the supplies. Any error introduced by this ac signal is

expressed as a percentage of reading—see the Measurement

Error definition.

The CF jitter is then computed as

Maximum− Minimum

Average

Harmonic Power Measurement Error

CF_JITTER

=

×100ꢀ

(2)

To measure the error in the harmonic active and reactive power

calculations made by the ADE7880, the voltage channel is supplied

with a signal comprising a fundamental and one harmonic

component with amplitudes equal to 250 mV. The current

channel is supplied with a signal comprising a fundamental

with amplitude of 50 mV and one harmonic component of the

same index as the one in the voltage channel. The amplitude of

the harmonic is varied from 250 mV, down to 250 μV, 2000 times

lower than full scale.

For the dc PSR measurement, a reading at nominal supplies

(3.3 V) is taken. A second reading is obtained with the same

input signal levels when the power supplies are varied 10ꢀ.

Any error introduced is expressed as a percentage of the

reading.

ADC Offset Error

This refers to the dc offset associated with the analog inputs to

the ADCs. It means that with the analog inputs connected to

AGND, the ADCs still see a dc analog input signal. The magni-

tude of the offset depends on the gain and input range selection

(see the Typical Performance Characteristics section). However,

The error is defined by

Measurement Error =

Power Registered by ADE7880−TruePower

×100%

(3)

TruePower

Rev. A | Page 19 of 104

ADE7880

Data Sheet

POWER MANAGEMENT

The ADE7880 has four modes of operation, determined by the

state of the PM0 and PM1 pins (see Table 8). These pins provide

complete control of the ADE7880 operation and can easily be

connected to an external microprocessor I/O. The PM0 and

PM1 pins have internal pull-up resistors. See Table 10 and Table 11

for a list of actions that are recommended before and after setting

a new power mode.

during PSM1 (see the Current Mean Absolute Value Calculation

section for more details on the xIMAV registers).

The 20-bit mean absolute value measurements done in PSM1,

although available also in PSM0, are different from the rms

measurements of phase currents and voltages executed only in

PSM0 and stored in the HxIRMS and HxVRMS 24-bit registers.

See the Current Mean Absolute Value Calculation section for

details.

Table 8. Power Supply Modes

If the ADE7880 is set in PSM1 mode after it was in the PSM0

mode, the ADE7880 immediately begins the mean absolute

value calculations without any delay. The xIMAV registers are

accessible at any time; however, if the ADE7880 is set in PSM1

mode after it was in PSM2 or PSM3 modes, the ADE7880

signals the start of the mean absolute value computations by

Power Supply Modes

PSM0, Normal Power Mode

PSM1, Reduced Power Mode

PSM2, Low Power Mode

PSM3, Sleep Mode

PM1

PM0

0

1

0

1

PSM0—NORMAL POWER MODE (ALL PARTS)

IRQ1

triggering the

pin low. The xIMAV registers can be

In PSM0 mode, the ADE7880 is fully functional. The PM0 pin

is set to high, and the PM1 pin is set to low for the ADE7880 to

enter this mode. If the ADE7880 is in PSM1, PSM2, or PSM3

mode and is switched into PSM0 mode, then all control registers

take the default values with the exception of the threshold register,

LPOILVL, which is used in PSM2 mode, and the CONFIG2

register, both of which maintain their values.

accessed only after this moment.

PSM2—LOW POWER MODE

In the low power mode, PSM2, the ADE7880 compares all

phase currents against a threshold for a period of 0.02 ×

(LPLINE[4:0] + 1) seconds, independent of the line frequency.

LPLINE[4:0] are Bits[7:3] of the LPOILVL register (see Table 9).

The ADE7880 signals the end of the transition period by triggering

Table 9. LPOILVL Register

IRQ1

the

interrupt pin low and setting Bit 15 (RSTDONE) in the

Bit

Mnemonic Default Description

STATUS1 register to 1. This bit is 0 during the transition period

and becomes 1 when the transition is finished. The status bit is

[2:0] LPOIL[2:0]

111

Threshold is put at a value

corresponding to full scale

multiplied by LPOIL/8

The measurement period is

(LPLINE[4:0] + 1)/50 sec

IRQ1

cleared and the

pin is set back to high by writing to the

[7:3] LPLINE[4:0] 00000

STATUS1 register with the corresponding bit set to 1. Bit 15

(RSTDONE) in the interrupt mask register does not have any

The threshold is derived from Bits[2:0] (LPOIL[2:0]) of the

LPOILVL register as LPOIL[2:0]/8 of full scale. Every time

one phase current becomes greater than the threshold, a

counter is incremented. If every phase counter remains below

LPLINE[4:0] + 1 at the end of the measurement period, then

IRQ1

functionality attached even if the

pin goes low when Bit 15

(RSTDONE) in the STATUS1 register is set to 1. This makes the

RSTDONE interrupt unmaskable.

PSM1—REDUCED POWER MODE

In the reduced power mode, PSM1, the ADE7880 measures the

mean absolute values (mav) of the 3-phase currents and stores

the results in the AIMAV, BIMAV, and CIMAV 20-bit registers.

This mode is useful in missing neutral cases in which the voltage

supply of the ADE7880 is provided by an external battery. The

serial ports, I²C or SPI, are enabled in this mode; the active port

can be used to read the AIMAV, BIMAV, and CIMAV registers. It

is not recommended to read any of the other registers because their

values are not guaranteed in this mode. Similarly, a write operation

is not taken into account by the ADE7880 in this mode.

IRQ0

the

greater or equal to LPLINE[4:0] + 1 at the end of the measurement

IRQ1

pin is triggered low. If a single phase counter becomes

period, the

pin is triggered low. Figure 33 illustrates how

the ADE7880 behaves in PSM2 mode when LPLINE[4:0] = 2

and LPOIL[2:0] = 3. The test period is three 50 Hz cycles (60 ms),

and the Phase A current rises above the LPOIL[2:0] threshold three

IRQ1

times. At the end of the test period, the

pin is triggered low.

In summary, in this mode, it is not recommended to access any

re g i s t e r ot h e r t h a n A I M AV, B I M AV, a n d C I M AV. T h e c i rc u it

that computes the rms estimates is also active during PSM0;

therefore, its calibration can be completed in either PSM0 mode

or in PSM1 mode. Note that the ADE7880 does not provide any

register to store or process the corrections resulting from the

calibration process. The external microprocessor stores the gain

values in connection with these measurements and uses them

Rev. A | Page 20 of 104

Data Sheet

ADE7880

IRQ1

LPLINE[4:0] = 2

into Sleep Mode PSM3. If the

pin is triggered low at the

end of the measurement period, this signifies that at least one

current input is above the defined threshold and current is

flowing through the system, although no voltage is present at

the ADE7880 pins. This situation is often called missing neutral

and is considered a tampering situation, at which point the

external microprocessor sets the ADE7880 into PSM1 mode,

measures the mean absolute values of phase currents, and

integrates the energy based on their values and the nominal

voltage.

LPOIL[2:0]

THRESHOLD

IA CURRENT

It is recommended to use the ADE7880 in PSM2 mode when

Bits[2:0] (PGA1[2:0]) of the Gain register are equal to 1 or 2.

These bits represent the gain in the current channel datapath. It

is not recommended to use the ADE7880 in PSM2 mode when

the PGA1[2:0] bits are equal to 4, 8, or 16.

PHASE

COUNTER = 2

PHASE

COUNTER = 3

COUNTER = 1

IRQ1

IRQ

Figure 33. PSM2 Mode Triggering

Pin for LPLINE[4:0] = 2 (50 Hz Systems)

The I²C or SPI port is not functional during this mode. The PSM2

mode reduces the power consumption required to monitor the

currents when there is no voltage input and the voltage supply

PSM3—SLEEP MODE (ALL PARTS)

In sleep mode, the ADE7880 has most of its internal circuits

turned off and the current consumption is at its lowest level.

The I²C, HSDC, and SPI ports are not functional during this

IRQ0

of the ADE7880 is provided by an external battery. If the

pin is triggered low at the end of a measurement period, this

signifies all phase currents stayed below threshold and,

therefore, there is no current flowing through the system.

At this point, the external microprocessor sets the ADE7880

RESET

SS

mode, and the

, SCLK/SCL, MOSI/SDA, and /HSA pins

should be set high.

Table 10. Power Modes and Related Characteristics

Power Mode

All Registers¹

LPOILVL, CONFIG2

I²C/SPI

Functionality

PSM0

State After Hardware Reset Set to default

Set to default

Unchanged

I²C enabled

All circuits are active and DSP is in idle

mode.

All circuits are active and DSP is in idle

mode.

State After Software Reset

Set to default

Not available

Active serial port is

unchanged if lock-

in procedure has

been previously

executed

PSM1

PSM0 values retained

Enabled

Current mean absolute values are

computed and the results are stored

in the AIMAV, BIMAV, and CIMAV

registers. The I²C or SPI serial port is

enabled with limited functionality.

PSM2

PSM3

Not available

PSM0 values retained

Disabled

Compares phase currents against the

threshold set in LPOILVL. Triggers

IRQ0or IRQ1 pins accordingly. The

serial ports are not available.

Internal circuits shut down and the

serial ports are not available.

¹Setting for all registers except the LPOILVL and CONFIG2 registers.

Rev. A | Page 21 of 104

ADE7880

Data Sheet

Table 11. Recommended Actions When Changing Power Modes

Next Power Mode

Initial Power

Mode

Before Setting Next

Power Mode

PSM0

PSM1

PSM2

PSM3

PSM0

Stop DSP by setting the

Run register = 0x0000

Current mean absolute

values (mav) computed

immediately

Wait until the IRQ0

or IRQ1 pin is

triggered

No action

necessary

Disable HSDC by clearing

Bit 6 (HSDCEN) to 0 in the

CONFIG register

xIMAV registers can be

accessed immediately

accordingly

Mask interrupts by setting

MASK0 = 0x0 and

MASK1 = 0x0

Erase interrupt status flags

in the STATUS0 and STATUS1

registers

PSM1

PSM2

No action necessary

Wait until the IRQ1 pin

is triggered low

Poll the STATUS1

register until Bit 15

(RSTDONE) is set to 1

Wait until the IRQ0

or IRQ1 pin is

triggered

No action

necessary

accordingly

No action necessary

Wait until the IRQ1 pin

is triggered low

Wait until the IRQ1 pin

triggered low

No action

necessary

Poll the STATUS1

register until Bit 15

(RSTDONE) is set to 1

Current mean absolute

values compute at this

moment

xIMAV registers may be

accessed from this

moment

PSM3

No action necessary

Wait until the IRQ1 pin

is triggered low

Poll the STATUS1

register until Bit 15

(RSTDONE) is set to 1

Wait until the IRQ1 pin is Wait until the IRQ0

triggered low

or IRQ1 pin is

triggered

Current mav circuit

begins computations at

this time

accordingly

xIMAV registers can be

accessed from this

moment

Rev. A | Page 22 of 104

Data Sheet

ADE7880

POWER-UP PROCEDURE

3.3V – 10%

2.0V ± 10%

ADE7880

PSM0 READY

0V

26ms

40ms

MICROPROCESSOR

MAKES THE

CHOICE BETWEEN

I C AND SPI

ADE7880

POWERED UP

POR TIMER

TURNED ON

ADE7880

ENTER PSM3

MICROPROCESSOR RSTDONE

2

SETS ADE7880

IN PSM0

INTERRUPT

TRIGGERED

Figure 34. Power-Up Procedure

The ADE7880 contains an on-chip power supply monitor that

supervises the power supply (VDD). At power-up, until VDD

reaches 2 V 10ꢀ, the chip is in an inactive state. As VDD

crosses this threshold, the power supply monitor keeps the chip

in this inactive state for an additional 26 ms, allowing VDD to

achieve 3.3 V − 10ꢀ, the minimum recommended supply

voltage. Because the PM0 and PM1 pins have internal pull-up

resistors and the external microprocessor keeps them high, the

ADE7880 always powers up in sleep mode (PSM3). Then, an

external circuit (that is, a microprocessor) sets the PM1 pin to a

low level, allowing the ADE7880 to enter normal mode (PSM0).

The passage from PSM3 mode, in which most of the internal

circuitry is turned off, to PSM0 mode, in which all functionality

is enabled, is accomplished in less than 40 ms (see Figure 34 for

details).

The ADE7880 signals the end of the transition period by triggering

IRQ1

the STATUS1 register to 1. This bit is 0 during the transition

period and becomes 1 when the transition ends. The status bit is

the

interrupt pin low and setting Bit 15 (RSTDONE) in

IRQ1

cleared and the

pin is returned high by writing the STATUS1

register with the corresponding bit set to 1. Because the RSTDONE

is an unmaskable interrupt, Bit 15 (RSTDONE) in the STATUS1

IRQ1

register must be cancelled for the

IRQ1

pin to return high. It is

recommended to wait until the

pin goes low before accessing

the STATUS1 register to test the state of the RSTDONE bit. At

this point, as a good programming practice, it is also recommended

to cancel all other status flags in the STATUS1 and STATUS0

registers by writing the corresponding bits with 1.

Initially, the DSP is in idle mode, which means it does not

execute any instruction. This is the moment to initialize all

ADE7880 registers. The last register in the queue must be

written three times to ensure the register has been initialized.

Then write 0x0001 into the Run register to start the DSP (see

the Digital Signal Processor section for details on the Run

register).

If PSM0 mode is the only desired power mode, the PM1 pin

may be set low permanently, using a direct connection to

ground. The PM0 pin may be left open because the internal pull

up resistor ensures its state is high. At power up, the ADE7880

briefly passes through PSM3 mode and then enters PSM0.

When the ADE7880 enters PSM0 mode, the I²C port is the

If the supply voltage, VDD, drops lower than 2 V 10ꢀ,

the ADE7880 enters an inactive state, which means that no

measurements or computations are executed.

SS

active serial port. If the SPI port is used, then the /HSA pin

must be toggled three times, high to low. This action selects the

SPI port for further use. If I²C is the active serial port, Bit 1

(I2C_LOCK) of the CONFIG2 register must be set to 1 to lock

it in. From this moment, the ADE7880 ignores spurious toggling

SS

of the /HSA pin, and an eventual switch to use the SPI port is

no longer possible. Likewise, if SPI is the active serial port, any

write to the CONFIG2 register locks the port, at which time a

switch to use the I²C port is no longer possible. Only a power-

RESET

down or by setting the

pin low can the ADE7880 be

reset to use the I²C port. Once locked, the serial port choice is

maintained when the ADE7880 changes PSMx power modes.

Immediately after entering PSM0, the ADE7880 sets all registers

to their default values, including the CONFIG2 and LPOILVL

registers.

Rev. A | Page 23 of 104

ADE7880

Data Sheet

HARDWARE RESET

SOFTWARE RESET FUNCTIONALITY

RESET

Bit 7 (SWRST) in the CONFIG register manages the software

reset functionality in PSM0 mode. The default value of this bit is 0.

If this bit is set to 1, then the ADE7880 enters the software reset

state. In this state, almost all internal registers are set to their

default values. In addition, the choice of which serial port, I²C or

SPI, is in use remains unchanged if the lock-in procedure has

been executed previously (see the Serial Interfaces section for

details). The registers that maintain their values despite the

SWRST bit being set to 1 are the CONFIG2 and LPOILVL

registers. When the software reset ends, Bit 7 (SWRST) in the

The ADE7880 has a

RESET

pin. If the ADE7880 is in PSM0

mode and the

pin is set low, then the ADE7880 enters

the hardware reset state. The ADE7880 must be in PSM0 mode

RESET

for a hardware reset to be considered. Setting the

low while the ADE7880 is in PSM1, PSM2, and PSM3 modes

does not have any effect.

RESET

If the ADE7880 is in PSM0 mode and the

pin is toggled

from high to low and then back to high after at least 10 μs, all the

registers are set to their default values, including the CONFIG2 and

LPOILVL registers. The ADE7880 signals the end of the transition

IRQ1

CONFIG register is cleared to 0, the

interrupt pin is set

IRQ1

period by triggering the

interrupt pin low and setting Bit 15

low, and Bit 15 (RSTDONE) in the STATUS1 register is set to 1.

This bit is 0 during the transition period and becomes 1 when

(RSTDONE) in the STATUS1 register to 1. This bit is 0 during

the transition period and becomes 1 when the transition ends.

The status bit is cleared and the

writing to the STATUS1 register with the corresponding bit set

to 1.

IRQ1

the transition ends. The status bit is cleared and the

pin is

IRQ1

pin is returned high by

set back high by writing to the STATUS1 register with the

corresponding bit set to 1.

After a software reset ends, the DSP is in idle mode, which

means it does not execute any instruction. As a good programming

practice, it is recommended to initialize all the ADE7880 registers

and then write 0x0001 into the Run register to start the DSP

(see the Digital Signal Processor section for details on the Run

register).

After a hardware reset, the DSP is in idle mode, which means it

does not execute any instruction.

Because the I²C port is the default serial port of the ADE7880, it

becomes active after a reset state. If SPI is the port used by the

external microprocessor, the procedure to enable it must be

RESET

repeated immediately after the

pin is toggled back to

Software reset functionality is not available in PSM1, PSM2, or

PSM3 mode.

high (see the Serial Interfaces section for details).

At this point, it is recommended to initialize all of the ADE7880

registers and then write 0x0001 into the Run register to start the

DSP. See the Digital Signal Processor section for details on the

Run register.

Rev. A | Page 24 of 104

Data Sheet

ADE7880

THEORY OF OPERATION

DIFFERENTIAL INPUT

V

+ V = 500mV MAX PEAK

ANALOG INPUTS

1

2

COMMON MODE

V

1

The ADE7880 has seven analog inputs forming current and

voltage channels. The current channels consist of four pairs of

fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP

and ICN, and INP and INN. These voltage input pairs have a

maximum differential signal of 0.5 V.

V

= ±25mV MAX

CM

VAP, VBP,

+500mV

OR VCP

V

1

V

CM

VN

CM

–500mV

The maximum signal level on analog inputs for the IxP/IxN

pair is also 0.5 V with respect to AGND. The maximum

common-mode signal allowed on the inputs is 25 mV. Figure 35

presents a schematic of the input for the current channels and

their relation to the maximum common-mode voltage.

DIFFERENTIAL INPUT

Figure 37. PGA in Current and Voltage Channels

ANALOG-TO-DIGITAL CONVERSION

The ADE7880 has seven sigma-delta (Σ-ꢁ) analog-to-digital

converters (ADCs). In PSM0 mode, all ADCs are active. In

PSM1 mode, only the ADCs that measure the Phase A, Phase B,

and Phase C currents are active. The ADCs that measure the

neutral current and the A, B, and C phase voltages are turned

off. In PSM2 and PSM3 modes, the ADCs are powered down to

minimize power consumption.

V

+ V = 500mV MAX PEAK

1

2

COMMON MODE

V

+ V

2

1

V

= ±25mV MAX

CM

IAP, IBP,

ICP, OR INP

+500mV

V

1

2

V

CM

IAN, IBN,

ICN, OR INN

V

CM

For simplicity, the block diagram in Figure 38 shows a first-

order Σ-ꢁ ADC. The converter is composed of the Σ-ꢁ modulator

and the digital low-pass filter.

–500mV

Figure 35. Maximum Input Level, Current Channels, Gain = 1

CLKIN/16

All inputs have a programmable gain amplifier (PGA) with a

possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and

IC inputs is set in Bits[2:0] (PGA1[2:0]) of the Gain register.

The gain of the IN input is set in Bits[5:3] (PGA2[2:0]) of the

Gain register; thus, a different gain from the IA, IB, or IC inputs

is possible. See Table 43for details on the Gain register.

ANALOG

DIGITAL

LOW-PASS

FILTER

LOW-PASS FILTER

INTEGRATOR

LATCHED

COMPARATOR

R

+

–

C

24

V

REF

.....10100101.....

1-BIT DAC

The voltage channel has three single-ended voltage inputs: VAP,

VBP, and VCP. These single-ended voltage inputs have a maximum

input voltage of 0.5 V with respect to VN. The maximum

signal level on analog inputs for VxP and VN is also 0.5 V

with respect to AGND. The maximum common-mode signal

allowed on the inputs is 25 mV. Figure 36 presents a schematic

of the voltage channels inputs and their relation to the maximum

common-mode voltage.

Figure 38. First-Order Σ-∆ ADC

A Σ-ꢁ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7880, the sampling clock is equal to 1.024 MHz

(CLKIN/16). The 1-bit DAC in the feedback loop is driven by

the serial data stream. The DAC output is subtracted from the

input signal. If the loop gain is high enough, the average value

of the DAC output (and, therefore, the bit stream) can approach

that of the input signal level. For any given input value in a

single sampling interval, the data from the 1-bit ADC is

virtually meaningless. Only when a large number of samples are

averaged is a meaningful result obtained. This averaging is

carried out in the second part of the ADC, the digital low-pass

filter. By averaging a large number of bits from the modulator,

the low-pass filter can produce 24-bit data-words that are

proportional to the input signal level.

GAIN

SELECTION

IxP, VyP

V

K × V

IN

IxN, VN

NOTES

1. x = A, B, C, N

y = A, B, C.

Figure 36. Maximum Input Level, Voltage Channels, Gain = 1

All inputs have a programmable gain with a possible gain

selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]

(PGA3[2:0]) in the Gain register (see Table 43).

Figure 37 shows how the gain selection from the Gain register

works in both current and voltage channels.

Rev. A | Page 25 of 104

ADE7880

Data Sheet

The Σ-ꢁ converter uses two techniques to achieve high resolu-

tion from what is essentially a 1-bit conversion technique. The

first is oversampling. Oversampling means that the signal is

sampled at a rate (frequency) that is many times higher than

the bandwidth of interest. For example, the sampling rate in

the ADE7880 is 1.024 MHz, and the bandwidth of interest is

40 Hz to 3.3 kHz. Oversampling has the effect of spreading the

quantization noise (noise due to sampling) over a wider

bandwidth. With the noise spread more thinly over a wider

bandwidth, the quantization noise in the band of interest is

lowered, as shown in Figure 39. However, oversampling alone is

not efficient enough to improve the signal-to-noise ratio (SNR)

in the band of interest. For example, an oversampling factor of 4 is

required just to increase the SNR by a mere 6 dB (1 bit). To keep

the oversampling ratio at a reasonable level, it is possible to

shape the quantization noise so that the majority of the noise

lies at the higher frequencies. In the Σ-ꢁ modulator, the noise is

shaped by the integrator, which has a high-pass-type response

for the quantization noise. This is the second technique used to

achieve high resolution. The result is that most of the noise is at

the higher frequencies where it can be removed by the digital

low-pass filter. This noise shaping is shown in Figure 39.

sampling frequency, that is, 1.024 MHz, move into the band of

interest for metering, that is, 40 Hz to 3.3 kHz. To attenuate the

high frequency (near 1.024 MHz) noise and prevent the distortion

of the band of interest, a low-pass filter (LPF) must be introduced.

For conventional current sensors, it is recommended to use one

RC filter with a corner frequency of 5 kHz for the attenuation to

be sufficiently high at the sampling frequency of 1.024 MHz.

The 20 dB per decade attenuation of this filter is usually

sufficient to eliminate the effects of aliasing for conventional

current sensors. However, for a di/dt sensor such as a Rogowski

coil, the sensor has a 20 dB per decade gain. This neutralizes the

20 dB per decade attenuation produced by the LPF. Therefore,

when using a di/dt sensor, take care to offset the 20 dB per

decade gain. One simple approach is to cascade one additional

RC filter, thereby producing a −40 dB per decade attenuation.

ALIASING EFFECTS

SAMPLING

FREQUENCY

0

3.3

4

512

1024

FREQUENCY (kHz)

ANTIALIAS FILTER

(RC)

IMAGE

FREQUENCIES

DIGITAL FILTER

SIGNAL

SHAPED NOISE

Figure 40. Aliasing Effects

SAMPLING

FREQUENCY

ADC Transfer Function

NOISE

All ADCs in the ADE7880 are designed to produce the same

24-bit signed output code for the same input signal level. With a

full-scale input signal of 0.5 V and an internal reference of 1.2 V,

the ADC output code is nominally 5,326,737 (0x514791) and

usually varies for each ADE7880 around this value. The code

from the ADC can vary between 0x800000 (−8,388,608) and

0x7FFFFF (+8,388,607); this is equivalent to an input signal

level of 0.787 V. However, for specified performance, do not

exceed the nominal range of 0.5 V; ADC performance is

guaranteed only for input signals lower than 0.5 V.

0

3.3

4

512

1024

FREQUENCY (kHz)

HIGH RESOLUTION

OUTPUT FROM

DIGITAL LPF

SIGNAL

NOISE

0

3.3

4

512

1024

FREQUENCY (kHz)

CURRENT CHANNEL ADC

Figure 39. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

Figure 41 shows the ADC and signal processing path for Input

IA of the current channels (it is the same for IB and IC). The

ADC outputs are signed twos complement 24-bit data-words

and are available at a rate of 8 kSPS (thousand samples per

second). With the specified full-scale analog input signal

of 0.5V, the ADC produces its maximum output code value.

Figure 41 shows a full-scale voltage signal applied to the differ-

ential inputs (IAP and IAN). The ADC output swings between

−5,326,737 (0xAEB86F) and +5,326,737 (0x514791). Note that

these are nominal values and every ADE7880 varies around

these values. The input, IN, corresponds to the neutral current

of a 3-phase system. If no neutral line is present, connect this

input to AGND. The datapath of the neutral current is similar

to the path of the phase currents as shown in Figure 42.

Antialiasing Filter

Figure 38 also shows an analog low-pass filter (RC) on the input

to the ADC. This filter is placed outside the ADE7880, and its role

is to prevent aliasing. Aliasing is an artifact of all sampled systems

as shown in Figure 40. Aliasing means that frequency components

in the input signal to the ADC, which are higher than half the

sampling rate of the ADC, appear in the sampled signal at a

frequency below half the sampling rate. Frequency components

above half the sampling frequency (also known as the Nyquist

frequency, that is, 512 kHz) are imaged or folded back down

below 512 kHz. This happens with all ADCs regardless of the

architecture. In the example shown, only frequencies near the

Rev. A | Page 26 of 104

Data Sheet

ADE7880

ZX SIGNAL

DATA RANGE

ZX DETECTION

LPF1

0x514791 =

+5,326,737

CURRENT PEAK,

OVERCURRENT

DETECT

0V

CURRENT RMS (IRMS)

CALCULATION

INTEN BIT

CONFIG[0]

DSP

PGA1 BITS

HPFEN BIT

CONFIG3[0]

REFERENCE

ADC

GAIN[2:0]

IAWV WAVEFORM

SAMPLE REGISTER

0xAEB86F =

–5,326,737

×1, ×2, ×4, ×8, ×16

AIGAIN[23:0]

DIGITAL

INTEGRATOR

IAP

TOTAL/FUNDAMENTAL

ACTIVE AND REACTIVE

POWER CALCULATION

V

PGA1

IN

HPF

IAN

CURRENT CHANNEL

DATA RANGE AFTER

INTEGRATION

V

CURRENT CHANNEL

DATA RANGE

IN

+0.5V/GAIN

0x514791 =

+5,326,737

0x5A7540 =

+5,928,256

0V

0xAEB86F =

–5,326,737

0xA58AC0 =

–5,928,256

–0.5V/GAIN

ANALOG INPUT RANGE

ANALOG OUTPUT RANGE

Figure 41. Current Channel Signal Path

ININTEN BIT

CONFIG3[3]

DSP

PGA2 BITS

GAIN[5:3]

HPFEN BIT

CONFIG3[0]

REFERENCE

ADC

CURRENT RMS (IRMS)

×1, ×2, ×4, ×8, ×16

NIGAIN[23:0]

DIGITAL

INTEGRATOR

CALCULATION

IAP

INWV WAVEFORM

SAMPLE REGISTER

V

PGA2

IN

HPF

IAN

Figure 42. Neutral Current Signal Path

31

28 27

24 23

0

Current Waveform Gain Registers

0000

24-BIT NUMBER

There is a multiplier in the signal path of each phase and

neutral current. The current waveform can be changed by

100ꢀ by writing a corresponding twos complement number to

the 24-bit signed current waveform gain registers (AIGAIN,

BIGAIN, CIGAIN, and NIGAIN). For example, if 0x400000 is

written to those registers, the ADC output is scaled up by 50ꢀ.

To scale the input by −50ꢀ, write 0xC00000 to the registers.

Equation 4 describes mathematically the function of the current

waveform gain registers.

BITS[27:24] ARE

EQUAL TO BIT 23

BIT 23 IS A SIGN BIT

Figure 43. 24-Bit xIGAIN Transmitted as 32-Bit Words

Current Channel HPF

The ADC outputs can contain a dc offset. This offset can create

errors in power and rms calculations. High-pass filters (HPFs)

are placed in the signal path of the phase and neutral currents

and of the phase voltages. If enabled, the HPF eliminates any dc

offset on the current channel. All filters are implemented in the

DSP and, by default, they are all enabled: Bit 0 (HPFEN) of the

CONFIG3[7:0] register is set to 1. All filters are disabled by

setting Bit 0 (HPFEN) to 0.

Current Waveform =

Content of Current GainRegister

⎛

⎞

(4)

ADCOutput ×⎜1 +

⎟

⎜

2²³

⎝

⎠

Changing the content of the AIGAIN, BIGAIN, CIGAIN, or

INGAIN registers affects all calculations based on its current;

that is, it affects the corresponding phase active/reactive/

apparent energy and current rms calculation. In addition,

waveform samples scale accordingly.

Note that the serial ports of the ADE7880 work on 32-, 16-, or

8-bit words, and the DSP works on 28 bits. The 24-bit AIGAIN,

BIGAIN, CIGAIN, and NIGAIN registers are accessed as 32-bit

registers with the four most significant bits (MSBs) padded with

0s and sign extended to 28 bits. See Figure 43 for details.

Rev. A | Page 27 of 104

ADE7880

Data Sheet

allows for using a different current sensor to measure the neutral

current (for example a current transformer) from the current

sensors used to measure the phase currents (for example di/dt

sensors). The digital integrators are managed by Bit 0 (INTEN) of

the CONFIG register and by Bit 3 (ININTEN) of the CONFIG3

register. Bit 0 (INTEN) of the CONFIG register manages the

integrators in the phase current channels. Bit 3 (ININTEN) of the

CONFIG3 register manages the integrator in the neutral current

channel. When the INTEN bit is 0 (default), all integrators in the

phase current channels are disabled. When INTEN bit is 1, the

integrators in the phase currents datapaths are enabled. When the

ININTEN bit is 0 (default), the integrator in the neutral current

channel is disabled. When the ININTEN bit is 1, the integrator in

the neutral current channel is enabled.

Current Channel Sampling

The waveform samples of the current channel are taken at the

output of HPF and stored in the 24-bit signed registers, IAWV,

IBWV, ICWV, and INWV at a rate of 8 kSPS. All power and rms

calculations remain uninterrupted during this process. Bit 17

(DREADY) in the STATUS0 register is set when the IAWV, IBWV,

ICWV, and INWV registers are available to be read using the I²C

or SPI serial port. Setting Bit 17 (DREADY) in the MASK0

register enables an interrupt to be set when the DREADY flag is

set. See the Digital Signal Processor section for more details on

Bit DREADY.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

When the IAWV, IBWV, ICWV, and INWV 24-bit signed

registers are read from the ADE7880, they are transmitted sign

extended to 32 bits. See Figure 44 for details.

Figure 46 and Figure 47 show the magnitude and phase

response of the digital integrator.

31

24 23 22

0

Note that the integrator has a −20 dB/dec attenuation and

approximately −90° phase shift. When combined with a di/dt

sensor, the resulting magnitude and phase response should be a

flat gain over the frequency band of interest. However, the di/dt

sensor has a 20 dB/dec gain associated with it and generates sig-

nificant high frequency noise. At least a second order antialiasing

filter is needed to avoid noise aliasing back in the band of

interest when the ADC is sampling (see the Antialiasing Filter

section).

24-BIT SIGNED NUMBER

BITS[31:24] ARE

EQUAL TO BIT 23

BIT 23 IS A SIGN BIT

Figure 44. 24-Bit IxWV Register Transmitted as 32-Bit Signed Word

The ADE7880 contains a high speed data capture (HSDC) port

that is specially designed to provide fast access to the waveform

sample registers. See the HSDC Interface section for more details.

50

di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR

The di/dt sensor detects changes in the magnetic field caused by

the ac current. Figure 45 shows the principle of a di/dt current

sensor.

0

–50

0.01

0.1

1

10

100

1000

FREQUENCY (Hz)

MAGNETIC FIELD CREATED BY CURRENT

(DIRECTLY PROPORTIONAL TO CURRENT)

0

–50

+

–

EMF (ELECTROMOTIVE FORCE)

INDUCED BY CHANGES IN

MAGNETIC FLUX DENSITY (di/dt)

–100

0

500

1000

1500

2000

2500

3000

3500 4000

Figure 45. Principle of a di/dt Current Sensor

FREQUENCY (Hz)

Figure 46. Combined Gain and Phase Response of the

Digital Integrator

The flux density of a magnetic field induced by a current is

directly proportional to the magnitude of the current. The

changes in the magnetic flux density passing through a conductor

loop generate an electromotive force (EMF) between the two

ends of the loop. The EMF is a voltage signal that is propor-

tional to the di/dt of the current. The voltage output from the

di/dt current sensor is determined by the mutual inductance

between the current carrying conductor and the di/dt sensor.

The DICOEFF 24-bit signed register is used in the digital

integrator algorithm. At power-up or after a reset, its value is

0x000000. Before turning on the integrator, this register must be

initialized with 0xFFF8000. DICOEFF is not used when the

integrator is turned off and can remain at 0x000000 in that case.

Due to the di/dt sensor, the current signal needs to be filtered

before it can be used for power measurement. On each phase and

neutral current datapath, there are built-in digital integrators to

recover the current signal from the di/dt sensor. The digital

integrators placed on the phase currents data paths are independent

of the digital integrator placed in the neutral current data path. This

Rev. A | Page 28 of 104

Data Sheet

ADE7880

–15

signed register is accessed as a 32-bit register with four MSBs

padded with 0s and sign extended to 28 bits, which practically

means it is transmitted equal to 0x0FFF8000.

–20

–25

–30

When the digital integrator is switched off, the ADE7880 can

be used directly with a conventional current sensor, such as

a current transformer (CT).

30

35

40

45

50

55

60

65

70

FREQUENCY (Hz)

–89.96

VOLTAGE CHANNEL ADC

Figure 48 shows the ADC and signal processing chain for

Input VA in the voltage channel. The VB and VC channels

have similar processing chains. The ADC outputs are signed

twos complement 24-bit words and are available at a rate of

8 kSPS. With the specified full-scale analog input signal of

0.5 V, the ADC produces its maximum output code value.

Figure 48 shows a full-scale voltage signal being applied to the

differential inputs (VA and VN). The ADC output swings

between −5,326,737 (0xAEB86F) and +5,326,737 (0x514791).

Note these are nominal values and every ADE7880 varies

around these values.

–89.97

–89.98

–89.99

30

35

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 47. Combined Gain and Phase Response of the

Digital Integrator (40 Hz to 70 Hz)

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

Similar to the registers shown in Figure 43, the DICOEFF 24-bit

VOLTAGE PEAK,

OVERVOLTAGE,

SAG DETECT

CURRENT RMS (VRMS)

CALCULATION

DSP

PGA3 BITS

HPFEN BIT

REFERENCE

ADC

GAIN[8:6]

VAWV WAVEFORM

SAMPLE REGISTER

CONFIG3[0]

×1, ×2, ×4, ×8, ×16

AVGAIN[23:0]

VAP

TOTAL/FUNDAMENTAL

ACTIVE AND REACTIVE

POWER CALCULATION

V

PGA3

IN

HPF

VN

V

VOLTAGE CHANNEL

DATA RANGE

IN

ZX DETECTION

LPF1

+0.5V/GAIN

0x514791 =

+5,326,737

ZX SIGNAL

DATA RANGE

0V

0x514791 =

+5,326,737

0xAEB86F =

–5,326,737

–0.5V/GAIN

0V

ANALOG INPUT RANGE

ANALOG OUTPUT RANGE

0xAEB86F =

–5,326,737

Figure 48. Voltage Channel Datapath

Rev. A | Page 29 of 104

ADE7880

Data Sheet

Voltage Waveform Gain Registers

CHANGING PHASE VOLTAGE DATA PATH

There is a multiplier in the signal path of each phase voltage.

The voltage waveform can be changed by 100ꢀ by writing

a corresponding twos complement number to the 24-bit signed

voltage waveform gain registers (AVGAIN, BVGAIN, and

CVGAIN). For example, if 0x400000 is written to those registers,

the ADC output is scaled up by 50ꢀ. To scale the input by −50ꢀ,

write 0xC00000 to the registers. Equation 5 describes mathe-

matically the function of the current waveform gain registers.

The ADE7880 can direct one phase voltage input to the

computational data path of another phase. For example, Phase A

voltage can be introduced in the Phase B computational data path,

which means all powers computed by the ADE7880 in Phase B

are based on Phase A voltage and Phase B current.

Bits[9:8] (VTOIA[1:0]) of the CONFIG register manage the

Phase A voltage measured at the VAP pin. If VTOIA[1:0] = 00

(default value), the voltage is directed to the Phase A computa-

tional data path. If VTOIA[1:0] = 01, the voltage is directed to

the Phase B path. If VTOIA[1:0] = 10, the voltage is directed to the

Phase C path. If VTOIA[1:0] = 11, the ADE7880 behaves as if

VTOIA[1:0] = 00.

Voltage Waveform =

Contentof VoltageGainRegister

⎛

⎞

ADC Output× 1+

⎜

⎟

(5)

2²³

⎜

⎝

⎠

Changing the content of the AVGAIN, BVGAIN, and CVGAIN

registers affects all calculations based on its voltage; that is, it

affects the corresponding phase active/reactive/apparent energy

and voltage rms calculation. In addition, waveform samples are

scaled accordingly.

Bits[11:10] (VTOIB[1:0]) of the CONFIG register manage the

Phase B voltage measured at the VBP pin. If VTOIB[1:0] = 00

(default value), the voltage is directed to the Phase B computa-

tional data path. If VTOIB[1:0] = 01, the voltage is directed to

the Phase C path. If VTOIB[1:0] = 10, the voltage is directed to

the Phase A path. If VTOIB[1:0] = 11, the ADE7880 behaves

as if VTOIB[1:0] = 00.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words,

and the DSP works on 28 bits. As presented in Figure 43, the

AVGAIN, BVGAIN, and CVGAIN registers are accessed as

32-bit registers with four MSBs padded with 0s and sign

extended to 28 bits.

Bits[13:12] (VTOIC[1:0]) of the CONFIG register manage the

Phase C voltage measured at the VCP pin. If VTOIC[1:0] = 00

(default value), the voltage is directed to Phase C computational

data path, if VTOIC[1:0] = 01, the voltage is directed to the

Phase A path. If VTOIC[1:0] = 10, the voltage is directed to the

Phase B path. If VTOIC[1:0] = 11, the ADE7880 behaves as if

VTOIC[1:0] = 00.

Voltage Channel HPF

As explained in the Current Channel HPF section, the ADC

outputs can contain a dc offset that can create errors in power

and rms calculations. HPFs are placed in the signal path of the

phase voltages, similar to the ones in the current channels. Bit 0

(HPFEN) of CONFIG3 register can enable or disable the filters.

See the Current Channel HPF section for more details.

IA

PHASE A

COMPUTATIONAL

DATAPATH

APHCAL

BPHCAL

CPHCAL

VTOIA[1:0] = 01,

PHASE A VOLTAGE

DIRECTED

VA

IB

Voltage Channel Sampling

TO PHASE B

The waveform samples of the voltage channel are taken at the

output of HPF and stored into VAWV, VBWV, and VCWV 24-

bit signed registers at a rate of 8 kSPS. All power and rms

calculations remain uninterrupted during this process. Bit 17

(DREADY) in the STATUS0 register is set when the VAWV,

VBWV, and VCWV registers are available to be read using the

I²C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0

register enables an interrupt to be set when the DREADY flag is

set. See the Digital Signal Processor section for more details on

Bit DREADY.

PHASE B

COMPUTATIONAL

DATAPATH

VTOIB[1:0] = 01,

PHASE B VOLTAGE

DIRECTED

VB

IC

TO PHASE C

PHASE C

COMPUTATIONAL

DATAPATH

VTOIC[1:0] = 01,

PHASE C VOLTAGE

DIRECTED

VC

TO PHASE A

Figure 49. Phase Voltages Used in Different Datapaths

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

Similar to registers presented in Figure 44, the VAWV, VBWV,

and VCWV 24-bit signed registers are transmitted sign

extended to 32 bits.

Figure 49 presents the case in which the Phase A voltage is used

in the Phase B data path, the Phase B voltage is used in the Phase C

data path, and the Phase C voltage is used in the Phase A data path.

The ADE7880 contains an HSDC port especially designed to

provide fast access to the waveform sample registers. See the

HSDC Interface section for more details.

Rev. A | Page 30 of 104

Data Sheet

ADE7880

IRQ1

cleared and the

pin is set to high by writing to the STATUS1

POWER QUALITY MEASUREMENTS

Zero-Crossing Detection

register with the status bit set to 1.

Zero-Crossing Timeout

The ADE7880 has a zero-crossing (ZX) detection circuit on the

phase current and voltage channels. The neutral current data

path does not contain a zero-crossing detection circuit. Zero-

crossing events are used as a time base for various power quality

measurements and in the calibration process.

Every zero-crossing detection circuit has an associated timeout

register. This register is loaded with the value written into the

16-bit ZXTOUT register and is decremented (1 LSB) every

62.5 μs (16 kHz clock). The register is reset to the ZXTOUT

value every time a zero crossing is detected. The default value of

this register is 0xFFFF. If the timeout register decrements to 0

before a zero crossing is detected, one of Bits[8:3] of the STATUS1

register is set to 1. Bit 3 (ZXTOVA), Bit 4 (ZXTOVB), and Bit 5

(ZXTOVC) in the STATUS1 register refer to Phase A, Phase B,

and Phase C of the voltage channel; Bit 6 (ZXTOIA), Bit 7

(ZXTOIB), and Bit 8 (ZXTOIC) in the STATUS1 register refer

to Phase A, Phase B, and Phase C of the current channel.

The output of LPF1 is used to generate zero crossing events.

The low-pass filter is intended to eliminate all harmonics of

50 Hz and 60 Hz systems, and to help identify the zero-crossing

events on the fundamental components of both current and

voltage channels.

The digital filter has a pole at 80 Hz and is clocked at 256 kHz.

As a result, there is a phase lag between the analog input signal

(one of IA, IB, IC, VA, VB, and VC) and the output of LPF1.

The error in ZX detection is 0.0703° for 50 Hz systems (0.0843°

for 60 Hz systems). The phase lag response of LPF1 results in a

time delay of approximately 31.4° or 1.74 ms (at 50 Hz) between

its input and output. The overall delay between the zero crossing

on the analog inputs and ZX detection obtained after LPF1 is

about 39.6° or 2.2 ms (at 50 Hz). The ADC and HPF introduce

the additional delay. The LPF1 cannot be disabled to assure a

good resolution of the ZX detection. Figure 50 shows how the

zero-crossing signal is detected.

If a ZXTOIx or ZXTOVx bit is set in the MASK1 register, the

IRQ1

interrupt pin is driven low when the corresponding status bit

IRQ1

is set to 1. The status bit is cleared and the

high by writing to the STATUS1 register with the status bit set to 1.

pin is returned to

The resolution of the ZXOUT register is 62.5 μs (16 kHz clock)

per LSB. Thus, the maximum timeout period for an interrupt is

4.096 sec: 2¹⁶/16 kHz.

Figure 51 shows the mechanism of the zero-crossing timeout

detection when the voltage or the current signal stays at a fixed

dc level for more than 62.5 μs × ZXTOUT μs.

DSP

IA, IB, IC,

OR

VA, VB, VC

HPFEN BIT

CONFIG3[0]

REFERENCE

GAIN[23:0]

16-BIT INTERNAL

REGISTER VALUE

ZXTOUT

ZX

PGA

ADC

DETECTION

HPF

LPF1

39.6° OR 2.2ms @ 50Hz

1

0.855

ZX

0V

ZX

VOLTAGE

OR

CURRENT

SIGNAL

ZX

LPF1 OUTPUT

IA, IB, IC, IN

0V

OR

VA, VB, VC

Figure 50. Zero-Crossing Detection on Voltage and Current Channels

To provide further protection from noise, input signals to the

voltage channel with amplitude lower than 10ꢀ of full scale do

not generate zero-crossing events at all. The Current Channel ZX

detection circuit is active for all input signals independent of their

amplitudes.

ZXZOxy FLAG IN

STATUS1[31:0], x = V, A

y = A, B, C

IRQ1 INTERRUPT PIN

Figure 51. Zero-Crossing Timeout Detection

The ADE7880 contains six zero-crossing detection circuits, one

for each phase voltage and current channel. Each circuit drives

one flag in the STATUS1 register. If a circuit placed in the Phase

A voltage channel detects one zero-crossing event, Bit 9 (ZXVA)

in the STATUS1 register is set to 1.

Phase Sequence Detection

The ADE7880 has on-chip phase sequence error detection

circuits. This detection works on phase voltages and considers

only the zero crossings determined by their negative-to-positive

transitions. The regular succession of these zero-crossing events is

Phase A followed by Phase B followed by Phase C (see Figure 53).

If the sequence of zero-crossing events is, instead, Phase A followed

by Phase C followed by Phase B, then Bit 19 (SEQERR) in the

STATUS1 register is set.

Similarly, the Phase B voltage circuit drives Bit 10 (ZXVB), the

Phase C voltage circuit drives Bit 11 (ZXVC), and circuits placed

in the current channel drive Bit 12 (ZXIA), Bit 13 (ZXIB), and

Bit 14 (ZXIC) in the STATUS1 register. If a ZX detection bit is

IRQ1

set in the MASK1 register, the

interrupt pin is driven low

and the corresponding status flag is set to 1. The status bit is

Rev. A | Page 31 of 104

ADE7880

Data Sheet

If Bit 19 (SEQERR) in the MASK1 register is set to 1 and a

PHASE A

PHASE B

PHASE C

IRQ1

phase sequence error event is triggered, the

interrupt pin

IRQ1

is driven low. The status bit is cleared and the

pin is set

high by writing to the STATUS1 register with the Status Bit 19

(SEQERR) set to 1.

The phase sequence error detection circuit is functional only

when the ADE7880 is connected in a 3-phase, 4-wire, three voltage

sensors configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE

register, set to 00). In all other configurations, only two voltage

sensors are used; therefore, it is not recommended to use the

detection circuit. In these cases, use the time intervals between

phase voltages to analyze the phase sequence (see the Time

Interval Between Phases section for details).

ZX A

ZX B

ZX C

Figure 53. Regular Succession of Phase A, Phase B, and Phase C

When the ANGLESEL[1:0] bits are set to 00, the default value,

the delays between voltages and currents on the same phase are

measured. The delay between Phase A voltage and Phase A

current is stored in the 16-bit unsigned ANGLE0 register (see

Figure 54 for details). In a similar way, the delays between

voltages and currents on Phase B and Phase C are stored in the

ANGLE1 and ANGLE2 registers, respectively.

Figure 52 presents the case in which Phase A voltage is not

followed by Phase B voltage but by Phase C voltage. Every time

a negative-to-positive zero crossing occurs, Bit 19 (SEQERR) in

the STATUS1 register is set to 1 because such zero crossings on

Phase C, Phase B, or Phase A cannot come after zero crossings

from Phase A, Phase C, or respectively, Phase B zero crossings.

PHASE A

VOLTAGE

PHASE A

CURRENT

PHASE A

PHASE C

PHASE B

A, B, C PHASE

VOLTAGES AFTER

LPF1

ANGLE0

Figure 54. Delay Between Phase A Voltage and Phase A Current Is

Stored in the ANGLE0 Register

When the ANGLESEL[1:0] bits are set to 01, the delays between

phase voltages are measured. The delay between Phase A

voltage and Phase C voltage is stored into the ANGLE0 register.

The delay between Phase B voltage and Phase C voltage is

stored in the ANGLE1 register, and the delay between Phase A

voltage and Phase B voltage is stored in the ANGLE2 register

(see Figure 55 for details).

ZX A

ZX C

ZX B

BIT 19 (SEQERR) IN

STATUS1 REGISTER

IRQ1

STATUS1[19] SET TO 1

STATUS1[19] CANCELLED

BY A WRITE TO THE

STATUS1 REGISTER WITH

SEQERR BIT SET

When the ANGLESEL[1:0] bits are set to 10, the delays between

phase currents are measured. Similar to delays between phase

voltages, the delay between Phase A and Phase C currents is

stored into the ANGLE0 register, the delay between Phase B and

Phase C currents is stored in the ANGLE1 register, and the

delay between Phase A and Phase B currents is stored into the

ANGLE2 register (see Figure 55 for details).

Figure 52. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by

Phase C Voltage

Once a phase sequence error has been detected, the time

measurement between various phase voltages (see the Time

Interval Between Phases section) can help to identify which

phase voltage should be considered with another phase current

in the computational data path. Bits[9:8] (VTOIA[1:0]),

Bits[11:10] (VTOIB[1:0]), and Bits[13:12] (VTOIC[1:0]) in the

CONFIG register can be used to direct one phase voltage to the

data path of another phase. See the Changing Phase Voltage

Data path section for details.

PHASE A

PHASE B

PHASE C

Time Interval Between Phases

ANGLE2

ANGLE1

The ADE7880 has the capability to measure the time delay

between phase voltages, between phase currents, or between

voltages and currents of the same phase. The negative-to-positive

transitions identified by the zero-crossing detection circuit are

used as start and stop measuring points. Only one set of such

measurements is available at one time, based on Bits[10:9]

(ANGLESEL[1:0]) in the COMPMODE register.

ANGLE0

Figure 55. Delays Between Phase Voltages (Currents)

The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit

unsigned registers with 1 LSB corresponding to 3.90625 ꢂs

(256 kHz clock), which means a resolution of 0.0703° (360° ×

50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/

Rev. A | Page 32 of 104

Data Sheet

ADE7880

256 kHz) for 60 Hz systems. The delays between phase voltages

or phase currents are used to characterize how balanced the

load is. The delays between phase voltages and currents are

used to compute the power factor on each phase as shown in

the following Equation 6:

in STATUS1 register is set to 1 to indicate the condition and the bit

VSPHASE[0] in the PHSTATUS register is set back to 0.

Bits VSPHASE[1] and VSPHASE[2] relate to the sag events on

Phase B and Phase C in the same way: when Phase B or Phase C

voltage stays below SAGLVL, they are set to 1. When the phase

voltages are above SAGLVL, they are set to 0.

PHASE B VOLTAGE

360^o× f_LINE

⎡

⎤

⎥

⎦

cosφ_x= cos ANGLEx ×

(6)

⎢

256kHz

⎣

FULL SCALE

SAGLVL[23:0]

where f_LINE= 50 Hz or 60 Hz.

Period Measurement

The ADE7880 provides the period measurement of the line in

the voltage channel. The period of each phase voltage is

measured and stored in three different registers, APERIOD,

BPERIOD, and CPERIOD. The period registers are 16-bit

unsigned registers and update every line period. Because of the

LPF1 filter (see Figure 50), a settling time of 30 ms to 40 ms is

associated with this filter before the measurement is stable.

SAGCYC[7:0] = 0x4

PHASE A VOLTAGE

STATUS1[16] CANCELLED BY

A WRITE TO STATUS1[31:0]

WITH SAG BIT SET

SAGCYC[7:0] = 0x4

The period measurement has a resolution of 3.90625 ꢂs/LSB

(256 kHz clock), which represents 0.0195ꢀ (50 Hz/256 kHz)

when the line frequency is 50 Hz and 0.0234ꢀ (60 Hz/256 kHz)

when the line frequency is 60 Hz. The value of the period registers

for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and

for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The

length of the registers enables the measurement of line frequencies

as low as 3.9 Hz (256 kHz/2¹⁶). The period registers are stable at

1 LSB when the line is established and the measurement does

not change.

BIT 16 (SAG) IN

STATUS[16] SET TO 1

STATUS1[31:0]

IRQ1 PIN GOES HIGH

BECAUSE STATUS1[16]

CANCELLED BY A WRITE

TO STATUS[31:0] WITH SAG

BIT SET

IRQ1 PIN

PHSTATUS[12] SET TO 1

BECAUSE PHASE A

VOLTAGE WAS BELOW

SAGLVL FOR SAGCYC

HALF LINE CYCLES

VSPHASE[0] =

PHSTATUS[12]

PHSTATUS[12] CLEARED

TO 0 BECAUSE PHASE A

VOLTAGE WAS ABOVE

SAGLVL FOR SAGCYC

HALF LINE CYCLES

VSPHASE[1] =

PHSTATUS[13]

PHSTATUS[13] SET TO 1

The following equations can be used to compute the line period

and frequency using the period registers:

Figure 56. SAG Detection

The SAGCYC register represents the number of half-line cycles

the phase voltage must remain below or above the level indicated

in the SAGLVL register to trigger a SAG interrupt ; 0 is not a

valid number for SAGCYC. For example, when the SAG cycle

(SAGCYC[7:0]) contains 0x07, the SAG flag in the STATUS1

register is set at the end of the seventh half line cycle for which

the line voltage falls below the threshold. If Bit 16 (SAG) in

PERIOD[15:0]

T_L=

f_L=

[

sec

]

(7)

(8)

256E3

[Hz]

PERIOD[15:0]

Phase Voltage Sag Detection

IRQ1

MASK1 is set, the

interrupt pin is driven low in case of a

The ADE7880 can be programmed to detect when the absolute

value of any phase voltage drops below or grows above a certain

peak value for a number of half-line cycles. The phase where

this event takes place and the state of the phase voltage relative

to the threshold is identified in Bits[14:12] (VSPHASE[x]) of

the PHSTATUS register. An associated interrupt is triggered

when any phase drops below or grows above a threshold. This

condition is illustrated in Figure 56.

SAG event in the same moment the Status Bit 16 (SAG) in

STATUS1 register is set to 1. The SAG status bit in the STATUS1

IRQ1

register and the

pin is returned to high by writing to the

STATUS1 register with the status bit set to 1.

When the Phase B voltage falls below the indicated threshold

into the SAGLVL register for two line cycles, Bit VSPHASE[1]

in the PHSTATUS register is set to 1 (see Figure 56). Simultane-

ously, Bit 16 (SAG) in the STATUS1 register is set to 1 to indicate

the condition.

Figure 56 shows Phase A voltage falling below a threshold that

is set in the SAG level register (SAGLVL) for four half-line cycles

(SAGCYC = 4). When Bit 16 (SAG) in the STATUS1 register is set

to 1 to indicate the condition, Bit VSPHASE[0] in the PHSTATUS

register is also set to 1 because the phase A voltage is below

SAGLVL. The microcontroller then writes back STATUS1 register

Note that the internal zero-crossing counter is always active. By

setting the SAGLVL register, the first SAG detection result is,

therefore, not executed across a full SAGCYC period. Writing to

the SAGCYC register when the SAGLVL register is already initia-

lized resets the zero-crossing counter, thus ensuring that the first

SAG detection result is obtained across a full SAGCYC period.

IRQ1

with Bit 16 (SAG) set to 1 to erase the bit and bring

interrupt

pin back high. Then the phase A voltage stays above the SAGLVL

threshold for four half-line cycles (SAGCYC = 4). The Bit 16 (SAG)

Rev. A | Page 33 of 104

ADE7880

Data Sheet

IPPHASE/VPPHASE BITS

27 26 25 24 23

The recommended procedure to manage SAG events is the

following:

31

00000

0

24-BIT UNSIGNED NUMBER

1. Enable SAG interrupts in the MASK1 register by setting

Bit 16 (SAG) to 1.

PEAK DETECTED

ON PHASE C

PEAK DETECTED

ON PHASE A

IRQ1

2. When a SAG event happens, the

interrupt pin goes

PEAK DETECTED

ON PHASE B

low and Bit 16 (SAG) in the STATUS1 is set to 1.

3. The STATUS1 register is read with Bit 16 (SAG) set to 1.

4. The PHSTATUS register is read, identifying on which

phase or phases a SAG event happened.

5. The STATUS1 register is written with Bit 16 (SAG) set to 1.

Immediately, the SAG bit is erased.

Figure 58. Composition of IPEAK[31:0] and VPEAK[31:0] Registers

PEAK VALUE WRITTEN INTO

IPEAK AT THE END OF FIRST

PEAKCYC PERIOD

END OF FIRST

PEAKCYC = 16 PERIOD

END OF SECOND

PEAKCYC = 16 PERIOD

SAG Level Set

The content of the SAGLVL[23:0] SAG level register is compared

to the absolute value of the output from HPF. Writing 5,928,256

(0x5A7540) to the SAGLVL register, puts the SAG detection

level at full scale (see the Voltage Channel ADC section), thus;

the SAG event is triggered continuously. Writing 0x00 or 0x01

puts the SAG detection level at 0, therefore, the SAG event is

never triggered.

PHASE A

CURRENT

BIT 24 OF IPEAK

CLEARED TO 0 AT

THE END OF SECOND

PEAKCYC PERIOD

BIT 24

OF IPEAK

31

24 23

0

0000 0000

24-BIT NUMBER

PHASE B

CURRENT

Figure 57. SAGLVL Register Transmitted as a 32-Bit Word

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

The SAGLVL register is accessed as a 32-bit register with eight

MSBs padded with 0s. See Figure 57 for details.

BIT 25 OF IPEAK

SET TO 1 AT THE

END OF SECOND

PEAKCYC PERIOD

PEAK VALUE WRITTEN INTO

IPEAK AT THE END OF

SECOND PEAKCYC PERIOD

BIT 25

OF IPEAK

Peak Detection

Figure 59. Peak Level Detection

The ADE7880 records the maximum absolute values reached by

the voltage and current channels over a certain number of half-

line cycles and stores them into the less significant 24 bits of the

VPEAK and IPEAK 32-bit registers.

Figure 59 shows how the ADE7880 records the peak value on the

current channel when measurements on Phase A and Phase B are

enabled (Bit PEAKSEL[2:0] in the MMODE register are 011).

PEAKCYC is set to 16, meaning that the peak measurement

cycle is four line periods. The maximum absolute value of Phase A

is the greatest during the first four line periods (PEAKCYC = 16),

so the maximum absolute value is written into the less signifi-

cant 24 bits of the IPEAK register, and Bit 24 (IPPHASE[0]) of

the IPEAK register is set to 1 at the end of the period. This bit

remains at 1 for the duration of the second PEAKCYC period of

four line cycles. The maximum absolute value of Phase B is the

greatest during the second PEAKCYC period; therefore, the

maximum absolute value is written into the less significant

24 bits of the IPEAK register, and Bit 25 (IPPHASE[1]) in the

IPEAK register is set to 1 at the end of the period.

The PEAKCYC register contains the number of half-line cycles

used as a time base for the measurement. The circuit uses the

zero-crossing points identified by the zero-crossing detection

circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE register select

the phases upon which the peak measurement is performed. Bit 2

selects Phase A, Bit 3 selects Phase B, and Bit 4 selects Phase C.

Selecting more than one phase to monitor the peak values

decreases proportionally the measurement period indicated in

the PEAKCYC register because zero crossings from more

phases are involved in the process. When a new peak value is

determined, one of Bits[26:24] (IPPHASE[2:0] or VPPHASE[2:0])

in the IPEAK and VPEAK registers is set to 1, identifying the

phase that triggered the peak detection event. For example, if a

peak value has been identified on Phase A current, Bit 24

(IPPHASE[0]) in the IPEAK register is set to 1. If next time a

new peak value is measured on Phase B, Bit 24 (IPPHASE[0])

of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1])

of the IPEAK register is set to 1. Figure 58 shows the

At the end of the peak detection period in the current channel,

Bit 23 (PKI) in the STATUS1 register is set to 1. If Bit 23 (PKI)

IRQ1

in the MASK1 register is set, the

interrupt pin is driven low

at the end of the PEAKCYC period, and Status Bit 23 (PKI) in

the STATUS1 register is set to 1. In a similar way, at the end of

the peak detection period in the voltage channel, Bit 24 (PKV) in

the STATUS1 register is set to 1. If Bit 24 (PKV) in the MASK1

composition of the IPEAK and VPEAK registers.

IRQ1

register is set, the

interrupt pin is driven low at the end of

PEAKCYC period and Status Bit 24 (PKV) in the STATUS1

Rev. A | Page 34 of 104

Data Sheet

ADE7880

register is set to 1. To find the phase that triggered the interrupt,

one of either the IPEAK or VPEAK registers is read immediately

after reading the STATUS1 register. Next, the status bits are

Whenever the absolute instantaneous value of the voltage goes

above the threshold from the OVLVL register, Bit 18 (OV) in

the STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS

register are set to 1. Bit 18 (OV) of the STATUS1 register and

Bit 9 (OVPHASE[0]) in the PHSTATUS register are cancelled

when the STATUS1 register is written with Bit 18 (OV) set to 1.

IRQ1

cleared, and the

pin is set to high by writing to the

STATUS1 register with the status bit set to 1.

Note that the internal zero-crossing counter is always active. By

setting Bits[4:2] (PEAKSEL[2:0]) in the MMODE register, the

first peak detection result is, therefore, not executed across a full

PEAKCYC period. Writing to the PEAKCYC register when the

PEAKSEL[2:0] bits are set resets the zero-crossing counter,

thereby ensuring that the first peak detection result is obtained

across a full PEAKCYC period.

The recommended procedure to manage overvoltage events is

the following:

1. Enable OV interrupts in the MASK1 register by setting

Bit 18 (OV) to 1.

IRQ1

2. When an overvoltage event happens, the

pin goes low.

interrupt

Overvoltage and Overcurrent Detection

3. The STATUS1 register is read with Bit 18 (OV) set to 1.

4. The PHSTATUS register is read, identifying on which

phase or phases an overvoltage event happened.

5. The STATUS1 register is written with Bit 18 (OV) set to 1.

In this moment, Bit OV is erased and also all Bits[11:9]

(OVPHASE[2:0]) of the PHSTATUS register.

The ADE7880 detects when the instantaneous absolute value

measured on the voltage and current channels becomes greater

than the thresholds set in the OVLVL and OILVL 24-bit

unsigned registers. If Bit 18 (OV) in the MASK1 register is set,

IRQ1

the

interrupt pin is driven low in case of an overvoltage

IRQ1

event. There are two status flags set when the

interrupt

In case of an overcurrent event, if Bit 17 (OI) in the MASK1

pin is driven low: Bit 18 (OV) in the STATUS1 register and one

of Bits[11:9] (OVPHASE[2:0]) in the PHSTATUS register to

identify the phase that generated the overvoltage. The Status

Bit 18 (OV) in the STATUS1 register and all Bits[11:9]

IRQ1

register is set, the

interrupt pin is driven low. Immediately,

Bit 17 (OI) in the STATUS1 register and one of Bits[5:3]

(OIPHASE[2:0]) in the PHSTATUS register, which identify

the phase that generated the interrupt, are set. To find the

phase that triggered the interrupt, the PHSTATUS register

is read immediately after reading the STATUS1 register. Next,

Status Bit 17 (OI) in the STATUS1 register and Bits[5:3]

(OIPHASE[2:0]) in the PHSTATUS register are cleared and the

(OVPHASE[2:0]) in the PHSTATUS register are cleared, and

IRQ1

the

pin is set to high by writing to the STATUS1 register

with the status bit set to 1. Figure 60 presents overvoltage

detection in the Phase A voltage.

PHASE A

VOLTAGE CHANNEL

IRQ1

pin is set to high by writing to the STATUS1 register with

OVERVOLTAGE

DETECTED

the status bit set to 1. The process is similar with overvoltage

detection.

OVLVL[23:0]

Overvoltage and Overcurrent Level Set

The content of the overvoltage (OVLVL), and overcurrent,

(OILVL) 24-bit unsigned registers is compared to the absolute

value of the voltage and current channels. The maximum value of

these registers is the maximum value of the HPF outputs:

+5,326,737 (0x514791). When the OVLVL or OILVL register is

equal to this value, the overvoltage or overcurrent conditions

are never detected. Writing 0x0 to these registers signifies the

overvoltage or overcurrent conditions are continuously

detected, and the corresponding interrupts are permanently

triggered.

BIT 18 (OV) OF

STATUS1

STATUS1[18] AND

PHSTATUS[9]

CANCELLED BY A

WRITE OF STATUS1

WITH OV BIT SET.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

Similar to the register presented in Figure 57, OILVL and

OVLVL registers are accessed as 32-bit registers with the eight

MSBs padded with 0s.

BIT 9 (OVPHASE)

OF PHSTATUS

Figure 60. Overvoltage Detection

Rev. A | Page 35 of 104

ADE7880

Data Sheet

Neutral Current Mismatch

ISUMLVL, the positive threshold used in the process, is a 24-bit

signed register. Because it is used in a comparison with an

absolute value, always set ISUMLVL as a positive number,

somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses

the same scale of the current ADCs outputs, so writing

+5,326,737 (0x514791) to the ISUMLVL register puts the

mismatch detection level at full scale; see the Current Channel

ADC section for details. Writing 0x000000, the default value, or

a negative value, signifies the MISMTCH event is always triggered.

The right value for the application should be written into the

ISUMLVL register after power-up or after a hardware/software

reset to avoid continuously triggering MISMTCH events.

In 3-phase systems, the neutral current is equal to the algebraic

sum of the phase currents

I_N(t) = I_A(t) + I_B(t) + I_C(t)

If there is a mismatch between these two quantities, then a

tamper situation may have occurred in the system.

The ADE7880 computes the sum of the phase currents adding

the content of the IAWV, IBWV, and ICWV registers, and

storing the result into the ISUM 28-bit signed register: I_SUM(t) =

I_A(t) + I_B(t) + I_C(t). ISUM is computed every 125 μs (8 kHz

frequency), the rate at which the current samples are available,

and Bit 17 (DREADY) in the STATUS0 register is used to signal

when the ISUM register can be read. See the Digital Signal

Processor section for more details on Bit DREADY.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. As presented in Figure 61, ISUM,

the 28-bit signed register, is accessed as a 32-bit register with the

four most significant bits padded with 0s.

To recover I_SUM(t) value from the ISUM register, use the

following equation:

31

28 27

0

ISUM[27:0]

ADC_MAX

0000

28-BIT SIGNED NUMBER

I

_SUM(t) =

×I_FS

BIT 27 IS A SIGN BIT

where:

Figure 61. The ISUM[27:0] Register is Transmitted As a 32-Bit Word

ADC_MAX= 5,928,256, the ADC output when the input is at full

scale.

Similar to the registers presented in Figure 43, the ISUMLVL

register is accessed as a 32-bit register with four most significant

bits padded with 0s and sign extended to 28 bits.

I

_FSis the full-scale ADC phase current.

Note that the ADE7880 also computes the rms of ISUM and

stores it into NIRMS register when Bit 2 (INSEL) in CONFIG3

register is set to 1 (see Current RMS Calculation section for

details).

PHASE COMPENSATION

As described in the Current Channel ADC and Voltage Channel

ADC sections, the data path for both current and voltages is the

same. The phase error between current and voltage signals

introduced by the ADE7880 is negligible. However, the ADE7880

must work with transducers that may have inherent phase

errors. For example, a current transformer (CT) with a phase

error of 0.1° to 3° is not uncommon. These phase errors can

vary from part to part, and they must be corrected to perform

accurate power calculations.

The ADE7880 computes the difference between the absolute

values of ISUM and the neutral current from the INWV

register, take its absolute value and compare it against the

ISUMLVL threshold.

If

ISUM − INWV ≤ ISUMLVL

,

then it is assumed that the neutral current is equal to the sum

of the phase currents, and the system functions correctly.

The errors associated with phase mismatch are particularly

noticeable at low power factors. The ADE7880 provides a

means of digitally calibrating these small phase errors. The

ADE7880 allows a small time delay or time advance to be

introduced into the signal processing chain to compensate for

the small phase errors.

If

ISUM − INWV > ISUMLVL

,

then a tamper situation may have occurred, and Bit 20

(MISMTCH) in the STATUS1 register is set to 1. An interrupt

attached to the flag can be enabled by setting Bit 20

The phase calibration registers (APHCAL, BPHCAL, and

CPHCAL) are 10-bit registers that can vary the time advance

in the voltage channel signal path from −374.0 μs to +61.5 ꢂs.

Negative values written to the PHCAL registers represent a time

advance whereas positive values represent a time delay. One LSB

is equivalent to 0.976 μs of time delay or time advance (clock

rate of 1.024 MHz). With a line frequency of 60 Hz, this gives

a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the

fundamental. This corresponds to a total correction range of

−8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is

IRQ1

(MISMTCH) in the MASK1 register. If enabled, the

set low when Status Bit MISMTCH is set to 1. The status bit is

IRQ1

pin is

cleared and the

pin is set back to high by writing to the

STATUS1 register with Bit 20 (MISMTCH) set to 1.

If ISUM − INWV ≤ ISUMLVL , then MISMTCH = 0

If ISUM − INWV > ISUMLVL , then MISMTCH = 1

Rev. A | Page 36 of 104

Data Sheet

ADE7880

−6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/

1.024 MHz).

Figure 63 illustrates how the phase compensation is used to

remove x = −1° phase lead in IA of the current channel from the

external current transducer (equivalent of 55.5 μs for 50 Hz

systems). To cancel the lead (1°) in the current channel of

Phase A, a phase lead must be introduced into the corresponding

voltage channel. Using Equation 8, APHCAL is 57 least

significant bits, rounded up from 56.8. The phase lead is

achieved by introducing a time delay of 55.73 μs into the Phase

A current.

Given a phase error of x degrees, measured using the phase

voltage as the reference, the corresponding LSBs are computed

dividing x by the phase resolution (0.0211°/LSB for 60 Hz and

0.0176°/LSB for 50 Hz). Results between −383 and +63 only are

acceptable; numbers outside this range are not accepted. If the

current leads the voltage, the result is negative and the absolute

value is written into the PHCAL registers. If the current lags the

voltage, the result is positive and 512 is added to the result

before writing it into xPHCAL.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words. As

shown in Figure 62, APHCAL, BPHCAL, and CPHCAL 10-bit

registers are accessed as 16-bit registers with the six MSBs padded

with 0s.

APHCAL, BPHCAL, or CPHCAL

⎧

⎫

x

,x ≤ 0

⎪

⎨

⎪

⎬

phase _resolution

x

phase _resolution

15

10

9

0

=

(9)

0000 00

xPHCAL

⎪

+ 512,x > 0

⎪

⎩

⎪

⎭

Figure 62. xPHCAL Registers Communicated As 16-Bit Registers

IAP

IA

PGA1

ADC

IAN

PHASE

CALIBRATION

APHCAL = 57

VAP

VA

PGA3

VN

1°

IA

PHASE COMPENSATION

ACHIEVED DELAYING

IA BY 56µs

VA

50Hz

Figure 63. Phase Calibration on Voltage Channels

Rev. A | Page 37 of 104

ADE7880

Data Sheet

values. Next, write the last register in the queue two additional

times to flush the pipeline and then write the Run register with

0x0001. In this way, the DSP starts the computations from a

desired configuration.

REFERENCE CIRCUIT

The nominal reference voltage at the REF_IN/OUTpin is 1.2

0.075ꢀ V. This is the reference voltage used for the ADCs in

the ADE7880. The REF_IN/OUTpin can be overdriven by an

external source, for example, an external 1.2 V reference.

The voltage of the ADE7880 reference drifts slightly with

temperature; see the Specifications section for the temperature

coefficient specification (in ppm/°C). The value of the temperature

drift varies from part to part. Because the reference is used for

all ADCs, any x percentage drift in the reference results in a 2×

percentage deviation of the meter accuracy. The reference drift

resulting from temperature changes is usually very small and

typically much smaller than the drift of other components on a

meter. Alternatively, the meter can be calibrated at multiple

temperatures.

To protect the integrity of the data stored in the data memory

RAM of the DSP (between Address 0x4380 and Address

0x43BE), a write protection mechanism is available. By default,

the protection is disabled and registers placed between 0x4380

and 0x43BE can be written without restriction. When the

protection is enabled, no writes to these registers is allowed.

Registers can be always read, without restriction, independent

of the write protection state. To enable the protection, write

0xAD to an internal 8-bit register located at address 0xE7FE,

followed by a write of 0x80 to an internal 8-bit register located

at Address 0xE7E3. To disable the protection, write 0xAD to an

internal 8-bit register located at Address 0xE7FE, followed by a

write of 0x00 to an internal 8-bit register located at Address

0xE7E3. It is recommended to enable the write protection

before starting the DSP. If any data memory RAM based register

needs to be changed, simply disable the protection, change the

value and then enable back the protection. There is no need to

stop the DSP in order to change these registers.

If Bit 0 (EXTREFEN) in the CONFIG2 register is cleared to 0 (the

default value), the ADE7880 uses the internal voltage reference.

If the bit is set to 1, the external voltage reference is used. Set the

CONFIG2 register during the PSM0 mode. Its value is maintained

during the PSM1, PSM2, and PSM3 power modes.

DIGITAL SIGNAL PROCESSOR

The ADE7880 contains a fixed function digital signal processor

(DSP) that computes all powers and rms values. It contains

program memory ROM and data memory RAM.

The recommended procedure to initialize the registers located

in the data memory RAM is:

•

Initialize all registers. Write the last register in the queue

three times to ensure its value was written into the RAM.

All the other registers of the ADE7880 should also be

initialized here.

The program used for the power and rms computations is

stored in the program memory ROM and the processor executes

it every 8 kHz. The end of the computations is signaled by

setting Bit 17 (DREADY) to 1 in the STATUS0 register. An

interrupt attached to this flag can be enabled by setting Bit 17

•

Enable the write protection by writing 0xAD to an internal

8-bit register located at Address 0xE7FE, followed by a write

of 0x80 to an internal 8-bit register located at Address 0xE7E3.

IRQ0

(DREADY) in the MASK0 register. If enabled, the

set low and Status Bit DREADY is set to 1 at the end of the

IRQ0

pin is

computations. The status bit is cleared and the

pin is set

•

Read back all data memory RAM registers to ensure they

were initialized with the desired values.

to high by writing to the STATUS0 register with Bit 17 (DREADY)

set to 1.

In the remote case one or more registers are not initialized

correctly, disable the protection by writing 0xAD to an

internal 8-bit register located at Address 0xE7FE, followed

by a write of 0x00 to an internal 8-bit register located at

Address 0xE7E3. Initialize again the registers. Write the

last register in the queue three times. Enable the write

protection by writing 0xAD to an internal 8-bit register

located at Address 0xE7FE, followed by a write of 0x80 to

an internal 8-bit register located at Address 0xE7E3.

The registers used by the DSP are located in the data memory

RAM, at addresses between 0x4380 and 0x43BE. The width of

this memory is 28 bits. A two-stage pipeline is used when write

operations to the data memory RAM are executed. This means

two things: when only one register needs to be initialized, write

it two more times to ensure the value has been written into

RAM. When two or more registers need to be initialized, write

the last register in the queue two more times to ensure the value

has been written into RAM.

•

Start the DSP by setting Run = 1.

As explained in the Power-Up Procedure section, at power-up

or after a hardware or software reset, the DSP is in idle mode.

No instruction is executed. All the registers located in the data

memory RAM are initialized at 0, their default values and they

can be read/written without any restriction. The Run register,

used to start and stop the DSP, is cleared to 0x0000. The Run

register needs to be written with 0x0001 for the DSP to start

code execution. It is recommended to first initialize all ADE7880

registers located in the data memory RAM with their desired

There is no obvious reason to stop the DSP if the ADE7880 is

maintained in PSM0 normal mode. All ADE7880 registers,

including ones located in the data memory RAM, can be

modified without stopping the DSP. However, to stop the DSP,

0x0000 has to be written into Run register. To restart the DSP,

one of the following procedures must be followed:

Rev. A | Page 38 of 104

Data Sheet

ADE7880

After the LPF and the execution of the square root, the rms

value of f(t) is obtained by

•

If the ADE7880 registers located in the data memory RAM

have not been modified, write 0x0001 into the Run register to

start the DSP.

If the ADE7880 registers located in the data memory RAM

have to be modified, first execute a software or a hardware

reset, initialize all ADE7880 registers at desired values,

enable the write protection and then write 0x0001 into the

Run register to start the DSP.

∞

F²

(14)

F =

•

∑

k

k=1

The rms calculation based on this method is simultaneously

processed on all seven analog input channels. Each result is

available in the 24-bit registers: AIRMS, BIRMS, CIRMS,

AVRMS, BVRMS, CVRMS, and NIRMS.

As mentioned in the Power Management section, when the

ADE7880 switch out of PSM0 power mode, it is recommended to

stop the DSP by writing 0x0000 into the Run register (see Table 10

and Table 11 for the recommended actions when changing

power modes).

The second method computes the absolute value of the input

signal and then filters it to extract its dc component. It computes

the absolute mean value of the input. If the input signal in

Equation 12 has a fundamental component only, its average

value is

ROOT MEAN SQUARE MEASUREMENT

T

2

⎡

⎢

⎤

⎥

Root mean square (rms) is a measurement of the magnitude of

an ac signal. Its definition can be both practical and mathematical.

Defined practically, the rms value assigned to an ac signal is the

amount of dc required to produce an equivalent amount of

power in the load. Mathematically, the rms value of a conti-

nuous signal f(t) is defined as

T

1

T

F_DC

=

2 ×F₁×sin(ωt)dt − 2 ×F ×sin(ωt)dt

∫

1

T

0

⎢

⎣

⎥

⎦

2

π

F_DC

=

× 2 × F₁

The calculation based on this method is simultaneously processed

only on the three phase currents. Each result is available in the

20-bit registers AIMAV, BMAV, and CMAV. Note that the

proportionality between mav and rms values is maintained for

the fundamental components only. If harmonics are present in the

current channel, the mean absolute value is no longer

proportional to rms.

1

t

F rms =

^tf ²

(

t

)

dt

(10)

∫

0

For time sampling signals, rms calculation involves squaring the

signal, taking the average, and obtaining the square root.

N

1

N

f ²

[n]

(11)

F rms =

∑

N =1

Current RMS Calculation

Equation 10 implies that for signals containing harmonics, the

rms calculation contains the contribution of all harmonics, not

only the fundamental. The ADE7880 uses two different methods

to calculate rms values. The first one is very accurate and is active

only in PSM0 mode. The second one is less accurate, uses the

estimation of the mean absolute value (mav) measurement, is

active in PSM0 and PSM1 modes.

This section presents the first approach to compute the rms

values of all phase and neutral currents. The ADE7880 also

computes the rms of the sum of the instantaneous values of the

phase currents if Bit 2 (INSEL) in the CONFIG3 register is set

to 1. Note that the instantaneous value of the sum is stored into

ISUM register presented in the Neutral Current Mismatch

section. In 3-phase four wired systems that only require sensing

the phase currents, this value provides a measure of the neutral

current.

The ADE7880 also computes the rms values of various

fundamental and harmonic components of phase currents,

phase voltages and neutral current as part of the harmonic

calculations block. Refer to Harmonics Calculations section for

details.

Figure 65 shows the detail of the signal processing chain for the

rms calculation on one of the phases of the current channel.

The current channel rms value is processed from the samples

used in the current channel. The current rms values are signed

24-bit values and they are stored into the AIRMS, BIRMS, CIRMS,

NIRMS registers. The update rate of the current rms measurement

is 8 kHz. If Bit 2 (INSEL) of the CONFIG3 register is 0 (default),

the NIRMS register contains the rms value of the neutral

current. If the INSEL bit is 1, the NIRMS register contains the

rms value of the sum of the instantaneous values of the phase

currents.

The first method is to low-pass filter the square of the input

signal (LPF) and take the square root of the result (see Figure 65).

∞

f (t) =

F

2 sin

(kωt + γ_k

)

If

(12)

∑

k

k=1

then,

∞

f ²(t) = F²− F²cos(2kωt + 2 γ ) +

∑

k=1

k

k=1

∞

(13)

With the specified full-scale analog input signal of 0.5 V, the

ADC produces an output code that is approximately 5,326,737.

The equivalent rms value of a full-scale sinusoidal signal is

3,766,572 (0x39792C), independent of the line frequency. If

+ 2 2× F × F sin

(

kωt + γ_k

)

×sin

(mωt + γ_m

)

∑

m

k

k,m=1

k≠m

Rev. A | Page 39 of 104

ADE7880

Data Sheet

the integrator is enabled, that is, when Bit 0 (INTEN) in the

CONFIG register is set to 1, the equivalent rms value of a full-

scale sinusoidal signal at 50 Hz is 3,759,718 (0x395E66) and at

60 Hz is 3,133,207 (0x2FCF17).

Table 12. Settling Time for I RMS Measurement

Integrator Status 50 Hz Input Signals 60 Hz Input Signals

Integrator Off

Integrator On

580 ms

700 ms

580 ms

700 ms

The accuracy of the current rms is typically 0.1ꢀ error from

the full-scale input down to 1/1000 of the full-scale input when

PGA = 1. Additionally, this measurement has a bandwidth of

3.3 kHz. It is recommended to read the rms registers synchronous

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

Similar to the register presented in Figure 64, the AIRMS,

BIRMS, CIRMS, NIRMS 24-bit signed registers are accessed as

32-bit registers with the eight MSBs padded with 0s.

IRQ1

to the voltage zero crossings to ensure stability. The

inter-

rupt can be used to indicate when a zero crossing has occurred

(see the Interrupts section). Table 12 shows the settling time for

the I rms measurement, which is the time it takes for the rms

register to reflect the value at the input to the current channel

when starting from 0.

31

24 23

0

0000 0000

24-BIT NUMBER

Figure 64. 24-Bit AIRMS, BIRMS, CIRMS and NIRMS Registers Transmitted as

32-Bit Words

xIRMSOS[23:0]

7

2

CURRENT SIGNAL FROM

2

HPF OR INTEGRATOR

(IF ENABLED)

x

xIRMS[23:0]

LPF

0x514791 =

5,326,737

0V

0xAEB86F =

–5,326,737

Figure 65. Current RMS Signal Processing

Rev. A | Page 40 of 104

Data Sheet

ADE7880

212000

Current RMS Offset Compensation

211500

211000

210500

210000

209500

209000

208500

208000

207500

The ADE7880 incorporates a current rms offset compensation

register for each phase: AIRMSOS, BIRMSOS, CIRMSOS, and

NIRMSOS. These are 24-bit signed registers that are used to

remove offsets in the current rms calculations. An offset can

exist in the rms calculation due to input noises that are

integrated in the dc component of I²(t). One LSB of the current

rms offset compensation register is equivalent to one LSB of the

current rms register. Assuming that the maximum value from the

current rms calculation is 3,766,572 with full-scale ac inputs

(50 Hz), one LSB of the current rms offset represents 0.00045ꢀ

207000

⎛

⎜

⎝

⎞

⎠

3767²+128 /3767−1 ×100

45

50

55

60

65

⎟

FREQUENCY (Hz)

Figure 67. xIMAV Register Values at Full Scale, 45 Hz to 65 Hz Line

Frequencies

of the rms measurement at 60 dB down from full scale. Conduct

offset calibration at low current; avoid using currents equal to

zero for this purpose.

The mav values of full-scale sinusoidal signals of 50 Hz and

60 Hz are 209,686 and 210,921, respectively. As seen in Figure 67,

there is a 1.25ꢀ variation between the mav estimate at 45 Hz

and the one at 65 Hz for full-scale sinusoidal inputs. The accuracy

of the current mav is typically 0.5ꢀ error from the full-scale

input down to 1/100 of the full-scale input. Additionally, this

measurement has a bandwidth of 3.3 kHz. The settling time for

the current mav measurement, that is the time it takes for the

mav register to reflect the value at the input to the current

channel within 0.5ꢀ error, is 500 ms.

I rms = I rms₀²+128×IRMSOS

(15)

where I rms₀is the rms measurement without offset correction.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to the register presented

in Figure 43, the AIRMSOS, BIRMSOS, CIRMSOS, and

NIRMSOS 24-bit signed registers are accessed as 32-bit registers

with four MSBs padded with 0s and sign extended to 28 bits.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

As presented in Figure 68, the AIMAV, BIMAV, and CIMAV 20-

bit unsigned registers are accessed as 32-bit registers with the 12

MSBs padded with 0s.

Current Mean Absolute Value Calculation

This section presents the second approach to estimate the rms

values of all phase currents using the mean absolute value (mav)

method. This approach is used in PSM1 mode, to allow energy

accumulation based on current rms values when the missing

neutral case demonstrates to be a tamper attack. This data path

is active also in PSM0 mode to allow for its gain calibration.

The gain is used in the external microprocessor during PSM1

mode. The mav value of the neutral current is not computed

using this method. Figure 66 shows the details of the signal

processing chain for the mav calculation on one of the phases of

the current channel.

31

20 19

0

0000 0000 0000

20-BIT UNSIGNED NUMBER

Figure 68. xIMAV Registers Transmitted as 32-Bit Registers

Current MAV Gain and Offset Compensation

The current rms values stored in the AIMAV, BIMAV, and

CIMAV registers can be calibrated using gain and offset

coefficients corresponding to each phase. It is recommended to

calculate the gains in PSM0 mode by supplying the ADE7880

with nominal currents. The offsets can be estimated by

supplying the ADE7880 with low currents, usually equal to the

minimum value at which the accuracy is required. Every time

the external microcontroller reads the AIMAV, BIMAV, and

CIMAV registers, it uses these coefficients stored in its memory

to correct them.

CURRENT SIGNAL

COMING FROM ADC

xIMAV[23:0]

|X|

HPF

Figure 66. Current MAV Signal Processing for PSM1 Mode

The current channel mav value is processed from the samples

used in the current channel waveform sampling mode. The

samples are passed through a high-pass filter to eliminate the

eventual dc offsets introduced by the ADCs and the absolute

values are computed. The outputs of this block are then filtered

to obtain the average. The current mav values are unsigned 20-bit

values and they are stored in the AIMAV, BIMAV, and CIMAV

registers. The update rate of this mav measurement is 8 kHz.

Rev. A | Page 41 of 104

ADE7880

Data Sheet

Voltage Channel RMS Calculation

this measurement has a bandwidth of 3.3 kHz. It is

recommended to read the rms registers synchronous to the

IRQ1

can be used to indicate when a zero crossing has occurred (see

the Interrupts section).

Figure 69 shows the detail of the signal processing chain for the

rms calculation on one of the phases of the voltage channel. The

voltage channel rms value is processed from the samples used in

the voltage channel. The voltage rms values are signed 24-bit

values and they are stored into the Registers AVRMS, BVRMS,

and CVRMS. The update rate of the current rms measurement

is 8 kHz.

voltage zero crossings to ensure stability. The

interrupt

The V rms measurement settling time is 580 ms for both 50 Hz

and 60 Hz input signals. The V rms measurement settling time

is the time it takes for the rms register to reflect the value at the

input to the voltage channel when starting from 0.

With the specified full-scale analog input signal of 0.5 V, the

ADC produces an output code that is approximately 5,326,737.

The equivalent rms value of a full-scale sinusoidal signal is

3,766,572 (0x39792C), independent of the line frequency.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

Similar to the register presented in Figure 57, the AVRMS,

BVRMS, and CVRMS 24-bit signed registers are accessed as

32-bit registers with the eight MSBs padded with 0s.

The accuracy of the voltage rms is typically 0.1ꢀ error from the

full-scale input down to 1/1000 of the full-scale input. Additionally,

xVRMSOS[23:0]

7

2

VOLTAGE SIGNAL

2

x

xVRMS[23:0]

FROM HPF

LPF

0x14791 =

+5,326,737

0V

0xAEB86F =

–5,326,737

Figure 69. Voltage RMS Signal Processing

Rev. A | Page 42 of 104

Data Sheet

ADE7880

Voltage RMS Offset Compensation

Total Active Power Calculation

The ADE7880 incorporates voltage rms offset compensation

registers for each phase: AVRMSOS, BVRMSOS, and CVRMSOS.

These are 24-bit signed registers used to remove offsets in the

voltage rms calculations. An offset can exist in the rms calcula-

tion due to input noises that are integrated in the dc component

of V²(t). One LSB of the voltage rms offset compensation register is

equivalent to one LSB of the voltage rms register. Assuming that

the maximum value from the voltage rms calculation is 3,766,572

with full-scale ac inputs (50 Hz), one LSB of the current rms offset

represents 0.00045ꢀ

Electrical power is defined as the rate of energy flow from source

to load, and it is given by the product of the voltage and current

waveforms. The resulting waveform is called the instantaneous

power signal, and it is equal to the rate of energy flow at every

instant of time. The unit of power is the watt or joules/sec. If an

ac system is supplied by a voltage, v(t), and consumes the current,

i(t), and each of them contains harmonics, then

v(t) = ^∞V 2 sin (kωt + φ_k)

(17)

∑

k

k=1

∞

i(t) =

I 2 sin

(

kωt + γ_k

)

∑

⎛

⎜

⎝

⎞

⎠

k

3767²+128 /3767 −1 ×100

k=1

⎟

(

where:

of the rms measurement at 60 dB down from full scale. Conduct

offset calibration at low current; avoid using voltages equal to zero

for this purpose.

V_k, I_kare rms voltage and current, respectively, of each

harmonic.

φ_k, γ_kare the phase delays of each harmonic.

V rms = V rms₀²+128×VRMSOS

(16)

The instantaneous power in an ac system is

^∞V I

p(t) = v(t) × i(t) =

cos(φ_k– γ_k) −

cos(2kωt + φ_k+ γ_k)

k

where V rms₀is the rms measurement without offset correction.

∑

k

k=1

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to registers presented in

Figure 43, the AVRMSOS, BVRMSOS, and CVRMSOS 24-bit

registers are accessed as 32-bit registers with the four most

significant bits padded with 0s and sign extended to 28 bits.

^∞V I

+

_m{cos[(k − m)ωt + φ_k– γ_m] – cos[(k + m)ωt + φ_k+ γ_m]}

∑

k, m=1

k≠m

k

(18)

The average power over an integral number of line cycles (n) is

given by the equation in Equation 19.

Voltage RMS in 3-Phase Three Wire Delta Configurations

nT

dt = ^∞V I cos(φ_k– γ_k)

(19)

1

nT

P =

p

(

t

)

In 3-phase three wire delta configurations, Phase B is

considered the ground of the system, and Phase A and Phase C

voltages are measured relative to it. This configuration is chosen

using CONSEL bits equal to 01 in ACCMODE register (see

Table 15 for all configurations where the ADE7880 may be

used). In this situation, all Phase B active, reactive, and apparent

powers are 0.

∑

∫

k

k=1

0

where:

T is the line cycle period.

P is referred to as the total active or total real power.

Note that the total active power is equal to the dc component of

the instantaneous power signal p(t) in Equation 18, that is,

^∞V I

cos(φ_k– γ_k)

∑

In this configuration, the ADE7880 computes the rms value of

the line voltage between Phase A and Phase C and stores the

result into BVRMS register. BVGAIN and BVRMSOS registers

may be used to calibrate BVRMS register computed in this

configuration.

k

k=1

This is the equation used to calculate the total active power in the

ADE7880 for each phase. The equation of fundamental active

power is obtained from Equation 18 with k = 1, as follows:

ACTIVE POWER CALCULATION

FP = V₁I₁cos(φ₁– γ₁)

(20)

The ADE7880 computes the total active power on every phase.

Total active power considers in its calculation all fundamental

and harmonic components of the voltages and currents. In

addition, the ADE7880 computes the fundamental active power,

the power determined only by the fundamental components of

the voltages and currents.

Figure 70 shows how the ADE7880 computes the total active

power on each phase. First, it multiplies the current and voltage

signals in each phase. Next, it extracts the dc component of the

instantaneous power signal in each phase (A, B, and C) using

LPF2, the low-pass filter.

If the phase currents and voltages contain only the fundamental

component, are in phase (that is φ₁= γ₁= 0), and they correspond

to full-scale ADC inputs, then multiplying them results in an

instantaneous power signal that has a dc component, V₁× I₁,

and a sinusoidal component, V₁× I₁cos(2ωt); Figure 71 shows

the corresponding waveforms.

The ADE7880 also computes the harmonic active powers, the

active powers determined by the harmonic components of the

voltages and currents. See the Harmonics Calculations section

for details.

Rev. A | Page 43 of 104

ADE7880

Data Sheet

HPFEN BIT

CONFIG3[0]

INTEN BIT

CONFIG[0]

AIGAIN

IA

APGAIN AWATTOS

LPSEL BIT

HPF

CONFIG3[1]

HPFEN BIT

CONFIG3[0]

INSTANTANEOUS

PHASE A

ACTIVE POWER

APHCAL

AVGAIN

LPF

VA

:

AWATT

HPF

4

2

DIGITAL SIGNAL PROCESSOR

Figure 70. Total Active Power Data Path

0

INSTANTANEOUS

POWER SIGNAL

p(t)= V rms × I rms – V rms × I rms × cos(2ωt)

0x339CBBC =

54,119,356

INSTANTANEOUS

ACTIVE POWER

SIGNAL: V rms × I rms

–5

–10

–15

–20

–25

V rms × I rms

0x19CE5DE =

27,059,678

0x000 0000

i(t) = √2 × I rms × sin(ωt)

v(t) = √2 × V rms × sin(ωt)

Figure 71. Active Power Calculation

0.1

1

3

10

FREQUENCY (Hz)

Because LPF2 does not have an ideal brick wall frequency

response, the active power signal has some ripple due to the

instantaneous power signal. This ripple is sinusoidal and has a

frequency equal to twice the line frequency. Because the ripple

is sinusoidal in nature, it is removed when the active power

signal is integrated over time to calculate the energy. Bit 1

(LPFSEL) of CONFIG3 register selects the LPF2 strength. If

LPFSEL is 0 (default), the settling time is 650 ms and the ripple

attenuation is 65 dB. If LPFSEL is 1, the settling time is 1300 ms

and the ripple attenuation is 128 dB. Figure 72 shows the

frequency response of LPF2 when LPFSEL is 0 and Figure 73

shows the frequency response of LPF2 when LPFSEL is 1.

Figure 72. Frequency Response of the LPF Used to Filter Instantaneous Power

in Each Phase When the LPFSEL Bit of CONFIG3 is 0 (Default)

0

–10

–20

–30

–40

The ADE7880 stores the instantaneous total phase active

powers into the AWATT, BWATT, and CWATT registers. Their

equation is

∞

1

U_k

I_k

0.1

1

10

cos(φ – γ ) × PMAX ×

×

(21)

xWATT =

×

k

∑

FREQUENCY (Hz)

2⁴

_k=1U_FSI_FS

Figure 73. Frequency Response of the LPF Used to Filter Instantaneous Power

in Each Phase when the LPFSEL Bit of CONFIG3 is 1

where:

U_FS, I_FSare the rms values of the phase voltage and current when

the ADC inputs are at full scale.

PMAX = 27,059,678 it is the instantaneous power computed

when the ADC inputs are at full scale and in phase.

The xWATT[23:0] waveform registers can be accessed using

various serial ports. Refer to the Waveform Sampling Mode

section for more details.

Rev. A | Page 44 of 104

Data Sheet

ADE7880

Fundamental Active Power Calculation

The output is scaled by −50ꢀ by writing 0xC00000 to the watt

gain registers, and it is increased by +50ꢀ by writing 0x400000

to them. These registers are used to calibrate the active, reactive

and apparent power (or energy) calculation for each phase.

The ADE7880 computes the fundamental active power using

a proprietary algorithm that requires some initializations function

of the frequency of the network and its nominal voltage measured

in the voltage channel. Bit 14 (SELFREQ) in the COMPMODE

register must be set according to the frequency of the network in

which the ADE7880 is connected. If the network frequency is

50 Hz, clear this bit to 0 (the default value). If the network fre-

quency is 60 Hz, set this bit to 1. In addition, initialize the VLEVEL

24-bit signed register with a positive value based on the

following equation:

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words,

and the DSP works on 28 bits. Similar to registers presented in

Figure 43, the APGAIN, BPGAIN, and CPGAIN 24-bit signed

registers are accessed as 32-bit registers with the four MSBs

padded with 0s and sign extended to 28 bits.

Active Power Offset Calibration

U _FS

× 4 ×10⁶

(22)

The ADE7880 incorporates a watt offset 24-bit register on each

phase and on each active power. The AWATTOS, BWATTOS,

and CWATTOS registers compensate the offsets in the total

active power calculations, and the AFWATTOS, BFWATTOS,

and CFWATTOS registers compensate offsets in the fundamental

active power calculations. These are signed twos complement,

24-bit registers that are used to remove offsets in the active

power calculations. An offset can exist in the power calculation

due to crosstalk between channels on the PCB or in the chip

itself. One LSB in the active power offset register is equivalent

to 1 LSB in the active power multiplier output. With full-scale

current and voltage inputs, the LPF2 output is PMAX =

27,059,678. At −80 dB down from the full scale (active power

scaled down 10⁴times), one LSB of the active power offset

register represents 0.0369ꢀ of PMAX.

VLEVEL =

U_n

where:

U_FSis the rms value of the phase voltages when the ADC inputs

are at full scale.

U_nis the rms nominal value of the phase voltage.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to the registers presented

in Figure 43, the VLEVEL 24-bit signed register is accessed as a

32-bit register with four most significant bits padded with 0s

and sign extended to 28 bits.

Table 13 presents the settling time for the fundamental active

power measurement.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to registers presented in

Figure 43, the AWATTOS, BWATTOS, CWATTOS, AFWATTOS,

BFWAT TOS, and CFWAT TOS 24-bit signed registers are

accessed as 32-bit registers with the four MSBs padded with

0s and sign extended to 28 bits.

Table 13. Settling Time for Fundamental Active Power

Input Signals

63% PMAX

100% PMAX

375 ms

875 ms

Active Power Gain Calibration

Note that the average active power result from the LPF2 output

in each phase can be scaled by 100ꢀ by writing to the phase’s

watt gain 24-bit register (APGAIN, BPGAIN, CPGAIN). The

xPGAIN registers are placed on data paths of all powers

computed by the ADE7880: total active powers, fundamental

active and reactive powers and apparent powers. This is possible

because all power data paths have identical overall gains.

Therefore, to compensate the gain errors in various powers data

paths it is sufficient to analyze only one power data path, for

example the total active power, calculate the correspondent

APGAIN, BPGAIN and CPGAIN registers and all the power

data paths are gain compensated.

Sign of Active Power Calculation

The average active power is a signed calculation. If the phase

difference between the current and voltage waveform is

more than 90°, the average power becomes negative. Negative

power indicates that energy is being injected back on the grid.

The ADE7880 has sign detection circuitry for active power

calculations. It can monitor the total active powers or the

fundamental active powers. As described in the Active Energy

Calculation section, the active energy accumulation is performed

in two stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is, after the energy

accumulated into the internal accumulator reaches the WTHR

register threshold, a dedicated interrupt is triggered. The sign of

each phase active power can be read in the PHSIGN register.

The power gain registers are twos complement, signed registers

and have a resolution of 2⁻²³/LSB. Equation 23 describes

mathematically the function of the power gain registers.

Bit 6 (REVAPSEL) in the ACCMODE register sets the type of

active power being monitored. When REVAPSEL is 0, the

default value, the total active power is monitored. When

REVAPSEL is 1, the fundamental active power is monitored.

Average Power Data =

(23)

Power Gain Register

⎛

⎞

⎟

LPF 2 Output × 1 +

⎜

2²³

⎝

⎠

Rev. A | Page 45 of 104

ADE7880

Data Sheet

Bits[8:6] (REVAPC, REVAPB, and REVAPA, respectively) in the

STATUS0 register are set when a sign change occurs in the

power selected by Bit 6 (REVAPSEL) in the ACCMODE

register.

PHSIGN register is read immediately after reading the STATUS0

IRQ0

register. Next, the status bit is cleared and the

pin is returned

to high by writing to the STATUS0 register with the corresponding

bit set to 1.

Bits[2:0] (CWSIGN, BWSIGN, and AWSIGN, respectively) in

the PHSIGN register are set simultaneously with the REVAPC,

REVAPB, and REVAPA bits. They indicate the sign of the

power. When they are 0, the corresponding power is positive.

When they are 1, the corresponding power is negative.

Active Energy Calculation

As previously stated, power is defined as the rate of energy flow.

This relationship can be expressed mathematically as

dEnergy

Power=

(24)

dt

Conversely, energy is given as the integral of power, as follows:

Energy = p dt

(25)

Bit REVAPx of STATUS0 and Bit xWSIGN in the PHSIGN

register refer to the total active power of Phase x, the power type

being selected by Bit 6 (REVAPSEL) in the ACCMODE register.

t

( )

∫

Interrupts attached to Bits[8:6] (REVAPC, REVAPB, and

REVAPA, respectively) in the STATUS0 register can be enabled

Total and fundamental active energy accumulations are always

signed operations. Negative energy is subtracted from the active

energy contents.

IRQ0

by setting Bits[8:6] in the MASK0 register. If enabled, the

pin is set low, and the status bit is set to 1 whenever a change of

sign occurs. To find the phase that triggered the interrupt, the

HPFEN BIT

CONFIG3[0]

INTEN BIT

CONFIG[0]

AIGAIN

IA

APGAIN AWATTOS

REVAPA BIT IN

STATUS0[31:0]

HPF

HPFEN BIT

CONFIG3[0]

AWATTHR[31:0]

APHCAL

INTERNAL

ACCUMULATOR

AVGAIN

LPF

32-BIT REGISTER

:

AWATT

VA

HPF

THRESHOLD

4

2

DIGITAL SIGNAL PROCESSOR

34

27 26

0

WTHR

0

Figure 74. Total Active Energy Accumulation

Rev. A | Page 46 of 104

Data Sheet

ADE7880

∞

The ADE7880 achieves the integration of the active power signal

in two stages (see Figure 74). The process is identical for both

total and fundamental active powers. The first stage accumulates

the instantaneous phase total or fundamental active power at

1.024MHz, although they are computed by the DSP at 8 kHz

rate. Every time a threshold is reached, a pulse is generated and

the threshold is subtracted from the internal register.

⎧

⎨

⎫

⎬

⎭

Energy = p

(

t

)

dt =

p

(

nT

)

× T

(27)

Lim

∑

∫

T→0

n=0

⎩

where:

n is the discrete time sample number.

T is the sample period.

In the ADE7880, the total phase active powers are accumulated in

the AWATTHR, BWATTHR, and CWATTHR 32-bit signed

registers, and the fundamental phase active powers are

accumulated in AFWAT THR, BFWAT THR, and C F WAT T H R

32-bit signed registers. The active energy register content can

roll over to full-scale negative (0x80000000) and continue

increasing in value when the active power is positive. Conversely, if

the active power is negative, the energy register underflows to

full-scale positive (0x7FFFFFFF) and continues decreasing in value.

The sign of the energy in this moment is considered the sign

of the active power (see the Sign of Active Power Calculation

section for details). The second stage consists of accumulating

the pulses generated at the first stage into internal 32-bit accu-

mulation registers. The content of these registers is transferred

to watt-hour registers, xWATTHR and xFWATTHR, when

these registers are accessed.

THRESHOLD

The ADE7880 provides a status flag to signal when one of the

xWATTHR and xFWATTHR registers is half full. Bit 0 (AEHF)

in the STATUS0 register is set when Bit 30 of one of the

xWATTHR registers changes, signifying one of these registers is

half full. If the active power is positive, the watt-hour register

becomes half full when it increments from 0x3FFF FFFF to 0x4000

0000. If the active power is negative, the watt-hour register

becomes half full when it decrements from 0xC000 0000 to

0xBFFF FFFF. Similarly, Bit 1 (FAEHF) in STATUS0 register, is

set when Bit 30 of one of the xFWATTHR registers changes,

signifying one of these registers is half full.

FIRST STAGE OF

ACTIVE POWER

ACCUMULATION

PULSES

GENERATED

AFTER FIRST

STAGE

1 PULSE = 1LSB OF WATTHR[31:0]

Figure 75. Active Power Accumulation Inside the DSP

Figure 75 explains this process. The threshold is formed by

concatenating the WTHR 8-bit unsigned register to 27 bits

equal to 0. It is introduced by the user and is common for total

and fundamental active powers on all phases. Its value depends

on how much energy is assigned to one LSB of watt-hour regis-

ters. Supposing a derivative of Wh [10ⁿWh], n as an integer, is

desired as one LSB of the xWATTHR register, WTHR is

computed using the following equation:

Setting Bits[1:0] in the MASK0 register enable the FAEHF and

IRQ0

AEHF interrupts, respectively. If enabled, the

pin is set

low and the status bit is set to 1 whenever one of the energy

registers, xWATTHR (for the AEHF interrupt) or xFWATTHR

(for the FAEHF interrupt), become half full. The status bit is

IRQ0

cleared and the

pin is set to logic high by writing to the

STATUS0 register with the corresponding bit set to 1.

Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a

read-with-reset for all watt-hour accumulation registers, that is,

the registers are reset to 0 after a read operation.

PMAX × f_S×3600×10ⁿ

WTHR =

(26)

U_FS× I_FS× 2²⁷

Integration Time Under Steady Load

where:

PMAX = 27,059,678 = 0x19CE5DE as the instantaneous power

computed when the ADC inputs are at full scale.

f_S= 1.024 MHz, the frequency at which every instantaneous

power computed by the DSP at 8 kHz is accumulated.

U_FS, I_FSare the rms values of phase voltages and currents when

the ADC inputs are at full scale.

The discrete time sample period (T) for the accumulation register

is 976.5625 ns (1.024MHz frequency). With full-scale sinusoidal

signals on the analog inputs and the watt gain registers set to

0x00000, the average word value from each LPF2 is PMAX =

27,059,678 = 0x19CE5DE. If the WTHR register threshold is set

at 3, its minimum recommended value, the first stage accumulator

generates a pulse that is added to watt-hour registers every

WTHR register is an 8-bit unsigned number, so its maximum

value is 2⁸− 1. Its default value is 0x3. Values lower than 3, that

is 2 or 1 should be avoided and 0 should never be used as the

threshold must be a non-zero value.

3× 2²⁷

=14.531μsec

PMAX ×1.024×10⁶

The maximum value that can be stored in the watt-hour

accumulation register before it overflows is 2³¹− 1 or

0x7FFFFFFF. The integration time is calculated as

This discrete time accumulation or summation is equivalent to

integration in continuous time following the description in

Equation 27.

Time = 0x7FFF,FFFF × 14.531 ꢂs = 8 hr 40 min 6 sec (28)

Rev. A | Page 47 of 104

ADE7880

Data Sheet

Energy Accumulation Modes

mode, the ADE7880 transfers the active energy accumulated in the

32-bit internal accumulation registers into the xWATHHR or

xFWATTHR registers after an integral number of line cycles, as

shown in Figure 76. The number of half line cycles is specified

in the LINECYC register.

The active power is accumulated in each watt-hour

accumulation 32-bit register (AWATTHR, BWATTHR,

CWAT THR, AFWAT THR , BFWAT THR, and CFWAT THR)

according to the configuration of Bit 5 and Bit 4 (CONSEL bits) in

the ACCMODE register. The various configurations are described

in Table 14.

The line cycle energy accumulation mode is activated by setting

Bit 0 (LWATT) in the LCYCMODE register. The energy accu-

mulation over an integer number of half line cycles is written

to the watt-hour accumulation registers after LINECYC number

of half line cycles is detected. When using the line cycle

accumulation mode, the Bit 6 (RSTREAD) of the LCYCMODE

register should be set to Logic 0 because the read with reset of

watt-hour registers is not available in this mode.

Table 14. Inputs to Watt-Hour Accumulation Registers

CONSEL

AWATTHR

BWATTHR

CWATTHR

00

VA × IA

VB × IB

VC × IC

01

VA × IA

VB × IB

VB = VA – VC¹

VB × IB

10

11

VA × IA

VC × IC

Phase A, Phase B, and Phase C zero crossings are, respectively,

included when counting the number of half line cycles by setting

Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-

nation of the zero crossings from all three phases can be used

for counting the zero crossing. Select only one phase at a time

for inclusion in the zero crossings count during calibration.

VB = −VA − VC

VB × IB

VB = −VA

¹In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the

rms value of the line voltage between Phase A and Phase C and stores the

result into BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta

Configurations section). Consequently, the ADE7880 computes powers

associated with Phase B that do not have physical meaning. To avoid any

errors in the frequency output pins (CF1, CF2, or CF3) related to the powers

associated with Phase B, disable the contribution of Phase B to the energy-to-

frequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or

TERMSEL3[1] to 0 in the COMPMODE register (see the Energy-to-Frequency

Conversion section).

ZXSEL[0] IN

LCYCMODE[7:0]

ZERO-

CROSSING

DETECTION

(PHASE A)

ZXSEL[1] IN

LINECYC[15:0]

LCYCMODE[7:0]

Depending on the polyphase meter service, choose the appro-

priate formula to calculate the active energy. The American

ANSI C12.10 standard defines the different configurations of

the meter. Table 15 describes which mode to choose in these

various configurations.

ZERO-

CROSSING

DETECTION

(PHASE B)

CALIBRATION

CONTROL

ZXSEL[2] IN

LCYCMODE[7:0]

ZERO-

CROSSING

DETECTION

(PHASE C)

Table 15. Meter Form Configuration

ANSI Meter Form

Configuration

3-wire delta

4-wire wye

4-wire delta

4-wire wye

CONSEL

AWGAIN AWATTOS

AWATTHR[31:0]

5S/13S

6S/14S

8S/15S

9S/16S

01

10

11

00

OUTPUT

FROM

LPF2

INTERNAL

ACCUMULATOR

32-BIT

REGISTER

THRESHOLD

Bits[1:0] (WATTACC[1:0]) in the ACCMODE register determine

how the active power is accumulated in the watt-hour registers

and how the CF frequency output can be generated as a

function of the total and fundamental active powers. See the

Energy-to-Frequency Conversion section for details.

34

27 26

0

WTHR

0

Figure 76. Line Cycle Active Energy Accumulation Mode

The number of zero crossings is specified by the LINECYC 16-bit

unsigned register. The ADE7880 can accumulate active power

for up to 65,535 combined zero crossings. Note that the internal

zero-crossing counter is always active. By setting Bit 0 (LWATT)

in the LCYCMODE register, the first energy accumulation

result is, therefore, incorrect. Writing to the LINECYC register

when the LWATT bit is set resets the zero-crossing counter, thus

ensuring that the first energy accumulation result is accurate.

Line Cycle Active Energy Accumulation Mode

In line cycle energy accumulation mode, the energy accumula-

tion is synchronized to the voltage channel zero crossings such

that active energy is accumulated over an integral number of

half line cycles. The advantage of summing the active energy

over an integer number of line cycles is that the sinusoidal compo-

nent in the active energy is reduced to 0. This eliminates any

ripple in the energy calculation and allows the energy to be

accumulated accurately over a shorter time. By using the line

cycle energy accumulation mode, the energy calibration can be

greatly simplified, and the time required to calibrate the meter

can be significantly reduced. In line cycle energy accumulation

At the end of an energy calibration cycle, Bit 5 (LENERGY) in

the STATUS0 register is set. If the corresponding mask bit in

the MASK0 interrupt mask register is enabled, the

also goes active low. The status bit is cleared and the

IRQ0

pin is

Rev. A | Page 48 of 104

Data Sheet

ADE7880

^∞V I

set to high again by writing to the STATUS0 register with the

corresponding bit set to 1.

π

2

{

cos[(k – m)ωt + φ_k− γ_k− ]−

∑

m

k

k,m=1

k≠m

Because the active power is integrated on an integer number of

half-line cycles in this mode, the sinusoidal components are

reduced to 0, eliminating any ripple in the energy calculation.

Therefore, total energy accumulated using the line cycle

accumulation mode is

π

2

^cos[(k + m)ωt + φ_k+ γ_k+ ]}

(33)

The average total reactive power over an integral number of line

cycles (n) is shown in Equation 34.

t+nT

dt = nT ^∞V I

nT

q t

( )

dt = ^∞V I

e =

p

(

t

)

cos(φ_k– γ_k)

k

(29)

1

nT

π

2

∑

∫

k

Q =

cos(φ_k– γ_k−

k

)

(34)

∑

k=1

∫

k

t

k=1

0

where nT is the accumulation time.

∞

Q = V I sin(φ_k– γ_k)

∑

k

Note that line cycle active energy accumulation uses the same

signal path as the active energy accumulation. The LSB size of

these two methods is equivalent.

k=1

where:

T is the period of the line cycle.

Q is referred to as the total reactive power. Note that the total

reactive power is equal to the dc component of the instantaneous

reactive power signal q(t) in Equation 32, that is,

FUNDAMENTAL REACTIVE POWER CALCULATION

The ADE7880 computes the fundamental reactive power, the

power determined only by the fundamental components of the

voltages and currents.

∞

V I

sin(φ_k– γ_k)

k

∑

k

The ADE7880 also computes the harmonic reactive powers, the

reactive powers determined by the harmonic components of the

voltages and currents. See Harmonics Calculations section for

details. A load that contains a reactive element (inductor or

capacitor) produces a phase difference between the applied ac

voltage and the resulting current. The power associated with

reactive elements is called reactive power, and its unit is VAR.

Reactive power is defined as the product of the voltage and current

waveforms when all harmonic components of one of these

signals are phase shifted by 90°.

k=1

This is the relationship used to calculate the total reactive power

for each phase. The instantaneous reactive power signal, q(t), is

generated by multiplying each harmonic of the voltage signals by

the 90° phase-shifted corresponding harmonic of the current in

each phase.

The expression of fundamental reactive power is obtained from

Equation 33 with k = 1, as follows:

FQ = V₁I₁sin(φ₁– γ₁)

Equation 31 is an example of the instantaneous reactive power

signal in an ac system when the phase of the current channel is

shifted by +90°.

The ADE7880 computes the fundamental reactive power using

a proprietary algorithm that requires some initialization

function of the frequency of the network and its nominal

voltage measured in the voltage channel. These initializations

are introduced in the Active Power Calculation section and are

common for both fundamental active and reactive powers.

∞

v(t) =

i(t) =

i'(t) =

V

2

sin(kωt + φ_k)

(30)

(31)

∑

k

k=1

∞

I

2 sin kωt + γ_k

(

)

∑

The ADE7880 stores the instantaneous fundamental phase

reactive powers into the AFVAR , BFVAR, and CFVAR registers.

Their equation is

k

k=1

∞

π

2

⎛

⎝

⎞

⎟

⎠

I

2 sin kωt +γ +

∑

⎜

k

k=1

U₁

I₁

1

xFVAR =

×

sin(φ₁– γ₁) × PMAX ×

(35)

U_FSI_FS

2⁴

where i’(t) is the current waveform with all harmonic

components phase shifted by 90°.

where:

Next, the instantaneous reactive power, q(t), can be expressed as

U_FS, I_FSare the rms values of the phase voltage and current when

the ADC inputs are at full scale.

q(t) = v(t) × iʹ(t)

(32)

PMAX = 27,059,678, the instantaneous power computed when

the ADC inputs are at full scale and in phase.

q(t) = ^∞V I ×2

π

2

sin(kωt + φ_k) × sin(kωt + γ_k+

) +

∑

k

k=1

The xFVAR waveform registers are not mapped with an address

in the register space and can be accessed only through HSDC

port in the waveform sampling mode (see Waveform Sampling

Mode section for details). Fundamental reactive power

information is also available through the harmonic calculations

of the ADE7880 (see Harmonics Calculations section for details).

^∞V I

π

2

× 2sin(kωt + φ_k) × sin(mωt + γ_m+

)

∑

k,m=1

k≠m

m

k

Note that q(t) can be rewritten as

q(t) = ^∞V I

π

2

π

2

{cos(φ_k− γ_k− )− cos(2 kωt + φ_k+ γ_k+ )}+

∑

k

k=1

Rev. A | Page 49 of 104

ADE7880

Data Sheet

Table 16 presents the settling time for the fundamental reactive

power measurement, which is the time it takes the power to

reflect the value at the input of the ADE7880.

Fundamental Reactive Power Offset Calibration

The ADE7880 provides a fundamental reactive power offset

register on each phase. The AFVAROS, BFVAROS, and CFVAROS

registers compensate the offsets in the fundamental reactive

power calculations. These are signed twos complement, 24-bit

registers that are used to remove offsets in the fundamental

reactive power calculations. An offset can exist in the power

calculation due to crosstalk between channels on the PCB or in

the chip itself. The resolution of the registers is the same as for

the active power offset registers (see the Active Power Offset

Calibration section).

Table 16. Settling Time for Fundamental Reactive Power

Input Signals

63% PMAX

100% PMAX

375 ms

875 ms

Fundamental Reactive Power Gain Calibration

The average fundamental reactive power from the LPF output in

each phase can be scaled by 100ꢀ by writing to one of the phase’s

VAR gain 24-bit register (APGAIN, BPGAIN, or CPGAIN). Note

that these registers are the same gain registers used to

compensate the other powers computed by the ADE7880. See

the Active Power Gain Calibration section for details on these

registers.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to the registers presented

in Figure 43, the AFVAROS, BFVAROS, and CFVAROS 24-bit

signed registers are accessed as 32-bit registers with the four

MSBs padded with 0s and sign extended to 28 bits.

HPFEN BIT

CONFIG3[0]

DIGITAL

INTEGRATOR

AIGAIN

IA

APGAIN AFVAROS

REVFRPA BIT IN

STATUS0[31:0]

HPF

FUNDAMENTAL

REACTIVE

HPFEN BIT

CONFIG3[0]

AFVARHR[31:0]

POWER

APHCAL

INTERNAL

ACCUMULATOR

AVGAIN

ALGORITHM

32-BIT REGISTER

:

AFVAR

VA

HPF

THRESHOLD

4

2

DIGITAL SIGNAL PROCESSOR

34

27 26

0

VARTHR

0

Figure 77. Fundamental Reactive Energy Accumulation

Rev. A | Page 50 of 104

Data Sheet

ADE7880

Sign of Fundamental Reactive Power Calculation

Similar to active power, the ADE7880 achieves the integration

of the reactive power signal in two stages (see Figure 77).

Note that the fundamental reactive power is a signed calculation.

Table 17 summarizes the relationship between the phase difference

between the voltage and the current and the sign of the resulting

reactive power calculation.

•

The first stage accumulates the instantaneous phase

fundamental reactive power at 1.024 MHz, although they

are computed by the DSP at 8 kHz rate. Every time a

threshold is reached, a pulse is generated and the threshold

is subtracted from the internal register. The sign of the

energy in this moment is considered the sign of the

reactive power (see the Sign of Fundamental Reactive

Power Calculation section for details).

The ADE7880 has sign detection circuitry for reactive power

calculations that can monitor the fundamental reactive powers.

As described in the Fundamental Reactive Energy Calculation

section, the reactive energy accumulation is executed in two

stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is, after the energy

accumulated into the internal accumulator reaches the VARTHR

register threshold, a dedicated interrupt is triggered. The sign of

each phase reactive power can be read in the PHSIGN register.

•

The second stage consists in accumulating the pulses

generated after the first stage into internal 32-bit

accumulation registers. The content of these registers is

transferred to the var-hour registers (xFVARHR) when these

registers are accessed. AFWATTHR, BFWATTHR, and

CFWATTHR represent phase fundamental reactive energies.

Bits[12:10] (REVFRPC, REVFRPB, and REVFRPA, respect-

tively) in the STATUS0 register are set when a sign change

occurs in the fundamental reactive power.

Figure 77 explains this process. The threshold is formed by

concatenating the VARTHR 8-bit unsigned register to 27 bits

equal to 0 and it is introduced by the user. Its value depends on

how much energy is assigned to one LSB of var-hour registers.

Supposing a derivative of a volt ampere reactive hour (varh) [10ⁿ

varh] where n is an integer, is desired as one LSB of the VARHR

register, the VARTHR register can be computed using the

following equation:

Bits[6:4] (CFVARSIGN, BFVARSIGN, and AFVARSIGN,

respectively) in the PHSIGN register are set simultaneously with

the REVFRPC, REVFRPB, and REVFRPA bits. They indicate the

sign of the fundamental reactive power. When they are 0, the

reactive power is positive. When they are 1, the reactive power

is negative.

Bit REVFRPx of the STATUS0 register and Bit xFVARSIGN in

the PHSIGN register refer to the reactive power of Phase x.

PMAX × f_s× 3600 ×10ⁿ

VARTHR =

U_FS× I_FS× 2²⁷

Setting Bits[12:10] in the MASK0 register enables the REVFRPC,

REVFRPB, and REVFRPA interrupts, respectively. If enabled,

(37)

where:

IRQ0

the

pin is set low and the status bit is set to 1 whenever a

PMAX = 27,059,678 = 0x19CE5DE, the instantaneous power

computed when the ADC inputs are at full scale.

f_S= 1.024 MHz, the frequency at which every instantaneous

power computed by the DSP at 8 kHz is accumulated.

U_FS, I_FSare the rms values of phase voltages and currents when

the ADC inputs are at full scale.

change of sign occurs. To find the phase that triggered the

interrupt, the PHSIGN register is read immediately after read-

ing the STATUS0 register. Next, the status bit is cleared and the

IRQ0

pin is set to high by writing to the STATUS0 register with

the corresponding bit set to 1.

Table 17. Sign of Reactive Power Calculation

VARTHR register is an 8-bit unsigned number, so its maximum

value is 2⁸− 1. Its default value is 0x3. Values lower than 3, that

is 2 or 1 should be avoided and 0 should never be used as the

threshold must be a non-zero value.

Φ¹

Sign of Reactive Power

Between 0 to +180

Between −180 to 0

Positive

Negative

¹Φ is defined as the phase angle of the voltage signal minus the current

signal; that is, Φ is positive if the load is inductive and negative if the load is

capacitive.

This discrete time accumulation or summation is equivalent to

integration in continuous time, shown in Equation 38:

Fundamental Reactive Energy Calculation

∞

⎧

⎨

⎩

⎫

⎬

⎭

ReactiveEnergy

=

q

(

t

)

dt

=

q nT × T

( )

∑

n=0

(38)

Lim

∫

Fundamental reactive energy is defined as the integral of

fundamental reactive power.

T→0

where:

Reactive Energy = ∫q(t)dt

(36)

n is the discrete time sample number.

T is the sample period.

The fundamental reactive energy accumulation is always a

signed operation. Negative energy is subtracted from the

reactive energy contents.

Rev. A | Page 51 of 104

ADE7880

Data Sheet

On the ADE7880, the fundamental phase reactive powers are

accumulated in the AFVARHR, BFVARHR, and CFVARHR 32-

bit signed registers. The reactive energy register content can roll

over to full-scale negative (0x80000000) and continue increasing in

value when the reactive power is positive. Conversely, if the reactive

power is negative, the energy register underflows to full-scale

positive (0x7FFFFFFF) and continues to decrease in value.

Table 18. Inputs to Var-Hour Accumulation Registers

CONSEL[1:0] AFVARHR

BFVARHR

CFVARHR

00

01

VA × IA’

VB × IB’

VB = VA − VC¹

VB × IB’

VB = −VA − VC

VB × IB’

VC × IC’

10

11

VA × IA’

VC x IC’

VC × IC’

The ADE7880 provides a status flag to signal when one of the

xFVARHR registers is half full. Bit 3 (FREHF) in the STATUS0

register is set when Bit 30 of one of the xFVARHR registers

changes, signifying one of these registers is half full. If the reactive

power is positive, the var-hour register becomes half full when it

increments from 0x3FFF FFFF to 0x4000 0000. If the reactive

power is negative, the var-hour register becomes half full when it

decrements from 0xC000 0000 to 0xBFFF FFFF.

VB = −VA

¹In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the

rms value of the line voltage between phases A and C and stores the result

into BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta

Configurations section). Consequently, the ADE7880 computes powers

associated with Phase B that do not have physical meaning. To avoid any

errors in the frequency output pins (CF1, CF2, or CF3) related to the powers

associated with Phase B, disable the contribution of Phase B to the energy to

frequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or

TERMSEL3[1] to 0 in COMPMODE register (see the Energy-to-Frequency

Conversion section).

Setting Bit3 in the MASK0 register enables the FREHF

IRQ0

interrupt. If enabled, the

is set to 1 whenever one of the energy registers, xFVARHR,

IRQ0

pin is set low and the status bit

Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine

how the reactive power is accumulated in the var-hour registers

and how the CF frequency output can be generated function of

total and fundamental active and reactive powers. See the Energy-

to-Frequency Conversion section for details.

becomes half full. The status bit is cleared and the

set to high by writing to the STATUS0 register with the

corresponding bit set to 1.

pin is

Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a

read-with-reset for all var-hour accumulation registers, that is,

the registers are reset to 0 after a read operation.

Line Cycle Reactive Energy Accumulation Mode

As mentioned in the Line Cycle Active Energy Accumulation

Mode section, in line cycle energy accumulation mode, the

energy accumulation can be synchronized to the voltage

channel zero crossings so that reactive energy can be

accumulated over an integral number of half line cycles.

Integration Time Under Steady Load

The discrete time sample period (T) for the accumulation register

is 976.5625 ns (1.024 MHz frequency). With full-scale

sinusoidal signals on the analog inputs and a 90° phase difference

between the voltage and the current signal (the largest possible

reactive power), the average word value representing the reactive

power is PMAX = 27,059,678 = 0x19CE5DE. If the VARTHR

threshold is set at 3, its minimum recommended value, the first

stage accumulator generates a pulse that is added to var-hour

In this mode, the ADE7880 transfers the reactive energy

accumulated in the 32-bit internal accumulation registers into

the xFVARHR registers after an integral number of line cycles,

as shown in Figure 78. The number of half line cycles is

specified in the LINECYC register.

The line cycle reactive energy accumulation mode is activated by

setting Bit 1 (LVAR) in the LCYCMODE register. The

3× 2²⁷

=14.531μsec

registers every

PMAX ×1.024×10⁶

fundamental reactive energy accumulated over an integer

number of half line cycles or zero crossings is available in the var-

hour accumulation registers after the number of zero crossings

specified in the LINECYC register is detected. When using the

line cycle accumulation mode, Bit 6 (RSTREAD) of the

LCYCMODE register should be set to Logic 0 because a read

with the reset of var-hour registers is not available in this mode.

The maximum value that can be stored in the var-hour

accumulation register before it overflows is 2³¹− 1 or

0x7FFFFFFF. The integration time is calculated as

Time = 0x7FFF,FFFF × 14.531 ꢂs = 8 hr 40 min 6 sec (39)

Energy Accumulation Modes

The fundamental reactive power accumulated in each var-hour

accumulation 32-bit register (AFVARHR, BFVARHR, and

CFVARHR) depends on the configuration of Bits[5:4]

(CONSEL[1:0]) in the ACCMODE register, in correlation with

the watt-hour registers. The different configurations are

described in Table 18. Note that IA’/IB’/IC’ are the phase-

shifted current waveforms.

Rev. A | Page 52 of 104

Data Sheet

ADE7880

ZXSEL[0] IN

LCYCMODE[7:0]

power is by multiplying the voltage rms value by the current

rms value (also called the arithmetic apparent power).

ZERO-

CROSSING

DETECTION

(PHASE A)

S = V rms × I rms

(40)

where:

ZXSEL[1] IN

LCYCMODE[7:0]

LINECYC[15:0]

S is the apparent power.

V rms and I rms are the rms voltage and current, respectively.

ZERO-

CROSSING

DETECTION

(PHASE B)

CALIBRATION

CONTROL

The ADE7880 computes the arithmetic apparent power on each

phase. Figure 79 illustrates the signal processing in each phase

for the calculation of the apparent power in the ADE7880.

Because V rms and I rms contain all harmonic information, the

apparent power computed by the ADE7880 is total apparent

power. The ADE7880 computes fundamental and harmonic

apparent powers determined by the fundamental and harmonic

components of the voltages and currents. See the Harmonics

Calculations section for details.

ZXSEL[2] IN

LCYCMODE[7:0]

ZERO-

CROSSING

DETECTION

(PHASE C)

APGAIN AFVAROS

AFVARHR[31:0]

INTERNAL

ACCUMULATOR

32-BIT

REGISTER

OUTPUT FROM

THRESHOLD

FUNDAMENTAL REACTIVE

POWER ALGORITHM

The ADE7880 stores the instantaneous phase apparent powers

into the AVA, BVA, and CVA registers. Their equation is

34 27 26

VARTHR

0

U

I

1

xVA =

×

×PMAX×

(41)

U_FSI_FS

2⁴

Figure 78. Line Cycle Fundamental Reactive Energy Accumulation Mode

Phase A, Phase B, and Phase C zero crossings are, respectively,

included when counting the number of half line cycles by

setting Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any

combination of the zero crossings from all three phases can be

used for counting the zero crossing. Select only one phase at a

time for inclusion in the zero-crossings count during calibration.

where:

U, I are the rms values of the phase voltage and current.

U_FS, I_FSare the rms values of the phase voltage and current when

the ADC inputs are at full scale.

PMAX = 27,059,678, the instantaneous power computed when

the ADC inputs are at full scale and in phase.

For details on setting the LINECYC register and the Bit 5

(LENERGY) in the MASK0 interrupt mask register associated

with the line cycle accumulation mode, see the Line Cycle

Active Energy Accumulation Mode section.

The xVA[23:0] waveform registers may be accessed using

various serial ports. Refer to the Waveform Sampling Mode

section for more details.

The ADE7880 can compute the apparent power in an alternative

way by multiplying the phase rms current by an rms voltage

introduced externally. See the Apparent Power Calculation

Using VNOM section for details.

APPARENT POWER CALCULATION

Apparent power is defined as the maximum active power that

can be delivered to a load. One way to obtain the apparent

APGAIN

AIRMS

AVAHR[31:0]

INTERNAL

ACCUMULATOR

32-BIT REGISTER

:

AVA

AVRMS

THRESHOLD

DIGITAL SIGNAL

PROCESSOR

4

2

34

27 26

0

VATHR

0

Figure 79. Apparent Power Data Flow and Apparent Energy Accumulation

Rev. A | Page 53 of 104

ADE7880

Data Sheet

Apparent Power Gain Calibration

registers. The content of these registers is transferred to the VA-

hour registers, xVAHR, when these registers are accessed.

The average apparent power result in each phase can be scaled

by 100ꢀ by writing to one of the phase’s PGAIN 24-bit

registers (APGAIN, BPGAIN, or CPGAIN). Note that these

registers are the same gain registers used to compensate the

other powers computed by the ADE7880. See the Active Power

Gain Calibration section for details on these registers.

Figure 79 illustrates this process. The threshold is formed by the

VATHR 8-bit unsigned register concatenated to 27 bits equal to

0. It is introduced by the user and is common for all phase total

active and fundamental powers. Its value depends on how much

energy is assigned to one LSB of VA-hour registers. When a

derivative of apparent energy (VAh) [10ⁿVAh], where n is an

integer, is desired as one LSB of the xVAHR register, the

Apparent Power Offset Calibration

Each rms measurement includes an offset compensation register

to calibrate and eliminate the dc component in the rms value

(see the Root Mean Square Measurement section). The voltage

and current rms values are multiplied together in the apparent

power signal processing. As no additional offsets are created in

the multiplication of the rms values, there is no specific offset

compensation in the apparent power signal processing. The offset

compensation of the apparent power measurement in each phase is

accomplished by calibrating each individual rms measurement.

xVATHR register can be computed using the following equation:

PMAX × f_s×3600×10ⁿ

VATHR =

U_FS× I_FS× 2²⁷

(44)

where:

PMAX = 27,059,678 = 0x19CE5DE, the instantaneous power

computed when the ADC inputs are at full scale.

f_S= 1.024 MHz, the frequency at which every instantaneous

power computed by the DSP at 8 kHz is accumulated.

U_FS, I_FSare the rms values of phase voltages and currents when

the ADC inputs are at full scale.

Apparent Power Calculation Using VNOM

The ADE7880 can compute the apparent power by multiplying

the phase rms current by an rms voltage introduced externally in

the VNOM 24-bit signed register.

The VATHR register is an 8-bit unsigned number, so its

maximum value is 2⁸− 1. Its default value is 0x3. Values lower

than 3, that is 2 or 1 should be avoided and 0 should never be

used as the threshold must be a non-zero value.

When one of Bits[13:11] (VNOMCEN, VNOMBEN, or

VNOMAEN) in the COMPMODE register is set to 1, the

apparent power in the corresponding phase (Phase x for

VNOMxEN) is computed in this way. When the VNOMxEN

bits are cleared to 0, the default value, then the arithmetic

apparent power is computed.

This discrete time accumulation or summation is equivalent to

integration in continuous time following the description in

Equation 45.

∞

The VNOM register contains a number determined by U, the

desired rms voltage, and U_FS, the rms value of the phase voltage

when the ADC inputs are at full scale:

⎧

⎨

⎩

⎫

⎬

⎭

ApparentEnergy = s

(

t

)

dt =

s nT × T

( )

∑

n=0

(45)

Lim

∫

T→0

where:

U

n is the discrete time sample number.

VNOM =

×3,766,572

(42)

U_FS

T is the sample period.

In the ADE7880, the phase apparent powers are accumulated in

the AVAHR, BVAHR, and CVAHR 32-bit signed registers. The

apparent energy register content can roll over to full-scale

negative (0x80000000) and continue increasing in value when the

apparent power is positive. Conversely, if because of offset

compensation in the rms data path, the apparent power is

negative, the energy register underflows to full-scale positive

(0x7FFFFFFF) and continues to decrease in value.

where U is the nominal phase rms voltage.

As stated in the Current Waveform Gain Registers, the serial

ports of the ADE7880 work on 32-, 16-, or 8-bit words. Similar

to the register presented in Figure 57, the VNOM 24-bit signed

register is accessed as a 32-bit register with the eight MSBs

padded with 0s.

Apparent Energy Calculation

Apparent energy is defined as the integral of apparent power.

The ADE7880 provides a status flag to signal when one of the

xVAHR registers is half full. Bit 4 (VAEHF) in the STATUS0

register is set when Bit 30 of one of the xVAHR registers changes,

signifying one of these registers is half full. As the apparent

power is always positive and the xVAHR registers are signed, the

VA-hour registers become half full when they increment from

0x3FFFFFFF to 0x40000000. Interrupts attached to Bit VAEHF in

the STATUS0 register can be enabled by setting Bit 4 in the MASK0

Apparent Energy = ∫s(t)dt

(43)

Similar to active and reactive powers, the ADE7880 achieves

the integration of the apparent power signal in two stages (see

Figure 79). The first stage accumulates the instantaneous

apparent power at 1.024 MHz, although they are computed by

the DSP at 8 kHz rate. Every time a threshold is reached, a pulse

is generated and the threshold is subtracted from the internal

register. The second stage consists in accumulating the pulses

generated after the first stage into internal 32-bit accumulation

IRQ0

register. If enabled, the

set to 1 whenever one of the Energy Registers xVAHR becomes

IRQ0

pin is set low and the status bit is

half full. The status bit is cleared and the

pin is set to high

Rev. A | Page 54 of 104

Data Sheet

ADE7880

ZXSEL[0] IN

by writing to the STATUS0 register with the corresponding bit

set to 1.

LCYCMODE[7:0]

ZERO-

CROSSING

DETECTION

(PHASE A)

Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a

read-with-reset for all xVAHR accumulation registers, that is,

the registers are reset to 0 after a read operation.

LINECYC[15:0]

ZXSEL[1] IN

LCYCMODE[7:0]

ZERO-

CROSSING

DETECTION

(PHASE B)

CALIBRATION

CONTROL

Integration Time Under Steady Load

The discrete time sample period for the accumulation register

is 976.5625 ns (1.024 MHz frequency). With full-scale pure

sinusoidal signals on the analog inputs, the average word value

representing the apparent power is PMAX. If the VATHR

threshold register is set at 3, its minimum recommended value,

the first stage accumulator generates a pulse that is added to the

ZXSEL[2] IN

LCYCMODE[7:0]

ZERO-

CROSSING

DETECTION

(PHASE C)

AIRMS

APGAIN

AVAHR[31:0]

3× 2²⁷

INTERNAL

ACCUMULATOR

=14.531μsec

xVAHR registers every

PMAX ×1.024×10⁶

32-BIT REGISTER

AVRMS

THRESHOLD

The maximum value that can be stored in the xVAHR

accumulation register before it overflows is 2³¹− 1 or

0x7FFFFFFF. The integration time is calculated as

34

27 26

0

VATHR

0

Time = 0x7FFFFFFF × 14.531 ꢂs = 8 hr 40 min 6 sec (46)

Figure 80. Line Cycle Apparent Energy Accumulation Mode

Energy Accumulation Mode

The line cycle apparent energy accumulation mode is activated

by setting Bit 2 (LVA) in the LCYCMODE register. The apparent

energy accumulated over an integer number of zero crossings is

written to the xVAHR accumulation registers after the number

of zero crossings specified in LINECYC register is detected. When

using the line cycle accumulation mode, set Bit 6 (RSTREAD) of

the LCYCMODE register to Logic 0 because a read with the reset of

xVAHR registers is not available in this mode.

The apparent power accumulated in each accumulation register

depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the

ACCMODE register. The various configurations are described

in Table 19.

Table 19. Inputs to VA-Hour Accumulation Registers

CONSEL[1:0]

AVAHR

BVAHR

CVAHR

00

01

AVRMS × AIRMS

BVRMS × BIRMS

CVRMS × CIRMS

BVRMS × BIRMS

VB = VA – VC¹

Phase A, Phase B, and Phase C zero crossings are, respectively,

included when counting the number of half line cycles by setting

Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-

nation of the zero crossings from all three phases can be used

for counting the zero crossing. Select only one phase at a time

for inclusion in the zero-crossings count during calibration.

10

11

AVRMS × AIRMS

BVRMS × BIRMS

VB = −VA − VC

BVRMS × BIRMS

VB = −VA

CVRMS × CIRMS

¹In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the

rms value of the line voltage between Phase A and Phase C and stores the

result into the BVRMS register (see the Voltage RMS in 3-Phase Three Wire

Delta Configurations section). Consequently, the ADE7880 computes powers

associated with Phase B that do not have physical meaning. To avoid any

errors in the frequency output pins (CF1, CF2, or CF3) related to the powers

associated with Phase B, disable the contribution of phase B to the energy to

frequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or

TERMSEL3[1] to 0 in COMPMODE register (see the Energy-to-Frequency

Conversion section).

For details on setting the LINECYC register and Bit 5 (LENERGY)

in the MASK0 interrupt mask register associated with the line

cycle accumulation mode, see the Line Cycle Active Energy

Accumulation Mode section.

POWER FACTOR CALCULATION

The ADE7880 provides a direct power factor measurement

simultaneously on all phases. Power factor in an ac circuit is

defined as the ratio of the total active power flowing to the load

to the apparent power. The absolute power factor measurement

is defined in terms of leading or lagging referring to whether the

current is leading or lagging the voltage waveform. When the

current is leading the voltage, the load is capacitive and this is

defined as a negative power factor. When the current is lagging

the voltage, the load is inductive and this defined as a positive

power factor. The relationship of the current to the voltage

waveform is illustrated in Figure 81.

Line Cycle Apparent Energy Accumulation Mode

As described in the Line Cycle Active Energy Accumulation

Mode section, in line cycle energy accumulation mode, the

energy accumulation can be synchronized to the voltage channel

zero crossings allowing apparent energy to be accumulated over an

integral number of half line cycles. In this mode, the ADE7880

transfers the apparent energy accumulated in the 32-bit internal

accumulation registers into the xVAHR registers after an

integral number of line cycles, as shown in Figure 80. The

number of half line cycles is specified in the LINECYC register.

Rev. A | Page 55 of 104

ADE7880

Data Sheet

enabled on both the active and apparent energies. This is done

by setting the xLWATT and xLVA bits in the LCYCMODE

register (Address 0xE702). The update rate of the power factor

measurement is now an integral number of half line cycles that

can be programmed into the LINECYC register (Address 0xE60C).

For full details on setting up the line cycle accumulation mode

see the Line Cycle Active Energy Accumulation Mode and Line

Cycle Apparent Energy Accumulation Mode sections.

ACTIVE (–)

REACTIVE (–)

PF (+)

ACTIVE (+)

REACTIVE (–)

PF (–)

CAPACITIVE:

CURRENT LEADS

VOLTAGE

θ = +60° PF = –0.5

θ = –60° PF = +0.5

V

Note that the power factor measurement is effected by the no

load condition if it is enabled (see the No Load Condition

section). If the apparent energy no load is true, then the power

factor measurement is set to 1. If the no load condition based

on total active and apparent energies is true, the power factor

measurement is set at 0.

INDUCTIVE:

CURRENT LAGS

VOLTAGE

I

ACTIVE (–)

REACTIVE (+)

PF (–)

ACTIVE (+)

REACTIVE (+)

PF (+)

Figure 81. Capacitive and Inductive Loads

The ADE7880 also computes the power factor on the

fundamental and harmonic components based on the

fundamental and harmonic active, reactive and apparent

powers. See the Harmonics Calculations section for details.

As shown in Figure 81, the reactive power measurement is

negative when the load is capacitive, and positive when the load

is inductive. The sign of the reactive power can therefore be

used to reflect the sign of the power factor. Note that the ADE7880

computes the fundamental reactive power, so its sign is used as

the sign of the absolute power factor. If the fundamental

reactive power is in no load state, then the sign of the power

factor is the sign of the total active power.

HARMONICS CALCULATIONS

The ADE7880 contains a harmonic engine that analyzes one

phase at a time. Harmonic information is computed with a no

attenuation pass band of 2.8 kHz (corresponding to a −3 dB

bandwidth of 3.3 kHz) and it is specified for line frequencies

between 45 Hz and 66 Hz. Neutral current can also be analyzed

simultaneously with the sum of the phase currents. Figure 82

presents a synthesized diagram of the harmonic engine, its

settings and its output registers.

The mathematical definition of power factor is shown in

Equation 47:

Power Factor = (Sign Fundamental Reactive Power) ×

Total Active Power

(47)

Apparent Power

Theory of Operation

As previously mentioned, the ADE7880 provides a power factor

measurement on all phases simultaneously. These readings are

provided into three 16-bit signed registers, APF (Address

0xE609 ) for Phase A, BPF (Address 0xE60A) for Phase B, and

CPF (Address 0xE60B) for Phase C. The registers are signed

twos complement register with the MSB indicating the polarity

of the power factor. Each LSB of the APF, BPF, and CPF

registers equates to a weight of 2⁻¹⁵, hence the maximum

register value of 0x7FFF equating to a power factor value of 1.

The minimum register value of 0x8000 corresponds to a power

factor of −1. If because of offset and gain calibrations, the power

factor is outside the −1 to +1 range, the result is set at −1 or +1

depending on the sign of the fundamental reactive power.

Consider an nonsinusoidal ac system supplied by a voltage, v(t)

that consumes the current i(t). Then

v(t) = ^∞V 2 sin (kωt + φ_k)

(48)

∑

k

k=1

∞

i(t) =

I

2 sin

(

kωt +γ _k

)

∑

k

k=1

where:

V_k, I_kare rms voltage and current, respectively, of each

harmonic.

Φ_k, γ_kare the phase delays of each harmonic.

ω is the angular velocity at the fundamental (line) frequency f.

The ADE7880 harmonics calculations are specified for line

frequencies between 45 Hz and 66 Hz. The phase nominal

voltage used as time base must have an amplitude greater than

20ꢀ of full scale.

By default the instantaneous total phase active and apparent

powers are used to calculate the power factor and the registers

are updated at a rate of 8 kHz. The sign bit is taken from the

instantaneous fundamental phase reactive energy measurement

on each phase.

The number of harmonics N that can be analyzed within the

2.8 kHz pass band is the whole number of 2800/f. The absolute

maximum number of harmonics accepted by the ADE7880

is 63.

Should a measurement with more averaging be required, the

ADE7880 provides an option of using the line cycle accumulation

measurement on the active and apparent energies to determine

the power factor. This option provides a more stable power

factor reading. This mode is enabled by setting the PFMODE

bit (Bit 7) in the LCYCMODE register (Address 0xE702). When

this mode is enabled the line cycle accumulation mode must be

⎡

⎤

2800

, N≤63

N =

⎢

⎣

⎥

⎦

f

Rev. A | Page 56 of 104

Data Sheet

ADE7880

When the ADE7880 analyzes a phase, the following metering

quantities are computed:

P

z

pf_z sgn



Q_z



, z = 2, 3,…, N

S_z



Fundamental phase current rms: I₁

Fundamental phase voltage rms: V₁

RMS of up to three harmonics of phase current:

I_x, I_y, I_z, x,y,z=2, 3,…, N

RMS of up to three harmonics of phase voltage:

V_x, V_y, V_z, x,y,z=2, 3,…, N

Fundamental phase active power

P₁= V₁I₁cos(φ₁− γ₁)

Fundamental phase reactive power

Q₁= V₁I₁sin(φ₁− γ₁)



Total harmonic distortion of the phase current

I ² I₁²

THD_I



I₁



Total harmonic distortion of the phase voltage

V ²V₁²



THD _V



V₁

Harmonic distortion of up to three harmonics on the phase

current



Fundamental phase apparent power

S₁= V₁I₁

Power factor of the fundamental

I_x

HD_I



x

I₁

P

1

, x = 2, 3,…, N

, y = 2, 3,…, N

, z = 2, 3,…, N

pf₁ sgn



Q₁



S₁

I _y

I₁

y

z

Active power of up to three harmonics:

P_x= V_xI_xcos(φ_x– γ_x), x=2, 3,…, N

P_y= V_yI_ycos(φ_y– γ_y), y=2, 3,…, N

P_z= V_zI_zcos(φ_z– γ_z), z=2, 3,…, N

I_z

I₁



Reactive power of up to three harmonics:

Q_x= V_xI_xsin(φ_x– γ_x), x=2, 3,…, N

Q_y= V_yI_ysin(φ_y– γ_y), y=2, 3,…, N

Q_z= V_zI_zsin(φ_z– γ_z), z=2, 3,…, N

Apparent power of up to three harmonics:

S_x= V_xI_x, x = 2, 3, …, N

S_y= V_yI_y, y = 2 , 3, …, N

S_z= V_zI_z, z = 2, 3, …, N

Power factor of up to three harmonics:



Harmonic distortion of up to three harmonics on the phase

voltage:

V_x

HD_V



x

V₁

, x = 2, 3,…, N

, y = 2, 3,…, N

, z = 2, 3,…, N

V_y

V₁

y

z

V_z

V₁

P

x

pf_x sgn



Q_x



S_x

, x = 2, 3,…, N

, y = 2, 3,…, N

P_y

S_y



pf_y sgn Q_y





Rev. A | Page 57 of 104

Data Sheet

ADE7880

ACTPHSEL BITS HCONFIG[9,8] SELECT

THE PHASE USED TO AS TIME BASE

HPHASE BITS

HCONFIG[2,1]

OUTPUT REGISTERS USED WHEN ONE OF PHASES A, B, C IS ANALYZED

SELECT THE PHASE

BEING MONITORED

FVRMS

FIRMS

FWATT

FVAR

FVA

FPF

VTHD

HXVHD

HYVHD

HZVHD

ITHD

HXVRMS HXIRMS HXWATT HXVAR

HYVRMS HYIRMS HYWATT HYVAR

HZVRMS HZIRMS HZWATT HZVAR

HXVA

HYVA

HZVA

HXPF

HYPF

HZPF

HXIHD

HYIHD

HZIHD

IA, VA

IB, VB

IC, VC

ADE7880 HARMONIC

CALCULATIONS

HXVRMS HXIRMS

HYVRMS HYIRMS

HZVRMS HZIRMS

HXVHD

HYVHD

HZVHD

HXIHD

HYIHD

HZIHD

OUTPUT REGISTERS

USED WHEN NEUTRAL

CURRENT IS ANALYZED

IN, ISUM

HX, HY, HZ REGISTERS SELECT THE

HARMONICS TO MONITOR

ISUM

IN

ISUM

IN

RESULTS RESULTS RESULTS RESULTS

HRATE BITS HCONFIG[7:5] SELECT THE

UPDATE RATE OF HARMONIC

REGISTERS

HSTIME BITS HCONFIG[4,3] SELECT

THE DELAY IN TRIGGERING HREADY

INTERRUPT

HRCFG BIT HCONFIG[0] SELECTS IF

HREADY FLAG IN STATUS0 IS SET

IMMEDIATELY OF AFTER HSTIME

Figure 82. ADE7880 Harmonic Engine Block Diagram

When the neutral current and the sum of the three phase

currents represented by ISUM register are analyzed, the

following metering quantities are computed for both currents:

the register for that harmonic to be monitored. If the second

harmonic is monitored, write 2. If harmonic 51 is desired, write

51. The fundamental components are always monitored,

independent of the values written into HX, HY, or HZ.

Therefore, if one of these registers is made equal to 1, the

ADE7880 monitors the fundamental components multiple times.

The maximum index allowed in HX, HY, and HZ registers is 63.

The no attenuation pass band is 2.8 kHz, corresponding to a −3

dB bandwidth of 3.3 kHz, thus all harmonics of frequency lower

than 2800 Hz are supported without attenuation.

•

RMS of fundamental and of up to 2 harmonics or rms of

up to three harmonics: I_x, I_y, I_z, x, y, z = 1,2, 3,…, N.

Harmonic distortions of the analyzed harmonics.

•

Configuring the Harmonic Calculations

The ADE7880 requires a time base provided by a phase voltage.

Bit 9 and Bit 8 (ACTPHSEL) of HCONFIG[15:0]register select

this phase voltage. If ACTPHSEL = 00, the phase A is used. If

ACTPHSEL = 01, the Phase B is used and if ACTPHSEL = 10,

the Phase C is used. If the phase voltage used as time base is

down, select another phase, and the harmonic engine continues

to work properly.

The rms of the phase voltage and phase current fundamental

components are stored into FVRMS and FIRMS 24-bit signed

registers. The associated data path is presented in Figure 83.

Similar to the rms current and voltage rms data paths presented

in Root Mean Square Measurement section, the data path

contains 24-bit signed offset compensation registers xIRMSOS,

xVRMSOS, x = A, B, C for each phase quantity. The rms of the

phase current and phase voltage three harmonic components

are stored into HXVRMS, HXIRMS, HYVRMS, HYIRMS,

HZVRMS, and HZIRMS 24-bit signed registers. The associated

data path is presented in Figure 84 and contains the following

24-bit signed offset compensation registers: HXIRMSOS,

HYIRMSOS, HZIRMSOS, HXVRMSOS, HYVRMSOS, and

HZVRMSOS.

The phase under analysis is selected by Bit 2 and Bit 1

(HPHASE) of HCONFIG[15:0]register. If HPHASE = 00, the

Phase A is monitored. If HPHASE = 01, the Phase B is

monitored and if HPHASE = 10, the Phase C is monitored. If

HPHASE = 11, the neutral current together with the sum of the

phase currents represented by ISUM register are monitored.

Harmonic Calculations When a Phase is Monitored

When a phase is monitored, fundamental information together

with information about up to three harmonics is computed. The

indexes of the three additional harmonics simultaneously

monitored by the ADE7880 are provided by the 8-bit registers

HX, HY, and HZ. Simply write the index of the harmonic into

It is recommended to leave the offset compensation registers at

0, the default value.

Rev. A | Page 58 of 104

Data Sheet

ADE7880

Table 20. Harmonic Engine Outputs When Phase A, Phase B, or Phase C is Analyzed and the Registers Where the Values are Stored

Quantity

Definition

ADE7880 Register

FVRMS, FIRMS

HXVRMS, HXIRMS

HYVRMS, HYIRMS

HZVRMS, HZIRMS

FWATT

RMS of the Fundamental Component

RMS of a Harmonic Component

V1, I1

V_x, I_x, x = 2, 3,…, N

V_y, I_y, y = 2, 3,…, N

V_z, I_z, z = 2, 3,…, N

Active Power of the Fundamental Component

Active Power of a Harmonic Component

P₁= V₁I₁cos(φ₁− γ₁)

P_x= V_xI_xcos(φ_x– γ_x), x = 2, 3,…, N

P_y= V_yI_ycos(φ_y– γ_y), y = 2, 3,…, N

P_z= V_zI_zcos(φ_z– γ_z), z = 2, 3,…, N

Q₁= V₁I₁sin(φ₁− γ₁)

HXWATT

HYWATT

HZWATT

FVAR

Reactive Power of the Fundamental Component

Reactive Power of a Harmonic Component

Q_x= V_xI_xsin(φ₁− γ₁), x = 2, 3,…, N

Q_y= V_yI_ysin(φ_y– γ_y), y = 2, 3,…, N

Q_z= V_zI_zsin(φ_z– γ_z), z = 2, 3,…, N

S₁= V₁I₁

HXVAR

HYVAR

HZVAR

Apparent Power of the Fundamental Component

Apparent Power of a Harmonic Component

FVA

S_x= V_xI_x, x = 2, 3, …, N

S_y= V_yI_y, y = 2, 3, …, N

S_z= V_zI_z, z = 2, 3, …, N

HXVA

HYVA

HZVA

Power Factor of the Fundamental Component

Power Factor of a Harmonic Component

FPF

P

1

pf₁= sgn

(

Q₁×

)

S₁

P

HXPF

HYPF

x

pf_x= sgn

(

Q_x×

)

, x = 2, 3,…, N

, y = 2, 3,…, N

, z = 2, 3,…, N

S_x

P

y

pf_y= sgn

(

Q_y

)

×

S_y

HZPF

VTHD

P

z

pf_z= sgn

(Q_z

S_z

Total Harmonic Distortion

V ²−V₁²

(

THD

)

=

V

V₁

ITHD

I ²− I₁²

(THD

)

=

I

I₁

Harmonic Distortion of a Harmonic Component

HXVHD, HXIHD

HYVHD, HYIHD

HZVHD, HZIHD

V_x

V₁

I_x

I₁

HD_V

=

HD =

,

I_x

, x = 2, 3,…, N

,y = 2, 3,…, N

,z = 2, 3,…, N

x

V_y

V₁

I_y

I₁

HD

=

,

I_y

y

V_z

V₁

I_z

I₁

HD_I

,

z

Rev. A | Page 59 of 104

ADE7880

Data Sheet

Table 21. Harmonic Engine Outputs when Neutral Current and ISUM are Analyzed and the Registers Where the Values are Stored

ADE7880

Quantity

Definition

Register

HXIRMS

HYIRMS

HZIRMS

HXVRMS

HYVRMS

HZVRMS

HXIHD

RMS of a Harmonic Component (Including the Fundamental) of the Neutral Current

I_x, x = 1,2, 3,…, N

I_y, y = 1,2, 3,…, N

I_z, z = 1,2, 3,…, N

ISUMx, x = 1,2,3,…,N

ISUMy, y = 1,2,3,…,N

ISUMz, z = 1,2,3,…,N

RMS of a Harmonic Component (Including the Fundamental) of ISUM

Harmonic Distortion of a Harmonic Component (Including the Fundamental) of the

Neutral Current (Note that the HX Register Must be Set to 1 for These Calculations to be

Executed)

I_x

HD_I

=

x

I₁

, x = 1,2,3,…,N

, y = 1,2,3,…,N

HYIHD

HZIHD

HXVHD

I _y

I₁

y

z

I_z

I₁

, z = 1,2,3,…,N

Harmonic Distortion of a Harmonic Component (Including the Fundamental) of ISUM.

(Note that the HX Register Must be Set to 1 for These Calculations to be Executed)

ISUM_x

HD_ISUM

=

x

ISUM₁

,

x = 1,2,3,…,N

HYVHD

HZVHD

ISUM _y

HD_ISUM

=

,

y

ISUM₁

y = 1,2,3,…,N

ISUM_z

ISUM₁

HD_ISUM

=

,

z

z = 1,2,3,…,N

Rev. A | Page 60 of 104

Data Sheet

ADE7880

HPHASE BITS

HCONFIG[2, 1] SELECT THE

PHASE BEING MONITORED

AIRMSOS

7

2

BIRMSOS

CIRMSOS

FIRMS

HPHASE BITS

HCONFIG[2, 1] SELECT THE

GAIN BEING USED

APGAIN OR

BPGAIN OR

CPGAIN

HPHASE BITS

HCONFIG[2, 1] SELECT THE

PHASE BEING MONITORED

FVA

AVRMSOS

7

2

BVRMSOS

CVRMSOS

FVRMS

Figure 83. Fundamental RMS Signal Processing

The active, reactive, and apparent powers of the fundamental

component are stored into the FWATT, FVAR, and FVA 24-bit

signed registers. Figure 85 presents the associated data path.

The active, reactive and apparent powers of the 3 harmonic

components are stored into the HXWATT, HXVAR, HXVA,

HYWATT, HYVAR, HYVA, HZWATT, HZVAR, and HZVA

24-bit signed registers. Figure 86 presents the associated data path.

harmonic components are stored into the HXPF, HYPF, and

HZPF 24-bit signed registers.

The total harmonic distortion ratios computed using the rms of

the fundamental components and the rms of the phase current

and the phase voltage (see Root Mean Square Chapter for

details about these measurements) are stored into the VTHD

and ITHD 24-bit registers in 3.21 signed format. This means

the ratios are limited to +3.9999 and all greater results are

clamped to it.

The power factor of the fundamental component is stored into

FPF 24-bit signed register. The power factors of the three

Rev. A | Page 61 of 104

ADE7880

Data Sheet

HXIRMSOS

HYIRMSOS

HZIRMSOS

7

2

HXIRMS

HYIRMS

HZIRMS

HXVRMSOS

HYVRMSOS

HXVRMSOS

7

2

HXVRMS

HYVRMS

HZVRMS

Figure 84. Harmonic RMS Signal Processing

HPHASE BITS

HCONFIG[2, 1] SELECT THE

PHASE BEING MONITORED

2

APGAIN

BPGAIN

CPGAIN

AFWATTOS

BFWATTOS

CFWATTOS

2

÷

2

FWATT

÷

2

÷

HPHASE BITS

HCONFIG[2, 1] SELECT THE

PHASE BEING MONITORED

2

APGAIN

BPGAIN

CPGAIN

AFVAROS

BFVAROS

CFVAROS

2

÷

2

FVAR

÷

2

÷

Figure 85. Fundamental Active and Reactive Powers Signal Processing

Rev. A | Page 62 of 104

Data Sheet

ADE7880

2

HPGAIN

HXWATTOS

HYWATTOS

HZWATTOS

HXWATT

HYWATT

HZWATT

÷

2

÷

2

÷

2

HPGAIN

HXVAROS

HYVAROS

HZVAROS

2

HXVAR

HYVAR

HZVAR

÷

2

÷

2

÷

Figure 86. Harmonic Active and Reactive Powers Signal Processing

The harmonic distortions of the three harmonic components

are stored into the HXVHD, HXIHD, HYVHD, HYIHD,

HZVHD, and HZIHD 24-bit registers in 3.21 signed format.

This means the ratios are limited to +3.9999 and all greater

results are clamped to it.

HYVHD, HYIHD, HZVHD, and HZIHD 24-bit registers. The

distortions of the neutral current are saved into HYIHD and

HZIHD registers and the distortions of the ISUM are stored

into the HYVHD and HZVHD registers. As HX is set to 1, the

HXIHD and HXVHD registers contain 0x1FFFFF, a number

representing 1 in 3.21 signed format.

As a reference, Table 20 presents the ADE7880 harmonic engine

outputs when one phase is analyzed and the registers in which

the outputs are stored.

As a reference, Table 21 presents the ADE7880 harmonic engine

outputs when the neutral current and ISUM are analyzed and

the registers in which the outputs are stored.

Harmonic Calculations When the Neutral is Monitored

Configuring Harmonic Calculations Update Rate

When the neutral current and the sum of phase currents are

monitored, only the harmonic rms related registers are updated.

The ADE7880 harmonic engine functions at 8 kHz rate. From

the moment the HCONFIG register is initialized and the

harmonic indexes are set in the HX, HY and HZ index registers,

the ADE7880 calculations take typically 750 ms to settle within

the specification parameters.

The registers HX, HY and HZ identify the index of the harmonic,

including the fundamental. When a phase is analyzed, the

fundamental rms values are calculated continuously and the

results are stored in dedicated registers FIRMS and FVRMS.

When the neutral is analyzed, the fundamental information is

calculated by setting one of the harmonic index registers HX,

HY or HZ to 1 and the results are stored in harmonic registers.

The maximum index allowed in HX, HY and HZ registers is 63.

The no attenuation pass band is 2.8 kHz, corresponding to a

−3 dB bandwidth of 3.3 kHz, thus all harmonics of frequency

lower than 2800 Hz are supported without attenuation.

The update rate of the harmonic engine output registers is

managed by Bits[7:5] (HRATE) in HCONFIG register and is

independent of the engine’s calculations rate of 8 kHz. The default

value of 000 means the registers are updated every 125 μsec

(8 kHz rate). Other update periods are: 250 μsec (HRATE =

001), 1 ms (010), 16 ms (011), 128 ms (100), 512 ms (101),

1.024 sec (110). If HRATE bits are 111, then the harmonic

calculations are disabled.

HXIRMS, HYIRMS and HZIRMS registers contain the harmonic

rms components of the neutral current and HXVRMS, HYVRMS

and HZVRMS registers contain the harmonic rms components

of ISUM. Note that in this case, the rms of the fundamental

component is not computed into FIRMS or FVRMS registers,

but it is computed if one of the index registers HX, HY and HZ

is initialized with 1.

The ADE7880 provides two ways to manage the harmonic

computations. The first approach, enabled when Bit 0 (HRCFG)

of HCONFIG register is cleared to its default value of 0, sets Bit

19 (HREADY) in STATUS0 register to 1 after a certain period

of time and then every time the harmonic calculations are updated

at HRATE frequency. This allows an external microcontroller to

access the harmonic calculations only after they have settled.

The time period is determined by the state of Bits[4:3] (HSTIME)

in the HCONFIG register. The default value of 01 sets the time

If the HX register is initialized to 1, the ADE7880 computes the

harmonic distortions of the other harmonics identified into HY

and HZ registers and stores them in 3.21 signed format into the

Rev. A | Page 63 of 104

ADE7880

Data Sheet

to 750 ms, the settling time of the harmonic calculations. Other

possible values are 500 ms (HSTIME = 00), 1 sec (10) and 1250

ms (11).

•

Initialize the gain registers used in the harmonic

calculations. Leave the offset registers to 0.

Read the registers in which the harmonic information is

stored using the burst or regular reading mode at high to

low transitions of CF2/HREADY pin.

The second approach, enabled when Bit 0 (HRCFG) of

HCONFIG register is set to 1, sets Bit 19 (HREADY) in

STATUS0 register to 1 every time the harmonic calculations are

updated at the update frequency determined by HRATE bits

without waiting for the harmonic calculations to settle. This

allows an external microcontroller to access the harmonic

calculations immediately after they have been started. If the

corresponding mask bit in the MASK0 interrupt mask register

WAVEFORM SAMPLING MODE

The waveform samples of the current and voltage waveform,

the active, reactive, and apparent power outputs are stored

every 125 μs (8 kHz rate) into 24-bit signed registers that can be

accessed through various serial ports of the ADE7880. Table 22

provides a list of registers and their descriptions.

IRQ

is enabled, the

pin also goes active low. The status bit is

IRQ

cleared and the pin

is set to high again by writing to the

Table 22. Waveform Registers List

STATUS0 register with the corresponding bit set to 1.

Register

IAWV

VAWV

IBWV

VBWV

ICWV

VCWV

INWV

AVA

BVA

CVA

AWATT

BWATT

CWATT

Description

Additionally, the ADE7880 provides a periodical output signal

called HREADY at the CF2/HREADY pin synchronous to the

moment the harmonic calculations are updated in the harmonic

registers. This functionality is chosen if Bit 2 (CF2DIS) is set to

1 in the CONFIG register. If CF2DIS is set to 0 (default value),

the CF2 energy to frequency converter output is provided at

CF2/HREADY pin. The default state of this signal is high. Every

time the harmonic registers are updated based on HRATE bits

in HCONFIG register, the signal HREADY goes low for

approximately 10 μsec and then goes back high. If Bit 0

(HRCFG) in the HCONFIG register is 0, that is the HREADY

bit in the STATUS1 register is set to 1 every HRATE period

right after the harmonic calculations have started, the signal

HREADY toggles high, low and back synchronously. If the

HRCFG bit is 1, that is, Bit HREADY in the STATUS1 register

is set to 1 after the HSTIME period, the HREADY signal toggles

high, low and back synchronously. The HREADY signal allows

fast access to the harmonic registers without having to use

HREADY interrupt in MASK1 register.

Phase A current

Phase A voltage

Phase B current

Phase B voltage

Phase C current

Phase C voltage

Neutral current

Phase A apparent power

Phase B apparent power

Phase C apparent power

Phase A active power

Phase B active power

Phase C active power

Bit 17 (DREADY) in the STATUS0 register can be used to

signal when the registers listed in Table 22 can be read using

I²C or SPI serial ports. An interrupt attached to the flag can be

enabled by setting Bit 17 (DREADY) in the MASK0 register. (see

the Digital Signal Processor section for more details on

Bit DREADY).

In order to facilitate the fast reading of the registers in which

the harmonic calculations are stored, a special burst registers

reading has been implemented in the serial interfaces. See the

I²C Read Operation of Harmonic Calculations Registers and the

SPI Read Operation sections for details.

The ADE7880 contains a high speed data capture (HSDC) port

that is specially designed to provide fast access to the waveform

sample registers. Read the HSDC Interface section for more

details.

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.

All registers listed in Table 22 are transmitted signed extended

from 24 bits to 32 bits (see Figure 44).

Recommended Approach to Managing Harmonic

Calculations

The recommended approach to managing the ADE7880

harmonic calculations is the following:

ENERGY-TO-FREQUENCY CONVERSION

•

Set up Bit 2 (CF2DIS) in the CONFIG register. Set the

CF2DIS bit to 1 to use the CF2/HREADY pin to signal

when the harmonic calculations have settled and are

updated. The high to low transition of HREADY signal

indicates when to read the harmonic registers. Use the

burst reading mode to read the harmonic registers as it is

the most efficient way to read them.

The ADE7880 provides three frequency output pins: CF1, CF2,

and CF3. The CF2 pin is multiplexed with the HREADY pin of

the harmonic calculations block. When HREADY is enabled,

the CF2 functionality is disabled at the pin. The CF3 pin is

multiplexed with the HSCLK pin of the HSDC interface. When

HSDC is enabled, the CF3 functionality is disabled at the pin.

CF1 pin is always available. After initial calibration at manu-

facturing, the manufacturer or end customer verifies the energy

meter calibration. One convenient way to verify the meter

calibration is to provide an output frequency proportional to the

•

Choose the harmonics to be monitored by setting HX, HY

and HZ appropriately.

Select all the HCONFIG register bits.

Rev. A | Page 64 of 104

Data Sheet

ADE7880

active, reactive, or apparent powers under steady load conditions.

This output frequency can provide a simple, single-wire,

optically isolated interface to external calibration equipment.

Figure 87 illustrates the energy-to-frequency conversion in the

ADE7880.

First, Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),

and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register

decide which phases, or which combination of phases, are added.

The TERMSEL1 bits refer to the CF1 pin, the TERMSEL2 bits

refer to the CF2 pin, and the TERMSEL3 bits refer to the CF3

pin. The TERMSELx[0] bits manage Phase A. When set to 1,

Phase A power is included in the sum of powers at the CFx

converter. When cleared to 0, Phase A power is not included.

The TERMSELx[1] bits manage Phase B, and the TERMSELx[2]

bits manage Phase C. Setting all TERMSELx bits to 1 means all

3-phase powers are added at the CFx converter. Clearing all

TERMSELx bits to 0 means no phase power is added and no

CF pulse is generated.

The DSP computes the instantaneous values of all phase powers:

total active, fundamental active, fundamental reactive, and

apparent. The process in which the energy is sign accumulated

in various xWATTHR, xFVARHR, and xVAHR registers has

already been described in the energy calculation sections: Active

Energy Calculation, Fundamental Reactive Energy Calculation,

and Apparent Energy Calculation. In the energy-to-frequency

conversion process, the instantaneous powers generate signals

at the frequency output pins (CF1, CF2, and CF3). One digital-

to-frequency converter is used for every CFx pin. Every converter

sums certain phase powers and generates a signal proportional

to the sum. Two sets of bits decide what powers are converted.

Second, Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and

Bits[8:6] (CF3SEL[2:0]) in the CFMODE register decide what

type of power is used at the inputs of the CF1, CF2, and CF3

converters, respectively. Table 23 shows the values that CFxSEL

can have: total active, apparent, fundamental active, or fundamental

reactive powers.

Table 23. CFxSEL Bits Description

CFxSEL

Description

Registers Latched When CFxLATCH = 1

000

001

CFx signal proportional to the sum of total phase active powers

Reserved

AWATTHR, BWATTHR, CWATTHR

010

CFx signal proportional to the sum of phase apparent powers

AVAHR, BVAHR, CVAHR

011

CFx signal proportional to the sum of fundamental phase active

powers

AFWATTHR, BFWATTHR, CFWATTHR

100

CFx signal proportional to the sum of fundamental phase reactive

powers

AFVARHR, BFVARHR, CFVARHR

101 to 111

Reserved

Rev. A | Page 65 of 104

ADE7880

Data Sheet

10³

By default, the TERMSELx bits are all 1 and the CF1SEL bits are

000, the CF2SEL bits are 100, and the CF3SEL bits are 010. This

means that by default, the CF1 digital-to-frequency converter

produces signals proportional to the sum of all 3-phase total

active powers, CF2 produces signals proportional to fundamental

reactive powers, and CF3 produces signals proportional to

apparent powers.

CFxDEN =

(49)

MC[imp/kwh]×10ⁿ

The derivative of wh must be chosen in such a way to obtain a

CFxDEN register content greater than 1. If CFxDEN = 1, then

the CFx pin stays active low for only 1 μs. Thus, CFxDEN

register should not be set to 1. The frequency converter cannot

accommodate fractional results; the result of the division must be

rounded to the nearest integer. If CFxDEN is set equal to 0, then

the ADE7880 considers it to be equal to 1.

Similar to the energy accumulation process, the energy-to-

frequency conversion is accomplished in two stages. The first

stage is the same stage illustrated in the energy accumulation

sections of active, reactive and apparent powers (see Active

Energy Calculation, Fundamental Reactive Energy Calculation,

Apparent Energy Calculation sections). The second stage

consists of the frequency divider by the CFxDEN 16-bit

unsigned registers. The values of CFxDEN depend on the meter

constant (MC), measured in impulses/kWh and how much

energy is assigned to one LSB of various energy registers:

xWATTHR, xFVARHR, and so forth. Suppose a derivative of

Wh [10ⁿWh] where n is a positive or negative integer, is desired

as one LSB of xWATTHR register. Then, CFxDEN is as follows:

The CFx pulse output stays low for 80 ms if the pulse period is

larger than 160 ms (6.25 Hz). If the pulse period is smaller than

160 ms and CFxDEN is an even number, the duty cycle of the

pulse output is exactly 50ꢀ. If the pulse period is smaller than

160 ms and CFxDEN is an odd number, the duty cycle of the

pulse output is

(1+1/CFxDEN) × 50ꢀ

TERMSELx BITS IN

COMPMODE

CFxSEL BITS IN

CFMODE

INSTANTANEOUS

PHASE A

ACTIVE POWER

VA

WATT

FWATT

FVAR

7

2

INSTANTANEOUS

PHASE B

ACTIVE POWER

REVPSUMx BIT OF

STATUS0[31:0]

INTERNAL

ACCUMULATOR

CFx PULSE

FREQ DIVIDER

OUTPUT

INSTANTANEOUS

PHASE C

ACTIVE POWER

THRESHOLD

CFxDEN

DIGITAL SIGNAL

PROCESSOR

7

2

34

27 26

0

WTHR

0

Figure 87. Energy-to-Frequency Conversion

Rev. A | Page 66 of 104

Data Sheet

ADE7880

The CFx pulse output is active low and preferably connected to

an LED, as shown in Figure 88.

Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the

CFMODE register enable this process when set to 1. When

cleared to 0, the default state, no latch occurs. The process is

available even if the CFx output is not enabled by the CFxDIS

bits in the CFMODE register.

V

DD

CFx PIN

Energy Registers and CF Outputs for Various

Accumulation Modes

Bits[1:0] (WATTACC[1:0]) in the ACCMODE register deter-

mine the accumulation modes of the total and fundamental active

powers when signals proportional to the active powers are chosen

at the CFx pins (the CFxSEL[2:0] bits in the CFMODE register

equal 000 or 011). They also determine the accumulation modes

of the watt-hour energy registers (AWATTHR, BWATTHR,

CWAT THR, AFWAT THR, BFWAT THR and CFWAT THR).

When WATTACC[1:0] = 00 (the default value), the active powers

are sign accumulated in the watt-hour registers and before entering

the energy-to-frequency converter. Figure 90 shows how signed

active power accumulation works. In this mode, the CFx pulses

synchronize perfectly with the active energy accumulated in

xWATTHR registers because the powers are sign accumulated in

both data paths.

Figure 88. CFx Pin Recommended Connection

Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE

register decide if the frequency converter output is generated at

the CF3, CF2, or CF1 pin. When Bit CFxDIS is set to 1 (the

default value), the CFx pin is disabled and the pin stays high.

When Bit CFxDIS is cleared to 0, the corresponding CFx pin

output generates an active low signal.

Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask register

MASK0 manage the CF3, CF2, and CF1 related interrupts.

When the CFx bits are set, whenever a high-to-low transition at

the corresponding frequency converter output occurs, an

IRQ0

interrupt

is triggered and a status bit in the STATUS0

register is set to 1. The interrupt is available even if the CFx

output is not enabled by the CFxDIS bits in the CFMODE

register.

ACTIVE ENERGY

Synchronizing Energy Registers with CFx Outputs

The ADE7880 contains a feature that allows synchronizing the

content of phase energy accumulation registers with the

generation of a CFx pulse. When a high-to-low transition at one

frequency converter output occurs, the content of all internal

phase energy registers that relate to the power being output at

CFx pin is latched into hour registers and then resets to 0.

See Table 23 for the list of registers that are latched based on

the CFxSEL[2:0] bits in the CFMODE register. All 3-phase

registers are latched independent of the TERMSELx bits of the

COMPMODE register. The process is shown in Figure 89 for

CF1SEL[2:0] = 010 (apparent powers contribute at the CF1 pin)

and CFCYC = 2.

NO-LOAD

THRESHOLD

ACTIVE POWER

NO-LOAD

THRESHOLD

REVAPx BIT

IN STATUS0

xWSIGN BIT

IN PHSIGN

APNOLOAD

SIGN = POSITIVE

POS

NEG POS NEG

Figure 90. Active Power Signed Accumulation Mode

The CFCYC 8-bit unsigned register contains the number of

high to low transitions at the frequency converter output between

two consecutive latches. Avoid writing a new value into the

CFCYC register during a high-to-low transition at any CFx pin.

When WATTACC[1:0] = 01, the active powers are accumulated

in positive only mode. When the powers are negative, the watt-

hour energy registers are not accumulated. CFx pulses are

generated based on signed accumulation mode. In this mode,

the CFx pulses do not synchronize perfectly with the active

energy accumulated in xWATTHR registers because the powers are

accumulated differently in each data path. Figure 91 shows how

positive only active power accumulation works.

CF1 PULSE

BASED ON

PHASE A AND

PHASE B

APPARENT

POWERS

CFCYC = 2

AVAHR, BVAHR,

CVAHR LATCHED

ENERGY REGISTERS

RESET

AVAHR, BVAHR,

CVAHR LATCHED

ENERGY REGISTERS

RESET

WATTACC[1:0] = 10 setting is reserved and the ADE7880

behaves identically to the case when WATTACC[1:0] = 00.

Figure 89. Synchronizing AVAHR and BVAHR with CF1

When WATTACC[1:0] = 11, the active powers are accumulated

in absolute mode. When the powers are negative, they change

sign and accumulate together with the positive power in the

watt-hour registers and before entering the energy-to-frequency

Rev. A | Page 67 of 104

ADE7880

Data Sheet

converter. In this mode, the CFx pulses synchronize perfectly

with the active energy accumulated in xWATTHR registers because

the powers are accumulated in the same way in both data paths.

Figure 92 shows how absolute active power accumulation works.

ACTIVE ENERGY

NO-LOAD

THRESHOLD

ACTIVE ENERGY

ACTIVE POWER

NO-LOAD

THRESHOLD

NO-LOAD

THRESHOLD

ACTIVE POWER

REVAPx BIT

IN STATUS0

NO-LOAD

THRESHOLD

xWSIGN BIT

IN PHSIGN

REVAPx BIT

IN STATUS0

POS

NEG POS NEG

APNOLOAD

SIGN = POSITIVE

xWSIGN BIT

IN PHSIGN

Figure 92. Active Power Absolute Accumulation Mode

POS

NEG POS NEG

APNOLOAD

SIGN = POSITIVE

Figure 91. Active Power Positive Only Accumulation Mode

REACTIVE

ENERGY

Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine the

accumulation modes of the fundamental reactive powers when

signals proportional to the fundamental reactive powers are

chosen at the CFx pins (the CFxSEL[2:0] bits in the CFMODE

register equal 100). When VARACC[1:0] = 00, the default value,

the fundamental reactive powers are sign accumulated in the

var-hour energy registers and before entering the energy-to-

frequency converter. Figure 93 shows how signed fundamental

reactive power accumulation works. In this mode, the CFx

pulses synchronize perfectly with the fundamental reactive

energy accumulated in the xFVARHR registers because the

powers are sign accumulated in both data paths.

NO-LOAD

THRESHOLD

REACTIVE

POWER

NO-LOAD

THRESHOLD

REVRPx BIT

IN STATUS0

xVARSIGN BIT

IN PHSIGN

POS

NEG POS NEG

VARNOLOAD

SIGN = POSITIVE

VARACC[1:0] = 01 setting is reserved and ADE7880 behaves

identically to the case when VARACC[1:0] = 00.

Figure 93. Fundamental Reactive Power Signed Accumulation Mode

When VARACC[1:0] = 11, the fundamental reactive powers are

accumulated in absolute mode. When the powers are negative,

they change sign and accumulate together with the positive

power in the var-hour registers. CFx pulses are generated based

on signed accumulation mode. In this mode, the CFx pulses do

not synchronize perfectly with the fundamental reactive energy

accumulated in x VARHR registers because the powers are

accumulated differently in each data path. Figure 95 shows how

absolute fundamental reactive power accumulation works.

When VARACC[1:0] = 10, the fundamental reactive powers are

accumulated depending on the sign of the corresponding active

power in the var-hour energy registers and before entering the

energy-to-frequency converter. If the fundamental active power

is positive or considered 0 when lower than the no load threshold,

the fundamental reactive power is accumulated as is. If the

fundamental active power is negative, the sign of the fundamental

reactive power is changed for accumulation. Figure 94 shows how

the sign adjusted fundamental reactive power accumulation

mode works. In this mode, the CFx pulses synchronize perfectly

with the fundamental reactive energy accumulated in xFVARHR

registers because the powers are accumulated in the same way in

both data paths.

Sign of Sum-of-Phase Powers in the CFx Datapath

The ADE7880 has sign detection circuitry for the sum of phase

powers that are used in the CFx data path. As seen in the

beginning of the Energy-to-Frequency Conversion section, the

energy accumulation in the CFx data path is executed in two

stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is, after the

Rev. A | Page 68 of 104

Data Sheet

ADE7880

energy accumulated into the accumulator reaches one of the

WTHR, VARTHR, or VATHR thresholds, a dedicated interrupt

can be triggered synchronously with the corresponding CFx

pulse. The sign of each sum can be read in the PHSIGN register.

indicate the sign of the sum of phase powers. When cleared to

0, the sum is positive. When set to 1, the sum is negative.

Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,

REVPSUM2, and REVPSUM1, respectively) in the STATUS0

register are enabled by setting Bit 18, Bit 13, and Bit 9 in the

IRQ0

MASK0 register. If enabled, the

pin is set low, and the

status bit is set to 1 whenever a change of sign occurs. To find

the phase that triggered the interrupt, the PHSIGN register is

read immediately after reading the STATUS0 register. Next, the

REACTIVE

ENERGY

NO-LOAD

THRESHOLD

IRQ0

status bit is cleared, and the

pin is set high again by writing

REACTIVE

POWER

to the STATUS0 register with the corresponding bit set to 1.

NO-LOAD

THRESHOLD

NO LOAD CONDITION

NO-LOAD

THRESHOLD

The no load condition is defined in metering equipment standards

as occurring when the voltage is applied to the meter and no cur-

rent flows in the current circuit. To eliminate any creep effects in

the meter, the ADE7880 contains three separate no load

detection circuits: one related to the total active power, one

related to the fundamental active and reactive powers, and one

related to the apparent powers.

ACTIVE

POWER

REVRPx BIT

IN STATUS0

xVARSIGN BIT

IN PHSIGN

POS NEG POS

VARNOLOAD

SIGN = POSITIVE

No Load Detection Based On Total Active Power and

Apparent Power

Figure 94. Fundamental Reactive Power Accumulation in Sign

Adjusted Mode

This no load condition uses the total active energy and the

apparent energy to trigger this no load condition. The apparent

energy is proportional to the rms values of the corresponding

phase current and voltage. If neither total active energy nor

apparent energy are accumulated for a time indicated in the

respective APNOLOAD and VANOLOAD unsigned 16-bit

registers, the no load condition is triggered, the total active

energy of that phase is not accumulated and no CFx pulses are

generated based on the total active energy.

REACTIVE ENERGY

NO-LOAD

THRESHOLD

The equations used to compute the APNOLOAD and

VANOLOAD unsigned 16-bit values are

REACTIVE POWER

Y ×WTHR×2¹⁷

NO-LOAD

APNOLOAD= 2¹⁶

VANOLOAD= 2¹⁶

−

THRESHOLD

PMAX

REVAPx BIT

IN STATUS0

Y ×VATHR×2¹⁷

−

(50)

xVARSIGN BIT

IN PHSIGN

PMAX

where:

POS

NEG POS NEG

VARNOLOAD

SIGN = POSITIVE

Y is the required no load current threshold computed relative to

full scale. For example, if the no load threshold current is set

10,000 times lower than full scale value, then Y = 10,000.

WTHR and VATHR represent values stored in the WTHR and

VATHR registers and are used as the thresholds in the first stage

energy accumulators for active and apparent energy, respectively

(see Active Energy Calculation section). PMAX = 27,059,678 =

0x19CE5DE, the instantaneous active power computed when

the ADC inputs are at full scale.

Figure 95. Fundamental Reactive Power Accumulation in Absolute Mode

Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and

REVPSUM1, respectively) of the STATUS0 register are set

to 1 when a sign change of the sum of powers in CF3, CF2,

or CF1 data paths occurs. To correlate these events with the

pulses generated at the CFx pins, after a sign change occurs,

Bit REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 are set

in the same moment in which a high-to-low transition at the

CF3, CF2, and CF1 pin, respectively, occurs.

Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and SUM1SIGN,

respectively) of the PHSIGN register are set in the same moment

with Bit REVPSUM3, Bit REVPSUM2, and Bit EVPSUM1 and

Rev. A | Page 69 of 104

ADE7880

Data Sheet

An interrupt attached to the Bit 1 (FNLOAD) in the STATUS1

register can be enabled by setting Bit 1 in the MASK1 register. If

The VANOLOAD register usually contains the same value

as the APNOLOAD register. When APNOLOAD and

IRQ1

enabled, the

pin is set low and the status bit is set to 1

VANOLOAD are set to 0x0, the no load detection circuit

is disabled. If only VANOLOAD is set to 0, then the no load

condition is triggered based only on the total active power

being lower than APNOLOAD. In the same way, if only

APNOLOAD is set to 0x0, the no load condition is triggered

based only on the apparent power being lower than VANOLOAD.

whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD register is read immediately after reading the

IRQ1

STATUS1 register. Then the status bit is cleared and the

pin is set back high by writing to the STATUS1 register with the

corresponding bit set to 1.

Bit 0 (NLOAD) in the STATUS1 register is set when a no load

condition in one of the three phases is triggered. Bits[2:0]

(NLPHASE[2:0]) in the PHNOLOAD register indicate the state

of all phases relative to a no load condition and are set simulta-

neously with Bit NLOAD in the STATUS1 register. NLPHASE[0]

indicates the state of Phase A, NLPHASE[1] indicates the state

of Phase B, and NLPHASE[2] indicates the state of Phase C.

When Bit NLPHASE[x] is cleared to 0, it means the phase is out

of a no load condition. When set to 1, it means the phase is in a

no load condition.

No Load Detection Based on Apparent Power

This no load condition is triggered when no less significant bits

are accumulated into the apparent energy register on one phase

(xVAHR, x = A, B, or C) for a time indicated by the VANOLOAD

unsigned 16-bit register. In this case, the apparent energy of that

phase is not accumulated and no CFx pulses are generated based

on this energy.

The equation used to compute the VANOLOAD unsigned

16-bit value is

An interrupt attached to Bit 0 (NLOAD) in the STATUS1

register can be enabled by setting Bit 0 in the MASK1 register.

Y ×VATHR×2¹⁷

VANOLOAD= 2¹⁶

−

(51)

PMAX

IRQ1

If enabled, the

pin is set to low, and the status bit is set

to 1 whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD register is read immediately after reading the

where:

Y is the required no load current threshold computed relative to

full scale. For example, if the no load threshold current is set

10,000 times lower than full scale value, then Y=10,000.

IRQ1

STATUS1 register. Next, the status bit is cleared, and the

pin is set to high by writing to the STATUS1 register with the

corresponding bit set to 1.

VATHR is the VATHR register used as the threshold of the first

stage energy accumulator (see Apparent Energy Calculation

section) PMAX = 27,059,678 = 0x19CE5DE, the instantaneous

apparent power computed when the ADC inputs are at full

scale. When the VANOLOAD register is set to 0x0, the no load

detection circuit is disabled.

No Load Detection Based on Fundamental Active and

Reactive Powers

This no load condition is triggered when no less significant bits

are accumulated into the fundamental active and reactive energy

registers on one phase (xFWATTHR and xFVARHR, x = A, B,

or C) for a time indicated in the respective APNOLOAD and

VARNOLOAD unsigned 16-bit registers. In this case, the

fundamental active and reactive energies of that phase are not

accumulated and no CFx pulses are generated based on these

energies. APNOLOAD is the same no load threshold set for

the total active powers. The VARNOLOAD register usually

contains the same value as the APNOLOAD register. If only

APNOLOAD is set to 0x0, then the fundamental active power

is accumulated without restriction. In the same way, if only

VARNOLOAD is set to 0x0, the fundamental reactive power is

accumulated without restriction.

Bit 2 (VANLOAD) in the STATUS1 register is set when this no

load condition in one of the three phases is triggered. Bits[8:6]

(VANLPHASE[2:0]) in the PHNOLOAD register indicate the

state of all phases relative to a no load condition and they are set

simultaneously with Bit VANLOAD in the STATUS1 register:

•

Bit VANLPHASE[0] indicates the state of Phase A.

Bit VANLPHASE[1] indicates the state of Phase B.

Bit VANLPHASE[2] indicates the state of Phase C.

When Bit VANLPHASE[x] is cleared to 0, it means the phase is

out of no load condition. When set to 1, it means the phase is in

no load condition.

Bit 1 (FNLOAD) in the STATUS1 register is set when this no

load condition in one of the three phases is triggered. Bits[5:3]

(FNLPHASE[2:0]) in the PHNOLOAD register indicate the

state of all phases relative to a no load condition and are set

simultaneously with Bit FNLOAD in the STATUS1 register.

FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]

indicates the state of Phase B, and FNLPHASE[2] indicates the

state of Phase C. When Bit FNLPHASE[x] is cleared to 0, it

means the phase is out of the no load condition. When set to 1,

it means the phase is in a no load condition.

An interrupt attached to Bit 2 (VANLOAD) in the STATUS1

register is enabled by setting Bit 2 in the MASK1 register. If

IRQ1

enabled, the

pin is set low and the status bit is set to 1

whenever one of three phases enters or exits this no load

condition. To find the phase that triggered the interrupt, the

PHNOLOAD register is read immediately after reading the

IRQ1

STATUS1 register. Next, the status bit is cleared, and the

pin is set to high by writing to the STATUS1 register with the

corresponding bit set to 1.

Rev. A | Page 70 of 104

Data Sheet

ADE7880

•

g_i, i = 0, 1, 2, …, 31 are the coefficients of the generating

polynomial defined by the IEEE802.3 standard as follows:

CHECKSUM REGISTER

The ADE7880 has a checksum 32-bit register, CHECKSUM, that

ensures the configuration registers maintain their desired value

during Normal Power Mode PSM0.

G(x) = x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+

x⁵+ x⁴+ x²+ x + 1

(52)

The registers covered by this register are MASK0, MASK1,

COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,

CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,

all registers located in the DSP data memory RAM between

Address 0x4380 and Address 0x43BE and another eight 8-bit

reserved internal registers that always have default values. The

ADE7880 computes the cyclic redundancy check (CRC) based

on the IEEE802.3 standard. The registers are introduced one-by-

one into a linear feedback shift register (LFSR) based generator

starting with the least significant bit (as shown in Figure 96).

The 32-bit result is written in the CHECKSUM register. After

power-up or a hardware/software reset, the CRC is computed

on the default values of the registers giving a result equal to

0xAFFA63B9.

g₀= g₁= g₂= g₄= g₅= g₇= 1

g₈= g₁₀= g₁₁= g₁₂= g₁₆= g₂₂= g₂₆= 1

(53)

All of the other g_icoefficients are equal to 0.

FB(j) = a_{j – 1}XOR b₃₁(j − 1)

(54)

(55)

b₀(j) = FB(j) AND g₀

b_i(j) = FB(j) AND g_iXOR b_{i – 1}(j – 1), i = 1, 2, 3, ..., 31 (56)

Equation 54, Equation 55, and Equation 56 must be repeated for

j = 1, 2, …, 2272. The value written into the CHECKSUM register

contains the Bit b_i(2272), i = 0, 1, …, 31.

Every time a configuration register of the ADE7880 is written or

changes value inadvertently, the Bit 25 (CRC) in STATUS1 register

is set to 1 to signal CHECKSUM value has changed. If Bit 25 (CRC)

IRQ1

in MASK1 register is set to 1, then the

low and the status flag CRC in STATUS1 is set to 1. The status bit is

IRQ1

interrupt pin is driven

Figure 97 shows how the LFSR works: the MASK0, MASK1,

COMPMODE, Gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,

CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG

registers, the registers located between Address 0x4380, and

Address 0x43BE and the eight 8-bit reserved internal registers

form the bits [a₂₂₇₁, a₂₂₇₀,…, a₀] used by LFSR. Bit a₀is the least

significant bit of the first register to enter LFSR; Bit a₂₂₇₁is the

most significant bit of the last register to enter LFSR. The

formulas that govern LFSR are as follows:

cleared and the

pin is set to high by writing to the STATUS1

register with the status bit set to 1.

When Bit CRC in STATUS1 is set to 1 without any register

being written, it can be assumed that one of the registers has

changed value and therefore, the ADE7880 has changed

configuration. The recommended response is to initiate a

hardware/software reset that sets the values of all registers to the

default, including the reserved ones, and then reinitialize the

configuration registers.

•

b_i(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that

form the CRC. Bit b₀is the least significant bit, and Bit b₃₁

is the most significant.

2271

0

LFSR

GENERATOR

ARRAY OF 2272 BITS

Figure 96. CHECKSUM Register Calculation

g₀

g₁

g₂

g₃

g₃₁

FB

b₀

b₁

b₂

b₃₁

LFSR

a₁₇₆₇, a₁₇₆₆,....,a₂, a₁, a₀

Figure 97. LFSR Generator Used in CHECKSUM Register Calculation

Rev. A | Page 71 of 104

ADE7880

Data Sheet

The following bits in the MASK0 register work with the status bits

in the PHSIGN register:

INTERRUPTS

IRQ0

IRQ1

and . Each of the

The ADE7880 has two interrupt pins,

•

Bits[6:8] (REVAPx)

Bits[10:12] (REVRPx)

Bit 9, Bit 13, and Bit 18 (REVPSUMx)

pins is managed by a 32-bit interrupt mask register, MASK0 and

MASK1, respectively. To enable an interrupt, a bit in the MASKx

register must be set to 1. To disable it, the bit must be cleared

to 0. Two 32-bit status registers, STATUS0 and STATUS1, are

associated with the interrupts. When an interrupt event occurs

in the ADE7880, the corresponding flag in the interrupt status

register is set to a logic 1 (see Table 36 and Table 37). If the mask

bit for this interrupt in the interrupt mask register is logic 1,

When the STATUSx register is read and one of these bits is set

to 1, the status register associated with the bit is immediately

read to identify the phase that triggered the interrupt and only

at that time can the STATUSx register be written back with the bit

set to 1.

IRQx

then the

logic output goes active low. The flag bits in the

Using the Interrupts with an MCU

interrupt status register are set irrespective of the state of the mask

bits. To determine the source of the interrupt, the MCU should

perform a read of the corresponding STATUSx register and

identify which bit is set to 1. To erase the flag in the status register,

write back to the STATUSx register with the flag set to 1. After an

interrupt pin goes low, the status register is read and the source of

the interrupt is identified. Then, the status register is written back

IRQx

Figure 98 shows a timing diagram that illustrates a suggested

implementation of the ADE7880 interrupt management using an

IRQx

MCU. At Time t₁, the

pin goes active low indicating that

one or more interrupt events have occurred in the ADE7880, at

which point the following steps should be taken:

IRQx

1. Tie the

pin to a negative-edge-triggered external

interrupt on the MCU.

without any change to clear the status flag to 0. The

remains low until the status flag is cancelled.

2. On detection of the negative edge, configure the MCU to

start executing its interrupt service routine (ISR).

3. On entering the ISR, disable all interrupts using the global

interrupt mask bit. At this point, the MCU external

interrupt flag can be cleared to capture interrupt events

that occur during the current ISR.

4. When the MCU interrupt flag is cleared, a read from

STATUSx, the interrupt status register, is carried out. The

interrupt status register content is used to determine the

source of the interrupt(s) and, hence, the appropriate

action to be taken.

By default, all interrupts are disabled. However, the RSTDONE

interrupt is an exception. This interrupt can never be masked

(disabled) and, therefore, Bit 15 (RSTDONE) in the MASK1

IRQ1

register does not have any functionality. The

pin always

goes low, and Bit 15 (RSTDONE) in the STATUS1 register is set

to 1 whenever a power-up or a hardware/software reset process

ends. To cancel the status flag, the STATUS1 register has to be

written with Bit 15 (RSTDONE) set to 1.

Certain interrupts are used in conjunction with other status

registers. The following bits in the MASK1 register work in

conjunction with the status bits in the PHNOLOAD register:

5. The same STATUSx content is written back into the

IRQx

ADE7880 to clear the status flag(s) and reset the

to logic high (t₂).

line

•

Bit 0 (NLOAD)

Bit 1 (FNLOAD)

Bit 2 (VANLOAD)

If a subsequent interrupt event occurs during the ISR (t₃), that

event is recorded by the MCU external interrupt flag being

set again.

The following bits in the MASK1 register work with the status bits

in the PHSTATUS register:

On returning from the ISR, the global interrupt mask bit is

cleared (same instruction cycle) and the external interrupt flag

uses the MCU to jump to its ISR once again. This ensures that

the MCU does not miss any external interrupts.

•

Bit 16, (SAG)

Bit 17 (OI)

Bit 18 (OV)

Figure 99 shows a recommended timing diagram when the

status bits in the STATUSx registers work in conjunction with

The following bits in the MASK1 register work with the status bits

in the IPEAK and VPEAK registers, respectively:

IRQx

bits in other registers. When the

pin goes active low, the

•

Bit 23 (PKI)

Bit 24 (PKV)

STATUSx register is read, and if one of these bits is 1, a second

status register is read immediately to identify the phase that

triggered the interrupt. The name, PHx, in Figure 99 denotes

one of the PHSTATUS, IPEAK, VPEAK, or PHSIGN registers.

Then, STATUSx is written back to clear the status flag(s).

Rev. A | Page 72 of 104

Data Sheet

ADE7880

MCU

INTERRUPT

FLAG SET

t₁

t₂

t₃

IRQx

WRITE

GLOBAL

INTERRUPT

MASK

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

CLEAR MCU

INTERRUPT

FLAG

READ

STATUSx

JUMP

TO ISR

PROGRAM

SEQUENCE

ISR ACTION

(BASED ON STATUSx CONTENTS)

JUMP

TO ISR

BACK

STATUSx

Figure 98. Interrupt Management

MCU

INTERRUPT

FLAG SET

t₁

t₂

t₃

IRQx

WRITE

READ

GLOBAL

INTERRUPT

MASK

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

CLEAR MCU

INTERRUPT

FLAG

ISR ACTION

(BASED ON STATUSx CONTENTS)

READ

STATUSx

JUMP

TO ISR

PROGRAM

SEQUENCE

JUMP

TO ISR

BACK

PHx

STATUSx

Figure 99. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved

read using either the I²C or SPI interfaces. The HSDC port

provides the state of up to 16 registers representing instantaneous

values of phase voltages and neutral currents, and active, reactive,

and apparent powers.

SERIAL INTERFACES

The ADE7880 has three serial port interfaces: one fully licensed

I²C interface, one serial peripheral interface (SPI), and one high

speed data capture port (HSDC). As the SPI pins are multiplexed

with some of the pins of the I²C and HSDC ports, the ADE7880

accepts two configurations: one using the SPI port only and one

using the I²C port in conjunction with the HSDC port.

Communication Verification

The ADE7880 includes a set of three registers that allow any

communication via I²C or SPI to be verified. The LAST_OP

(Address 0xEA01), LAST_ADD (Address 0xE9FE) and

LAST_RWDATA registers record the nature, address and data

of the last successful communication respectively. The

LAST_RWDATA register has three separate addresses

depending on the length of the successful communication.

Serial Interface Choice

After reset, the HSDC port is always disabled. Choose between

2

SS

the I C and SPI ports by manipulating the /has pin after

power-up or after a hardware reset. If the /HSA pin is kept

high, then the ADE7880 uses the I²C port until a new hardware

SS

reset is executed. If the /HSA pin is toggled high to low three

Table 24. LAST_RWDATA Register Locations

times after power-up or after a hardware reset, the ADE7880

uses the SPI port until a new hardware reset is executed. This

Communication type

Address

0xE7FD

0xE9FF

0xE5FF

8-Bit Read/Write

16-Bit Read/Write

24-Bit Read/Write

SS

manipulation of the /HSA pin can be accomplished in two

SS

ways. First, use the /HSA pin of the master device (that is, the

microcontroller) as a regular I/O pin and toggle it three times.

Second, execute three SPI write operations to a location in the

address space that is not allocated to a specific ADE7880 register

(for example 0xEBFF, where eight bit writes can be executed).

After each successful communication with the ADE7880, the

address of the register that was last accessed is stored in the

16-bit LAST_ADD register (Address 0xE9FE). This is a read

only register that stores the value until the next successful read

or write is complete. The LAST_OP register (Address 0xEA01)

stores the nature of the operation. That is, it indicates whether a

read or a write was performed. If the last operation is a write,

the LAST_OP register stores the value 0xCA. If the last

operation is a read, the LAST_OP register stores the value 0x35.

The LAST_RWDATA register stores the data that was written

or read from the register. Any unsuccessful read or write

operation is not reflected in these registers.

SS

These writes allow the /HSA pin to toggle three times. See the

SPI Write Operation section for details on the write protocol

involved.

After the serial port choice is completed, it needs to be locked.

Consequently, the active port remains in use until a hardware

reset is executed in PSM0 normal mode or until a power-down.

If I²C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2

register must be set to 1 to lock it in. From this moment, the

SS

ADE7880 ignores spurious toggling of the pin and an eventual

When LAST_OP, LAST_ADD and LAST_RWDATA registers

are read, their values are not stored into themselves.

switch into using the SPI port is no longer possible. If the SPI is

the active serial port, any write to the CONFIG2 register locks

the port. From this moment, a switch into using the I²C port is

no longer possible. Once locked, the serial port choice is

maintained when the ADE7880 changes PSMx power modes.

The functionality of the ADE7880 is accessible via several on-

chip registers. The contents of these registers can be updated or

Rev. A | Page 73 of 104

ADE7880

Data Sheet

I²C-Compatible Interface

I²C Write Operation

The ADE7880 supports a fully licensed I²C interface. The I²C

interface is implemented as a full hardware slave. SDA is the

data I/O pin, and SCL is the serial clock. These two pins are

shared with the MOSI and SCLK pins of the on-chip SPI

interface. The maximum serial clock frequency supported by this

interface is 400 kHz.

The write operation using the I²C interface of the ADE7880

initiate when the master generates a start condition and consists

in one byte representing the address of the ADE7880 followed

by the 16-bit address of the target register and by the value of

the register.

The most significant seven bits of the address byte constitute

the address of the ADE7880 and they are equal to 0111000b.

The two pins used for data transfer, SDA and SCL, are configured

in a wire-AND’ed format that allows arbitration in a multimaster

system.

The transfer sequence of an I²C system consists of a master device

initiating a transfer by generating a start condition while the bus

is idle. The master transmits the address of the slave device and

the direction of the data transfer in the initial address transfer. If

the slave acknowledges, the data transfer is initiated. This

continues until the master issues a stop condition, and the bus

becomes idle.

write

Bit 0 of the address byte is a read/

bit. Because this is a

write operation, it has to be cleared to 0; therefore, the first byte

of the write operation is 0x70. After every byte is received, the

ADE7880 generates an acknowledge. As registers can have 8, 16,

or 32 bits, after the last bit of the register is transmitted and the

ADE7880 acknowledges the transfer, the master generates a

stop condition. The addresses and the register content are sent

with the most significant bit first. See Figure 100 for details of

the I²C write operation.

15

8

7

0

31

24

23

16

15

8

7

0

S

0

1

0

S

SLAVE ADDRESS

MOST SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

LESS SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

BYTE 3 (MOST

SIGNIFICANT)

OF REGISTER

BYTE 2 OF REGISTER

BYTE 1 OF REGISTER

BYTE 0 (LESS

SIGNIFICANT) OF

REGISTER

ACK GENERATED

BY ADE7880

Figure 100. I²C Write Operation of a 32-Bit Register

Rev. A | Page 74 of 104

Data Sheet

ADE7880

I²C Read Operation

with the master generating a new start condition followed by an

address byte. The most significant seven bits of this address byte

constitute the address of the ADE7880, and they are equal to

The read operation using the I²C interface of the ADE7880 is

accomplished in two stages. The first stage sets the pointer to

the address of the register. The second stage reads the content of

the register.

write

0111000b. Bit 0 of the address byte is a read/

bit. Because this

is a read operation, it must be set to 1; thus, the first byte of the

read operation is 0x71. After this byte is received, the ADE7880

generates an acknowledge. Then, the ADE7880 sends the value

of the register, and after every eight bits are received, the master

generates an acknowledge. All the bytes are sent with the most

significant bit first. Because registers can have 8, 16, or 32 bits,

after the last bit of the register is received, the master does not

acknowledge the transfer but generates a stop condition.

As seen in Figure 101, the first stage initiates when the master

generates a start condition and consists in one byte representing

the address of the ADE7880 followed by the 16-bit address of the

target register. The ADE7880 acknowledges every byte received.

The address byte is similar to the address byte of a write operation

and is equal to 0x70 (see the I²C Write Operation section for

details). After the last byte of the register address has been sent

and acknowledged by the ADE7880, the second stage begins

15

8

7

0

S

0 1 1 1 0 0 0 0

SLAVE ADDRESS

MOST SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

LESS SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

ACK GENERATED

BY ADE7880

ACKNOWLEDGE

GENERATED BY

MASTER

31

24

23

16

15

8

7

0

S

0

1

0

1

S

SLAVE ADDRESS

BYTE 3

(MOST SIGNIFICANT)

OF REGISTER

BYTE 2 OF

REGISTER

BYTE 1 OF

REGISTER

BYTE 0

(LESS SIGNIFICANT)

OF REGISTER

ACK GENERATED

BY ADE7880

Figure 101. I²C Read Operation of a 32-Bit Register

15

8

7

0

S

0

1

1 1 0 0 0 0

SLAVE ADDRESS

MOST SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

LESS SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

ACK GENERATED

BY ADE7880

ACKNOWLEDGE

GENERATED BY

MASTER

31

24

7

0

31

24

7

0

S

0

1

0

1

S

SLAVE ADDRESS

BYTE 3

(MOST SIGNIFICANT)

OF REGISTER 0

BYTE 0

(LESS SIGNIFICANT)

OF REGISTER 0

BYTE 3

(MOST SIGNIFICANT)

OF REGISTER 1

BYTE 0

(LESS SIGNIFICANT)

OF REGISTER n

ACK GENERATED

BY ADE7880

Figure 102. I²C Read Operation of n 32-Bit Harmonic Calculations Registers

Rev. A | Page 75 of 104

ADE7880

Data Sheet

I²C Read Operation of Harmonic Calculations Registers

connection between the ADE7880 SPI and a master device

containing an SPI interface.

The registers containing the harmonic calculation results are

located starting at Address 0xE880 and are all 32-bit width.

They can be read in two ways: one register at a time (see the I²C

Read Operation section for details) or multiple consecutive

registers at a time in a burst mode. This burst mode is

accomplished in two stages. As seen in Figure 102, the first

stage sets the pointer to the address of the register and is

identical to the first stage executed when only one register is

read. The second stage reads the content of the registers. The

second stage begins with the master generating a new start

condition followed by an address byte equal to the address byte

used when one single register is read, 0x71. After this byte is

received, the ADE7880 generates an acknowledge. Then, the

ADE7880 sends the value of the first register located at the

pointer, and after every eight bits are received, the master

generates an acknowledge. All the bytes are sent with the most

significant bit first. After the bytes of the first register are sent, if

the master acknowledges the last byte, the ADE7880 increments

the pointer by one location to position it at the next register and

begins to send it out byte by byte, most significant bit first. If the

master acknowledges the last byte, the ADE7880 increments the

pointer again and begins to send data from the next register.

The process continues until the master ceases to generate an

acknowledge at the last byte of the register and then generates a

stop condition. It is recommended to not allow locations greater

then 0xE89F, the last location of the harmonic calculations

registers.

SS

The logic input is the chip select input. This input is used

SS

when multiple devices share the serial bus. Drive the input

SS

low for the entire data transfer operation. Bringing high

during a data transfer operation aborts the transfer and places

the serial bus in a high impedance state. A new transfer can

SS

then be initiated by returning the logic input to low.

However, because aborting a data transfer before completion

leaves the accessed register in a state that cannot be guaranteed,

every time a register is written, its value should be verified by

reading it back. The protocol is similar to the protocol used in

I²C interface.

SPI DEVICE

ADE7880

MOSI

MISO

SCLK

SS

MISO

SCK

SS

Figure 103. Connecting ADE7880 SPI with an SPI Device

SPI Read Operation

The read operation using the SPI interface of the ADE7880

SS

initiate when the master sets the /HSA pin low and begins

sending one byte, representing the address of the ADE7880, on

the MOSI line. The master sets data on the MOSI line starting

with the first high-to-low transition of SCLK. The SPI of the

ADE7880 samples data on the low-to-high transitions of SCLK.

The most significant seven bits of the address byte can have any

value, but as a good programming practice, they should be

different from 0111000b, the seven bits used in the I²C protocol.

SPI-Compatible Interface

The SPI of the ADE7880 is always a slave of the communication

and consists of four pins (with dual functions): SCLK/SCL,

write

Bit 0 (read/

) of the address byte must be 1 for a read

SS

MOSI/SDA, MISO/HSD, and /HSA. The functions used in

operation. Next, the master sends the 16-bit address of the

register that is read. After the ADE7880 receives the last bit of

address of the register on a low-to-high transition of SCLK, it

begins to transmit its contents on the MISO line when the next

SCLK high-to-low transition occurs; thus, the master can

sample the data on a low-to-high SCLK transition. After the

SS

the SPI-compatible interface are SCLK, MOSI, MISO, and

.

The serial clock for a data transfer is applied at the SCLK logic

input. All data transfer operations synchronize to the serial

clock. Data shifts into the ADE7880 at the MOSI logic input

on the falling edge of SCLK and the ADE7880 samples it on

the rising edge of SCLK. Data shifts out of the ADE7880 at

the MISO logic output on a falling edge of SCLK and can be

sampled by the master device on the raising edge of SCLK. The

most significant bit of the word is shifted in and out first. The

maximum serial clock frequency supported by this interface

is 2.5 MHz. MISO stays in high impedance when no data is

transmitted from the ADE7880. See Figure 103 for details of the

SS

master receives the last bit, it sets the and SCLK lines high

and the communication ends. The data lines, MOSI and MISO,

go into a high impedance state. See Figure 104 for details of the

SPI read operation.

Rev. A | Page 76 of 104

Data Sheet

ADE7880

SS

SCLK

15 14

1 0

MOSI

MISO

REGISTER ADDRESS

0

0 0 0 0 0 0 1

31 30

1 0

REGISTER VALUE

Figure 104. SPI Read Operation of a 32-Bit Register

SS

SCLK

REGISTER

ADDRESS

MOSI

MISO

0

0 0 0 0 0 0 1

31

0

31

0

REGISTER 0

VALUE

REGISTER n

VALUE

Figure 105. SPI Read Operation of n 32-Bit Harmonic Calculations Registers

lines, MOSI and MISO, go into a high impedance state. See

Figure 105 for details of the SPI read operation of harmonic

calculations registers.

SPI Read Operation of Harmonic Calculations Registers

The registers containing the harmonic calculation results are

located starting at Address 0xE880 and are all 32-bit width.

They can be read in two ways: one register at a time (see the SPI

Read Operation section for details) or multiple consecutive

registers at a time in a burst mode. The burst mode initiates

SPI Write Operation

The write operation using the SPI interface of the ADE7880

SS

initiates when the master sets the /HSA pin low and begins

SS

when the master sets the /HSA pin low and begins sending

sending one byte representing the address of the ADE7880 on

the MOSI line. The master sets data on the MOSI line starting

with the first high-to-low transition of SCLK. The SPI of the

ADE7880 samples data on the low-to-high transitions of SCLK.

The most significant seven bits of the address byte can have any

value, but as a good programming practice, they should be

different from 0111000b, the seven bits used in the I²C protocol.

one byte, representing the address of the ADE7880, on the

MOSI line. The address is the same address byte used for

reading only one register. The master sets data on the MOSI line

starting with the first high-to-low transition of SCLK. The SPI

of the ADE7880 samples data on the low-to-high transitions of

SCLK. Next, the master sends the 16-bit address of the first

harmonic calculations register that is read. After the ADE7880

receives the last bit of the address of the register on a low-to-

high transition of SCLK, it begins to transmit its contents on the

MISO line when the next SCLK high-to-low transition occurs;

thus, the master can sample the data on a low-to-high SCLK

transition. After the master receives the last bit of the first

register, the ADE7880 sends the harmonic calculations register

placed at the next location and so forth until the master sets the

write

Bit 0 (read/

) of the address byte must be 0 for a write

operation. Next, the master sends both the 16-bit address of the

register that is written and the 32-, 16-, or 8-bit value of that

register without losing any SCLK cycle. After the last bit is

SS

transmitted, the master sets the and SCLK lines high at the

end of the SCLK cycle and the communication ends. The data

lines, MOSI and MISO, go into a high impedance state. See

Figure 106 for details of the SPI write operation.

SS

and SCLK lines high and the communication ends. The data

Rev. A | Page 77 of 104

ADE7880

Data Sheet

SS

SCLK

15 14

1

0

31 30

1 0

MOSI

REGISTER ADDRESS

REGISTER VALUE

0

0 0 0 0 0 0 0

Figure 106. SPI Write Operation of a 32-Bit Register

HSDC Interface

is 1, the clock frequency is 4 MHz. A bit of data is transmitted

for every HSCLK high-to-low transition. The slave device that

receives data from HSDC samples the HSD line on the low-to-

high transition of HSCLK.

The high speed data capture (HSDC) interface is disabled after

default. It can be used only if the ADE7880 is configured with an

I²C interface. The SPI interface of ADE7880 cannot be used at

the same time with HSDC.

The words can be transmitted as 32-bit packages or as 8-bit

packages. When Bit 1 (HSIZE) in the HSDC_CFG register is 0 (the

default value), the words are transmitted as 32-bit packages. When

Bit HSIZE is 1, the registers are transmitted as 8-bit packages. The

HSDC interface transmits the words MSB first.

Bit 6 (HSDCEN) in the CONFIG register activates HSDC when

set to 1. If Bit HSDCEN is cleared to 0, the default value, the

HSDC interface is disabled. Setting Bit HSDCEN to 1 when SPI

is in use does not have any effect. HSDC is an interface for

sending to an external device (usually a microprocessor or a

DSP) up to sixteen 32-bit words. The words represent the

instantaneous values of the phase currents and voltages, neutral

current, and active, reactive, and apparent powers. The registers

being transmitted include IAWV, VAWV, IBWV, VBWV, ICWV,

VCWV, AVA, INWV, BVA, CVA, AWATT, BWATT, CWATT,

AFVAR, BFVAR, and CFVAR. All are 24-bit registers that are

sign extended to 32-bits (see Figure 44 for details).

Bit 2 (HGAP) introduces a gap of seven HSCLK cycles between

packages when Bit 2 (HGAP) is set to 1. When Bit HGAP is

cleared to 0 (the default value), no gap is introduced between

packages and the communication time is shortest. In this case,

HSIZE does not have any influence on the communication and

a data bit is placed on the HSD line with every HSCLK high-to-

low transition.

Bits[4:3] (HXFER[1:0]) decide how many words are transmitted.

When HXFER[1:0] is 00, the default value, then all 16 words are

transmitted. When HXFER[1:0] is 01, only the words representing

the instantaneous values of phase and neutral currents and phase

voltages are transmitted in the following order: IAWV, VAWV,

IBWV, VBWV, ICWV, VCWV, and one 32-bit word that is always

equal to INWV. When HXFER[1:0] is 10, only the instantaneous

values of phase powers are transmitted in the following order:

AVA, BVA, CVA, AWATT, BWATT, CWATT, AFVAR, BFVAR,

and CFVAR. The value, 11, for HXFER[1:0] is reserved and

writing it is equivalent to writing 00, the default value.

HSDC can be interfaced with SPI or similar interfaces. HSDC is

always a master of the communication and consists of three

pins: HSA, HSD, and HSCLK. HSA represents the select signal.

It stays active low or high when a word is transmitted and it is

usually connected to the select pin of the slave. HSD sends data

to the slave and it is usually connected to the data input pin of

the slave. HSCLK is the serial clock line that is generated by the

ADE7880 and it is usually connected to the serial clock input of

the slave. Figure 107 shows the connections between the

ADE7880 HSDC and slave devices containing an SPI interface.

SPI DEVICE

ADE7880

Bit 5 (HSAPOL) determines the polarity of HSA function of the

SS

/HSA pin during communication. When HSAPOL is 0 (the

HSD

HSCLK

HSA

MISO

SCK

SS

default value), HSA is active low during the communication.

This means that HSA stays high when no communication is in

progress. When a communication is executed, HSA is low when

the 32-bit or 8-bit packages are transferred, and it is high during

Figure 107. Connecting the ADE7880 HSDC with an SPI

SS

the gaps. When HSAPOL is 1, the HSA function of the /HSA

The HSDC communication is managed by the HSDC_CFG

register (see Table 52). It is recommended to set the HSDC_CFG

register to the desired value before enabling the port using Bit 6

(HSDCEN) in the CONFIG register. In this way, the state of

various pins belonging to the HSDC port do not take levels incon-

sistent with the desired HSDC behavior. After a hardware reset

pin is active high during the communication. This means that

HSA stays low when no communication is in progress. When a

communication is executed, HSA is high when the 32-bit or

8-bit packages are transferred, and it is low during the gaps.

Bits[7:6] of the HSDC_CFG register are reserved. Any value

written into these bits does not have any consequence on HSDC

behavior.

SS

or after power-up, the MISO/HSD and /HSA pins are set high.

Bit 0 (HCLK) in the HSDC_CFG register determines the serial

clock frequency of the HSDC communication. When HCLK is

0 (the default value), the clock frequency is 8 MHz. When HCLK

Rev. A | Page 78 of 104

Data Sheet

ADE7880

Figure 108 shows the HSDC transfer protocol for HGAP = 0,

HXFER[1:0] = 00 and HSAPOL = 0. Note that the HSDC

interface sets a data bit on the HSD line every HSCLK high-to-

low transition and the value of Bit HSIZE is irrelevant.

See Table 52 for the HSDC_CFG register and descriptions for

the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.

Table 25 lists the time it takes to execute an HSDC data transfer

for all HSDC_CFG register settings. For some settings, the

transfer time is less than 125 ꢂs (8 kHz), the waveform sample

registers update rate. This means the HSDC port transmits data

every sampling cycle. For settings in which the transfer time is

greater than 125 ꢂs, the HSDC port transmits data only in the

first of two consecutive 8 kHz sampling cycles. This means it

transmits registers at an effective rate of 4 kHz.

Figure 109 shows the HSDC transfer protocol for HSIZE = 0,

HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the

HSDC interface introduces a seven-HSCLK cycles gap between

every 32-bit word.

Figure 110 shows the HSDC transfer protocol for HSIZE = 1,

HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the

HSDC interface introduces a seven-HSCLK cycles gap between

every 8-bit word.

Table 25. Communication Times for Various HSDC Settings

HXFER[1:0]

HGAP

HSIZE¹

HCLK

Communication Time (μs)

00

01

10

0

1

0

1

0

1

N/A

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64

128

77.125

154.25

119.25

238.25

28

56

33.25

66.5

51.625

103.25

36

72

43

1

N/A

0

1

N/A

0

1

86

66.625

133.25

1

¹N/A means not applicable.

HSCLK

31

0

31

0

31

0

31

0

HSD

HSA

IAVW (32-BIT)

VAWV (32-BIT)

IBWV (32-BIT)

CFVAR (32-BIT)

Figure 108. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant

Rev. A | Page 79 of 104

ADE7880

Data Sheet

HSCLK

31

IAVW (32-BIT)

0

31

0

31

IBWV (32-BIT)

0

31

0

HSDATA

HSA

VAWV (32-BIT)

CFVAR (32-BIT)

7 HCLK

CYCLES

7 HCLK

CYCLES

Figure 109. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0

HSCLK

31

24

23

16

15

IAVW (BYTE 1)

8

7

0

HSDATA

IAVW (BYTE 3)

IAVW (BYTE 2)

CFVAR (BYTE 0)

7 HCLK

CYCLES

7 HCLK

CYCLES

HSA

Figure 110. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0

5. Initialize WTHR, VARTHR, VATHR, VLEVEL and

VNOM registers based Equation 26, Equation 37, Equation

44, Equation 22, and Equation 42, respectively.

ADE7880 QUICK SETUP AS ENERGY METER

An energy meter is usually characterized by the nominal

current I_n, nominal voltage V_n, nominal frequency f_n, and the

meter constant MC.

6. Enable the data memory RAM protection, by writing

0xAD to an internal 8-bit register located at Address

0xE7FE, followed by a write of 0x80 to an internal 8-bit

register located at Address 0xE7E3.

To quickly set up the ADE7880, execute the following steps:

1. Select the PGA gains in the phase currents, voltages and

neutral current channels: Bits[2:0] (PGA1), Bits[5:3]

(PGA2) and Bits[8:6] (PGA3) in the Gain register.

7. Start the DSP by setting Run = 1.

For a quick setup of the ADE7880 harmonic calculations,

see the Recommended Approach to Managing Harmonic

Calculations section.

2. If Rogowski coils are used, enable the digital integrators in

the phase or neutral currents channels: Bit 0 (INTEN) in

CONFIG register and Bit 3 (ININTEN) in CONFIG3

register.

ADE7880 EVALUATION BOARD

An evaluation board built upon the ADE7880 configuration

is available. Visit www.analog.com/ADE7880 for details.

3. If f_n= 60 Hz, set Bit 14 (SELFREQ) to 1 in the

COMPMODE register.

4. Initialize CF1DEN, CF2DEN, and CF3DEN registers based

in Equation 49.

DIE VERSION

The register named version identifies the version of the die.

It is an 8-bit, read-only register located at Address 0xE707.

Rev. A | Page 80 of 104

Data Sheet

ADE7880

SILICON ANOMALY

This anomaly list describes the known issues with the ADE7880 silicon identified by the Version register (Address 0xE707) being equal to 1.

Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries

to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended

workarounds outlined here.

ADE7880 FUNCTIONALITY ISSUES

Silicon Revision

Identifier

Chip Marking

Silicon Status

Anomaly Sheet

No. of Reported Issues

Version = 1

ADE7880ACPZ

Preliminary

Rev. A

4 (er001, er002, er003, er004)

FUNCTIONALITY ISSUES

Table 26. LAST_ADD Register Shows Wrong Value for Harmonic Calculations Registers in SPI Mode [er001, Version = 1 Silicon]

When any ADE7880 register is read using SPI or I²C communication, the address is stored in the LAST_ADD register

Background

Issue

When the harmonic calculation registers located between Address 0xE880 and Address 0xE89F are read using SPI

communication, the LAST_ADD register contains the address of the register incremented by 1. The issue is not present if

the I²C communication is used.

Workaround

If the LAST_ADD register is read after one of the registers located between Address 0xE880 and Address 0xE89F was read

using SPI communication, subtract 1 from it to recover the right address.

None.

Related Issues

Table 27. To Obtain Best Accuracy Performance, Internal Setting Must Be Changed [er002, Version = 1 Silicon]

Internal default settings provide best accuracy performance for ADE7880.

Background

It was found that if a different setting is used, the accuracy performance can be improved.

To enable a new setting for this internal register, execute three consecutive write operations:

The first write operation is to an 8-bit location: 0xAD is written to Address 0xE7FE.

The second write operation is to a 16-bit location: 0x3BD is written to Address 0xE90C.

The third write operation is to an 8-bit location: 0x00 is written to Address 0xE7EF.

Issue

Workaround

The write operations must be executed consecutively without any other read/write operation in between. As a

verification that the value was captured correctly, a simple 16-bit read of Address 0xE90C should show the 0x3BD value.

None.

Related Issues

Table 28. High-Pass Filter Cannot be Disabled in Phase C Voltage Data Path [er003, Version = 1 Silicon]

Background

When Bit 0 (HPFEN) of the CONFIG3 register is 0, all high-pass filters (HPF) in the phase and neutral currents and phase

voltages data paths are disabled (see the ADE7880 data sheet for more information about the current channel HPF and

the voltage channel HPF).

The HPF in the Phase C voltage data path remains enabled independent of the state of Bit HPFEN.

Issue

There is no workaround.

None.

Workaround

Related Issues

Rev. A | Page 81 of 104

ADE7880

Data Sheet

Table 29. No Load Condition Does Not Function as Defined [er004, Version = 1 Silicon]

Background

Total active power no load uses the total active energy and the apparent energy to trigger the no load condition. If

neither total active energy nor apparent energy are accumulated for a time indicated in the respective APNOLOAD and

VANOLOAD unsigned, 16-bit registers, the no load condition is triggered, the total active energy of that phase is not

accumulated and no CF pulses are generated based on the total active energy.

Fundamental active and reactive powers no load uses the fundamental active and reactive energies to trigger the no load

condition. If neither the fundamental active energy nor the fundamental reactive energy are accumulated for a time

indicated in the respective APNOLOAD and VARNOLOAD unsigned 16-bit registers, the no load condition is triggered, the

fundamental active and reactive energies of that phase are not accumulated, and no CF pulses are generated based on

the fundamental active and reactive energies.

Issue

When the total active energy on Phase x (x = A, B, or C) is lower than APNOLOAD and the apparent energy is above

VANOLOAD, the no load condition should not be triggered. It was observed that although CF pulses continue to be

generated, the Bit 0 (NLOAD) and Bits[2:0] (NLPHASE) in STATUS1 and PHNOLOAD registers continue to be cleared to 0

indicating an out of no load condition, the xWATTHR register stops accumulating energy.

It was observed that the fundamental active energy no load functions independently of the fundamental reactive energy

no load. If, for example, the fundamental active energy is below APNOLOAD and the fundamental reactive energy is

above VARNOLOAD, both energies should continue to accumulate because the phase is out of no load condition. Instead,

the CF pulses, based on the phase fundamental active energy, are not generated and the FWATTHR registers are blocked,

while the CF pulses, based on the fundamental reactive energy, are generated. Thus, the FVARHR registers continue to

accumulate and the Bit 1 (FNLOAD) in the STATUS1 register and Bits[5:3] (FNLPHASE) in the PHNOLOAD register are

cleared to 0.

Because both no load conditions use the APNOLOAD threshold, a workaround for both issues is presented as follows:

Workaround



Clear APNOLOAD and VARNOLOAD to 0.

Set VANOLOAD at desired value.

When the Phase x (x = A, B, or C) apparent energy becomes smaller then VANOLOAD, the Bit 2 (VANLOAD) in STATUS1 is

set to 1, together with one of the Bits[2:0] (VANLPHASE) in PHNOLOAD. Then, set APNOLOAD and VARNOLOAD equal to

VANOLOAD.

The Phase x (x = A, B, or C) total active energy enters no load condition.



CF pulses stop.

Bit 0 (NLOAD) in the STATUS1 register is set to 1.

One of the Bits[2:0], (NLPHASE[2:0]), in the PHNOLOAD register is set to 1.

The xWATTHR register stops accumulating energy.

The Phase x (x = A, B, or C) fundamental active and reactive energies enter no load condition.



CF pulses stop.

Bit 1 (FNLOAD) in the STATUS1 register is set to 1.

One of the Bits[5:3], (FNLPHASE[2:0]), in the PHNOLOAD register is set to 1.

The xFWATTHR and xVARHR registers stop accumulating energy.

None.

Related Issues

SECTION 1. ADE7880 FUNCTIONALITY ISSUES

Reference Number Description

Status

er001

er002

er003

er004

The LAST_ADD register shows the wrong value for the harmonic calculations registers in SPI mode.

Identified

To obtain the best accuracy performance, the internal setting must be changed.

The high-pass filter cannot be disabled in the Phase C voltage data path

The no load condition does not function as defined.

Rev. A | Page 82 of 104

Data Sheet

ADE7880

REGISTERS LIST

Table 30. Registers Located in DSP Data Memory RAM

Register

Address Name

Bit

Bit Length During

R/W¹Length Communication²

Type ³

Default Value Description

0x4380

0x4381

0x4382

0x4383

0x4384

0x4385

0x4386

0x4387

AIGAIN

AVGAIN

BIGAIN

BVGAIN

CIGAIN

CVGAIN

NIGAIN

Reserved

R/W

24

32 ZPSE

S

0x000000

Phase A current gain adjust.

Phase A voltage gain adjust.

Phase B current gain adjust.

Phase B voltage gain adjust.

Phase C current gain adjust.

Phase C voltage gain adjust.

Neutral current gain adjust.

This location should not be written for proper

operation.

0x4388

DICOEFF

R/W

24

32 ZPSE

S

0x0000000

Register used in the digital integrator algorithm.

If the integrator is turned on, it must be set at

0xFF8000. In practice, it is transmitted as

0xFFF8000.

0x4389

0x438A

0x438B

0x438C

0x438D

0x438E

0x438F

0x4390

0x4391

0x4392

0x4393

0x4394

0x4395

APGAIN

AWATTOS

BPGAIN

BWATTOS

CPGAIN

CWATTOS

AIRMSOS

AVRMSOS

BIRMSOS

BVRMSOS

CIRMSOS

CVRMSOS

NIRMSOS

Reserved

R/W

N/A

24

N/A

32 ZPSE

N/A

S

N/A

0x000000

Phase A power gain adjust.

Phase A total active power offset adjust.

Phase B power gain adjust.

Phase B total active power offset adjust.

Phase C power gain adjust.

Phase C total active power offset adjust.

Phase A current rms offset.

Phase A voltage rms offset.

Phase B current rms offset.

Phase B voltage rms offset.

Phase C current rms offset.

Phase C voltage rms offset.

Neutral current rms offset.

These memory locations should not be written for

proper operation.

0x4396-

0x4397

0x4398

0x4399

HPGAIN

ISUMLVL

R/W

24

32 ZPSE

S

0x000000

Harmonic powers gain adjust.

Threshold used in comparison between the sum

of phase currents and the neutral current.

0x439A- Reserved

0x439E

N/A

R/W

N/A

24

N/A

S

0x000000

These memory locations should not be written for

proper operation.

Register used in the algorithm that computes the

fundamental active and reactive powers.

These memory locations should not be written for

proper operation.

0x439F

VLEVEL

32 ZPSE

N/A

0x43A0- Reserved

0x43A1

N/A

0x43A2

0x43A3

0x43A4

0x43A5

0x43A6

0x43A7

0x43A8

0x43A9

0x43AA

0x43AB

0x43AC

0x43AD

0x43AE

AFWATTOS

BFWATTOS

CFWATTOS

AFVAROS

BFVAROS

CFVAROS

AFIRMSOS

BFIRMSOS

CFIRMSOS

AFVRMSOS

BFVRMSOS

CFVRMSOS

R/W

24

32 ZPSE

S

0x000000

Phase A fundamental active power offset adjust.

Phase B fundamental active power offset adjust.

Phase C fundamental active power offset adjust.

Phase A fundamental reactive power offset adjust.

Phase B fundamental reactive power offset adjust.

Phase C fundamental reactive power offset adjust.

Phase A fundamental current rms offset.

Phase B fundamental current rms offset.

Phase C fundamental current rms offset.

Phase A fundamental voltage rms offset.

Phase B fundamental voltage rms offset.

Phase C fundamental voltage rms offset.

Active power offset adjust on harmonic X

HXWATTOS R/W

(see Harmonics Calculations section for details).

0x43AF

HYWATTOS R/W

24

32 ZPSE

S

0x000000

Aactive power offset adjust on harmonic Y

(see Harmonics Calculations section for details).

Rev. A | Page 83 of 104

ADE7880

Data Sheet

Register

Address Name

HZWATTOS R/W

Bit

Bit Length During

R/W¹Length Communication²

Type ³

Default Value Description

Active power offset adjust on harmonic Z

0x43B0

0x43B1

0x43B2

0x43B3

0x43B4

0x43B5

0x43B6

0x43B7

0x43B8

0x43B9

24

N/A

32 ZPSE

N/A

S

0x000000

(see Harmonics Calculations section for details).

Aactive power offset adjust on harmonic X

(see Harmonics Calculations section for details).

Active power offset adjust on harmonic Y

(see Harmonics Calculations section for details).

Aactive power offset adjust on harmonic Z

(see Harmonics Calculations section for details).

Current rms offset on harmonic X

(see Harmonics Calculations section for details).

Current rms offset on harmonic Y

(see Harmonics Calculations section for details).

Current rms offset on harmonic Z

(see Harmonics Calculations section for details).

Voltage rms offset on harmonic X

(see Harmonics Calculations section for details).

Voltage rms offset on harmonic Y

HXVAROS

HYVAROS

HZVAROS

HXIRMSOS

HYIRMSOS

HZIRMSOS

HXVRMSOS

HYVRMSOS

HZVRMSOS

Reserved

R/W

N/A

S

(see Harmonics Calculations section for details).

Voltage rms offset on harmonic Z

(see Harmonics Calculations section for details).

These memory locations should not be written for

proper operation.

S

0x43BA

to

N/A

0x43BF

0x43C0

0x43C1

0x43C2

0x43C3

0x43C4

0x43C5

0x43C6

0x43C7

AIRMS

AVRMS

BIRMS

BVRMS

CIRMS

CVRMS

NIRMS

ISUM

R

24

N/A

32 ZP

N/A

S

N/A

Phase A current rms value.

Phase A voltage rms value.

Phase B current rms value.

Phase B voltage rms value.

Phase C current rms value.

Phase C voltage rms value.

Neutral current rms value.

Sum of IAWV, IBWV and ICWV registers.

0x43C8

to

Reserved

N/A

These memory locations should not be written for

proper operation.

0x43FF

¹R is read, and W is write.

²32 ZPSE = 24-bit signed register that is transmitted as a 32-bit word with four MSBs padded with 0s and sign extended to 28 bits. Whereas 32 ZP = 28- bit or 24-bit

signed or unsigned register that is transmitted as a 32-bit word with four or eight MSBs, respectively, padded with 0s.

³U is unsigned register, and S is signed register in twos complement format.

Table 31. Internal DSP Memory RAM Registers

Bit Length

Register

Address Name

Bit

During

Default

R/W¹Length Communication

Type²Value

Description

0xE203

Reserved R/W

16

U

0x0000

This memory location should not be written for

proper operation.

Run register starts and stops the DSP. See the

Digital Signal Processor section for more details.

0xE228

Run R/W

U

0x0000

¹R is read, and W is write.

²U is unsigned register, and S is signed register in twos complement format.

Rev. A | Page 84 of 104

Data Sheet

ADE7880

Table 32. Billable Registers

Bit Length

During

Register

Address Name

Bit

Default

R/W^{1, 2}Length²Communication²Type^{2, 3}Value

Description

0xE400

0xE401

0xE402

0xE403

AWATTHR

BWATTHR

CWATTHR

AFWATTHR

R

32

S

0x00000000 Phase A total active energy accumulation.

0x00000000 Phase B total active energy accumulation.

0x00000000 Phase C total active energy accumulation.

0x00000000 Phase A fundamental active energy

accumulation.

0xE404

0xE405

BFWATTHR

CFWATTHR

Reserved

R

32

S

0x00000000 Phase B fundamental active energy

accumulation.

0x00000000 Phase C fundamental active energy

accumulation.

0xE406

to

0x00000000

0xE408

0xE409

0xE40A

0xE40B

AFVARHR

BFVARHR

CFVARHR

R

32

S

0x00000000 Phase A fundamental reactive energy

accumulation.

0x00000000 Phase B fundamental reactive energy

accumulation.

0x00000000 Phase C fundamental reactive energy

accumulation.

0xE40C

0xE40D

0xE40E

AVAHR

BVAHR

CVAHR

R

32

S

0x00000000 Phase A apparent energy accumulation.

0x00000000 Phase B apparent energy accumulation.

0x00000000 Phase C apparent energy accumulation.

¹R is read, and W is write.

²N/A is not applicable.

³U is unsigned register, and S is signed register in twos complement format.

Table 33. Configuration and Power Quality Registers

Bit Length

Bit

During

Default

Address

Register Name

R/W¹Length Communication²

Type³Value⁴

Description

0xE500

IPEAK

R

32

U

N/A

Current peak register. See Figure 58 and

Table 34 for details about its

composition.

Voltage peak register. See Figure 58 and

Table 35 for details about its

composition.

0xE501

VPEAK

U

N/A

0xE502

0xE503

0xE504

STATUS0

STATUS1

AIMAV

R/W

R

32

20

32

32 ZP

U

N/A

Interrupt Status Register 0. See Table 36.

Interrupt Status Register 1. See Table 37.

Phase A current mean absolute value

computed during PSM0 and PSM1

modes.

0xE505

0xE506

BIMAV

CIMAV

R

20

32 ZP

U

N/A

Phase B current mean absolute value

computed during PSM0 and PSM1

modes.

Phase C current mean absolute value

computed during PSM0 and PSM1

modes.

0xE507

0xE508

0xE509

0xE50A

0xE50B

0xE50C

0xE50D

0xE50E

OILVL

OVLVL

SAGLVL

MASK0

MASK1

IAWV

R/W

R

24

32

24

32 ZP

32

U

S

0xFFFFFF

0x000000

Overcurrent threshold.

Overvoltage threshold.

Voltage SAG level threshold.

0x00000000 Interrupt Enable Register 0. See Table 38.

0x00000000 Interrupt Enable Register 1. See Table 39.

N/A

32

32 SE

Instantaneous value of Phase A current.

Instantaneous value of Phase B current.

Instantaneous value of Phase C current.

IBWV

ICWV

R

S

Rev. A | Page 85 of 104

ADE7880

Data Sheet

Bit Length

During

Bit

Default

Address

0xE50F

0xE510

0xE511

0xE512

0xE513

Register Name

R/W¹Length Communication²

Type³Value⁴

Description

INWV

R

24

32 SE

S

N/A

Instantaneous value of neutral current.

Instantaneous value of Phase A voltage.

Instantaneous value of Phase B voltage.

Instantaneous value of Phase C voltage.

Instantaneous value of Phase A total

active power.

VAWV

VBWV

VCWV

AWATT

0xE514

0xE515

BWATT

CWATT

R

24

32

24

32 SE

32

S

U

S

N/A

Instantaneous value of Phase B total

active power.

Instantaneous value of Phase C total

active power.

R

N/A

0xE516 to Reserved

0xE518

R

0x000000

N/A

0xE519

0xE51A

0xE51B

0xE51F

0xE520

AVA

R

Instantaneous value of Phase A

apparent power.

Instantaneous value of Phase B

apparent power.

Instantaneous value of Phase C

apparent power.

BVA

R

N/A

CVA

R

N/A

CHECKSUM

VNOM

R

0xAFFA63B9 Checksum verification. See the

Checksum Register section for details.

0x000000

R/W

32 ZP

Nominal phase voltage rms used in the

alternative computation of the

apparent power.

0xE521 to Reserved

0xE5FE

These addresses should not be written

for proper operation.

0xE5FF

LAST_RWDATA32

R

32

U

N/A

Contains the data from the last successful

32-bit register communication.

0xE600

0xE601

PHSTATUS

ANGLE0

R

16

U

N/A

Phase peak register. See Table 40.

Time Delay 0. See the Time Interval

Between Phases section for details.

0xE602

0xE603

ANGLE1

ANGLE2

R

16

U

N/A

Time Delay 1. See the Time Interval

Between Phases section for details.

Time Delay 2. See the Time Interval

Between Phases section for details.

0xE604 to Reserved

0xE607

These address should not be written for

proper operation.

0xE608

PHNOLOAD

R

16

U

N/A

Phase no load register. See Table 41.

0xE609 to Reserved

0xE60B

These address should not be written for

proper operation.

0xE60C

0xE60D

0xE60E

0xE60F

0xE610

0xE611

0xE612

0xE613

0xE614

0xE615

0xE616

0xE617

0xE618

LINECYC

ZXTOUT

COMPMODE

Gain

CFMODE

CF1DEN

CF2DEN

CF3DEN

APHCAL

BPHCAL

CPHCAL

PHSIGN

CONFIG

R/W

R

16

10

16

16 ZP

16

U

0xFFFF

0x01FF

0x0000

0x0EA0

0x0000

N/A

Line cycle accumulation mode count.

Zero-crossing timeout count.

Computation-mode register. See Table 42.

PGA gains at ADC inputs. See Table 43.

CFx configuration register. See Table 44.

CF1 denominator.

CF2 denominator.

CF3 denominator.

Phase calibration of Phase A. See Table 45.

Phase calibration of Phase B. See Table 45.

Phase calibration Phase of C. See Table 45.

Power sign register. See Table 46.

ADE7880 configuration register.

See Table 47.

R/W

16

0x0002

0xE700

0xE701

MMODE

ACCMODE

R/W

8

U

0x1C

0x80

Measurement mode register. See Table 48.

Accumulation mode register.

Rev. A | Page 86 of 104

Data Sheet

ADE7880

Bit Length

During

Bit

Default

Address

Register Name

R/W¹Length Communication²

Type³Value⁴

Description

See Table 49.

0xE702

LCYCMODE

R/W

8

U

0x78

Line accumulation mode behavior.

See Table 51.

0xE703

0xE704

0xE705

PEAKCYC

SAGCYC

CFCYC

R/W

8

U

0x00

0x01

Peak detection half line cycles.

SAG detection half line cycles.

Number of CF pulses between two

consecutive energy latches. See the

Synchronizing Energy Registers with

CFx Outputs section.

0xE706

0xE707

0xE7FD

HSDC_CFG

Version

LAST_RWDATA8

R/W

R

8

U

0x00

N/A

HSDC configuration register. See Table 52.

Version of die.

Contains the data from the last

successful 8-bit register

communication.

0xE880

0xE881

0xE882

0xE883

0xE884

0xE885

0xE886

0xE887

0xE888

0xE889

FVRMS

FIRMS

FWATT

FVAR

R

24

32

S

N/A

The rms value of the fundamental

component of the phase voltage.

The rms value of the fundamental

component of the phase current

The active power of the fundamental

component.

The reactive power of the fundamental

component.

The apparent power of the fundamental

component.

The power factor of the fundamental

component.

Total harmonic distortion of the phase

voltage.

Total harmonic distortion of the phase

current.

FVA

FPF

VTHD

ITHD

HXVRMS

HXIRMS

The rms value of the phase voltage

harmonic X.

The rms value of the phase current

harmonic X.

0xE88A

0xE88B

0xE88C

0xE88D

0xE88E

HXWATT

HXVAR

HXVA

HXPF

HXVHD

R

24

32

S

N/A

The active power of the harmonic X.

The reactive power of the harmonic X.

The apparent power of the harmonic X.

The power factor of the harmonic X.

Harmonic distortion of the phase

voltage harmonic X relative to the

fundamental.

0xE88F

HXIHD

R

24

32

S

N/A

Harmonic distortion of the phase

current harmonic X relative to the

fundamental.

0xE890

0xE891

HYVRMS

HYIRMS

R

24

32

S

N/A

The rms value of the phase voltage

harmonic Y.

The rms value of the phase current

harmonic Y.

0xE892

0xE893

0xE894

0xE895

0xE896

HYWATT

HYVAR

HYVA

HYPF

HYVHD

R

24

32

S

N/A

The active power of the harmonic Y.

The reactive power of the harmonic Y.

The apparent power of the harmonic Y.

The power factor of the harmonic Y.

Harmonic distortion of the phase

voltage harmonic Y relative to the

fundamental.

0xE897

HYIHD

R

24

32

S

N/A

Harmonic distortion of the phase

Rev. A | Page 87 of 104

ADE7880

Data Sheet

Bit Length

During

Bit

Default

Address

Register Name

R/W¹Length Communication²

Type³Value⁴

Description

current harmonic Y relative to the

fundamental.

0xE898

0xE899

HZVRMS

HZIRMS

R

24

32

S

N/A

The rms value of the phase voltage

harmonic Z.

The rms value of the phase current

harmonic Z.

0xE89A

0xE89B

0xE89C

0xE89D

0xE89E

HZWATT

HZVAR

HZVA

HZPF

HZVHD

R

24

32

S

N/A

The active power of the harmonic Z.

The reactive power of the harmonic Z.

The apparent power of the harmonic Z.

The power factor of the harmonic Z.

Harmonic distortion of the phase

voltage harmonic Z relative to the

fundamental.

0xE89F

HZIHD

R

24

32

S

N/A

Harmonic distortion of the phase

current harmonic Z relative to the

fundamental.

0xE8A0 to Reserved

0xE8FF

24

16

32

16

Reserved. These registers are always 0.

0xE900

HCONFIG

R/W

U

0x08

Harmonic Calculations Configuration

register. See Table 54.

0xE902

0xE903

0xE904

0xE905

0xE906

0xE907

0xE908

APF

BPF

CPF

APERIOD

BPERIOD

CPERIOD

APNOLOAD

R

R/W

16

U

N/A

0x0000

Phase A power factor.

Phase B power factor.

Phase C power factor.

Line period on Phase A voltage.

Line period on Phase B voltage.

Line period on Phase C voltage.

No load threshold in the total/

fundamental active power data paths.

0xE909

0xE90A

0xE9FE

VARNOLOAD

VANOLOAD

LAST_ADD

R/W

R

16

U

0x0000

N/A

No load threshold in the total/

fundamental reactive power data path.

No load threshold in the apparent

power data path.

The address of the register successfully

accessed during the last read/write

operation.

0xE9FF

LAST_RWDATA16

R

16

U

N/A

Contains the data from the last successful

16-bit register communication.

0xEA00

0xEA01

CONFIG3

LAST_OP

R/W

R

8

U

0x01

N/A

Configuration register. See Table 53.

Indicates the type, read or write, of the

last successful read/write operation.

0xEA02

0xEA03

0xEA04

WTHR

R/W

8

U

0x03

Threshold used in phase total/

fundamental active power data path.

Threshold used in phase total/

fundamental reactive power data path.

Threshold used in phase apparent

power data path.

Reserved. These registers are always 0.

VARTHR

VATHR

0xEA05 to Reserved

0xEA07

0xEA08

0xEA09

0xEA0A

HX

HY

HZ

R/W

U

3

5

7

Selects an index of the harmonic

monitored by the harmonic

computations.

Selects an index of the harmonic

monitored by the harmonic

computations.

8

U

Selects an index of the harmonic

monitored by the harmonic

Rev. A | Page 88 of 104

Data Sheet

ADE7880

Bit Length

During

Bit

Default

Address

Register Name

R/W¹Length Communication²

Type³Value⁴

Description

computations.

0xEA0B to Reserved

0xEBFE

8

Reserved. These registers are always 0.

0xEBFF

Reserved

This address can be used in manipulating

the SS/HSA pin when SPI is chosen as

the active port. See the Serial Interfaces

section for details.

0xEC00

0xEC01

LPOILVL

R/W

8

U

0x07

0x00

Overcurrent threshold used during

PSM2 mode. See Table 55 in which the

register is detailed.

Configuration register used during

PSM1 mode. See Table 56.

CONFIG2

¹R is read, and W is write.

²32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that

is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.

³U is unsigned register, and S is signed register in twos complement format.

⁴N/A is not applicable.

Table 34. IPEAK Register (Address 0xE500)

Bit

Mnemonic

IPEAKVAL[23:0]

IPPHASE[0]

IPPHASE[1]

IPPHASE[2]

Default Value

Description

23:0

24

25

26

31:27

0

These bits contain the peak value determined in the current channel.

When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.

When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.

When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.

These bits are always 0.

00000

Table 35. VPEAK Register (Address 0xE501)

Bit

Mnemonic

Default Value

Description

23:0

24

25

26

31:27

VPEAKVAL[23:0]

VPPHASE[0]

VPPHASE[1]

VPPHASE[2]

0

These bits contain the peak value determined in the voltage channel.

When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.

When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.

When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.

These bits are always 0.

00000

Table 36. STATUS0 Register (Address 0xE502)

Bit

Mnemonic

Default Value

Description

0

AEHF

0

When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy

registers (AWATTHR, BWATTHR, or CWATTHR) has changed.

1

FAEHF

0

When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active

energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed.

2

3

Reserved

FREHF

0

This bit is always 0.

When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental

reactive energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed.

4

5

6

VAEHF

0

When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy

registers (AVAHR, BVAHR, or CVAHR) has changed.

LENERGY

REVAPA

When this bit is set to 1, in line energy accumulation mode, it indicates the end of an

integration over an integer number of half line cycles set in the LINECYC register.

When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6

(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The

sign itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 46).

7

8

REVAPB

REVAPC

0

When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6

(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The

sign itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 46).

When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6

(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The

sign itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 46).

Rev. A | Page 89 of 104

ADE7880

Data Sheet

Bit

Mnemonic

Default Value

Description

9

REVPSUM1

0

When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data

path has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN

register (see Table 46).

10

11

12

13

14

REVFRPA

REVFRPB

REVFRPC

REVPSUM2

CF1

0

When this bit is set to 1, it indicates that the Phase A fundamental reactive power

has changed sign. The sign itself is indicated in Bit 4 (AFVARSIGN) of the PHSIGN

register (see Table 46).

When this bit is set to 1, it indicates that the Phase B fundamental reactive power

has changed sign. The sign itself is indicated in Bit 5 (BFVARSIGN) of the PHSIGN

register (see Table 46).

When this bit is set to 1, it indicates that the Phase C fundamental reactive power

has changed sign. The sign itself is indicated in Bit 6 (CFVARSIGN) of the PHSIGN

register (see Table 46).

When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 data

path has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN

register (see Table 46).

When this bit is set to 1, it indicates a high-to-low transition has occurred at CF1 pin;

that is, an active low pulse has been generated. The bit is set even if the CF1 output

is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power

used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register

(see Table 44).

15

16

CF2

CF3

When this bit is set to 1, it indicates a high-to-low transition has occurred at the CF2

pin; that is, an active low pulse has been generated. The bit is set even if the CF2

output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of

power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE

register (see Table 44).

When this bit is set to 1, it indicates a high-to-low transition has occurred at CF3 pin;

that is, an active low pulse has been generated. The bit is set even if the CF3 output

is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power

used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see

Table 44).

17

18

DREADY

0

When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP

computations have finished.

REVPSUM3

When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 data

path has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN

register (see Table 46).

19

HREADY

0

When this bit is set to 1, it indicates the harmonic block output registers have been

updated. If Bit 1 (HRCFG) in the HCONFIG register is cleared to 0, this flag is set to 1

every time the harmonic block output registers are updated at 8 kHz rate. If Bit

HRCFG is set to 1, the HREADY flag is set to 1 every time the harmonic block output

registers are updated at 8 kHz rate starting 750 ms after the harmonic block setup .

31:18

Reserved

0 0000 0000 0000 Reserved. These bits are always 0.

Rev. A| Page 90 of 104

Data Sheet

ADE7880

Table 37. STATUS1 Register (Address 0xE503)

Bit

Mnemonic

Default Value

Description

0

NLOAD

0

When this bit is set to 1, it indicates that at least one phase entered no load

condition determined by the total active power and apparent power. The phase is

indicated in Bits[2:0] (NLPHASE[x]) in the PHNOLOAD register (see Table 41.)

1

2

FNLOAD

0

When this bit is set to 1, it indicates that at least one phase entered no load

condition based on fundamental active and reactive powers. The phase is indicated

in Bits[5:3] (FNLPHASE[x]) in the PHNOLOAD register (see Table 41).

VANLOAD

When this bit is set to 1, it indicates that at least one phase entered no load

condition based on apparent power. The phase is indicated in Bits[8:6]

(VANLPHASE[x]) in the PHNOLOAD register (see Table 41).

3

4

5

6

7

8

9

ZXTOVA

ZXTOVB

ZXTOVC

ZXTOIA

ZXTOIB

ZXTOIC

ZXVA

0

When this bit is set to 1, it indicates a zero crossing on Phase A voltage is missing.

When this bit is set to 1, it indicates a zero crossing on Phase B voltage is missing.

When this bit is set to 1, it indicates a zero crossing on Phase C voltage is missing.

When this bit is set to 1, it indicates a zero crossing on Phase A current is missing.

When this bit is set to 1, it indicates a zero crossing on Phase B current is missing.

When this bit is set to 1, it indicates a zero crossing on Phase C current is missing.

When this bit is set to 1, it indicates a zero crossing has been detected on Phase A

voltage.

10

11

12

13

14

15

ZXVB

ZXVC

ZXIA

0

1

When this bit is set to 1, it indicates a zero crossing has been detected on Phase B

voltage.

When this bit is set to 1, it indicates a zero crossing has been detected on Phase C

voltage.

When this bit is set to 1, it indicates a zero crossing has been detected on Phase A

current.

ZXIB

When this bit is set to 1, it indicates a zero crossing has been detected on Phase B

current.

ZXIC

When this bit is set to 1, it indicates a zero crossing has been detected on Phase C

current.

RSTDONE

In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG register,

or a transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set

to 1 at the end of the transition process and after all registers changed value to

default. The IRQ1 pin goes low to signal this moment because this interrupt cannot

be disabled.

16

SAG

0

When this bit is set to 1, it indicates one of phase voltages entered or exited a sag

state. The phase is indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register

(see Table 40).

17

18

19

OI

0

When this bit is set to 1, it indicates an overcurrent event has occurred on one of the

phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 40).

OV

When this bit is set to 1, it indicates an overvoltage event has occurred on one of the

phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 40).

SEQERR

When this bit is set to 1, it indicates a negative-to-positive zero crossing on Phase A

voltage was not followed by a negative-to-positive zero crossing on Phase B voltage

but by a negative-to-positive zero crossing on Phase C voltage.

20

MISMTCH

0

When this bit is set to 1, it indicates ISUM − INWV > ISUMLVL , where

ISUMLVL is indicated in the ISUMLVL register.

Reserved. This bit is always set to 1.

21

22

23

Reserved

PKI

1

0

Reserved. This bit is always set to 0.

When this bit is set to 1, it indicates that the period used to detect the peak value in

the current channel has ended. The IPEAK register contains the peak value and the

phase where the peak has been detected (see Table 34).

Rev. A| Page 91 of 104

ADE7880

Data Sheet

Bit

Mnemonic

Default Value

Description

24

PKV

0

When this bit is set to 1, it indicates that the period used to detect the peak value in

the voltage channel has ended. VPEAK register contains the peak value and the

phase where the peak has been detected (see Table 35).

25

CRC

0

When this bit is set to 1, it indicates the ADE7880 has computed a different

checksum relative to the one computed when the Run register was set to 1.

31:26

Reserved

000 0000

Reserved. These bits are always 0.

Table 38. MASK0 Register (Address 0xE50A)

Bit

Mnemonic

Default Value

Description

0

AEHF

0

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total

active energy registers (AWATTHR, BWATTHR, or CWATTHR) changes.

1

FAEHF

0

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the

fundamental active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR)

changes.

2

3

Reserved

FREHF

0

This bit does not manage any functionality.

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the

fundamental reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes.

4

5

VAEHF

0

When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the

apparent energy registers (AVAHR, BVAHR, or CVAHR) changes.

LENERGY

When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at

the end of an integration over an integer number of half line cycles set in the

LINECYC register.

6

7

8

REVAPA

REVAPB

REVAPC

0

When this bit is set to 1, it enables an interrupt when the Phase A active power

identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)

changes sign.

When this bit is set to 1, it enables an interrupt when the Phase B active power

identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)

changes sign.

When this bit is set to 1, it enables an interrupt when the Phase C active power

identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental)

changes sign.

9

REVPSUM1

REVFRPA

REVFRPB

REVFRPC

REVPSUM2

CF1

0

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in

the CF1 data path changes sign.

10

11

12

13

14

When this bit is set to 1, it enables an interrupt when the Phase A fundamental

reactive power changes sign.

When this bit is set to 1, it enables an interrupt when the Phase B fundamental

reactive power changes sign.

When this bit is set to 1, it enables an interrupt when the Phase C fundamental

reactive power changes sign.

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in

the CF2 data path changes sign.

When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs

at the CF1 pin, that is an active low pulse is generated. The interrupt can be enabled

even if the CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE

register. The type of power used at the CF1 pin is determined by Bits[2:0]

(CF1SEL[2:0]) in the CFMODE register (see Table 44).

15

16

17

CF2

When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs

at CF2 pin, that is an active low pulse is generated. The interrupt may be enabled

even if the CF2 output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE

register. The type of power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0])

in the CFMODE register (see Table 44).

CF3

When this bit is set to 1, it enables an interrupt when a high to low transition occurs

at CF3 pin, that is an active low pulse is generated. The interrupt may be enabled

even if the CF3 output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE

register. The type of power used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0])

in the CFMODE register (see Table 44).

DREADY

0

When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate)

DSP computations finish.

Rev. A| Page 92 of 104

Data Sheet

ADE7880

Bit

Mnemonic

Default Value

Description

18

REVPSUM3

0

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in

the CF3 data path changes sign.

19

HREADY

0

When this bit is set to 1, it enables an interrupt when the harmonic block output

registers have been updated. If Bit 1 (HRCFG) in HCONFIG register is cleared to 0, the

interrupt is triggered every time the harmonic calculations are updated at 8 kHz

rate. If Bit HRCFG is set to 1, the interrupt is triggered every time the harmonic

calculations are updated at 8 kHz rate starting 750 ms after the harmonic block

setup.

31:19

Reserved

00 0000 0000

0000

Reserved. These bits do not manage any functionality.

Table 39. MASK1 Register (Address 0xE50B)

Bit

Mnemonic

Default Value

Description

0

NLOAD

0

When this bit is set to 1, it enables an interrupt when at least one phase enters no

load condition determined by the total active power and VNOM based apparent

power.

1

FNLOAD

VANLOAD

ZXTOVA

ZXTOVB

ZXTOVC

ZXTOIA

ZXTOIB

ZXTOIC

ZXVA

0

When this bit is set to 1, it enables an interrupt when at least one phase enters no

load condition based on fundamental active and reactive powers.

2

When this bit is set to 1, it enables an interrupt when at least one phase enters no

load condition based on apparent power.

3

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A

voltage is missing.

4

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B

voltage is missing.

5

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C

voltage is missing.

6

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A

current is missing.

7

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B

current is missing.

8

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C

current is missing.

9

When this bit is set to 1, it enables an interrupt when a zero crossing is detected on

Phase A voltage.

10

11

12

13

14

15

16

ZXVB

When this bit is set to 1, it enables an interrupt when a zero crossing is detected on

Phase B voltage.

ZXVC

When this bit is set to 1, it enables an interrupt when a zero crossing is detected on

Phase C voltage.

ZXIA

When this bit is set to 1, it enables an interrupt when a zero crossing is detected on

Phase A current.

ZXIB

When this bit is set to 1, it enables an interrupt when a zero crossing is detected on

Phase B current.

ZXIC

When this bit is set to 1, it enables an interrupt when a zero crossing is detected on

Phase C current.

RSTDONE

SAG

Because the RSTDONE interrupt cannot be disabled, this bit does not have any

functionality attached. It can be set to 1 or cleared to 0 without having any effect.

When this bit is set to 1, it enables an interrupt when one of the phase voltages

entered or exited a sag state. The phase is indicated by Bits[14:12] (VSPHASE[x]) in

the PHSTATUS register (see Table 40).

17

18

19

OI

0

When this bit is set to 1, it enables an interrupt when an overcurrent event occurs

on one of the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register

(see Table 40).

OV

When this bit is set to 1, it enables an interrupt when an overvoltage event occurs

on one of the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register

(see Table 40).

SEQERR

When this bit is set to 1, it enables an interrupt when a negative-to-positive zero

crossing on Phase A voltage is not followed by a negative-to-positive zero crossing

on Phase B voltage, but by a negative-to-positive zero crossing on Phase C voltage.

Rev. A| Page 93 of 104

ADE7880

Data Sheet

Bit

Mnemonic

Default Value

Description

20

MISMTCH

0

When this bit is set to 1, it enables an interrupt

when ISUM − INWV > ISUMLVL is greater than the value indicated in

ISUMLVL register.

22:21

23

Reserved

PKI

00

0

Reserved. These bits do not manage any functionality.

When this bit is set to 1, it enables an interrupt when the period used to detect the

peak value in the current channel has ended.

24

PKV

0

When this bit is set to 1, it enables an interrupt when the period used to detect the

peak value in the voltage channel has ended.

25

CRC

0

When this bit is set to 1, it enables an interrupt when the latest checksum value is

different from the checksum value computed when Run register was set to 1.

31:26

Reserved

000 0000

Reserved. These bits do not manage any functionality.

Table 40. PHSTATUS Register (Address 0xE600)

Bit

2:0

3

Mnemonic

Default Value Description

Reserved

000

0

Reserved. These bits are always 0.

OIPHASE[0]

OIPHASE[1]

OIPHASE[2]

Reserved

When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.

When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.

When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.

Reserved. These bits are always 0.

4

0

5

0

8:6

9

000

0

OVPHASE[0]

OVPHASE[1]

OVPHASE[2]

VSPHASE[0]

When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.

When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.

When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.

10

11

12

0

0: Phase A voltage is above SAGLVL level for SAGCYC half line cycles

1: Phase A voltage is below SAGLVL level for SAGCYC half line cycles

When this bit is switches from 0 to 1 or from 1 to 0, the Phase A voltage generates Bit 16

(SAG) in the STATUS1 register.

13

14

15

VSPHASE[1]

VSPHASE[2]

Reserved

0

0: Phase B voltage is above SAGLVL level for SAGCYC half line cycles

1: Phase B voltage is below SAGLVL level for SAGCYC half line cycles

When this bit is switches from 0 to 1 or from 1 to 0, the Phase B voltage generates Bit 16

(SAG) in the STATUS1 register.

0: Phase C voltage is above SAGLVL level for SAGCYC half line cycles

1: Phase C voltage is below SAGLVL level for SAGCYC half line cycles

When this bit is switches from 0 to 1 or from 1 to 0, the Phase C voltage generates Bit 16

(SAG) in the STATUS1 register.

Reserved. This bit is always 0.

Table 41. PHNOLOAD Register (Address 0xE608)

Bit

Mnemonic

Default Value Description

0

NLPHASE[0]

0

0: Phase A is out of no load condition determined by the Phase A total active power and

apparent power.

1: Phase A is in no load condition determined by phase A total active power and apparent

power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.

1

2

3

NLPHASE[1]

NLPHASE[2]

FNLPHASE[0]

0: Phase B is out of no load condition determined by the Phase B total active power and

apparent power.

1: Phase B is in no load condition determined by the Phase B total active power and

apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.

0: Phase C is out of no load condition determined by the Phase C total active power and

apparent power.

1: Phase C is in no load condition determined by the Phase C total active power and

apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.

0: Phase A is out of no load condition based on fundamental active/reactive powers.

1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is

set together with Bit 1 (FNLOAD) in STATUS1.

Rev. A| Page 94 of 104

Data Sheet

ADE7880

Bit

Mnemonic

Default Value Description

4

FNLPHASE[1]

FNLPHASE[2]

VANLPHASE[0]

VANLPHASE[1]

VANLPHASE[2]

Reserved

0

0: Phase B is out of no load condition based on fundamental active/reactive powers.

1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is

set together with Bit 1 (FNLOAD) in STATUS1.

5

0

0: Phase C is out of no load condition based on fundamental active/reactive powers.

1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is

set together with Bit 1 (FNLOAD) in STATUS1.

6

0

0: Phase A is out of no load condition based on apparent power.

1: Phase A is in no load condition based on apparent power. Bit set together with Bit 2

(VANLOAD) in the STATUS1 register.

7

0

0: Phase B is out of no load condition based on apparent power.

1: Phase B is in no load condition based on apparent power. Bit set together with Bit 2

(VANLOAD) in the STATUS1 register.

8

0

0: Phase C is out of no load condition based on apparent power.

1: Phase C is in no load condition based on apparent power. Bit set together with Bit 2

(VANLOAD) in the STATUS1 register.

15:9

000 0000

Reserved. These bits are always 0.

Table 42. COMPMODE Register (Address 0xE60E)

Bit

Mnemonic

Default Value Description

0

TERMSEL1[0]

1

Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1

output. Phase A is included in the CF1 outputs calculations.

Phase B is included in the CF1 outputs calculations.

Phase C is included in the CF1 outputs calculations.

1

2

3

TERMSEL1[1]

TERMSEL1[2]

TERMSEL2[0]

1

Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2

output. Phase A is included in the CF2 outputs calculations.

4

5

6

TERMSEL2[1]

TERMSEL2[2]

TERMSEL3[0]

1

Phase B is included in the CF2 outputs calculations.

Phase C is included in the CF2 outputs calculations.

Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3

output. Phase A is included in the CF3 outputs calculations.

7

TERMSEL3[1]

TERMSEL3[2]

1

Phase B is included in the CF3 outputs calculations.

Phase C is included in the CF3 outputs calculations.

00: the angles between phase voltages and phase currents are measured.

01: the angles between phase voltages are measured.

10: the angles between phase currents are measured.

11: no angles are measured.

8

10:9

ANGLESEL[1:0] 00

11

12

13

VNOMAEN

VNOMBEN

VNOMCEN

0

When this bit is 0, the apparent power on Phase A is computed regularly.

When this bit is 1, the apparent power on Phase A is computed using VNOM register instead

of regular measured rms phase voltage.

When this bit is 0, the apparent power on Phase B is computed regularly.

When this bit is 1, the apparent power on Phase B is computed using VNOM register instead of

regular measured rms phase voltage.

When this bit is 0, the apparent power on Phase C is computed regularly.

When this bit is 1, the apparent power on Phase C is computed using VNOM register instead of

regular measured rms phase voltage.

14

15

SELFREQ

Reserved

0

When the ADE7880 is connected to 50 Hz networks, this bit should be cleared to 0 (default

value). When the ADE7880 is connected to 60 Hz networks, this bit should be set to 1.

This bit is 0 by default and it does not manage any functionality.

Rev. A| Page 95 of 104

ADE7880

Data Sheet

Table 43. Gain Register (Address 0xE60F)

Bit

Mnemonic

Default Value

Description

2:0

PGA1[2:0]

000

Phase currents gain selection.

000: gain = 1.

001: gain = 2.

010: gain = 4.

011: gain = 8.

100: gain = 16.

101, 110, 111: reserved. When set, the ADE7880 behaves like PGA1[2:0] =

000.

5:3

PGA2[2:0]

PGA3[2:0]

Reserved

000

Neutral current gain selection.

000: gain = 1.

001: gain = 2.

010: gain = 4.

011: gain = 8.

100: gain = 16.

101, 110, 111: reserved. When set, the ADE7880 behaves like PGA2[2:0] =

000.

8:6

000

Phase voltages gain selection.

000: gain = 1.

001: gain = 2.

010: gain = 4.

011: gain = 8.

100: gain = 16.

101, 110, 111: reserved. When set, the ADE7880 behaves like PGA3[2:0] =

000.

15:9

000 0000

Reserved. These bits do not manage any functionality.

Table 44. CFMODE Register (Address 0xE610)

Bit

Mnemonic

Default Value

Description

2:0

CF1SEL[2:0]

000

000: the CF1 frequency is proportional to the sum of total active powers on

each phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.

010: the CF1 frequency is proportional to the sum of apparent powers on

each phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.

011: the CF1 frequency is proportional to the sum of fundamental active

powers on each phase identified by Bits[2:0] (TERMSEL1[x]) in the

COMPMODE register.

100: the CF1 frequency is proportional to the sum of fundamental reactive

powers on each phase identified by Bits[2:0] (TERMSEL1[x]) in the

COMPMODE register.

001, 101, 110, 111: reserved.

5:3

CF2SEL[2:0]

100

000: the CF2 frequency is proportional to the sum of total active powers on

each phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.

010: the CF2 frequency is proportional to the sum of apparent powers on

each phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.

011: the CF2 frequency is proportional to the sum of fundamental active

powers on each phase identified by Bits[5:3] (TERMSEL2[x]) in the

COMPMODE register.

100: the CF2 frequency is proportional to the sum of fundamental reactive

powers on each phase identified by Bits[5:3] (TERMSEL2[x]) in the

COMPMODE register.

001, 101,110,111: reserved.

Rev. A| Page 96 of 104

Data Sheet

ADE7880

Bit

Mnemonic

Default Value

Description

8:6

CF3SEL[2:0]

010

000: the CF3 frequency is proportional to the sum of total active powers on

each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.

010: the CF3 frequency is proportional to the sum of apparent powers on

each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.

011: CF3 frequency is proportional to the sum of fundamental active powers

on each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE

register.

100: CF3 frequency is proportional to the sum of fundamental reactive

powers on each phase identified by Bits[8:6] (TERMSEL3[x]) in the

COMPMODE register.

001, 101,110,111: reserved.

9

CF1DIS

CF2DIS

CF3DIS

1

When this bit is set to 1, the CF1 output is disabled. The respective digital to

frequency converter remains enabled even if CF1DIS = 1.

When this bit is set to 0, the CF1 output is enabled.

10

11

When this bit is set to 1, the CF2 output is disabled. The respective digital to

frequency converter remains enabled even if CF2DIS = 1.

When this bit is set to 0, the CF2 output is enabled.

When this bit is set to 1, the CF3 output is disabled. The respective digital to

frequency converter remains enabled even if CF3DIS = 1.

When this bit is set to 0, the CF3 output is enabled.

12

13

14

15

CF1LATCH

CF2LATCH

CF3LATCH

Reserved

0

When this bit is set to 1, the content of the corresponding energy registers is

latched when a CF1 pulse is generated. See the Synchronizing Energy

Registers with CFx Outputs section.

When this bit is set to 1, the content of the corresponding energy registers is

latched when a CF2 pulse is generated. See the Synchronizing Energy

Registers with CFx Outputs section.

When this bit is set to 1, the content of the corresponding energy registers is

latched when a CF3 pulse is generated. See the Synchronizing Energy

Registers with CFx Outputs section.

Reserved. This bit does not manage any functionality.

Table 45. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)

Bit

Mnemonic

Default Value Description

9:0

PHCALVAL

0000000000 If current channel compensation is necessary, these bits can vary only between 0 and 383.

If voltage channel compensation is necessary, these bits can vary only between 512 and 575.

If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves

like PHCALVAL set between 256 and 383.

If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation

behaves like PHCALVAL bits set between 384 and 511.

15:10

Reserved

000000

Reserved. These bits do not manage any functionality.

Table 46. PHSIGN Register (Address 0xE617)

Bit

Mnemonic

Default Value Description

0

AWSIGN

0

0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of

fundamental) on Phase A is positive.

1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of

fundamental) on Phase A is negative.

1

2

BWSIGN

CWSIGN

0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of

fundamental) on Phase B is positive.

1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of

fundamental) on Phase B is negative.

0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of

fundamental) on Phase C is positive.

1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of

fundamental) on Phase C is negative.

Rev. A| Page 97 of 104

ADE7880

Data Sheet

Bit

Mnemonic

Default Value Description

3

SUM1SIGN

0

0: if the sum of all phase powers in the CF1 data path is positive.

1: if the sum of all phase powers in the CF1 data path is negative. Phase powers in the CF1

data path are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by

Bits[2:0] (CF1SEL[x]) of the CFMODE register.

4

5

6

7

AFVARSIGN

BFVARSIGN

CFVARSIGN

SUM2SIGN

0

0: if the fundamental reactive power on Phase A is positive.

1: if the fundamental reactive power on Phase A is negative.

0: if the fundamental reactive power on Phase B is positive.

1: if the fundamental reactive power on Phase B is negative.

0: if the fundamental reactive power on Phase C is positive.

1: if the fundamental reactive power on Phase C is negative.

0: if the sum of all phase powers in the CF2 data path is positive.

1: if the sum of all phase powers in the CF2 data path is negative. Phase powers in the CF2

data path are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by

Bits[5:3] (CF2SEL[x]) of the CFMODE register.

8

SUM3SIGN

Reserved

0

0: if the sum of all phase powers in the CF3 data path is positive.

1: if the sum of all phase powers in the CF3 data path is negative. Phase powers in the CF3

data path are identified by Bits[8:6] (TERMSEL3[x]) of the COMPMODE register and by

Bits[8:6] (CF3SEL[x]) of the CFMODE register.

15:9

000 0000

Reserved. These bits are always 0.

Table 47. CONFIG Register (Address 0xE618)

Bit

Mnemonic

Default Value Description

0

INTEN

0

This bit manages the integrators in the phase current channels.

If INTEN=0, then the integrators in the phase current channels are always disabled.

If INTEN=1, then the integrators in the phase currents channels are enabled.

The neutral current channel integrator is managed by Bit 3 (ININTEN ) of CONFIG3 register.

1

2

Reserved

CF2DIS

1

0

Reserved. This bit should be maintained at 1 for proper operation.

When this bit is cleared to 0, the CF2 functionality is chosen at CF2/HREADY pin.

When this bit is set to 1, the HREADY functionality is chosen at CF2/HREADY pin.

3

SWAP

0

When this bit is set to 1, the voltage channel outputs are swapped with the current channel

outputs. Thus, the current channel information is present in the voltage channel registers

and vice versa.

4

5

6

MOD1SHORT

MOD2SHORT

HSDCEN

0

When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put

to ground.

When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put

to ground.

When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at

CF3/HSCLK pin.

When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at CF3/HSCLK pin.

When this bit is set to 1, a software reset is initiated.

7

SWRST

0

9:8

VTOIA[1:0]

00

These bits decide what phase voltage is considered together with Phase A current in the

power path.

00 = Phase A voltage.

01 = Phase B voltage.

10 = Phase C voltage.

11 = reserved. When set, the ADE7880 behaves like VTOIA[1:0] = 00.

11:10

VTOIB[1:0]

00

These bits decide what phase voltage is considered together with Phase B current in the

power path.

00 = Phase B voltage.

01 = Phase C voltage.

10 = Phase A voltage.

11 = reserved. When set, the ADE7880 behaves like VTOIB[1:0] = 00.

Rev. A| Page 98 of 104

Data Sheet

ADE7880

Bit

Mnemonic

Default Value Description

00

These bits decide what phase voltage is considered together with Phase C current in the

13:12

VTOIC[1:0]

power path.

00 = Phase C voltage.

01 = Phase A voltage.

10 = Phase B voltage.

11 = reserved. When set, the ADE7880 behaves like VTOIC[1:0] = 00.

Reserved.

15:14

Reserved

Table 48. MMODE Register (Address 0xE700)

Bit

1:0

2

Mnemonic

Default Value Description

Reserved

Reserved.

PEAKSEL[0]

1

PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three

phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak

measurement period indicated in the PEAKCYC register decreases accordingly because zero

crossings are detected on more than one phase.

When this bit is set to 1, Phase A is selected for the voltage and current peak registers.

When this bit is set to 1, Phase B is selected for the voltage and current peak registers.

When this bit is set to 1, Phase C is selected for the voltage and current peak registers.

Reserved. These bits do not manage any functionality.

3

PEAKSEL[1]

PEAKSEL[2]

Reserved

1

4

1

7:5

000

Table 49. ACCMODE Register (Address 0xE701)

Bit

Mnemonic

Default Value Description

1:0

WATTACC[1:0]

00

00: signed accumulation mode of the total and fundamental active powers. The total and

fundamental active energy registers and the CFx pulses are generated in the same way.

01: positive only accumulation mode of the total and fundamental active powers. In this

mode, although the total and fundamental active energy registers are accumulated in

positive only mode, the CFx pulses are generated in signed accumulation mode.

10: reserved. When set, the device behaves like WATTACC[1:0] = 00.

11: absolute accumulation mode of the total and fundamental active powers. The total and

fundamental energy registers and the CFx pulses are generated in the same way.

3:2

VARACC[1:0]

00

00: signed accumulation of the fundamental reactive powers. The fundamental reactive

energy registers and the CFx pulses are generated in the same way.

01: reserved. When set, the device behaves like VARACC[1:0] = 00.

10: the fundamental reactive power is accumulated, depending on the sign of the

fundamental active power: if the active power is positive, the reactive power is accumulated

as is, whereas if the active power is negative, the reactive power is accumulated with reversed

sign. In this mode, although the total and fundamental reactive energy registers are

accumulated in absolute mode, the CFx pulses are generated in signed accumulation mode.

11: absolute accumulation mode of the fundamental reactive powers. In this mode,

although the total and fundamental reactive energy registers are accumulated in absolute

mode, the CFx pulses are generated in signed accumulation mode.

5:4

CONSEL[1:0]

00

These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’are IA, IB, and

IC shifted respectively by −90°. See Table 50.

00: 3-phase four wires with three voltage sensors.

01: 3-phase three wires delta connection. In this mode, BVRMS register contains the rms

value of VA-VC.

10: 3-phase four wires with two voltage sensors.

11: 3-phase four wires delta connection.

Rev. A| Page 99 of 104

ADE7880

Data Sheet

Bit

Mnemonic

Default Value Description

6

REVAPSEL

0

0: The total active power on each phase is used to trigger a bit in the STATUS0 register as

follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB), and on

Phase C triggers Bit 8 (REVAPC).

1: The fundamental active power on each phase is used to trigger a bit in the STATUS0

register as follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB),

and on Phase C triggers Bit 8 (REVAPC).

7

Reserved

1

Reserved. This bit does not manage any functionality.

Table 50. CONSEL[1:0] Bits in Energy Registers¹

Energy Registers

CONSEL[1:0] = 00

CONSEL[1:0] = 01

VA × IA

VB = VA – VC

VB ×IB¹

CONSEL[1:0] = 10

VA × IA

VB = −VA – VC

VB × IB

CONSEL[1:0] = 11

VA × IA

VB = −VA

AWATTHR, AFWATTHR

BWATTHR, BFWATTHR

VA × IA

VB × IB

CWATTHR, CFWATTHR

AVARHR, AFVARHR

BVARHR, BFVARHR

VC × IC

VA × IA’

VB × IB’

VC × IC

VA × IA’

VB = VA – VC

VB × IB’¹

VC × IC

VA × IA’

VB = −VA – VC

VB × IB’

VC × IC

VA × IA’

VB = −VA

VB × IB’

CVARHR, CFVARHR

AVAHR

BVAHR

VC ×IC’

VA rms × IA rms

VB rms × IB rms

VC × IC’

VA rms × IA rms

VB rms × IB rms

VC × IC’

VA rms × IA rms

VB rms × IB rms

VA rms × IA rms

VB rms × IB rms

VB = VA – VC¹

VC rms × IC rms

CVAHR

VC rms × IC rms

¹In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the rms value of the line voltage between Phase A and and Phase C and stores the result into

BVRMS register (see the Voltage RMS in 3-Phase Three Wire Delta Configurations section). Consequently, the ADE7880 computes powers associated with Phase B that

do not have physical meaning. To avoid any errors in the frequency output pins CF1, CF2 or CF3 related to the powers associated with Phase B, disable the

contribution of Phase B to the energy to frequency converters by setting bits TERMSEL1[1], or TERMSEL2[1], or TERMSEL3[1] to 0 in the COMPMODE register (see the

Energy-to-Frequency Conversion section).

Table 51. LCYCMODE Register (Address 0xE702)

Bit

Mnemonic Default Value Description

0

LWATT

0

1

0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,

BFWATTHR, and CFWATTHR) are placed in regular accumulation mode.

1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,

BFWATTHR, and CFWATTHR) are placed into line cycle accumulation mode.

1

2

3

LVAR

0: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed in regular

accumulation mode.

1: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed into line-

cycle accumulation mode.

LVA

0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed in regular

accumulation mode.

1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed into line-cycle

accumulation mode.

ZXSEL[0]

0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more

than one phase is selected for zero-crossing detection, the accumulation time is shortened

accordingly.

4

5

6

ZXSEL[1]

ZXSEL[2]

RSTREAD

1

0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.

0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.

0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,

LVAR, and LVA) are set to 1.

1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR registers.

This means a read of those registers resets them to 0.

Rev. A| Page 100 of 104

Data Sheet

ADE7880

Bit

Mnemonic Default Value Description

PFMODE

0: power factor calculation uses instantaneous values of various phase powers used in its

7

0

expression.

1: power factor calculation uses phase energies values calculated using line cycle accumulation

mode. Bits LWATT and LVA in LCYCMODE register must be enabled for the power factors to be

computed correctly. The update rate of the power factor measurement in this case is the integral

number of half line cycles that are programmed into the LINECYC register.

Table 52. HSDC_CFG Register (Address 0xE706)

Bit

Mnemonic

Default Value Description

0

HCLK

0

0: HSCLK is 8 MHz.

1: HSCLK is 4 MHz.

1

HSIZE

0

0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.

1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.

0: no gap is introduced between packages.

2

HGAP

0

1: a gap of seven HCLK cycles is introduced between packages.

4:3

HXFER[1:0]

00

00 = HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV,

VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT, AFVAR, BFVAR, and CFVAR.

01 = HSDC transmits seven instantaneous values of currents and voltages: IAWV, VAWV,

IBWV, VBWV, ICWV, VCWV, and INWV.

10 = HSDC transmits nine instantaneous values of phase powers: AVA, BVA, CVA, AWATT,

BWATT, CWATT, AFVAR, BFVAR, and CFVAR.

11 = reserved. If set, the ADE7880 behaves as if HXFER[1:0] = 00.

0: SS/has output pin is active low.

5

HSAPOL

0

1: SS/HSA output pin is active high.

7:6

Reserved

00

Reserved. These bits do not manage any functionality.

Table 53. CONFIG3 Register (Address 0xEA00)

Bit

Mnemonic

Default Value Description

0

HPFEN

1

When HPFEN = 1, then all high-pass filters in voltage and current channels are enabled.

When HPFEN = 0, then all high-pass filters are disabled.

1

LPFSEL

0

When LPFSEL = 0, the LPF in the total active power data path introduces a settling time of

650 ms.

When LPFSEL = 1, the LPF in the total active power data path introduces a settling time of

1300 ms.

2

3

INSEL

0

When INSEL = 0, the register NIRMS contains the rms value of the neutral current.

When INSEL = 1, the register NIRMS contains the rms value of ISUM, the instantaneous value

of the sum of all 3 phase currents, IA, IB, and IC.

ININTEN

This bit manages the integrator in the neutral current channel.

If ININTEN = 0, then the integrator in the neutral current channel is disabled.

If ININTDIS = 1, then the integrator in the neutral channel is enabled.

The integrators in the phase currents channels are managed by Bit 0 (INTEN) of CONFIG

register.

4

Reserved

0

Reserved. This bit should be maintained at 0 for proper operation.

Reserved. These bits do not manage any functionality.

7:5

000

Rev. A| Page 101 of 104

ADE7880

Data Sheet

Table 54. HCONFIG Register (Address 0xE900)

Bit

Mnemonic

Default Value Description

0

HRCFG

0

When this bit is cleared to 0, the bit 19 (HREADY) interrupt in MASK0 register is triggered

after a certain delay period. The delay period is set by bits HSTIME. The update frequency

after the settling time is determined by bits HRATE.

When this bit is set to 1, the bit 19 (HREADY) interrupt in MASK0 register is triggered starting

immediately after the harmonic calculations block has been setup. The update frequency is

determined by bits HRATE.

2:1

4:3

HPHASE

HSTIME

00

01

These bits decide what phase or neutral is analyzed by the harmonic calculations block.

00 = Phase A voltage and current.

01 = Phase B voltage and current.

10 = Phase C voltage and current.

11 = neutral current.

These bits decide the delay period after which, if HRCFG bit is set to 1, bit 19 (HREADY)

interrupt in MASK0 register is triggered.

00 = 500 ms.

01 = 750 ms.

10 = 1000 ms.

11 = 1250 ms.

7:5

HRATE

000

These bits manage the update rate of the harmonic registers.

000 = 125 μsec (8 kHz rate).

001 = 250 μsec (4 kHz rate).

010 = 1 ms (1 kHz rate).

011 = 16 ms (62.5 Hz rate).

100 = 128 ms (7.8125 Hz rate).

101 = 512 ms (1.953125 Hz rate).

110 = 1.024 sec (0.9765625 Hz rate).

111 = harmonic calculations disabled.

9:8

ACTPHSEL

Reserved

00

0

These bits select the phase voltage used as time base for harmonic calculations.

00 = Phase A voltage.

01 = Phase B voltage.

10 = Phase C voltage.

11 = reserved. If selected, phase C voltage is used.

15:10

Reserved. These bits do not manage any functionality.

Table 55. LPOILVL Register (Address 0xEC00)

Bit

2:0

7:3

Mnemonic

LPOIL[2:0]

LPLINE[4:0]

Default Value

Description

111

Threshold is put at a value corresponding to full scale multiplied by LPOIL/8.

The measurement period is (LPLINE + 1)/50 seconds.

00000

Table 56. CONFIG2 Register (Address 0xEC01)

Bit

Mnemonic Default Value Description

0

EXTREFEN

I2C_LOCK

0

When this bit is 0, it signifies that the internal voltage reference is used in the ADCs.

When this bit is 1, an external reference is connected to the Pin 17 REF_IN/OUT

.

1

When this bit is 0, the SS/HSA pin can be toggled three times to activate the SPI port. If I²C is the

active serial port, this bit must be set to 1 to lock it in. From this moment on, toggling of the SS

/HSA pin and an eventual switch into using the SPI port is no longer possible. If SPI is the active serial

port, any write to CONFIG2 register locks the port. From this moment on, a switch into using I²C

port is no longer possible. Once locked, the serial port choice is maintained when the ADE7880

changes PSMx power modes.

7:2

Reserved

0

Reserved. These bits do not manage any functionality.

Rev. A| Page 102 of 104

Data Sheet

ADE7880

OUTLINE DIMENSIONS

6.10

6.00 SQ

5.90

0.30

0.23

0.18

PIN 1

INDICATOR

PIN 1

INDICATO

31

30

40

R

1

0.50

BSC

4.45

4.30 SQ

4.25

EXPOSED

PAD

21

20

10

11

0.45

0.40

0.35

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.

Figure 111. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad

(CP-40-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-40-10

ADE7880ACPZ

ADE7880ACPZ-RL

EVAL-ADE7880EBZ

−40°C to +85°C

40-Lead LFCSP_WQ

40-Lead LFCSP_WQ, 13”Tape and Reel

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. A| Page 103 of 104

ADE7880

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D10193-0-3/12(A)

Rev. A| Page 104 of 104


型号：	ADE7880
厂家：	ADI
描述：	Polyphase Multifunction Energy Metering IC 多相多功能电能计量IC
文件：	总104页 (文件大小：1297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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