ADF4153ABCPZ-RL7 [ADI]
Fractional-N Frequency Synthesizer;
| 型号： | ADF4153ABCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Fractional-N Frequency Synthesizer 信息通信管理 |
| 文件： | 总24页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fractional-N Frequency Synthesizer
Data Sheet
ADF4153A
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
The ADF4153A is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4106, ADF4110/ADF4111/
ADF4112/ADF4113, and ADF4153
Consistent RF output phase
Loop filter design possible with ADIsimPLL
APPLICATIONS
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DV
V
SDV
R
SET
DD
DD
P
DD
ADF4153A
REFERENCE
4-BIT
R COUNTER
×2
REF
IN
DOUBLER
+
PHASE
CP
CHARGE
PUMP
FREQUENCY
DETECTOR
V
DD
–
HIGH-Z
DGND
LOCK
DETECT
CURRENT
SETTING
OUTPUT
MUX
V
MUXOUT
DD
R
N
DIV
DIV
RFCP3 RFCP2 RFCP1
RF
RF
A
B
IN
N-COUNTER
IN
THIRD ORDER
FRACTIONAL
INTERPOLATOR
CLK
DATA
LE
FRACTION
REG
MODULUS
REG
INTEGER
REG
24-BIT
DATA
REGISTER
AGND
DGND
CPGND
Figure 1.
Rev. A
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ADF4153A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
N Divider Register, R0............................................................... 15
R Divider Register, R1................................................................ 15
Control Register, R2................................................................... 15
Noise and Spur Register, R3...................................................... 16
Reserved Bits............................................................................... 16
Initialization Sequence .............................................................. 17
RF Synthesizer: A Worked Example........................................ 17
Modulus....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus................................................ 17
Fastlock with Spurious Optimization...................................... 18
Spur Mechanisms ....................................................................... 18
Spur Consistency........................................................................ 19
Phase Resync............................................................................... 19
Filter Design—ADIsimPLL....................................................... 19
Interfacing ................................................................................... 19
PCB Design Guidelines for Chip Scale Package .................... 20
Applications Information .............................................................. 21
Local Oscillator for a GSM Base Station Transmitter ........... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 8
Reference Input Section............................................................... 8
RF Input Stage............................................................................... 8
RF INT Divider............................................................................. 8
INT, FRAC, MOD, and R Relationship ..................................... 8
RF R Counter ................................................................................ 8
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect........................................................ 9
Input Shift Registers..................................................................... 9
Program Modes ............................................................................ 9
Register Maps.................................................................................. 10
REVISION HISTORY
1/13—Rev. 0 to Rev. A
Added TSSOP Package ......................................................Universal
Added Figure 3, Renumbered Sequentially ...................................6
Updated Outline Dimensions........................................................22
Changes to Ordering Guide ...........................................................22
10/12—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADF4153A
SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF INPUT CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
See Figure 12 for an input circuit
−8 dBm minimum/0 dBm maximum
−10 dBm minimum/0 dBm maximum
0.5
1
4
4
GHz
GHz
For lower frequencies, ensure slew rate
(SR) > 400 V/µs
REFIN CHARACTERISTICS
REFIN Input Frequency
See Figure 11 for an input circuit
10
250
MHz
For f < 10 MHz, use a dc-coupled,
CMOS-compatible square wave;
slew rate > 25 V/µs
Biased at AVDD/21
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
0.7
AVDD
10
100
V p-p
pF
µA
32
MHz
ICP Sink/Source
Programmable; see Figure 19
With RSET = 4.7 kΩ
With RSET = 4.7 kΩ
High Value
Low Value
5
mA
µA
%
kΩ
nA
%
312.5
2.5
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Sink and Source Matching
ICP vs. VCP
With RSET = 4.7 kΩ
3.0
10
1
2
2
2
Sink and source current
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
%
%
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
1.4
1.4
V
V
µA
pF
0.6
1
10
V
V
Open-drain 1 kΩ pull-up to 1.8 V
IOL = 500 µA
0.4
3.3
2.7
V
DVDD, SDVDD
AVDD
VP
IDD
AVDD
5.5
24
V
mA
µA
20
1
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH
Normalized 1/f Noise (PN1_f)3
Phase Noise Performance4
1750 MHz Output5
2
)
−223
−121
dBc/Hz
dBc/Hz
PLL loop BW = 500 kHz
Measured at 10 kHz offset, normalized to 1 GHz
@ VCO output
−107
dBc/Hz
@ 5 kHz offset, 25 MHz PFD frequency
1 AC coupling ensures AVDD/2 bias.
2 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
3 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF
and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
4 The phase noise is measured with the EV-ADF4153ASD1Z and the Rohde & Schwarz FSUP spectrum analyzer operating in phase noise mode.
5 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.
,
Rev. A | Page 3 of 24
ADF4153A
Data Sheet
TIMING SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CLK to LE setup time
LE pulse width
t4
t5
CLK
t2
t3
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DB2
DATA
LE
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. A | Page 4 of 24
Data Sheet
ADF4153A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = 0 V,
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
V
DD = AVDD = DVDD = SDVDD, unless otherwise noted.
Table 3.
Parameter
Rating
VDD to GND
DVDD to AVDD
SDVDD to AVDD
VP to GND
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−65°C to +125°C
150°C
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
VP to VDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFIN to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
Reflow Soldering
ESD CAUTION
112°C/W
30.4°C/W
Peak Temperature
Time at Peak Temperature
260°C
40 sec
Rev. A | Page 5 of 24
ADF4153A
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
V
SET
P
CP
DV
DD
CPGND
AGND
AGND
1
2
3
4
5
15 MUXOUT
CPGND
AGND
MUXOUT
LE
14
13
12
11
LE
ADF4153A
TOP VIEW
(Not to Scale)
ADF4153A
DATA
TOP VIEW
RF
RF
B
DATA
CLK
IN
IN
(Not to Scale)
RF
RF
B
A
CLK
SDV
IN
IN
A
DD
AV
SDV
DD
DD
REF
DGND
IN
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GND.
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Pin No.
TSSOP LFCSP
Mnemonic Description
1
19
RSET
Connecting a resistor between RSET and ground sets the maximum charge pump output current.
The relationship between ICP and RSET is
23.5
ICPMAX
=
RSET
where RSET = 4.7 kΩ and ICPMAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, CP provides ICP to the external loop filter, which in turn
drives the external VCO.
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This pin should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF (see Figure 12).
6
7
5
6, 7
RFINA
AVDD
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. AVDD has a value of 3 V 10%. AVDD must have the same
voltage as DVDD
.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 kΩ (see Figure 11). This input can be driven from a TTL or CMOS crystal oscillator,
or it can be ac-coupled.
9
10
9, 10
11
DGND
SDVDD
Digital Ground.
Σ-Δ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible
to this pin. SDVDD has a value of 3 V 10%. SDVDD must have the same voltage as DVDD
.
11
12
13
14
15
12
CLK
Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is
latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is
a high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one
of four latches; the latch is selected using the control bits.
This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be externally accessed.
13
DATA
LE
14
15
MUXOUT
DVDD
16, 17
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD has a value of 3 V 10%. DVDD must have
the same voltage as AVDD
.
16
18
21
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
Exposed Pad. The exposed pad must be connected to GND.
Rev. A | Page 6 of 24
N/A
EPAD
Data Sheet
ADF4153A
TYPICAL PERFORMANCE CHARACTERISTICS
Settings for single-sideband plots and phase noise vs. temperature plot: loop bandwidth = 20 kHz, reference = 100 MHz, PFD = 25 MHz,
carrier frequency = 1720.2 MHz, N = 68, MOD = 125, FRAC = 101, ICP = 2.5 mA, VCO = Mini-Circuits ROS-1800+, evaluation board =
EV-ADF4153ASD1Z, measurements taken on the Agilent E5052 signal source analyzer operating in phase noise mode.
–30
–40
5
20kHz LOOP BW, LOWEST NOISE MODE,
= 1720.2MHz, PFD = 25MHz, N = 68
R
F
0
FRAC = 101, MOD = 125, I = 2.5mA
CP
–50
INTEGRATED PHASE ERROR = 0.126°
MINI-CIRCUITS ROS-1800+ VCO
–60
–5
–70
PRESCALER = 4/5
–80
–10
–15
–20
–25
–30
–35
–90
–100
–110
–120
–130
–140
–150
–160
–170
PRESCALER = 8/9
100
1k
10k
100k
1M
10M
100M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
OFFSET (Hz)
FREQUENCY (GHz)
Figure 5. Single-Sideband Phase Noise Plot (Lowest Noise Mode)
Figure 8. RF Input Sensitivity
6
5
–30
20kHz LOOP BW, LOW NOISE AND SPUR MODE,
–40
R
= 1720.2MHz, PFD = 25MHz, N = 68
F
FRAC = 101, MOD = 125, I = 2.5mA
INTEGRATED PHASE ERROR = 0.138°
MINI-CIRCUITS ROS-1800+ VCO
CP
–50
–60
4
3
–70
2
–80
1
–90
0
–100
–110
–120
–130
–140
–150
–160
–170
–1
–2
–3
–4
–5
–6
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
100
1k
10k
100k
1M
10M
100M
V
OFFSET (Hz)
CP
Figure 6. Single-Sideband Phase Noise Plot (Low Noise and Spur Mode)
Figure 9. Charge Pump Output Characteristics
–96
–98
–30
20kHz LOOP BW, LOW SPUR MODE,
–40
–50
R
= 1720.2MHz, PFD = 25MHz, N = 68
F
FRAC = 101, MOD = 125, I = 2.5mA
CP
INTEGRATED PHASE ERROR = 0.188°
MINI-CIRCUITS ROS-1800+ VCO
–60
–100
–102
–104
–106
–108
–110
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
100
1k
10k
100k
1M
10M
100M
–60
–40
–20
0
20
40
60
80
100
OFFSET (Hz)
TEMPERATURE (°C)
Figure 7. Single-Sideband Phase Noise Plot (Low Spur Mode)
Figure 10. Phase Noise vs. Temperature
Rev. A | Page 7 of 24
ADF4153A
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
RF INT DIVIDER
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is
POWER-DOWN
CONTROL
100kΩ
SW2
NC
TO R COUNTER
REF
IN
NC
SW1
RFOUT = FPFD × (INT + (FRAC/MOD))
(1)
BUFFER
SW3
where:
NC
RFOUT is the output frequency of the external voltage controlled
oscillator (VCO).
Figure 11. Reference Input Stage
INT is the preset divide ratio of the binary 9-bit counter (31
to 511).
FRAC is the numerator of the fractional division (0 to MOD − 1).
MOD is the preset fractional modulus (2 to 4095).
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
The PFD frequency is given by:
1.6V
BIAS
GENERATOR
F
PFD = REFIN × (1 + D)/R
(2)
AV
where:
DD
REFIN is the reference input frequency.
D is the REFIN doubler bit.
2kΩ
2kΩ
R is the preset divide ratio of the binary 4-bit programmable
reference counter (1 to 15).
RF
RF
A
B
IN
RF R COUNTER
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
IN
RF N DIVIDER
N = INT + FRAC/MOD
AGND
FROM RF
INPUT STAGE
TO PFD
Figure 12. RF Input Stage
N-COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
MOD
REG
FRAC
VALUE
Figure 13. RF N Divider
Rev. A | Page 8 of 24
Data Sheet
ADF4153A
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
INPUT SHIFT REGISTERS
The ADF4153A digital section includes a 4-bit RF R counter,
a 9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Figure 16
shows a summary of how the registers are programmed.
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic
of the phase frequency detector. The PFD includes a fixed
delay element that sets the width of the antibacklash pulse,
which is typically 1.8 ns. This pulse ensures that there is no
dead zone in the PFD transfer function and gives a consistent
reference spur level.
UP
HI
D1
Q1
U1
CLR1
Table 5. C2 and C1 Truth Table
+IN
Control Bits
C2
0
0
1
1
C1
0
1
0
1
Register
CHARGE
PUMP
CP
N divider register
R divider register
Control register
Noise and spur register
U3
DELAY
DOWN
CLR2
D2 Q2
HI
PROGRAM MODES
U2
–IN
Figure 16 through Figure 20 show how to set up the program
modes in the ADF4153A.
Figure 14. PFD Simplified Schematic
The ADF4153A programmable modulus is double buffered.
This means that two events have to occur before the part uses
a new modulus value. First, the new modulus value is latched
into the device by writing to the R divider register. Second,
a new write must be performed on the N divider register.
Therefore, to ensure that the modulus value is loaded correctly,
the N divider register must be written to any time that the
modulus value is updated.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4153A lets the user access
various internal points on the chip. The state of MUXOUT is
controlled by M3, M2, and M1 (see Figure 18). Figure 15
shows the MUXOUT section in block diagram form.
DV
DD
THREE-STATE OUTPUT
LOGIC LOW
DIGITAL LOCK DETECT
R COUNTER DIVIDER
N COUNTER DIVIDER
ANALOG LOCK DETECT
LOGIC HIGH
MUXOUT
MUX
CONTROL
DGND
Figure 15. MUXOUT Schematic
Rev. A | Page 9 of 24
ADF4153A
Data Sheet
REGISTER MAPS
N DIVIDER REG (R0)
CONTROL
BITS
9-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9 DB8
F8 F7
DB7
F6
DB6
F5
DB5
F4
DB4 DB3 DB2
F3 F2 F1
DB1
DB0
FL1
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
C2 (0) C1 (0)
R DIVIDER REG (R1)
4-BIT
R COUNTER
CONTROL
BITS
MUXOUT
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
P3 M3 M2 M1 P1 R4 R3 R2 R1 M12 M11 M10 M9 M8
DB8
M7
DB7
M6
DB6
M5
DB5
M4
DB4 DB3 DB2
DB1 DB0
0
M3
M2
M1
C2 (0) C1 (1)
CONTROL REG (R2)
CP CURRENT
SETTING
CONTROL
BITS
RESYNC
DB15 DB14 DB13 DB12 DB11 DB10
DB9
CP2
DB8
CP1
DB7
CP0
DB6
U5
DB5
U4
DB4
U3
DB3
U2
DB2
U1
DB1
DB0
S4
S3
S2
S1
U6
CP3
C2 (1) C1 (0)
NOISE AND SPUR REG (R3)
CONTROL
BITS
NOISE AND SPUR
MODE
RESERVED
DB10
0
DB9
T8
DB8
T7
DB7 DB6 DB5
T6 T5
DB4
0
DB3
DB2
T1
DB1
DB0
0
0
C2 (1) C1 (1)
Figure 16. Register Summary
Rev. A | Page 10 of 24
Data Sheet
ADF4153A
CONTROL
BITS
9-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
DB23 DB22
N9
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F7
DB7
F6
DB6
F5
DB5
F4
DB4 DB3 DB2
F3 F2 F1
DB1
DB0
N8
N7
N6
N5
N4
N3
N2
N1
C2 (0) C1 (0)
FL1
F8
F12
F11
F10
F9
F12
F11
F10
F3
F2
F1
FRACTIONAL VALUE (FRAC)
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
.
.
1
0
0
1
1
.
.
.
0
0
1
0
1
.
.
.
0
0
1
2
3
.
.
.
4092
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
4093
4094
4095
N9
N8
N7
N6
N5
N4
N3
N2
N1
INTEGER VALUE (INT)
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
31
32
0
0
.
0
0
.
0
0
.
1
1
.
0
0
.
0
0
.
0
0
.
0
1
.
1
0
.
33
34
.
.
.
.
.
.
.
.
.
.
.
.
1
.
1
.
1
.
1
.
1
...
1
.
1
.
0
.
1
.
509
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
510
511
FL1
FASTLOCK
0
1
NORMAL OPERATION
FASTLOCK ENABLED
Figure 17. N Divider Register Map (R0)
Rev. A | Page 11 of 24
ADF4153A
Data Sheet
CONTROL
BITS
MUXOUT
4-BIT R COUNTER
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
DB23 DB22 DB21
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
DB20 DB19
M1
M3
M2
0
P1
R4
R3
R2
R1
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
P3
C2 (0) C1 (1)
P3 LOAD CONTROL
P1
PRESCALER
INTERPOLATOR
MODULUS VALUE (MOD)
M12
M11
M10
M3
0
M2
1
M1
0
0
1
NORMAL OPERATION
LOAD RESYNC
0
1
4/5
8/9
0
0
0
..........
2
0
0
.
.
.
0
0
.
.
.
0
0
.
.
.
..........
..........
..........
..........
..........
..........
0
1
.
.
.
1
0
.
.
.
1
0
.
.
.
3
4
.
.
.
1
1
1
1
0
0
4092
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
4093
4094
4095
RF R COUNTER
DIVIDE RATIO
R4
R3
R2
R1
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
1
1
0
0
12
1
1
1
1
1
1
0
1
1
1
0
1
13
14
15
M3
M2
M1
MUXOUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
LOGIC HIGH
R DIVIDER OUTPUT
ANALOG LOCK DETECT
FASTLOCK SWITCH
LOGIC LOW
Figure 18. R Divider Register Map (R1)
Rev. A | Page 12 of 24
Data Sheet
ADF4153A
CP CURRENT
SETTING
CONTROL
BITS
RESYNC
DB15 DB14 DB13 DB12 DB11 DB10 DB9
S4 S3 S2 S1 U6 CP3 CP2
DB8
CP1
DB7
CP0
DB6
U5
DB5
U4
DB4
U3
DB3 DB2
U2 U1
DB1
DB0
C2 (1) C1 (0)
REFERENCE
DOUBLER
U6
0
1
DISABLED
ENABLED
U1
COUNTER RESET
0
1
DISABLED
ENABLED
S4
S3
S2
S1
RESYNC
0
0
0
.
0
0
0
.
0
1
1
.
1
0
1
.
1
2
3
U2
CP THREE-STATE
.
.
.
.
.
.
0
1
DISABLED
THREE-STATE
.
.
.
.
.
1
1
1
1
1
1
0
1
1
1
0
1
13
14
15
U3
POWER-DOWN
0
1
NORMAL OPERATION
POWER-DOWN
I
(mA)
CP
CP3
CP2
CP1
CP0
3.0kΩ
4.7kΩ
10kΩ
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.979
1.958
2.938
3.917
4.896
5.875
6.854
7.833
0.625
1.250
1.875
2.500
3.125
3.750
4.375
5.000
0.294
0.588
0.881
1.175
1.469
1.763
2.056
2.350
U4
LDP
0
1
24 PFD CYCLES
40 PFD CYCLES
U5
PD POLARITY
0
1
NEGATIVE
POSITIVE
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.490
0.979
1.469
1.958
2.448
2.938
3.427
3.917
0.313
0.625
0.938
1.250
1.563
1.875
2.188
2.500
0.147
0.294
0.441
0.588
0.734
0.881
1.028
1.175
Figure 19. Control Register Map (R2)
Rev. A | Page 13 of 24
ADF4153A
Data Sheet
NOISE AND SPUR
MODE
CONTROL
BITS
RESERVED
DB10
0
DB9
T8
DB8
T7
DB7
T6
DB6
T5
DB5
0
DB4
0
DB3
0
DB2
T1
DB1
DB0
C2 (1) C1 (1)
DB10, DB5, DB4, DB3
0
RESERVED
RESERVED
THESE BITS MUST BE SET TO 0
FOR NORMAL OPERATION.
DB9, DB8, DB7, DB6, DB2 NOISE AND SPUR SETTING
00000
11100
11111
LOW SPUR MODE
LOW NOISE AND SPUR MODE
LOWEST NOISE MODE
Figure 20. Noise and Spur Register (R3)
Rev. A | Page 14 of 24
Data Sheet
ADF4153A
the error again exceeds 30 ns. In this case, the digital lock detect
is reliable only as a loss-of-lock detector.
N DIVIDER REGISTER, R0
With R0[1, 0] set to [0, 0], the on-chip N divider register
is programmed. Figure 17 shows the input data format for
programming this register.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division
ratio from the RFIN to the PFD input.
9-Bit INT Value
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used
in Equation 1 (see the INT, FRAC, MOD, and R Relationship
section).
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on a
synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 2 GHz. Therefore, when operating the
ADF4153A above 2 GHz, this must be set to 8/9. The prescaler
limits the INT value.
12-Bit FRAC Value
These 12 bits control what is loaded as the FRAC value into
the fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
The FRAC value must be less than or equal to the value loaded
into the MOD register.
With P = 4/5, NMIN = 31.
With P = 8/9, NMIN = 91.
4-Bit R Counter
Fastlock
The 4-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the phase frequency detector (PFD). Division ratios from
1 to 15 are allowed.
When set to logic high, fastlock is enabled. This sets the charge
pump current to its maximum value. When set to logic low, the
charge pump current is equal to the value programmed into the
function register. Also, if MUXOUT is programmed to setting
the fastlock switch, MUXOUT is shorted to ground when the
fastlock bit is 1 and is high impedance when this bit is 0.
12-Bit Interpolator MOD Value
These programmable bits set the fractional modulus. This is the
ratio of the PFD frequency to the channel step resolution on the
RF output. Refer to the RF Synthesizer: A Worked Example
section for more information.
R DIVIDER REGISTER, R1
With R1[1, 0] set to [0, 1], the on-chip R divider register is
programmed. Figure 18 shows the input data format for
programming this register.
The ADF4153A programmable modulus is double buffered.
This means that two events have to occur before the part uses
a new modulus value. First, the new modulus value is latched
into the device by writing to the R divider register. Second,
a new write must be performed on the N divider register.
Therefore, any time that the modulus value has been updated,
the N divider register must then be written to in order to ensure
that the modulus value is loaded correctly.
Load Control
When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the
resync delay of the Σ-Δ. This is done to ensure phase resync
when changing frequencies. See the Phase Resync section for
more information and a worked example.
CONTROL REGISTER, R2
MUXOUT
With R2[1, 0] set to [1, 0], the on-chip control register
is programmed. Figure 19 shows the input data format for
programming this register.
The on-chip multiplexer is controlled by DB22, DB21, and
DB20 on the ADF4153A. See Figure 18 for the truth table.
Digital Lock Detect
RF Counter Reset
The digital lock detect output goes high if there are 24 succes-
sive PFD cycles with an input error of less than 15 ns (for LDP
is 0, see the Control Register, R2 section for a more thorough
explanation of the LDP bit). It stays high until a new channel is
programmed or until the error at the PFD input exceeds 30 ns
for one or more cycles. If the loop bandwidth is narrow compared
to the PFD frequency, the error at the PFD inputs may drop
below 15 ns for 24 cycles around a cycle slip. Therefore, the
digital lock detect may go falsely high for a short period until
DB2 is the RF counter reset bit for the ADF4153A. When this
is 1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
RF Charge Pump Three-State
DB3 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
Rev. A | Page 15 of 24
ADF4153A
Data Sheet
When the doubler is enabled and the lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REFIN
duty cycle. The phase noise degradation can be as much as 5 dB
for the REFIN duty cycles outside a 45% to 55% range. The phase
noise is insensitive to the REFIN duty cycle in the lowest noise
mode and in the lowest noise and spur mode. The phase noise
is insensitive to REFIN duty cycle when the doubler is disabled.
RF Power-Down
DB4 on the ADF4153A provides the programmable power-
down mode. Setting this bit to 1 performs a power-down.
Setting this bit to 0 returns the synthesizer to normal operation.
While in software power-down mode, the part retains all
information in its registers. Only when supplies are removed
are the register contents lost.
The maximum allowed REFIN frequency when the doubler is
enabled is 30 MHz.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
NOISE AND SPUR REGISTER, R3
2. The synthesizer counters are forced to their load state
conditions.
With R3[1, 0] set to [1, 1], the on-chip noise and spur register
is programmed. Figure 20 shows the input data format for
programming this register.
3. The charge pump is forced into three-state mode.
4. The digital lock detect circuitry is reset.
5. The RFIN input is debiased.
Noise and Spur Mode
Noise and spur mode lets the user optimize a design either for
improved spurious performance or for improved phase noise
performance. When the low spur setting is chosen, dither is
enabled. This randomizes the fractional quantization noise so
that it resembles white noise rather than spurious noise. As a
result, the part is optimized for improved spurious perfor-
mance. This operation would normally be used when the PLL
closed-loop bandwidth is wide, for fast-locking applications.
(Wide-loop bandwidth is seen as a loop bandwidth greater than
1/10 of the RFOUT channel step resolution (fRES).) A wide-loop
filter does not attenuate the spurs to the same level as a narrow-
loop bandwidth.
6. The input register remains active and capable of loading
and latching data.
Lock Detect Precision (LDP)
When DB5 is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4153A sets the phase detector polarity. When
the VCO characteristics are positive, this should be set to 1.
When they are negative, it should be set to 0.
When the low noise and spur setting is enabled, dither is disabled.
This optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded
in this mode compared to the low spur setting.
Charge Pump Current Setting
DB7, DB8, DB9, and DB10 set the charge pump current setting.
This should be set to the charge pump current that the loop
filter is designed with (see Figure 19).
To further improve noise performance, the lowest noise setting
option can be used, which reduces the phase noise. As well as
disabling the dither, it also ensures that the charge pump is
operating in an optimum region for noise performance. This
setting is extremely useful where a narrow-loop filter band-
width is available. The synthesizer ensures extremely low noise
and the filter attenuates the spurs. The typical performance
characteristics give the user an idea of the trade-off in a typical
W-CDMA setup for the different noise and spur settings.
REFIN Doubler
Setting DB11 to 0 feeds the REFIN signal directly to the 4-bit RF
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding into the 4-bit
R counter. When the doubler is disabled, the REFIN falling edge
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REFIN become active edges at the PFD input.
RESERVED BITS
These bits should be set to 0 for normal operation.
Rev. A | Page 16 of 24
Data Sheet
ADF4153A
For example, in a GSM 1800 system, where 1.8 GHz RF
INITIALIZATION SEQUENCE
frequency output (RFOUT) is required, a 13 MHz reference
frequency input (REFIN) is available and a 200 kHz channel
resolution (fRES) is required on the RF output. With REFIN
doubler (D) set to 0 and reference division (R) set to 1, from
Equation 4:
The following initialization sequence should be followed upon
powering up the part:
1. Write all zeros to the noise and spur register. This ensures
that all test modes are cleared.
2. Write again to the noise and spur register, this time
selecting which noise and spur mode is required. For
example, writing Hexadecimal 0003C7 to the part selects
lowest noise mode.
3. Enable the counter reset in the control register by writing a
1 to DB2; also select the required settings in the control
register. If using the phase resync function, set the resync
bits to the required settings.
4. Load the R divider register (with load control DB23
set to 0).
F
PFD = [13 MHz × (1 + 0)/1] = 13 MHz
(5)
(6)
MOD = FPFD/fRES
MOD = 13 MHz/200 kHz = 65
1.8 G = 13 MHz × (INT + FRAC/65)
where INT = 138; FRAC = 30
MODULUS
The choice of modulus (MOD) depends on the PFD frequency
(which depends on the available reference signal REFIN) and
the channel resolution (fRES) required at the RF output. For
example, a GSM system with 13 MHz REFIN sets the modulus to
65. This means that the RF output resolution (fRES) is the 200 kHz
(13 MHz/65) necessary for GSM. With dither off, the fractional
spur interval depends on the modulus values chosen. See Table 6
for more information.
5. Load the N divider register.
6. Disable the counter reset by writing a 0 to DB2 in the
control register.
The part now locks to the set frequency.
If using the phase resync function, an extra step is needed after
Step 3. This involves loading the R divider register with load
control = 1 and the required delay interval in place of the MOD
value. The previous sequence can then be followed, ensuring
that in Step 4 the value of MOD is written to the R divider
register with load control = 0.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
note that the PFD cannot be operated above specified limits due
to a limitation in the speed of the Σ-Δ circuit of the N divider.
See the Spur Consistency and Phase Resync sections for more
information on the phase resync feature.
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer is
programmed:
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4153A lets the
user program the modulus over a 12-bit range. This means that
the user can set up the part in many different configurations for
the application, when combined with the reference doubler and
the 4-bit R counter.
RFOUT = [INT + (FRAC/MOD)] × [FPFD
]
(3)
(4)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
The following is an example of an application that requires
1.75 GHz RF and 200 kHz channel step resolution. The system
has a 13 MHz reference signal.
MOD is the modulus.
The PFD frequency is given by:
F
PFD = [REFIN × (1 + D)/R]
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD. The modulus is now programmed to divide by
130. This also results in 200 kHz resolution and offers superior
phase noise performance over the previous setup.
Rev. A | Page 17 of 24
ADF4153A
Data Sheet
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC
and GSM 1800 standards, the programmable modulus is of
great benefit. PDC requires 25 kHz channel step resolution,
whereas GSM 1800 requires 200 kHz channel step resolution.
A 13 MHz reference signal can be fed directly to the PFD. The
modulus is programmed to 520 when in PDC mode (13 MHz/
520 = 25 kHz). The modulus is reprogrammed to 65 for GSM
1800 operation (13 MHz/65 = 200 kHz). It is important that the
PFD frequency remains constant (13 MHz). This lets the user
design one loop filter that can be used in both setups without
running into stability issues. It is the ratio of the RF frequency
to the PFD frequency that affects the loop design. By keeping
this relationship constant, the same loop filter can be used in
both applications.
When the PLL has locked to the new frequency, the charge
pump is again programmed to the lowest charge pump current
setting by setting the fastlock bit to 0. The internal switch opens
and the damping resistor reverts to its original value. This
narrows the loop bandwidth to its original cutoff frequency
to allow better attenuation of the spurs than the wide-loop
bandwidth.
SPUR MECHANISMS
The following section describes the three different spur mechan-
isms that arise with a fractional-N synthesizer and how to
minimize them in the ADF4153A.
Fractional Spurs
The fractional interpolator in the ADF4153A is a third-order
Σ-Δ modulator (SDM) with a modulus (MOD) that is program-
mable to any integer value from 2 to 4095. In low spur mode
(dither enabled), the minimum allowed value of MOD is 50.
The SDM is clocked at the PFD reference rate (FPFD) that allows
PLL output frequencies to be synthesized at a channel step
resolution of FPFD/MOD.
FASTLOCK WITH SPURIOUS OPTIMIZATION
As mentioned in the Noise and Spur Mode section, the part
can be optimized for spurious performance. However, in fast-
locking applications, the loop bandwidth needs to be wide,
and therefore the filter does not provide much attenuation of
the spurs. The programmable charge pump can be used to get
around this issue. The filter is designed for a narrow-loop
bandwidth so that steady-state spurious specifications are met.
This is designed using the lowest charge pump current setting.
In lowest noise mode and low noise and spur mode (dither off),
the quantization noise from the Σ-Δ modulator appears as frac-
tional spurs. The interval between spurs is FPFD/L, where L is the
repeat length of the code sequence in the digital Σ-Δ modulator.
For the third-order modulator used in the ADF4153A, the repeat
length depends on the value of MOD, as shown in Table 6.
To implement fastlock during a frequency jump, the charge
pump current is set to the maximum setting for the duration of
the jump by asserting the fastlock bit in the N divider register.
This widens the loop bandwidth, which improves lock time. To
maintain loop stability while in wide bandwidth mode, the loop
filter needs to be modified. This is achieved by switching in a
resistor (R1A) in parallel with the damping resistor in the loop
filter (see Figure 21). MUXOUT needs to be set to the fastlock
switch to use the internal switch. For example, if the charge
pump current is increased by 16, the damping resistor, R1,
needs to be decreased by ¼ while in wide bandwidth mode.
Table 6. Fractional Spurs with Dither Off
Repeat
Condition (Dither Off)
If MOD is divisible by 2, but not 3
If MOD is divisible by 3, but not 2
If MOD is divisible by 6
Otherwise
Length
2 × MOD
3 × MOD
6 × MOD
MOD
Spur Interval
Channel step/2
Channel step/3
Channel step/6
Channel step
In low spur mode (dither enabled), the repeat length is
extended to 221 cycles, regardless of the value of MOD, which
makes the quantization error spectrum look like broadband
noise. This can degrade the in-band phase noise at the PLL
output by as much as 10 dB. Therefore, for lowest noise, dither
off is a better choice, particularly when the final loop BW is low
enough to attenuate even the lowest frequency fractional spur.
CP
ADF4153A
MUXOUT
VCO
C2
C1
R1A
FL
R1
Integer Boundary Spurs
Another mechanism for fractional spur creation is interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (which is the
point of a fractional-N synthesizer), spur sidebands appear on
the VCO output spectrum at an offset frequency that corresponds
to the beat note or difference frequency between an integer
multiple of the reference and the VCO frequency.
Figure 21. ADF4153A with Fastlock
The value of R1A is then chosen so that the total parallel
resistance of R1 and R1A equals 1/4 of R1 alone. This gives
an overall 4× increase in loop bandwidth, while maintaining
stability in wide bandwidth mode.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference where the difference frequency can be inside the
loop bandwidth, therefore, the name integer boundary spurs.
Rev. A | Page 18 of 24
Data Sheet
ADF4153A
Reference Spurs
When a new frequency is programmed, the second next sync
pulse after the LE rising edge is used to resynchronize the output
phase to the reference. The tSYNC time should be programmed to
a value that is at least as long as the worst-case lock time. Doing
so guarantees that the phase resync occurs after the last cycle
slip in the PLL settling transient.
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the
loop bandwidth. However, any reference feedthrough mechan-
ism that bypasses the loop can cause a problem. One such
mechanism is feedthrough of low levels of on-chip reference
switching noise out through the RFIN pin back to the VCO,
resulting in reference spur levels as high as –90 dBc. Ensure that
in the PCB layout that the VCO is well separated from the input
reference to avoid a possible feed-through path on the board.
In the example shown in Figure 22, the PFD reference is
25 MHz and MOD = 125 for a 200 kHz channel spacing.
tSYNC is set to 400 µs by programming RESYNC = 10 and
RESYNC_DELAY = 1000.
SPUR CONSISTENCY
LE
tSYNC
When jumping from Frequency A to Frequency B and then
back again using some fractional-N synthesizers, the spur levels
often differ each time Frequency A is programmed. However,
in the ADF4153A, the spur levels on any particular channel are
always consistent.
SYNC
(INTERNAL)
LAST CYCLE SLIP
FREQUENCY
PLL SETTLES TO
INCORRECT PHASE
PHASE RESYNC
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
The output of a fractional-N PLL can settle to any one of MOD
phase offsets with respect to the input reference, where MOD
is the fractional modulus. The phase resync feature in the
ADF4153A can be used to produce a consistent output phase
offset with respect to the input reference. This is necessary
in applications where the output phase and frequency are
important, such as digital beam-forming.
PHASE
–100
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
Figure 22. Phase Resync Example
FILTER DESIGN—ADIsimPLL
When phase resync is enabled, an internal timer generates sync
signals at intervals of tSYNC given by the following formula:
A filter design and analysis program is available to help the user
implement PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL™ software. The software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter
architectures are allowed.
tSYNC = RESYNC × RESYNC_DELAY × tPFD
where tPFD is the PFD reference period.
RESYNC is the decimal value programmed in Bits DB[15…12]
of Register R2 and can be any integer in the range of 1 to 15. If
RESYNC is programmed to its default value of all zeros, then
the phase resync feature is disabled.
INTERFACING
The ADF4153A has a simple SPI®-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) is high, the 22 bits that are
clocked into the input register on each rising edge of SCLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the register truth table.
If phase resync is enabled, then RESYNC_DELAY must be
programmed to a value that is an integer multiple of the value
of MOD. RESYNC_DELAY is the decimal value programmed
into the MOD bits (DB[13…2] of Register R1 when load
control (Bit DB23 of Register R1) = 1.
The maximum allowable serial clock rate is 20 MHz.
Rev. A | Page 19 of 24
ADF4153A
Data Sheet
ADuC812 Interface
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
Figure 23 shows the interface between the ADF4153A and the
ADuC812 MicroConverter®. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4153A needs a
24-bit word, which is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. After the third byte is
written, the LE input should be brought high to complete the
transfer.
ADSP-21xx
ADF4153A
SCLK
CLK
DT
DATA
LE
TFS
MUXOUT
(LOCK DETECT)
I/O FLAGS
ADuC812
ADF4153A
Figure 24. ADSP-21xx to ADF4153A Interface
CLK
SCLOCK
DATA
LE
MOSI
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
I/O PORTS
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized.
MUXOUT
(LOCK DETECT)
Figure 23. ADuC812 to ADF4153A Interface
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
When operating in this mode, the maximum SCLOCK rate of
the ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 180 kHz.
ADSP-21xx Interface
Figure 24 shows the interface between the ADF4153A and the
ADSP-21xx digital signal processor. As discussed previously,
the ADF4153A needs a 24-bit serial word for each latch write.
The easiest way to accomplish this using the ADSP-21xx family
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with one ounce of copper to plug the
via. The user should connect the PDB thermal pad to AGND.
Rev. A | Page 20 of 24
Data Sheet
ADF4153A
APPLICATIONS INFORMATION
LOCAL OSCILLATOR FOR A GSM BASE STATION
TRANSMITTER
The charge pump current is ICP = 5 mA. ADIsimPLL is used to
calculate the loop filter. It is designed for a loop bandwidth of
20 kHz and a phase margin of 45 degrees.
Figure 25 shows the ADF4153A being used with a VCO to
produce the local oscillator (LO) for a GSM base station
transmitter.
The loop filter output drives the VCO, which in turn is fed back
to the RF input of the PLL synthesizer. It also drives the RF output
terminal. A T-circuit configuration provides 50 Ω matching
between the VCO output, the RF output, and the RFIN terminal
of the synthesizer.
The reference input signal is applied to the circuit at REFIN and,
in this case, is terminated in 50 Ω. A 25 MHz reference is used,
which is fed directly to the PFD. To achieve 200 kHz channel
spacing, a modulus of 125 is necessary. Note that with a modulus
of 125, which is not divisible by 2, 3, or 6, subfractional spurs are
avoided. See the Spur Mechanisms section for more information.
In a PLL system, it is important to know when the loop is in
lock. This is achieved by using the MUXOUT signal from the
synthesizer. The MUXOUT pin can be programmed to monitor
various internal signals in the synthesizer. One of these is the
lock detect signal.
The charge pump output of the ADF4153A drives the loop
filter.
V
V
DD
P
10pF
100nF
10µF
100nF
6
100nF
10µF
RF
OUT
100pF
7
16 17
18
14
V
P
18Ω
V
CC
100pF
18Ω
10
160Ω
20
2
11
CP
SV
VCO190-902T
DD
18Ω
1000pF
1000pF
8.2nF
8
22nF
82Ω
270nF
REF
FREF
IN
IN
51Ω
ADF4153A
15
LOCK
DETECT
MUXOUT
CLK
DATA
LE
100pF
5
4
RF
A
IN
R
SET
51Ω
4.7kΩ
RF
B
IN
100pF
1
2
3
9
10
DECOUPLING CAPACITORS SHOULD BE PLACED
AS CLOSE AS POSSIBLE TO THE PINS.
Figure 25. Local Oscillator for a GSM Base Station Transmitter
Rev. A | Page 21 of 24
ADF4153A
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeter
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
5
6
10
0.65
0.60
0.55
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 27. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-20-6
CP-20-6
RU-16
RU-16
ADF4153ABCPZ
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP
Evaluation board for ADF4153A in LFCSP package
ADF4153ABCPZ-RL7
ADF4153ABRUZ
ADF4153ABRUZ-RL7
EV-ADF4153ASD1Z
1 Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
Data Sheet
NOTES
ADF4153A
Rev. A | Page 23 of 24
ADF4153A
NOTES
Data Sheet
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11047-0-1/13(A)
Rev. A | Page 24 of 24
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