ADF4211BRU_技术文档

a

Dual RF/IF PLL Frequency Synthesizers

ADF4210/ADF4211/ADF4212/ADF4213

GENERAL DESCRIPTION

FEATURES

The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency

synthesizer that can be used to implement local oscillators (LO)

in the upconversion and downconversion sections of wireless

receivers and transmitters. They can provide the LO for both

the RF and IF sections. They consist of a low-noise digital PFD

(Phase Frequency Detector), a precision charge pump, a pro-

grammable reference divider, programmable A and B Counters

and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B

(12-bit) counters, in conjunction with the dual modulus prescaler

(P/P + 1), implement an N divider (N = BP + A). In addition,

the 14-bit reference counter (R Counter), allows selectable

REFIN frequencies at the PFD input. A complete PLL (Phase-

Locked Loop) can be implemented if the synthesizer is used with

an external loop ﬁlter and VCO (Voltage Controlled Oscillators).

ADF4210: 550 MHz/1.2 GHz

ADF4211: 550 MHz/2.0 GHz

ADF4212: 1.0 GHz/2.7 GHz

ADF4213: 1.0 GHz/3 GHz

2.7 V to 5.5 V Power Supply

Separate Charge Pump Supply (V_P) Allows Extended

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65

Programmable Charge Pump Currents

3-Wire Serial Interface

Analog and Digital Lock Detect

Fastlock Mode

Power-Down Mode

Control of all the on-chip registers is via a simple 3-wire interface.

The devices operate with a power supply ranging from 2.7 V to

5 V and can be powered down when not in use.

APPLICATIONS

Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANS

Communications Test Equipment

CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

V

1

V

2

V 1

V 2

R

SET

DD

P

12-BIT IF

B-COUNTER

REFERENCE

PHASE

COMPARATOR

IF

IN

IF

PRESCALER

CHARGE

PUMP

CP

IF

8-BIT IF

A-COUNTER

IF CURRENT

SETTING

IF

LOCK

DETECT

IFCP3 IFCP2 IFCP1

OSCILLATOR

REF

IN

14-BIT IF

R-COUNTER

OUTPUT

MUX

MUXOUT

CLOCK

DATA

LE

24-BIT

DATA

REGISTER

SDOUT

RFCP3 RFCP2 RFCP1

14-BIT RF

R-COUNTER

RF

LOCK

IF CURRENT

SETTING

DETECT

12-BIT RF

B-COUNTER

CHARGE

PUMP

CP

FL

RF

IN

RF

PRESCALER

PHASE

COMPARATOR

REFERENCE

6-BIT RF

A-COUNTER

R

ADF4210/ADF4211/

ADF4212/ADF4213

SET

FL SWITCH

O

DGND

RF

AGND

RF

DGND

IF

DGND

IF

AGND

IF

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS¹

(V_DD1 = V_DD2 = 3 V ꢀ 10%, 5 V ꢀ 10%; V_DD1, V_DD2 ≤ V_P1, V_P2 ≤ 6.0 V; AGND_RF= DGND_RF= AGND_IF= DGND_IF= 0 V; R_SET= 2.7 kꢁ dBm to 50 ꢁ;

T_A= T_MINto T_MAXunless otherwise noted.)

P

arameter

B Version

B Chips²

Unit

Test Conditions/Comments

RF/IF CHARACTERISTICS (3 V)

RF Input Frequency (RF_IN

)

See Figure 3 for Input Circuit.

ADF4210

ADF4211

ADF4212

ADF4213

0.1/1.2

0.1/2.0

0.15/2.7

0.2/3.0

–10/0

0.1/1.2

0.1/2.0

0.15/2.7

0.2/3.0

–10/0

GHz min/max Use a square wave for frequencies lower than F_MIN.

GHz min/max

dBm min/max

RF Input Sensitivity

IF Input Frequency (IF_IN

ADF4210

ADF4211

ADF4212

ADF4213

)

60/550

0.06/1.0

–10/0

60/550

0.06/1.0

–10/0

MHz min/max

GHz min/max

dBm min/max

IF Input Sensitivity

Maximum Allowable

Prescaler Output Frequency³

165

MHz max

RF/IF CHARACTERISTICS (5 V)

RF Input Frequency (RF_IN

)

See Figure 3 for Input Circuit.

ADF4210

ADF4211

ADF4212

ADF4213

0.18/1.2

0.18/2.0

0.2/2.3

0.2/2.5

–5/0

0.18/1.2

0.18/2.0

0.2/2.3

0.2/2.5

–5/0

GHz min/max Use a square wave for frequencies lower than F_MIN.

GHz min/max

dBm min/max

RF Input Sensitivity

IF Input Frequency (IF_IN

ADF4210

ADF4211

ADF4212

ADF4213

)

100/550

0.1/1.0

–5/0

100/550

0.1/1.0

–5/0

MHz min/max

GHz min/max

dBm min/max

IF Input Sensitivity

Maximum Allowable

Prescaler Output Frequency³

200

MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency

See Figure 2 for Input Circuit.

MHz min/max For F < 5 MHz, use dc-coupled square wave

0/115

–5/0

0/115

–5/0

(0 to V_DD).

REFIN Input Sensitivity⁴

dBm min/max AC-Coupled. When dc-coupled, 0 to V_DDmax

(CMOS-Compatible)

REFIN Input Capacitance

REFIN Input Current

10

100

10

100

pF max

µA max

PHASE DETECTOR

Phase Detector Frequency⁵

55

MHz max

CHARGE PUMP

I_CPSink/Source

High Value

Programmable: See Table V

With R_SET= 2.7 kΩ

5

625

3

5

625

3

mA typ

µA typ

% typ

kΩ, min/max

nA typ

% typ

Low Value

Absolute Accuracy

With R_SET= 2.7 kΩ

R

_SETRange

1.5/5.6

I_CPThree-State Leakage Current

Sink and Source Current Matching

I_CPvs. V_CP

1

2

1

2

0.5 V Յ V_CPՅ V_P– 0.5 V

V_CP= V_P/2

% typ

I_CPvs. Temperature

LOGIC INPUTS

V_INH, Input High Voltage

V_INL, Input Low Voltage

0.8 × DV_DD

0.2 × DV_DD

1

0.8 × DV_DD

0.2 × DV_DD

1

V min

V max

µA max

pF max

I

_INH/I_INL, Input Current

C_IN, Input Capacitance

10

LOGIC OUTPUTS

V

_OH, Output High Voltage

DV_DD– 0.4

0.4

DV_DD– 0.4

0.4

V min

V max

I_OH= 500 µA

I_OL= 500 µA

V_OL, Output Low Voltage

–2–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Parameter

B Version B Chips²Unit

Test Conditions/Comments

POWER SUPPLIES

V

V_DD

V_P

_DD1

2

2.7/5.5

V_DD

V_DD1/6.0

2.7/5.5

V_DD

V_DD1/6.0

V min/V max

V min/V max V_DD1, V_DD2 Յ V_DD1, V_DD2 Յ 6.0 V

1

I

_DD(RF + IF)⁶

ADF4210

ADF4211

ADF4212

ADF4213

_DD(RF Only)

ADF4210

ADF4211

ADF4212

ADF4213

_DD(IF Only)

ADF4210

ADF4211

ADF4212

ADF4213

11.5

15.0

17.5

20

11.5

15.0

17.5

20

mA max

9.0 mA typical

11.0 mA typical

13.0 mA typical

15 mA typical

6.75

10

12.5

15

6.75

10

12.5

15

mA max

5.0 mA typical

7.0 mA typical

9.0 mA typical

11 mA typical

5.5

1.0

1

5.5

1.0

1

mA max

µA typ

4.5 mA typical

I_P(I_P1 + I_P2)

Low-Power Sleep Mode

T_A= 25°C, 0.55 mA typical

NOISE CHARACTERISTICS

ADF4213 Phase Noise Floor⁷

–171

–164

–171

–164

dBc/Hz typ

@ 25 kHz PFD Frequency

@ 200 kHz PFD Frequency

@ VCO Output

Phase Noise Performance⁸

ADF4210/ADF4211, IF: 540 MHz Output⁹

ADF4212/ADF4213, IF: 900 MHz Output¹⁰

ADF4210/ADF4211, RF: 900 MHz Output¹⁰

ADF4212/ADF4213, RF: 900 MHz Output¹⁰

–91

–89

–91

–89

–91

–85

–67

–88

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

See Note 11

ADF4211/ADF4212, RF: 1750 MHz Output¹²–85

ADF4211/ADF4212, RF: 1750 MHz Output¹³–67

ADF4212/ADF4213, RF: 2400 MHz Output¹⁴–88

Spurious Signals

@ 200 Hz Offset and 10 kHz PFD Frequency

@ 1 kHz Offset and 1 MHz PFD Frequency

ADF4210/ADF4211, IF: 540 MHz Output⁹

ADF4212/ADF4213, IF: 900 MHz Output¹⁰

ADF4210/ADF4211, RF: 900 MHz Output¹⁰

ADF4212/ADF4213, RF: 900 MHz Output¹⁰

–88/–90

–90/–94

–80/–82

–65/–70

–80/–82

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

See Note 11

–90/–94

ADF4211/ADF4212, RF: 1750 MHz Output¹²–80/–82

ADF4211/ADF4212, RF: 1750 MHz Output¹³–65/–70

ADF4212/ADF4213, RF: 2400 MHz Output¹⁴–80/–82

See Note 11

@ 10 kHz/20 kHz and 10 kHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

¹Operating temperature range is as follows: B Version: –40°C to +85°C.

²The B Chip speciﬁcations are given as typical values.

³This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is

less than this value.

⁴V_DD1 = V_DD2 = 3 V; For V_DD1 = V_DD2 = 5 V, use CMOS-compatible levels, T_A= 25°C.

⁵Guaranteed by design. Sample tested to ensure compliance.

⁶V_DD= 3 V; P = 16; RF_IN= 900 MHz; IF_IN= 540 MHz, T_A= 25°C.

⁷The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See

TPC 16.

⁸The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the

REFIN for the synthesizer (f_REFOUT= 10 MHz @ 0 dBm).

⁹f_REFIN= 10 MHz; f_PFD= 200 kHz; Offset frequency = 1 kHz; f_IF= 540 MHz; N = 2700; Loop B/W = 20 kHz.

10

f

= 10 MHz; f_PFD= 200 kHz; Offset frequency = 1 kHz; f_RF= 900 MHz; N = 4500; Loop B/W = 20 kHz.

REFIN

¹¹Same conditions as listed in Note 10.

12

f

= 10 MHz; f_PFD= 200 kHz; Offset frequency = 1 kHz; f_RF= 1750 MHz; N = 8750; Loop B/W = 20 kHz.

= 10 MHz; f_PFD= 10 kHz; Offset frequency = 200 Hz; f_RF= 1750 MHz; N = 175000; Loop B/W = 1 kHz.

= 10 MHz; f_PFD= 1 MHz; Offset frequency = 1 kHz; f_RF= 1960 MHz; N = 9800; Loop B/W = 20 kHz.

REFIN

13

14

Speciﬁcations subject to change without notice.

–3–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

(V_DD1 = V_DD2 = 3 V ꢀ 10%, 5 V ꢀ 10%; V_DD1, V_DD2 ≤ V_P1, V_P2 ≤ 6 V ꢀ 10%; AGND_RF= DGND_RF

= AGND_IF= DGND_IF= 0 V; T_A= T_MINto T_MAXunless otherwise noted.)

TIMING CHARACTERISTICS

Limit at

T_MINto T_MAX

(B Version)

Parameter

Unit

Test Conditions/Comments

t₁

t₂

t₃

t₄

t₅

t₆

10

25

10

20

ns min

DATA to CLOCK Set-Up Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Set-Up Time

LE Pulsewidth

NOTES

Guaranteed by design but not production tested.

Speciﬁcations subject to change without notice.

t₃

t₄

CLOCK

t₁

t₂

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB20

DB19

DB2

DATA

(MSB)

(CONTROL BIT C2)

t₆

LE

t₅

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS^{1, 2}

(T_A= 25°C unless otherwise noted)

CSP θ_JA(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W

Lead Temperature, Soldering

V_DD1 to GND³. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V_DD1 to V_DD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

V_P1, V_P2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

V_P1, V_P2 to V_DD

1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Digital I/O Voltage to GND . . . . . . –0.3 V to DV_DD+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V_P+ 0.3 V

REF_IN, RF_INA, RF_INB,

IF_INA, IF_INB to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Operating Temperature Range

²This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ_JAThermal Impedance . . . . . . . . . . . . . 150.4°C/W

CSP θ_JA(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W

and assembly.

³GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

11749 (CMOS) and 522 (Bipolar).

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, per-

manent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,

proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option*

ADF4210BRU

ADF4210BCP

ADF4211BRU

ADF4211BCP

ADF4212BRU

ADF4212BCP

ADF4213BRU

ADF4213BCP

–40°C to +85°C

Thin Shrink Small Outline Package (TSSOP)

Chip Scale Package

Thin Shrink Small Outline Package (TSSOP)

Chip Scale Package

Thin Shrink Small Outline Package (TSSOP)

Chip Scale Package

RU-20

CP-20

RU-20

CP-20

RU-20

CP-20

RU-20

CP-20

Thin Shrink Small Outline Package (TSSOP)

Chip Scale Package

*Contact the factory for chip availability.

–4–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

PIN FUNCTION DESCRIPTIONS

Pin Number

TSSOP

Mnemonic

_DD1

Function

1

V

Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as

close as possible to this pin. V_DD1 should have a value of between 2.7 V and 5.5 V. V_DD1 must have

the same potential as V_DD2.

2

3

V_P1

Power Supply for the RF Charge Pump. This should be greater than or equal to V_DD1. In systems where

V

_DD1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

CP_RF

Output from the RF Charge Pump. This is normally connected to a loop ﬁlter which drives the input

to an external VCO.

4

5

6

7

8

DGND_RF

RF_IN

AGND_RF

FL_O

Ground Pin for the RF Digital Circuitry.

Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.

Ground Pin for the RF Analog Circuitry.

RF/IF Fastlock Mode.

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input

resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.

9

DGND_IF

Digital Ground for the IF Digital, Interface and Control Circuitry.

10

MUXOUT

This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled

Reference Frequency to be accessed externally.

11

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance

CMOS input.

12

13

14

DATA

LE

Serial Data Input. The serial data is loaded MSB ﬁrst with the two LSBs being the control bits. This

input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

one of the four latches, the latch being selected using the control bits.

R_SET

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output

current. The nominal voltage potential at the R_SETpin is 0.66 V. The relationship between I_CPand R_SETis

13.5

I_{CP MAX}

=

R_SET

So, with R_SET= 2.7 kΩ, I_{CP MAX}= 5 mA for both the RF and IF Charge Pumps.

15

16

17

18

AGND_IF

IF_IN

DGND_IF

CP_IF

Ground Pin for the IF Analog Circuitry.

Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.

Ground Pin for the IF Digital, Interface, and Control Circuitry.

Output from the IF Charge Pump. This is normally connected to a loop ﬁlter which drives the input

to an external VCO.

19

20

V_P2

Power Supply for the IF Charge Pump. This should be greater than or equal to V_DD2. In systems where

V_DD2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should

V_DD

2

be placed as close as possible to this pin. V_DD2 should have a value of between 2.7 V and 5.5 V. V_DD

2

must have the same potential as V_DD1.

PIN CONFIGURATIONS

CP-20

TSSOP

20

19

18

17

16

15

14

13

12

11

V

2

V

1

2

DD

20 19 18 17 16

V 1

V 2

P

ADF4210/

ADF4211/

ADF4212/

ADF4213

CP

3

RF

CP

IF

1

2

3

4

5

15

14

13

12

11

RF

DGND

ADF4210/

ADF4211/

ADF4212/

ADF4213

TOP VIEW

(Not to Scale)

IF

DGND

4

IF

IN

RF

IF

RF

IN

AGND

RF

IF

5

IF

IN

AGND

RF

R

SET

TOP VIEW

(Not to Scale)

AGND

6

RF

IF

FL

O

LE

R

7

FL

SET

O

LE

REF

8

6

7

8

9

10

IN

DGND

IF

DATA

CLK

9

10

MUXOUT

–5–

REV. A

–Typical Performance Characteristics

ADF4210/ADF4211/ADF4212/ADF4213

0

FREQUENCY

S

REAL

S

IMAG FREQUENCY

S

REAL

S

IMAG

11

V

= 3V

DD

= 3V

–5

P

50000000.0 0.955683 –0.052267 2150000000.0

150000000.0 0.956993 –0.112191 2250000000.0

250000000.0 0.935463 –0.185212 2350000000.0

350000000.0 0.919706 –0.252576 2450000000.0

0.138086 –0.699896

0.102483 –0.704160

0.054916 –0.696325

0.018475 –0.669617

–10

–15

450000000.0 0.871631 –0.323799 2550000000.0 –0.019935 –0.668056

550000000.0 0.838141 –0.350455 2650000000.0 –0.054445 –0.666995

650000000.0 0.799005 –0.408344 2750000000.0 –0.083716 –0.634725

750000000.0 0.749065 –0.455840 2850000000.0 –0.129543 –0.615246

850000000.0 0.706770 –0.471011 2950000000.0 –0.154974 –0.610398

950000000.0 0.671007 –0.535268

T

= +85ꢂC

A

T

= +25ꢂC

A

1050000000.0 0.630673 –0.557699

–20

1150000000.0 0.584013 –0.604256

T

= –40ꢂC

A

1250000000.0 0.537311 –0.622297

1350000000.0 0.505090 –0.642019

1450000000.0 0.459446 –0.686409

–25

–30

1550000000.0 0.381234 –0.693908

1650000000.0 0.363150 –0.679602

1750000000.0 0.330545 –0.721812

1850000000.0 0.264232 –0.697386

1950000000.0 0.242065 –0.711716

2050000000.0 0.181238 –0.723232

–35

0

1

2

3

RF INPUT FREQUENCY – GHz

TPC 4. Input Sensitivity (ADF4213)

TPC 1. S-Parameter Data for the ADF4213 RF Input

(Up to 3.0 GHz)

10dB/DIVISION

R

= –40dBc/Hz

RMS NOISE = 0.5421ꢂ

0.54ꢂ rms

L

–40

0

V

= 3V, V = 5V

P

REFERENCE

LEVEL = –5.2dBm

DD

= 5mA

–50

–60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

–70

–80

–90

–100

–110

–120

–130

–91.2dBc/Hz

–140

–2kHz

–1kHz

900MHz

+1kHz

+2kHz

100Hz

1kHz

10kHz

100kHz

1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

TPC 5. ADF4213 Integrated Phase Noise (900 MHz, 200 kHz,

TPC 2. ADF4213 Phase Noise (900 MHz, 200 kHz, 20 kHz)

20 kHz, Typical Lock Time: 400 µs)

10dB/DIVISION

R

= –40dBc/Hz

RMS NOISE = 0.6522ꢂ

0.65ꢂ rms

L

0

–40

V

= 3V, V = 5V

P

REFERENCE

LEVEL = –5.7dBm

DD

= 5mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–50

–60

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 4.2 SECONDS

AVERAGES = 20

–70

–80

–90

–100

–110

–120

–130

–91.0dBc/Hz

–140

900MHz

–400kHz

–200kHz

200kHz

400kHz

100Hz

1kHz

10kHz

100kHz

1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

TPC 3. ADF4213 Integrated Phase Noise (900 MHz,

TPC 6. ADF4213 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

200 kHz, 35 kHz, Typical Lock Time: 200 µs)

–6–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

V

= 3V, V = 5V

V

= 3V, V = 5V

P

DD

P

DD

I = 5mA

CP

REFERENCE

LEVEL = –8.0dBm

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LEVEL = –5.7dBm

I

= 5mA

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 4.2 SECONDS

AVERAGES = 25

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

AVERAGES = 10

–90.5dBc/Hz

–75.2dBc/Hz

–400kHz

–200kHz

900MHz

+200kHz

+400kHz

–400Hz

–200Hz

1750MHz

+200Hz

+400Hz

TPC 7. ADF4213 Reference Spurs (900 MHz,

200 kHz, 35 kHz)

TPC 10. ADF4213 Phase Noise (1750 MHz, 30 kHz, 3 kHz)

10dB/DIVISION

R

= –40dBc/Hz

RMS NOISE = 1.6ꢂ

L

–40

0

V

I

= 3V, V = 5V

P

DD

REFERENCE

LEVEL = –5.7dBm

–50

–60

–10

–20

–30

–40

–50

–60

–70

= 5mA

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 3Hz

VIDEO BANDWIDTH = 3Hz

SWEEP = 255 SECONDS

POSITIVE PEAK DETECT

MODE

–70

1.6ꢂ rms

–80

–90

–100

–110

–120

–130

–79.6dBc

–80

–90

–140

100Hz

–100

FREQUENCY OFFSET FROM 1750MHz CARRIER

1MHz

–80kHz

–40kHz

1750MHz

+40kHz

+80kHz

TPC 8. ADF4213 Integrated Phase Noise (1750 MHz,

30 kHz, 3 kHz)

TPC 11. ADF4213 Reference Spurs (1750 MHz,

30 kHz, 3 kHz)

10dB/DIVISION

R

= –40dBc/Hz

RMS NOISE = 1.7ꢂ

L

0

–40

V

= 3V, V = 5V

P

DD

REFERENCE

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–50

–60

LEVEL = –4.2dBm

I

= 5mA

CP

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 45

1.7ꢂ rms

–70

–80

–90

–100

–110

–120

–130

–86.6dBc/Hz

–140

100Hz

–2kHz

–1kHz

3100MHz

+1kHz

+2kHz

FREQUENCY OFFSET FROM 3100MHz CARRIER

1MHz

TPC 9. ADF4213 Phase Noise (2800 MHz, 1 MHz, 100 kHz)

TPC 12. ADF4213 Integrated Phase Noise (2800 MHz,

1 MHz, 100 kHz)

–7–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–120

–130

–140

–150

–160

–170

–180

0

V

= 3V

= 5V

V

I

= 3V, V = 5V

P

DD

= 5mA

REFERENCE

P

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LEVEL = –17.2dBm

CP

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 13 SECONDS

AVERAGES = 1

–80.6dBc

1

10

100

1000

10000

–2MHz

–1MHz

3100MHz

+1MHz

+2MHz

PHASE DETECTOR FREQUENCY – kHz

TPC 13. ADF4213 Reference Spurs (2800 MHz, 1 MHz,

100 kHz)

TPC 16. ADF4213 Phase Noise (Referred to CP Output)

vs. PFD Frequency

–60

V

= 3V

V

= 3V

= 5V

DD

P

–70

–80

–70

–80

–90

–100

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE – ꢂC

TPC 14. ADF4213 Phase Noise vs. Temperature (900 MHz,

200 kHz, 20 kHz)

TPC 17. ADF4213 Reference Spurs vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

–5

–60

–15

V

= 3V

DD

= 5V

V

= 3V

= 5V

DD

P

–25

–35

–70

–80

–45

–55

–65

–75

–85

–95

–105

–90

–100

0

1

2

3

4

5

–40

–20

0

20

40

60

80

100

TUNING VOLTAGE – Volts

TEMPERATURE – ꢂC

TPC 15. ADF4213 Reference Spurs (200 kHz) vs. V _TUNE

(900 MHz, 200 kHz, 20 kHz)

TPC 18. ADF4213 Phase Noise vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

–8–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–60

–70

PRESCALER (P/P + 1)

The dual modulus prescaler (P/P + 1), along with the A and

B counters, enables the large division ratio, N, to be realized

(N = PB + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF/IF input stage and divides

it down to a manageable frequency for the CMOS A and B

counters in the RF and If sections. The prescaler in both

sections is programmable. It can be set in software to 8/9, 16/17,

32/33, or 64/65. See Tables IV and VI. It is based on a syn-

chronous 4/5 core.

V

= 3V

= 5V

DD

P

–80

–90

RF/IF A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are speciﬁed to work when the

prescaler output is 200 MHz or less, when V_DD= 5 V. Typically,

they will work with 250 MHz output from the prescaler. Thus,

with an RF input frequency of 2.5 GHz, a prescaler value of

16/17 is valid, but a value of 8/9 is not valid.

–100

–40

–20

0

20

40

60

80

100

TEMPERATURE – ꢂC

TPC 19. ADF4213 Reference Spurs vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

Pulse Swallow Function

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown below in Figure 2. SW1 and

SW2 are normally-closed switches. SW3 is normally-open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

The A and B counters, in conjunction with the dual modulus

prescaler make it possible to generate output frequencies which

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

f

_VCO= [(P × B) + A] × f_REFIN/R

f_VCO= Output Frequency of external voltage controlled

oscillator (VCO).

POWER-DOWN

CONTROL

P

= Preset modulus of dual modulus prescaler (8/9,

16/17, etc.).

100kꢁ

SW2

NC

B

A

= Preset Divide Ratio of binary 13-bit counter

(3 to 8191).

TO R COUNTER

REF

IN

NC

SW1

BUFFER

= Preset Divide Ratio of binary 6-bit A counter

(0 to 63).

SW3

NO

NC = NO CONNECT

f_REFIN= External reference frequency oscillator.

Figure 2. Reference Input Stage

RF/IF INPUT STAGE

R

= Preset divide ratio of binary 15-bit programmable refer-

ence counter (1 to 32767).

The RF/IF input stage is shown in Figure 3. It is followed by a

2-stage limiting ampliﬁer to generate the CML (Current Mode

Logic) clock levels needed for the prescaler.

N = BP + A

TO PFD

13-BIT B-

COUNTER

LOAD

FROM RF

INPUT STAGE

PRESCALER

P/P + 1

1.6V

BIAS

GENERATOR

LOAD

5-BIT A-

AV

DD

MODULUS

CONTROL

COUNTER

2kꢁ

RF

A

B

IN

Figure 4. RF/IF A and B Counters

RF/IF COUNTER

IN

The 15-bit RF/IF R counter allows the input reference fre-

quency to be divided down to product the input clock to the

phase frequency detector (PFD). Division ratios from 1 to

32767 are allowed.

AGND

Figure 3. RF/IF Input Stage

–9–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE

PUMP

Lock Detect

MUXOUT can be programmed for two types of lock detect:

Digital Lock Detect and Analog Lock Detect. Digital Lock

Detect is active high. It is set high when the phase error on three

consecutive Phase Detector cycles is less than 15 ns. It will stay

set high until a phase error of greater than 25 ns is detected on

any subsequent PD cycle. The N-channel open-drain analog

lock detect should be operated with an external pull-up resistor

of 10 kΩ nominal. When lock has been detected, it is high with

narrow low-going pulses.

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 5 is a simpliﬁed schematic.

The PFD includes a ﬁxed-delay element that sets the width of

the antibacklash pulse. This is typically 3 ns. This pulse ensures

that there is no deadzone in the PFD transfer function and gives

a consistent reference spur level.

V

P

CHARGE

PUMP

RF/IF INPUT SHIFT REGISTER

UP

The ADF421x family digital section includes a 24-bit input shift

register, a 14-bit IF R counter and a 18-bit IF N counter, com-

prising a 6-bit IF A counter and a 12-bit IF B counter. Also

present is a 14-bit RF R counter and an 18-bit RF N counter,

comprising a 6-bit RF A counter and a 12-bit RF B counter.

Data is clocked into the 24-bit shift register on each rising edge

of CLK. The data is clocked in MSB ﬁrst. Data is transferred

from the shift register to one of four latches on the rising edge of

LE. The destination latch is determined by the state of the two

control bits (C2, C1) in the shift register. These are the two LSBs

DB1, DB0 as shown in the timing diagram of Figure 1. The

truth table for these bits is shown in Table VI. Table I shows a

summary of how the latches are programmed.

HI

D1

Q1

U1

R DIVIDER

CLR1

CP

DELAY

U3

CLR2

U2

DOWN

HI

D2

Q2

Table I. C2, C1 Truth Table

Control Bits

N DIVIDER

CPGND

R DIVIDER

N DIVIDER

C2

C1

Data Latch

0

1

0

1

0

1

IF R Counter

IF AB Counter (A and B)

RF R Counter

RF AB Counter (A and B)

CP OUTPUT

Figure 5. RF/IF PFD Simpliﬁed Schematic and Timing

(In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF421x family allows the

user to access various internal points on the chip. The state of

MUXOUT is controlled by P3, P4, P11, and P12. See Tables

III and V. Figure 6 shows the MUXOUT section in block dia-

gram form.

DV

DD

IF ANALOG LOCK DETECT

IF R COUNTER OUTPUT

IF N COUNTER OUTPUT

IF/RF ANALOG LOCK DETECT

RF R COUNTER OUTPUT

RF N COUNTER OUTPUT

RF ANALOG LOCK DETECT

DIGITAL LOCK DETECT

MUXOUT

MUX

CONTROL

DGND

Figure 6. MUXOUT Circuit

–10–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table II. ADF421x Family Latch Summary

IF R COUNTER LATCH

CONTROL

BITS

IF CP CURRENT

SETTING

15-BIT REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6 DB5 DB4 DB3 DB2

R5 R4 R3 R2 R1

DB1

DB0

IF

CP1

IF

CP0

R15

P4

P3

P2

P1

R14

R13

R12

R11

R10

R9

R8

C2 (0) C1 (0)

CP2

IF N COUNTER LATCH

IF

PRESCALER

CONTROL

BITS

6-BIT A COUNTER

12-BIT B COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

P8 P7 P6 P5 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2

DB8

B1

DB7

A6

DB6 DB5 DB4 DB3 DB2

A5 A4 A3 A2 A1

DB1

DB0

C2 (0)

C1 (1)

RF R COUNTER LATCH

CONTROL

BITS

RF CP CURRENT

SETTING

15-BIT REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6 DB5 DB4 DB3 DB2

R5 R4 R3 R2 R1

DB1

DB0

RF

CP1

RF

CP0

R15

P12 P11

P10

P9

R14

R13

R12

R11

R10

R9

R8

C2 (1) C1 (0)

CP2

RF N COUNTER LATCH

RF

PRESCALER

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

B1

DB7

A6

DB6 DB5 DB4 DB3 DB2

A5 A4 A3 A2 A1

DB1

DB0

P17

P16

P15

P14 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

C2 (1) C1 (1)

–11–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table III. IF R Counter Latch Map

IF R COUNTER LATCH

CONTROL

BITS

IF CP CURRENT

SETTING

15-BIT REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6 DB5 DB4 DB3 DB2

R5 R4 R3 R2 R1

DB1

DB0

IF

P4

P3

P2

P1

R14

R13

R12

R11

R10

R9

R8

C2 (0) C1 (0)

R15

CP2

CP1 CP0

R15

R14

R13

..........

R3

R2

0

1

0

.

0

R1

DIVIDE RATIO

1

2

3

4

.

0

.

1

0

.

1

0

.

1

0

1

.

1

0

1

0

.

0

32764

1

..........

1

0

1

0

1

32765

32766

32767

P1

IF PD POLARITY

0

1

NEGATIVE

POSITIVE

P2

CHARGE PUMP OUTPUT

0

1

NORMAL

THREE-STATE

P12

P11

FROM RF R LATCH

P4

P3

MUXOUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOGIC LOW STATE

IF ANALOG LOCK DETECT

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

IF DIGITAL LOCK DETECT

LOGIC HIGH STATE

RF REFERENCE DIVIDER OUTPUT

RF N DIVIDER OUTPUT

THREE-STATE OUTPUT

IF COUNTER RESET

RF DIGITAL LOCK DETECT

RF/IF DIGITAL LOCK DETECT

RF COUNTER RESET

IF AND RF COUNTER RESET

I

(mA)

CP

IF CP2

IF CP1

IF CP0

1.5kꢁ

1.088

2.176

3.264

4.352

5.44

6.528

7.616

8.704

2.7kꢁ

0.625

1.25

1.875

2.5

3.125

3.75

4.375

5.0

5.6kꢁ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.294

0.588

0.882

1.176

1.47

1.764

2.058

2.352

–12–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table IV. IF N Counter Latch Map

IF N COUNTER LATCH

IF

CONTROL

BITS

6-BIT A COUNTER

12-BIT B COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

B1

DB7

A6

DB6 DB5 DB4 DB3 DB2

DB1

C2 (0)

DB0

P8

P7

P6

P5

B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

A5

A4

A3

A2

A1

C1 (1)

A COUNTER

DIVIDE RATIO

P6

P5

IF PRESCALER

A6

A5

..........

A2

A1

0

1

0

1

0

1

8/9

0

.

0

.

..........

0

1

0

.

1

0

1

0

.

1

16/17

32/33

64/65

2

3

4

.

1

0

1

0

1

0

1

60

61

62

63

P7

IF POWER-DOWN

0

1

DISABLE

ENABLE

B12

0

B11

0

B10

0

B3

0

B2

1

B1

1

B COUNTER DIVIDE RATIO

3

..........

0

.

1

0

.

1

0

.

1

..........

1

.

1

0

.

0

.

0

4

.

4092

1

..........

1

0

1

0

1

4093

4094

4095

P8

IF CP GAIN

0

1

DISABLE

ENABLE

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.

B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS

2

VALUES OF N ꢃ F

, N

is (P – P).

REF

MIN

–13–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table V. RF R Latch Map

RF R COUNTER LATCH

CONTROL

BITS

RF CP CURRENT

SETTING

15-BIT REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6 DB5 DB4 DB3 DB2

R5 R4 R3 R2 R1

DB1

DB0

RF

R15

P12 P11

P10

P9

R14

R13

R12

R11

R10

R9

R8

C2 (1) C1 (0)

CP2

CP1 CP0

R15

R14

R13

..........

R3

R2

0

1

0

.

0

R1

DIVIDE RATIO

1

2

3

4

.

0

.

1

0

.

1

0

.

1

..........

0

1

.

1

0

1

0

.

0

32764

1

..........

1

0

1

0

1

32765

32766

32767

P9

RF PD POLARITY

0

1

NEGATIVE

POSITIVE

P10

CHARGE PUMP OUTPUT

0

1

NORMAL

THREE-STATE

FROM IF R LATCH

P11

P4

P3

MUXOUT

LOGIC LOW STATE

IF ANALOG LOCK DETECT

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

IF DIGITAL LOCK DETECT

LOGIC HIGH STATE

RF REFERENCE DIVIDER OUTPUT

RF N DIVIDER OUTPUT

THREE-STATE OUTPUT

IF COUNTER RESET

RF DIGITAL LOCK DETECT

RF/IF DIGITAL LOCK DETECT

RF COUNTER RESET

P12

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IF AND RF COUNTER RESET

I

(mA)

CP

RF CP2

RF CP1

RF CP0

1.5kꢁ

1.125

2.25

3.375

4.5

5.625

6.75

7.7875

9.0

2.7kꢁ

0.625

1.25

1.875

2.5

3.125

3.75

4.375

5.0

5.6kꢁ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.301

0.602

0.904

1.205

1.506

1.808

2.109

2.411

–14–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table VI. RF N Counter Latch Map

RF N COUNTER LATCH

RF

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

B1

DB7

A6

DB6 DB5 DB4 DB3 DB2

DB1

DB0

P17

P16

P15

P14 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

A5

A4

A3

A2

A1

C2 (1) C1 (1)

A COUNTER

DIVIDE RATIO

P15

P14

PRESCALER

A6

A5

..........

A2

A1

0

1

0

1

0

1

8/9

0

.

1

0

.

1

..........

0

1

0

.

0

1

0

1

0

.

0

1

0

1

2

3

4

.

60

61

62

63

16/17

32/33

64/65

P16

RF POWER-DOWN

0

1

DISABLE

ENABLE

B12

0

B11

0

B10

0

B3

0

B2

1

B1

1

B COUNTER DIVIDE RATIO

3

..........

0

.

1

0

.

1

0

.

1

..........

1

.

1

0

.

0

.

0

4

.

4092

1

..........

1

0

1

0

1

4093

4094

4095

P17

RF CP GAIN

0

1

DISABLE

ENABLE

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B

MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS

2

VALUES OF N ꢃ F

, N

is (P – P).

REF

MIN

–15–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

PROGRAM MODES

Table III and Table V show how to set up the Program Modes

in the ADF421x family. The following should be noted:

IF SECTION

PROGRAMMABLE IF REFERENCE (R) COUNTER

If control bits C2, C1 are 0, 0, the data is transferred from the

input shift register to the 14-bit IFR counter. Table III shows

the input shift register data format for the IFR counter and the

divide ratios possible.

1. IF and RF Analog Lock Detect indicate when the PLL is in

lock. When the loop is locked and either IF or RF Analog

Lock Detect is selected, the MUXOUT pin will show a logic

high with narrow low-going pulses. When the IF/RF Analog

Lock Detect is chosen, the locked condition is indicated only

when both IF and RF loops are locked.

2. The IF Counter Reset mode resets the R and AB counters in

the IF section and also puts the IF charge pump into three-

state. The RF Counter Reset mode resets the R and AB

counters in the RF section and also puts the RF charge

pump into three-state. The IF and RF Counter Reset mode

does both of the above. Upon removal of the reset bits, the

AB counter resumes counting in close alignment with the R

counter (maximum error is one prescaler output cycle).

IF Phase Detector Polarity

P1 sets the IF Phase Detector Polarity. When the IF VCO char-

acteristics are positive this should be set to “1.” When they are

negative it should be set to “0.” See Table III.

IF Charge Pump Three-State

P2 puts the IF charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

See Table III.

IF PROGRAM MODES

Table III and Table V show how to set up the Program Modes

in the ADF421x family.

3. The Fastlock mode uses MUXOUT to switch a second loop

ﬁlter damping resistor to ground during Fastlock operation.

Activation of Fastlock occurs whenever RF CP Gain in the

RF Reference counter is set to one.

IF Charge Pump Currents

IFCP2, IFCP1, IFCP0 program current setting for the IF

charge pump. See Table III.

IF Power-Down

It is possible to program the ADF421x family for either synchro-

nous or asynchronous power-down on either the IF or RF side.

PROGRAMMABLE IF AB COUNTER

If control bits C2, C1 are 0, 1, the data in the input register is used

to program the IF AB counter. The N counter consists of a 6-bit

swallow counter (A counter) and 12-bit programmable counter

(B counter). Table IV shows the input register data format for

programming the IF AB counter and the possible divide ratios.

Synchronous IF Power-Down

Programming a “1” to P7 of the ADF421x family will initiate a

power-down. If P2 of the ADF421x family has been set to “0”

(normal operation), a synchronous power-down is conducted.

The device will automatically put the charge pump into three-

state and then complete the power-down.

IF Prescaler Value

P5 and P6 in the IF A, B Counter Latch sets the IF prescaler

value. See Table IV.

Asynchronous IF Power-Down

IF Power-Down

Table III and Table V show the power-down bits in the

ADF421x family.

If P2 of the ADF421x family has been set to “1” (three-state the

IF charge pump), and P7 is subsequently set to “1,” an asyn-

chronous power-down is conducted. The device will go into

power-down on the rising edge of LE, which latches the “1” to

the IF power-down bit (P7).

IF Fastlock

The IF CP Gain bit (P8) of the IF N register in the ADF421x

family is the Fastlock Enable Bit. Only when this is “1” is IF

Fastlock enabled. When Fastlock is enabled, the IF CP current

is set to its maximum value. Since the IF CP Gain bit is con-

tained in the IF N Counter, only one write is needed to both

program a new output frequency and also initiate Fastlock. To

come out of Fastlock, the IF CP Gain bit on the IF N register

must be set to “0.” See Table IV.

Synchronous RF Power-Down

Programming a “1” to P16 of the ADF421x family will initiate a

power-down. If P10 of the ADF421x family has been set to “0”

(normal operation), a synchronous power-down is conducted. The

device will automatically put the charge pump into three-state

and then complete the power-down.

Asynchronous RF Power-Down

RF SECTION

If P10 of the ADF421x family has been set to “1” (three-state

the RF charge pump), and P16 is subsequently set to “1,” an

asynchronous power-down is conducted. The device will go into

power down on the rising edge of LE, which latches the “1” to

the RF power-down bit (P16).

PROGRAMMABLE RF REFERENCE (R) COUNTER

If control bits C2, C1 are 1, 0, the data is transferred from the

input shift register to the 14-bit RFR counter. Table V shows

the input shift register data format for the RFR counter and the

possible divide ratios.

Activation of either synchronous or asynchronous power-down

forces the IF/RF loop’s R and AB dividers to their load state

conditions and the IF/RF input section is debiased to a high-

impedance state.

RF Phase Detector Polarity

P9 sets the IF Phase Detector Polarity. When the RF VCO

characteristics are positive this should be set to “1.” When they

are negative it should be set to “0.” See Table V.

The REF_INoscillator circuit is only disabled if both the IF and

RF power-downs are set.

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

See Table V.

The input register and latches remain active and are capable of

loading and latching data during all the power-down modes.

The IF/RF section of the devices will return to normal powered

up operation immediately upon LE latching a “0” to the

appropriate power-down bit.

–16–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

RF PROGRAM MODES

APPLICATIONS SECTION

Table III and Table V show how to set up the Program Modes

in the ADF421x family.

Local Oscillator for GSM Handset Receiver

Figure 7 shows the ADF4210/ADF4211/ADF4212/ADF4213

being used with a VCO to produce the LO for a GSM base

station transmitter.

RF Charge Pump Currents

RFCP2, RFCP1, RFCP0 program current setting for the RF

charge pump. See Table V.

The reference input signal is applied to the circuit at FREF_IN

and, in this case, is terminated in 50 Ω. A typical GSM system

would have a 13 MHz TCXO driving the reference input with-

out any 50 Ω termination. In order to have a channel spacing of

200 kHz (the GSM standard), the reference input must be

divided by 65, using the on-chip reference.

PROGRAMMABLE RF N COUNTER

If control bits C2, C1 are 1, 1, the data in the input register is

used to program the RF N (A + B) counter. The N counter

consists of a 6-bit swallow counter (A Counter) and 12-bit

programmable counter (B Counter). Table IV shows the input

register data format for programming the RF N counter and the

possible divide ratios.

WIDEBAND PLL

Many of the wireless applications for synthesizers and VCOs in

PLLs are narrowband in nature. These applications include

various wireless standards such as GSM, DSC1800, CDMA, or

WCDMA. In each of these cases, the total tuning range for the

local oscillator is less than 100 MHz. However, there are also

wideband applications where the local oscillator could have up

to an octave tuning range. For example, cable TV tuners have

a total range of about 400 MHz. Figure 8 shows an applica-

tion where the ADF4213 is used to control and program the

Micronetics M3500–1324. The loop ﬁlter was designed for an

RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD

frequency of 1 MHz, I_CPof 10 mA (2.5 mA synthesizer I_CP

multiplied by the gain factor of 4), VCO K_Dof 80 MHz/V (sen-

sitivity of the M3500–1324 at an output of 2100 MHz) and a

phase margin of 45°C.

RF Prescaler Value

P14 and P15 in the RF A, B Counter Latch sets the RF pres-

caler value. See Table VI.

RF Power-Down

Table III and Table V show the power-down bits in the

ADF421x family.

RF Fastlock

The RF CP Gain bit (P17) of the RF N register in the ADF421x

family is the Fastlock Enable Bit. Only when this is “1” is IF

Fastlock enabled. When Fastlock is enabled, the RF CP current

is set to its maximum value. Also an extra loop ﬁlter damping

resistor to ground is switched in using the FL_Opin, thus com-

pensating for the change in loop characteristics while in Fastlock.

Since the RF CP Gain bit is contained in the RF N Counter, only

one write is needed to both program a new output frequency and

also initiate Fastlock. To come out of Fastlock, the RF CP Gain bit

on the RF N register must be set to “0.” See Table VI.

In narrowband applications, there is generally a small variation

(less than 10%) in output frequency and also a small variation

(typically < 10%) in VCO sensitivity over the range. However,

RF

IF

OUT

V

P

DD

P

100pF

18ꢁ

V 2

V

2

V

1

V 1

P

DD

V

CC

3.3kꢁ

CC

18ꢁ

CP

REF

IF

RF

IN

VCO190-

540T

VCO190-

902T

100pF

18ꢁ

620pF

1.3nF

620pF

5.6kꢁ

ADF4210/

ADF4211/

ADF4212/

ADF4213

8.2nF

R

SET

2.7kꢁ

LOCK

DETECT

100pF

MUXOUT

100pF

RF

IN

51ꢁ

1000pF 1000pF

CLK

DATA

LE

51ꢁ

FREF

RF

B

IN

51ꢁ

DECOUPLING CAPACITORS (22ꢄF/10PF) ON V , V OF THE

DD

P

ADF4211/ADF4212/ADF4213 AND ON V OF THE VCOS HAVE

CC

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4210/ADF4211/ADF4212/ADF4213

–17–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

RF

OUT

20V

12V

V

P

DD

3kꢁ

100pF

1kꢁ

V

18ꢁ

CC

100pF

18ꢁ

V

1 V 2 V 1 V 2

DD P P

OUT

1000pF

V_TUNE

1000pF

DD

AD820

20kꢁ

FREF

IN

REF

CP

IN

RF

M3500-1324

GND

51ꢁ

R

3.9nF

27nF

470ꢁ

130pF

SET

CE

CLK

2.7kꢁ

DATA

LE

LOCK

DETECT

MUXOUT

RF

IN

100pF

51ꢁ

ADF4213

DECOUPLING CAPACITORS ON V , V OF THE ADF4213,

DD

P

ON V OF THE AD820 AND ON THE V OF THE M3500-1324

CC

HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

THE IF SECTION OF THE CIRCUIT HAS ALSO BEEN OMITTED TO

SIMPLIFY THE SCHEMATIC.

Figure 8. Wideband PLL Circuit

in wide-band applications both of these parameters have a much

greater variation. In Figure 8, for example, we have –25% and

+30% variation in the RF output from the nominal 1.8 GHz.

The sensitivity of the VCO can vary from 130 MHz/V at

1900 MHz to 30 MHz/V at 2400 MHz. Variations in these

parameters will change the loop bandwidth. This in turn can

affect stability and lock time. By changing the programmable

I_CP, it is possible to obtain compensation for these varying

loop conditions and ensure that the loop is always operating

close to optimal conditions.

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be about

180 kHz.

SCLK

SDATA

LE

SCLOCK

MOSI

ADF4210/

ADF4211/

ADF4212/

ADF4213

ADuC812

I/O PORTS

CE

INTERFACING

MUXOUT

The ADF4210/ADF4211/ADF4212/ADF4213 family has a

simple SPI-compatible serial interface for writing to the device.

SCLK, SDATA, and LE control the data transfer. When LE

(Latch Enable) goes high, the 22 bits that have been clocked

into the input register on each rising edge of SCLK will be

transferred to the appropriate latch. See Figure 1 for the Timing

Diagram and Table I for the Latch Truth Table.

(LOCK DETECT)

Figure 9. ADuC812 to ADF421x Family Interface

ADSP-21xx to ADF421x Family Interface

Figure 10 shows the interface between the ADF421x family and

the ADSP-21xx Digital Signal Processor. As previously discussed,

the ADF421x family needs a 24-bit serial word for each latch

write. The easiest way to accomplish this, using the ADSP-21xx

family, is to use the Autobuffered Transmit Mode of operation

with Alternate Framing. This provides a means for transmitting

an entire block of serial data before an interrupt is generated.

Set up the word length for eight bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store the three 8-bit bytes, enable the Autobuffered mode, and

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz, or one update every 1.1 ms. This is certainly more

than adequate for systems that will have typical lock times in

hundreds of microseconds.

ADuC812 to ADF421x Family Interface

Figure 9 shows the interface between the ADF421x family and

the ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF421x family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

SCLK

SDATA

LE

SCLK

DT

ADF4210/

ADF4211/

ADF4212/

ADF4213

ADSP-21xx

TFS

CE

I/O FLAGS

MUXOUT

(LOCK DETECT)

On ﬁrst applying power to the ADF421x family, it needs four

writes (one each to the R counter latch and the AB counter latch

for both RF1 and RF2 sides) for the output to become active.

Figure 10. ADSP-21xx to ADF421x Family Interface

–18–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

grid pitch. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper

to plug the via. The user should connect the printed circuit

board pad to AGND.

PCB Guidelines for Chip Scale Package

The lands on the chip scale package (CP-20), are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the

pad. This will ensure that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be clearance of at least 0.25 mm between the thermal

pad and inner edges of the pad pattern. This will ensure that

shorting is avoided.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Thin Shrink Small Outline Package (TSSOP)

(RU-20)

0.260 (6.60)

0.252 (6.40)

20

11

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

0.246 (6.25)

1

10

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0433 (1.10)

MAX

8ꢂ

0ꢂ

0.0256 (0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

0.028 (0.70)

0.020 (0.50)

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

Chip Scale Package

(CP-20)

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.010 (0.25)

MIN

0.157 (4.0)

BSC SQ

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

16

15

20

1

PIN 1

0.012 (0.30)

0.009 (0.23)

0.007 (0.18)

0.030 (0.75)

0.022 (0.60)

0.014 (0.50)

0.080 (2.25)

0.083 (2.10) SQ

0.077 (1.95)

INDICATOR

0.148 (3.75)

BSC SQ

TOP

VIEW

BOTTOM

VIEW

11

10

5

6

0.031 (0.80) MAX

0.026 (0.65) NOM

0.080 (2.00)

REF

12ꢂ MAX

0.035 (0.90) MAX

0.033 (0.85) NOM

0.002 (0.05)

0.0004 (0.01)

0.0 (0.0)

SEATING

PLANE

0.020 (0.50)

BSC

0.008 (0.20)

REF

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

–19–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213–Revision History

Location

Page

Data Sheet changed from REV. 0 to REV. A.

Changes to Test Conditions/Comments section of Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edit to RF_INand IF_INFunction text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PCB Guidelines for Chip Scale Package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CP-20 Package replaced by CP-20[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

–20–

REV. A


型号：	ADF4211BRU
厂家：	ADI
描述：	Dual RF/IF PLL Frequency Synthesizers 双通道RF / IF PLL频率合成器
文件：	总20页 (文件大小：252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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