ADF4212LBCP-REEL7_技术文档

Dual Low Power PLL

Frequency Synthesizer

ADF4212L

FEATURES

GENERAL DESCRIPTION

I_DDtotal: 7.5 mA

Bandwidth RF/IF: 2.4 GHz/1.0 GHz

2.7 V to 3.3 V power supply

Separate V_Pallows extended tuning voltage

Programmable dual modulus prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65

Programmable charge pump currents

3-wire serial interface

The ADF4212L is a dual frequency synthesizer that can be used

to implement local oscillators (LO) in the up-conversion and

down-conversion sections of wireless receivers and transmitters.

It can provide the LO for both the RF and IF sections. It consists

of a low noise digital phase frequency detector (PFD), a precision

charge pump, a programmable reference divider, programmable

A and B counters, and a dual modulus prescaler (P/P + 1). The

A (6-bit) and B (12-bit) counters, in conjunction with the dual

modulus prescaler (P/P + 1), implement an N divider (N = BP +

A). In addition, the 15-bit reference counter (R counter) allows

selectable REF_INfrequencies at the PFD input. A complete phase-

locked loop (PLL) can be implemented if the synthesizer is used

with external loop filters and voltage controlled oscillators (VCOs).

Analog and digital lock detect

Fastlock mode

Power-down mode

20-lead TSSOP and 20-lead LFCSP packages

APPLICATIONS

Control of all the on-chip registers is via a simple 3-wire

interface with 1.8 V compatibility. The devices operate with a

power supply ranging from 2.7 V to 3.3 V and can be powered

down when not in use.

Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA,

WCDMA)

Base stations for wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless LANS

Cable TV tuners (CATV)

Communications test equipment

FUNCTIONAL BLOCK DIAGRAM

V

1

V

2

V

1

V

2

R

SET

DD

P

ADF4212L

IF PHASE

FREQUENCY

DETECTOR

REFERENCE

12-BIT IF

B-COUNTER

CHARGE

PUMP

CP

IF

IN

IF

PRESCALER

6-BIT IF

A-COUNTER

IF CURRENT

SETTING

IF

LOCK

DETECT

IFCP3 IFCP2 IFCP1

REF

OSCILLATOR

IN

15-BIT IF

R-COUNTER

OUTPUT

MUX

MUXOUT

CLK

22-BIT

DATA

REGISTER

DATA

LE

SDOUT

RFCP3 RFCP2 RFCP1

REFERENCE

RF

15-BIT RF

R-COUNTER

LOCK

DETECT

CHARGE

PUMP

12-BIT RF

B-COUNTER

CP

RF

IN

RF

RF PHASE

FREQUENCY

DETECTOR

PRESCALER

REFERENCE

6-BIT RF

A-COUNTER

R

SET

FL SWITCH

O

FL

O

DGND

RF

AGND

DGND

AGND

RF

IF

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

ADF4212L

TABLE OF CONTENTS

Features .............................................................................................. 1

MUXOUT and Lock Detect...................................................... 14

Lock Detect ................................................................................. 14

RF/IF Input Shift Register......................................................... 14

IF R Counter Latch..................................................................... 16

IF N Counter Latch.................................................................... 17

RF R Counter Latch ................................................................... 18

RF N Counter Latch................................................................... 19

Program Modes .............................................................................. 20

IF and RF Power-Down............................................................. 20

IF Section..................................................................................... 20

RF Section ................................................................................... 21

Applications Information.............................................................. 22

Local Oscillator for GSM Handset Receiver............................... 22

Wideband PLL............................................................................ 23

Interfacing ................................................................................... 24

PCB Design Guidelines for Lead Frame Chip Scale Package24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 26

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 9

Circuit Description......................................................................... 13

Reference Input Section............................................................. 13

RF/IF Input Stage........................................................................ 13

Prescaler (P/P + 1)...................................................................... 13

RF/IF A and B Counters............................................................ 13

Pulse Swallow Function............................................................. 13

RF/IF R Counter......................................................................... 13

Phase Frequency Detector (PFD) and Charge Pump............ 14

REVISION HISTORY

9/08—Rev. A to Rev B

Changes to Figure 32...................................................................... 23

Changes to Figure 33 and Figure 34............................................. 24

Added PCB Design Guidelines for Lead Frame Chip Scale

Package Section............................................................................... 24

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide.......................................................... 25

Updated Format..................................................................Universal

Changes to Figure 1 and General Description Section ............... 1

Changes to Prescaler Output Frequency Parameter and RF

Input Frequency (RF_IN) Parameter................................................. 3

Changes to Table 3 and Figure 2..................................................... 5

Changes to Figure 4.......................................................................... 7

Changes to Figure 27, RF/IF A and B Counters Section, Pulse

Swallow Function Section, and RF/IF R Counter Section........ 13

Changes to RF/IF Input Shift Register Section........................... 14

Changes to Programmable IF Reference (R) Counter Section,

IF Program Modes Section, and IF Power-Down Section........ 20

Changes to Programmable RF Reference (R) Counter Section,

RF Program Modes Section, Programmable RF N Counter

Section, and RF Power-Down Section......................................... 21

3/03—Data Sheet changed from REV. 0 to REV. A

Changes to General Description .....................................................1

Changes to Specifications.................................................................3

Changes to Table 9.......................................................................... 18

Changes to Table 11 ....................................................................... 20

Changes to Figure 31...................................................................... 23

11/02—Revision 0: Initial Version

Rev. B | Page 2 of 28

ADF4212L

SPECIFICATIONS

V_DD1 = V_DD2 = 2.7 V to 3.3 V; V_P1, V_P2 = V_DDto 5.5 V; AGND_RF= DGND_RF= AGND_IF= DGND_IF= 0 V; T_A= T_MINto T_MAX, unless

otherwise noted; dBm referred to 50 Ω.

Table 1.

Parameter¹

B Version

B Chips²

Unit

Test Conditions/Comments

RF/IF CHARACTERISTICS

RF Input Frequency (RF_IN)

0.2/2.4

GHz min/max

For lower frequencies, ensure that slew rate (SR)

> 140 V/µs

RF Input Sensitivity

IF Input Frequency (IF_IN)

IF Input Sensitivity

−10/0

100/1000

−10/0

100/1000

−10/0

dBm min/max

MHz min/max

dBm min/max

V_DD= 3 V

MAXIMUM ALLOWABLE

Prescaler Output Frequency³

REF_INCHARACTERISTICS

REF_INInput Frequency

REF_INInput Sensitivity

188

MHz max

See Figure 26 for input circuit

10/150

500 mV/V_DD

10/150

500 mV/V_DD

MHz min/max

V p-p min/max

AC-coupled; when dc-coupled, 0 V to V_DD

maximum (CMOS compatible)

REF_INInput Capacitance

REF_INInput Current

PHASE DETECTOR

Phase Detector Frequency⁴

CHARGE PUMP

10

100

10

100

pF max

μA max

75

MHz max

I_CPSink/Source

Programmable, see Table 10

With R_SET= 2.7 kΩ

High Value

Low Value

5

625

2

5

625

2

mA typ

μA typ

% typ

kΩ min/max

nA max

% typ

Absolute Accuracy

R_SETRange

I_CPThree-State Leakage Current

Sink and Source Current Matching

I_CPvs. V_CP

With R_SET= 2.7 kΩ

1.5/5.6

1

6

2

1

6

2

0.5 V < V_CP< V_P− 0.5 V

V_CP= V_P/2

% typ

I_CPvs. Temperature

LOGIC INPUTS

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

C_IN, Input Capacitance

LOGIC OUTPUTS

1.4

0.6

1

1.4

0.6

1

V min

V max

μA max

pF max

10

V_OH, Output High Voltage

V_OL, Output Low Voltage

POWER SUPPLIES

1.4

0.4

1.4

0.4

V min

V max

Open-drain 1 kΩ pull-up to 1.8 V

I_OL= 500 μA

V_DD

1

2

2.7/3.3

V_DD1

V min/max

mA typ/max

mA typ

V_DD1

V_P1, V_P2

I_DD(RF and IF)⁵

RF Only

IF Only

V_DD1/5.5

7.5/10

5.0/6

2.5/4

0.6

V_DD1/5.5

7.5/10

5.0/6

2.5/4

0.6

I_P(I_P1 + I_P2)

Low Power Sleep Mode

1

μA typ

¹Operating temperature range is as follows: B version: −40°C to +85°C.

²The B chip specifications are given as typical values.

³This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency less

than this value.

⁴Guaranteed by design. Sample tested to ensure compliance.

⁵T_A= 25°C. RF = 1 GHz; prescaler = 32/33. IF = 500 MHz; prescaler = 16/17.

Rev. B | Page 3 of 28

ADF4212L

V_DD1 = V_DD2 = 2.7 V to 3.3 V; V_P1, V_P2 = V_DDto 5.5 V; AGND_RF= DGND_RF= AGND_IF= DGND_IF= 0 V; T_A= T_MINto T_MAX, unless

otherwise noted; dBm referred to 50 V.

Table 2.

Parameter¹

B Version

B Chips²

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

RF Phase Noise Floor³

−170

−162

−170

−162

dBc/Hz typ

25 kHz PFD frequency

200 kHz PFD frequency

Phase Noise Performance⁴

IF: 540 MHz Output⁵

IF: 900 MHz Output⁶

RF: 900 MHz Output⁶

RF: 1750 MHz Output⁷

RF: 2400 MHz Output⁸

Spurious Signals

VCO output

−89

−87

−89

−84

−87

−89

−87

−89

−84

−87

dBc/Hz typ

1 kHz offset and 200 kHz PFD frequency

1 kHz Offset and 1 MHz PFD frequency

IF: 540 MHz Output⁵

IF: 900 MHz Output⁶

RF: 900 MHz Output⁶

RF: 1750 MHz Output⁷

RF: 2400 MHz Output⁸

−88/−90

−90/−94

−80/−82

−88/−90

−90/−94

−80/−82

dB typ

200 kHz/400 kHz and 200 kHz PFD frequency

¹Operating temperature range is as follows: B version: −40°C to +85°C.

²The B Chip specifications are given as typical values.

³The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

See Figure 9.

⁴The phase noise is measured with the EVAL-ADF4212EB and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer

(f_REFOUT= 10 MHz @ 0 dBm).

⁵f_REFIN= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_IF= 540 MHz; N = 2700; loop B/W = 20 kHz

⁶f_REFIN= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 900 MHz; N = 4500; loop B/W = 20 kHz

⁷f_REFIN= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 1750 MHz; N = 8750; loop B/W = 20 kHz

⁸f_REFIN= 10 MHz; f_PFD= 1 MHz; offset frequency = 1 kHz; f_RF= 2400 MHz; N = 9800; loop B/W = 20 kHz

Rev. B | Page 4 of 28

ADF4212L

TIMING CHARACTERISTICS

V_DD1 = V_DD2 = 2.6 V to 3.3 V; V_P1, V_P2 = V_DDto 5.5 V; AGND_RF= DGND_RF= AGND_IF= DGND_IF= 0 V; T_A= T_MINto T_MAX, unless

otherwise noted; dBm referred to 50 Ω.

Table 3.

Parameter¹

Limit at T_MINto T_MAX(B Version)

Unit

Test Conditions/Comments

LE setup time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

20

10

25

10

20

ns min

Data to clock setup time

Data to clock hold time

Clock high duration

Clock low duration

Clock to LE setup time

LE pulse width

¹Guaranteed by design but not production tested.

t₄

t₅

CLK

t₂

t₃

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

DB22

DB2

DATA

LE

(CONTROL BIT C2)

t₇

t₁

t₆

LE

Figure 2. Timing Diagram

Rev. B | Page 5 of 28

ADF4212L

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Parameter^{1, 2}

Rating

V_DD1 to GND

V_DD1 to V_DD2

V_P1, V_P2 to GND

−0.3 V to +3.6 V

−0.3 V to +0.3 V

−0.3 V to +3.6 V

−0.3 V to DV_DD+ 0.3 V

−0.3 V to V_DD+ 0.3 V

V_P1, V_P2 to V_DD1, V_DD2

Digital I/O Voltage to GND

Analog I/O Voltage to GND

REF_IN, RF_IN, IF_INto GND

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Maximum Junction Temperature

TSSOP θ_JAThermal Impedance

ESD CAUTION

−40°C to +85°C

−65°C to +150°C

150°C

150.4°C/W

122°C/W

LFCSP θ_JAThermal Impedance

(Paddle Soldered)

LFCSP θ_JAThermal Impedance

(Paddle Not Soldered)

216°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

215°C

220°C

¹This device is a high performance RF integrated circuit with an ESD rating of

<2 kV, and is ESD sensitive. Proper precautions should be taken for handling

and assembly.

³GND = AGND = DGND = 0 V.

Rev. B | Page 6 of 28

ADF4212L

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CP

DGND

RF

AGND

1

2

3

4

5

15 DGND

RF

IF

14 IF

IN

1

2

20

19

18

17

16

15

14

13

12

11

V

1

V

2

DD

ADF4212L

TOP VIEW

(Not to Scale)

DD

13 AGND

IN

IF

V

CP

V 2

P

12 R

P

RF

SET

FL

11 LE

O

3

CP

RF

IF

ADF4212L

TOP VIEW

(Not to Scale)

4

DGND

IF

5

RF

IF

IN

6

AGND

RF

7

FL

R

SET

O

8

REF

LE

NOTES

IN

1. IT IS RECOMMENDED THAT THE EXPOSED PAD

BE THERMALLY CONNECTED TO A COPPER PLANE

FOR ENHANCED THERMAL PERFORMANCE. THE PAD

SHOULD BE GROUNDED AS WELL.

9

DGND

DATA

CLK

IF

10

MUXOUT

Figure 4. LFCSP Pin Configuration

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic TSSOP LFCSP

Description

CP_RF

3

1

RF Charge Pump Output. When enabled, this provides I_CPto the external RF loop filter, which in turn

drives the external RF VCO.

DGND_RF

RF_IN

AGND_RF

FL_O

4

5

6

7

8

2

3

4

5

6

Digital Ground Pin for the RF Digital Circuitry.

Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.

Ground Pin for the RF Analog Circuitry.

Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input

resistance of 100 kΩ. See Figure 26. This input can be driven from a TTL or CMOS crystal oscillator, or can

be ac-coupled.

DGND_IF

MUXOUT

9, 17

10

7, 15

8

Digital Ground Pin for the IF Digital, Interface, and Control Circuitry.

This multiplexer output allows either the IF/RF lock detect, the scaled RF, the scaled IF, or the scaled

reference frequency to be accessed externally.

CLK

DATA

LE

11

12

13

14

9

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is

a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the four latches, with the latch selected using the control bits.

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output

current. The nominal voltage potential at the R_SETpin is 0.66 V. The relationship between I_CPand R_SETis,

therefore,

10

11

12

R_SET

13.5

R_SET

I_{CP MAX}

=

where R_SET= 2.7 kΩ and I_{CP MAX}= 5 mA for both the RF and IF charge pumps.

Ground Pin for the IF Analog Circuitry.

Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.

Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an

external VCO.

AGND_IF

IF_IN

CP_IF

15

16

18

13

14

16

V_P2

19

17

Power Supply for the IF Charge Pump. This should be greater than or equal to V_DD2. In systems where

V_DD2 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

Rev. B | Page 7 of 28

ADF4212L

Pin No.

Mnemonic TSSOP LFCSP

Description

V_DD2

20

18

19

20

Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane

should be placed as close as possible to this pin. V_DD2 should have a value of between 2.6 V and 3.3 V.

V_DD2 must have the same potential as V_DD1.

Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close

as possible to this pin. V_DD1 should have a value of between 2.6 V and 3.3 V. V_DD1 must have the same

potential as V_DD2.

V_DD1

1

V_P1

EP

2

Power Supply for the RF Charge Pump. This should be greater than or equal to V_DD1. In systems where

V_DD1 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

Exposed It is recommended that the exposed pad be thermally connected to a copper plane for enhanced

Pad

thermal performance. The pad should be grounded as well.

Rev. B | Page 8 of 28

ADF4212L

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

V

= 3V

DD

= 5V

V

I

= 3V, V = 5V

P

REFERENCE

LEVEL = –3.0dBm

DD

= 5mA

P

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1Hz

VIDEO BANDWIDTH = 1Hz

SWEEP = 2.5 SECONDS

AVERAGES = 20

–5

–10

–15

–20

–25

–30

–85.9dB

0

500

1000

1500

2000

2500

3000

–400k

–200k

1.75G

FREQUENCY (Hz)

200k

400k

FREQUENCY (MHz)

Figure 5. Input Sensitivity (RF Input)

Figure 8. Reference Spurs, RF Side (1750 MHz, 200 kHz, 20 kHz)

RMS NOISE = 1.38 DEGREES

1.38° RMS

10dB/DIV

R = –50dBc/Hz

L

–50

–60

0

–5

V

= 3V

DD

V

= 5V

P

–70

–80

–10

–90

–15

–20

–25

–30

–35

–100

–110

–120

–130

–140

–150

100Hz

1MHz

0

500

1000

1500

FREQUENCY OFFSET

FROM 1.75GHz CARRIER

FREQUENCY (MHz)

Figure 6. Input Sensitivity (IF Input)

Figure 9. Integrated Phase Noise (1750 MHz, 200 kHz/20 kHz)

0

V

= 3V, V = 5V

P

= 5mA

DD

REFERENCE

LEVEL = –4.3dBm

REFERENCE

LEVEL = –3.2dBm

V

= 3V, V = 5V

P

DD

= 5mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

I

CP

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 22

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 22

–84.2dBc/Hz

1k 2k

–88.8dBc/Hz

–2k

–1k

1.75G

FREQUENCY (Hz)

–2k

–1k

540M

FREQUENCY (Hz)

1k

2k

Figure 7. Phase Noise, RF Side (1750 MHz, 200 kHz, 20 kHz)

Figure 10. Phase Noise, IF Side (540 MHz, 200 kHz/20 kHz)

Rev. B | Page 9 of 28

ADF4212L

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–130

–140

–150

V

I

= 3V, V = 5V

P

REFERENCE

LEVEL = –7.0dBm

DD

= 5mA

V

= 3V

DD

= 5V

CP

P

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1Hz

VIDEO BANDWIDTH = 1Hz

SWEEP = 2.5 SECONDS

AVERAGES = 20

–160

–170

–180

–89.3dBc

–400k

–200k

200k

400k

540M

FREQUENCY (Hz)

10

100

1k

10k

PHASE DETECTOR FREQUENCY (kHz)

Figure 11. Reference Spurs, IF Side (540 MHz, 200 kHz, 20 kHz)

Figure 14. Phase Noise Referred to CP Output vs. PFD Frequency, IF Side

RMS NOISE =

0.83 DEGREES

10dB/DIV

R = –50dBc/Hz

L

–50

–60

6

4

0.83° RMS

–70

–80

2

–90

–100

–110

–120

–130

–140

–150

0

–2

–4

–6

100Hz

1MHz

0

1

2

3

4

5

FREQUENCY OFFSET

FROM 540MHz CARRIER

V

(V)

CP

Figure 12. Integrated Phase Noise (540 MHz, 200 kHz/20 kHz)

Figure 15. RF Charge Pump Output Characteristics

6

4

–130

–140

–150

V

= 3V

DD

= 5V

P

V

= 3V

DD

2 = 5.5V

P

2

0

–160

–170

–180

–2

–4

–6

0

1

2

3

4

5

10

100

1k

10k

V

(V)

PHASE DETECTOR FREQUENCY (kHz)

CP

Figure 13. Phase Noise Referred to CP Output vs. PFD Frequency, RF Side

Figure 16. IF Charge Pump Output Characteristics

Rev. B | Page 10 of 28

ADF4212L

0

–20

–40

–60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–40

–20

0

20

40

60

80

100

0

1

2

3

4

5

TEMPERATURE (°C)

TUNING VOLTAGE (V)

Figure 20. IF Phase Noise vs. Temperature (540 MHz, 200 kHz, 20 kHz)

Figure 17. RF Reference Spurs (200 kHz) vs. V_TUNE(1750 MHz, 200 kHz, 20 kHz)

0

–20

–40

–60

–80

–10

–20

–30

–40

–50

–60

–70

–80

–100

–120

–90

–100

0

1

2

3

4

5

0

1

2

3

4

5

TUNING VOLTAGE (V)

Figure 21. RF Noise vs. V_TUNE

Figure 18. IF Reference Spurs (200 kHz) vs. V_TUNE(1750 MHz, 200 kHz, 20 kHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

1

2

3

4

5

–40

–20

0

20

40

60

80

100

TUNING VOLTAGE (V)

TEMPERATURE (°C)

Figure 22. IF Noise vs. V_TUNE

Figure 19. RF Phase Noise vs. Temperature (1750 MHz, 200 kHz, 20 kHz)

Rev. B | Page 11 of 28

ADF4212L

0

–20

–40

–60

–80

FREQUENCY

(MHz)

FREQUENCY

(MHz)

s11.REAL s11.IMAG

50

0.97692

–0.021077 1550

–0.110459 1650

0.561872

0.529742

0.514244

0.405754

0.379354

0.312959

0.322646

0.288881

0.199294

0.206914

0.168344

0.092764

0.036125

0.037007

–0.646879

–0.668172

–0.702192

–0.714541

–0.703593

–0.802878

–0.803970

–0.807055

–0.758619

–0.725029

–0.770837

–0.776619

–0.706197

–0.716939

150

250

350

450

550

650

750

850

950

1050

1150

1250

1350

1450

0.942115

0.961217

0.920667

0.897441

0.888164

0.850012

0.760189

0.767363

0.779511

0.761034

0.624825

0.635364

0.630242

0.634506

–0.085802 1750

–0.185830 1850

–0.245482 1950

–0.282399 2050

–0.305457 2150

–0.358884 2250

–0.541032 2350

–0.585687 2450

–0.482539 2550

–0.530106 2650

–0.590526 2750

–0.592498 2850

–0.655932 2950

–100

–120

–40

–20

0

20

40

60

80

100

–0.053842 –0.736527

TEMPERATURE (°C)

Figure 23. RF Spurs vs. Temperature

Figure 25. S Parameter Data for the RF Input

0

–20

–40

–60

–80

–100

–120

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 24. IF Spurs vs. Temperature

Rev. B | Page 12 of 28

ADF4212L

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

RF/IF A AND B COUNTERS

The reference input stage is shown in Figure 26. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are specified to work when the

prescaler output is 188 MHz or less. Thus, with an RF input

frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a

value of 8/9 is not valid.

POWER-DOWN

CONTROL

PULSE SWALLOW FUNCTION

The A and B CMOS counters, in conjunction with the dual

modulus prescaler, make it possible to generate output

frequencies that are spaced only by the reference frequency

divided by R. The equation for the VCO frequency is as follows:

100kΩ

NC

SW2

REF

TO R COUNTER

IN

NC

BUFFER

SW1

SW3

NC = NO CONNECT

f

_VCO= [(P × B) + A] × f_REFIN/R

where:

_VCOis the output frequency of external voltage controlled

NO

Figure 26. Reference Input Stage

f

RF/IF INPUT STAGE

oscillator (VCO).

P is the preset modulus of the dual modulus prescaler (8/9,

16/17, and so on).

B is the preset divide ratio of the binary 12-bit counter (3 to 4095).

A is the preset divide ratio of the binary 6-bit swallow counter

(0 to 63).

The RF/IF input stage is shown in Figure 27. It is followed by a

two-stage limiting amplifier to generate the current mode logic

(CML) clock levels needed for the prescaler.

1.6V

BIAS

GENERATOR

AV

DD

f_REFINis the external reference oscillator frequency.

2kΩ

R is the preset divide ratio of the binary 15-bit programmable

reference counter (1 to 32,767).

RF

IN

N = BP + A

12-BIT B

TO PFD

COUNTER

100pF

AGND

LOAD

FROM RF

INPUT STAGE

PRESCALER

P/P + 1

LOAD

AGND

6-BIT A

COUNTER

Figure 27. RF/IF Input Stage

MODULUS

CONTROL

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B

counters, enables the large division ratio, N, to be realized (N =

PB + A). The dual modulus prescaler, operating at CML levels,

takes the clock from the RF/IF input stage and divides it down

to a manageable frequency for the A and B CMOS counters in the

RF and IF sections. The prescaler in both sections is programma-

ble. It can be set in software to 8/9, 16/17, 32/33, or 64/65 (see

Table 9 and Table 10). It is based on a synchronous 4/5 core.

Figure 28. RF/IF A and B Counters

RF/IF R COUNTER

The 15-bit RF/IF R counter allows the input reference frequency to

be divided down to produce the input clock to the phase frequency

detector (PFD). Division ratios from 1 to 16,383 are allowed.

Rev. B | Page 13 of 28

ADF4212L

DV

DD

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 29 is a simplified schematic.

The PFD includes a fixed delay element that sets the width of

the antibacklash pulse. This is typically 3 ns. This pulse ensures

that there is no dead zone in the PFD transfer function and

gives a consistent reference spur level.

IF ANALOG LOCK DETECT

IF R COUNTER OUTPUT

IF N COUNTER OUTPUT

MUXOUT

MUX

CONTROL

IF/RF ANALOG LOCK DETECT

RF R COUNTER OUTPUT

RF N COUNTER OUTPUT

RF ANALOG LOCK DETECT

UP

HI

D1

Q1

DGND

U1

CLR1

Figure 30. MUXOUT Schematic

+IN

RF/IF INPUT SHIFT REGISTER

The ADF4212L digital section includes a 24-bit input shift

register, a 15-bit IF R counter, and an 18-bit IF N counter

(comprising a 6-bit IF A counter and a 12-bit IF B counter).

Also present is a 15-bit RF R counter and an 18-bit RF N

counter (comprising a 6-bit RF A counter and a 12-bit RF B

counter). Data is clocked into the 24-bit shift register on each

rising edge of CLK. The data is clocked in MSB first. Data is

transferred from the shift register to one of four latches on the

rising edge of LE. The destination latch is determined by the

state of the two control bits (C2, C1) in the shift register. These

are the two LSBs, DB1 and DB0, as shown in the timing diagram

of Figure 2. The truth table for these bits is shown in Table 6.

CHARGE

PUMP

CP

U3

DELAY

DOWN

CLR2

D2 Q2

HI

U2

–IN

Figure 29. RF/IF PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4212L allows the user to

access various internal points on the chip. The state of MUXOUT

is controlled by P3, P4, P11, and P12 (see Table 8 and Table 10).

Figure 30 shows the MUXOUT section in block diagram form.

Table 7 shows a summary of how the latches are programmed.

Table 6. C2, C1 Truth Table

LOCK DETECT

Control Bits

MUXOUT can be programmed for two types of lock detect: digital

lock detect and analog lock detect. Digital lock detect is active

high. It is set high when the phase error on three consecutive phase

detector cycles is less than 15 ns. It stays set high until a phase

error of greater than 25 ns is detected on any subsequent PD cycle.

C2

0

C1

0

Data Latch

IF R counter

0

1

0

IF N counter (A and B)

RF R counter

1

RF N counter (A and B)

The N-channel open-drain analog lock detect should be operated

with an external pull-up resistor of 10 kΩ nominal. When lock

has been detected, it is high with narrow, low-going pulses.

Rev. B | Page 14 of 28

ADF4212L

Table 7. Latch Summary

IF R COUNTER LATCH

IF CP CURRENT

SETTING

CONTROL

BITS

15-BIT REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

IFCP2 IFCP1 IFCP0 P4 P3 P2 P1 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2

DB2 DB1

DB0

R1 C2 (0) C1 (0)

IF N COUNTER LATCH

IF

PRESCALER

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

P8 P7 P6 P5 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2

DB2 DB1

DB0

A1 C2 (0) C1 (1)

RF R COUNTER LATCH

RF CP CURRENT

SETTING

CONTROL

BITS

15-BIT RF REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2 DB1

DB0

RFCP2 RFCP1 RFCP0 P12

P11

P10

P9

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (1) C1 (0)

RF N COUNTER LATCH

RF

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

P17 P16 P15 P14 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2

DB2 DB1

DB0

A1 C2 (1) C1 (1)

Rev. B | Page 15 of 28

ADF4212L

IF R COUNTER LATCH

Table 8. IF R Counter Latch Map

IF CP CURRENT

SETTING

CONTROL

BITS

15-BIT IF REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2 DB1

DB0

IFCP2 IFCP1 IFCP0

P4

P3

P2

P1

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (0) C1 (0)

R15

R14

R13

..........

R3

R2

R1

DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

32764

1

..........

1

0

1

0

1

32765

32766

32767

P1

IF PD POLARITY

0

1

NEGATIVE

POSITIVE

CHARGE PUMP

OUTPUT

P2

0

1

NORMAL

THREE-STATE

P12

P11

P4

P3

FROM RF R LATCH

MUXOUT

LOGIC LOW STATE

IF ANALOG LOCK DETECT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

IF DIGITAL LOCK DETECT

LOGIC HIGH STATE

RF REFERENCE DIVIDER OUTPUT

RF N DIVIDER OUTPUT

THREE-STATE OUTPUT

IF COUNTER RESET

RF DIGITAL LOCK DETECT

RF/IF DIGITAL LOCK DETECT

RF COUNTER RESET

IF AND RF COUNTER RESET

I

(mA)

CP

IFCP2 IFCP1 IFCP0

1.5kΩ

2.7kΩ

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

5.6kΩ

0.301

0.602

0.904

1.205

1.506

1.808

2.109

2.411

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.1250

2.2500

3.3750

4.5000

5.6250

6.7500

7.7875

9.0000

Rev. B | Page 16 of 28

ADF4212L

IF N COUNTER LATCH

Table 9. IF N Counter Latch Map

IF

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2 DB1

DB0

P8

P7

P6

P5

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

A6

A5

A4

A3

A2

A1 C2 (0) C1 (1)

A COUNTER

DIVIDE RATIO

A6

0

.

A5

..........

A2

0

1

0

.

A1

P6 P5 PRESCALER VALUE

0

.

0

1

0

1

.

0

1

0

1

0

1

8/9

16/17

32/33

64/65

1

2

3

.

P7 IF POWER-DOWN

0

1

DISABLED

ENABLED

.

..........

.

1

.

1

.

0

.

0

.

60

1

..........

0

1

0

1

61

62

63

P8 IF CP GAIN

0

1

DISABLED

ENABLED

B12

B11

B10

B3

B2

B1

B COUNTER DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

1

0

.

1

0

.

3

4

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

4092

1

..........

1

0

1

0

1

4093

4094

4095

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.

B MUST BE GREATER THAN OR EQUAL TO A.

2

FOR CONTIGUOUS VALUES OF N, N

IS (p – P).

MIN

Rev. B | Page 17 of 28

ADF4212L

RF R COUNTER LATCH

Table 10. RF R Counter Latch Map

RF CP CURRENT

SETTING

CONTROL

BITS

15-BIT RF REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2 DB1

DB0

RFCP2 RFCP1 RFCP0 P12

P11

P10

P9

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (0) C1 (0)

R15

R14

R13

..........

R3

R2

R1

DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

32764

1

..........

1

0

1

0

1

32765

32766

32767

P9

RF PD POLARITY

0

1

NEGATIVE

POSITIVE

CHARGE PUMP

OUTPUT

P10

0

1

NORMAL

THREE-STATE

P12

P11

P4

P3

MUXOUT

FROM IF R LATCH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOGIC LOW STATE

IF ANALOG LOCK DETECT

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

IF DIGITAL LOCK DETECT

LOGIC HIGH STATE

RF REFERENCE DIVIDER OUTPUT

RF N DIVIDER OUTPUT

THREE-STATE OUTPUT

IF COUNTER RESET

RF DIGITAL LOCK DETECT

RF/IF DIGITAL LOCK DETECT

RF COUNTER RESET

IF AND RF COUNTER RESET

I

(mA)

CP

RFCP2 RFCP1 RFCP0

1.5kΩ

2.7kΩ

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

5.6kΩ

0.301

0.602

0.904

1.205

1.506

1.808

2.109

2.411

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.1250

2.2500

3.3750

4.5000

5.6250

6.7500

7.7875

9.0000

Rev. B | Page 18 of 28

ADF4212L

RF N COUNTER LATCH

Table 11. RF N Counter Latch Map

RF

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2 DB1

DB0

P17

P16

P15

P14 B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

A6

A5

A4

A3

A2

A1 C2 (1) C1 (1)

A6

A5

..........

A2

A1

A COUNTER

DIVIDE RATIO

P15 P14 PRESCALER VALUE

0

.

0

.

..........

0

1

0

.

0

1

0

1

.

0

1

2

3

.

0

1

0

1

0

1

8/9

16/17

32/33

64/65

P16 RF POWER-DOWN

0

1

DISABLED

ENABLED

.

..........

.

1

.

1

.

0

.

0

.

60

1

..........

0

1

0

1

61

62

63

P17 RF CP GAIN

0

1

DISABLED

ENABLED

B12

B11

B10

B3

B2

B1

B COUNTER DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

1

0

.

1

0

.

3

4

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

4092

1

..........

1

0

1

0

1

4093

4094

4095

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH

B MUST BE GREATER THAN OR EQUAL TO A

2

FOR CONTIGUOUS VALUES OF N, N

IS (P – P)

MIN

Rev. B | Page 19 of 28

ADF4212L

PROGRAM MODES

Table 8 and Table 10 show how to set up the program modes in

the ADF4212L. The following should be noted:

conditions, and the IF/RF input section is debiased to a high

impedance state.

The REF_INoscillator circuit is disabled only if both the IF and

RF power-downs are set.

•

IF and RF analog lock detect indicate when the PLL is in

lock. When the loop is locked and either IF or RF analog

lock detect is selected, the MUXOUT pin shows a logic

high with narrow, low-going pulses. When the IF/RF

analog lock detect is chosen, the locked condition is

indicated only when both IF and RF loops are locked.

The IF counter reset mode resets the R, A, and B counters

in the IF section and puts the IF charge pump into three-

state mode. The RF counter reset mode resets the R, A, and

B counters in the RF section and puts the RF charge pump

into three-state. The IF and RF counter reset mode does

both of the above. Upon removal of the reset bits, the A

and B counters resume counting in close alignment with

the R counter. (Maximum error is one prescaler output cycle.)

The fastlock mode uses MUXOUT to switch a second loop

filter damping resistor to ground during fastlock operation.

Activation of fastlock occurs whenever RF CP gain in the

RF reference counter is set to 1.

The input register and latches remain active and are capable of

loading and latching data during all power-down modes.

The IF/RF section of the device returns to normal powered-up

operation immediately upon LE latching a 0 to the appropriate

power-down bit.

•

IF SECTION

Programmable IF Reference (R) Counter

If Control Bits[C2:C1] = 00, the data is transferred from the

input shift register to the 15-bit IF R counter. Table 8 shows the

input shift register data format for the IF R counter and the

divide ratios that are possible.

•

IF Phase Detector Polarity

P1 sets the IF phase detector polarity. When the IF VCO

characteristics are positive, P1 should be set to 1. When

the IF VCO characteristics are negative, it should be set to 0.

See Table 8.

IF AND RF POWER-DOWN

It is possible to program the ADF4210 family for either synchron-

ous or asynchronous power-down on either the IF or RF side.

IF Charge Pump Three-State

P2 puts the IF charge pump into three-state mode when

programmed to a 1. It should be set to 0 for normal operation.

See Table 8.

Synchronous IF Power-Down

Programming a 1 to P7 of the ADF4212L initiates a power-

down. If P2 of the ADF4212L has been set to 0 (normal

operation), a synchronous power-down is conducted. The

device automatically puts the charge pump into three-state

mode and completes the power-down.

IF Program Modes

Table 8 shows how to set up the program modes in the

ADF4212L.

IF Charge Pump Currents

Asynchronous IF Power-Down

IFCP2, IFCP1, and IFCP0 program the current setting for the

IF charge pump. See Table 8.

If P2 of the ADF4212L has been set to 1 (the IF charge pump in

three-state mode) and P7 is subsequently set to 1, an asynchronous

power-down is conducted. The device goes into power-down on

the rising edge of LE, which latches the 1 to the IF power-down

bit (P7).

Programmable IF N Counter

If Control Bits[C2:C1] = 01, the data in the input register is

used to program the IF N (A + B) counter. The N counter

consists of a 6-bit swallow counter (A counter) and 12-bit

programmable counter (B counter). Table 9 shows the input

register data format for programming the IF A and B counters

and the divide ratios possible.

Synchronous RF Power-Down

Programming a 1 to P16 of the ADF4212L initiates a power-

down. If P10 of the ADF4212L has been set to 0 (normal

operation), a synchronous power-down is conducted. The

device automatically puts the charge pump into three-state

mode and then completes the power-down.

IF Prescaler Value

P5 and P6 in the IF N counter latch set the IF prescaler values.

See Table 9.

Asynchronous RF Power-Down

If P10 of the ADF4212L has been set to 1 (the RF charge pump in

three-state mode) and P16 is subsequently set to 1, an asynchron-

ous power-down is conducted. The device goes into power-down

on the rising edge of LE, which latches the 1 to the RF power-down

bit (P16).

IF Power-Down

Table 9 shows the power-down bits in the ADF4212L.

IF Fastlock

The IF CP gain bit (P8) of the IF N counter latch register in the

ADF4212L is the fastlock enable bit. Only when P8 is set to 1 is

IF fastlock enabled. When fastlock is enabled, the IF CP current

Activation of either synchronous or asynchronous power-down

forces the IF/RF loop’s R and A/B dividers to their load state

Rev. B | Page 20 of 28

ADF4212L

is set to the maximum value. Also, an extra loop filter damping

resistor to ground is switched in using the FL_Opin, thus

compensating for the change in loop characteristics while in

fastlock. Because the IF CP gain bit is contained in the IF N

counter, only one write is needed to both program a new output

frequency and initiate fastlock. To come out of fastlock, the IF

CP gain bit on the IF N counter latch register must be set to 0

(see Table 9).

RF Charge Pump Currents

RFCP2, RFCP1, and RFCP0 program the current setting for the

RF charge pump. See Table 10.

Programmable RF N Counter

If Control Bits[C2:C1] = 11, the data in the input register is

used to program the RF N (A + B) counter. The N counter

consists of a 6-bit swallow counter (A counter) and a 12-bit

programmable counter (B counter). Table 11 shows the input

register data format for programming the RF N counter and the

divide ratios that are possible.

RF SECTION

Programmable RF Reference (R) Counter

If Control Bits[C2: C1] = 10, the data is transferred from the

input shift register to the 15-bit RF R counter. Table 10 shows

the input shift register data format for the RF R counter and the

divide ratios possible.

RF Prescaler Value

P14 and P15 in the RF N counter latch set the RF prescaler

values. See Table 11.

RF Power-Down

RF Phase Detector Polarity

Table 11 shows the power-down bits in the ADF4212L.

P9 sets the IF phase detector polarity. When the RF VCO

characteristics are positive, P9 should be set to 1. When they are

negative, it should be set to 0 (see Table 10).

RF Fastlock

The RF CP gain bit (P17) of the RF N counter latch register in

the ADF4212L is the fastlock enable bit. Only when P17 is set to

1 is IF fastlock enabled. When fastlock is enabled, the RF CP

current is set to the maximum value. Also, an extra loop filter

damping resistor to ground is switched in using the FL_Opin,

thus compensating for the change in loop characteristics while

in fastlock. Because the RF CP gain bit is contained in the RF N

counter, only one write is needed to both program a new output

frequency and initiate fastlock. To come out of fastlock, the RF

CP gain bit on the RF N counter latch register must be set to 0.

See Table 11.

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when

programmed to a 1. It should be set to 0 for normal operation

(see Table 10).

RF Program Modes

Table 10 shows how to set up the program modes in the

ADF4212L.

Rev. B | Page 21 of 28

ADF4212L

APPLICATIONS INFORMATION

200 kHz (the GSM standard), the reference input must be

divided by 65, using the on-chip reference.

LOCAL OSCILLATOR FOR GSM HANDSET RECEIVER

Figure 31 shows the ADF4212L being used with a VCO to pro-

duce the required LOs for a GSM base station transmitter or

receiver. The reference input signal is applied to the circuit at

FREF_INand, in this case, is terminated in 50 Ω. Typical GSM

systems have a 13 MHz TCXO driving the reference input

without any 50 Ω termination. To have a channel spacing of

The RF output frequency range is 880 MHz to 915 MHz. The

loop filter is designed to give a 20 kHz loop bandwidth. The

filter is set up for a 5 mA charge pump current, and the VCO

sensitivity is 12 MHz/V. The IF output is fixed at 540 MHz. The

filter is again designed to have a bandwidth of 20 kHz, and the

system is programmed to give channel steps of 200 kHz.

RF

IFOUT

OUT

V

P

DD

P

100pF

18Ω

V 2

2

V

1

DD

V 1

P

100pF

DD

P

100pF

3.3kΩ

18Ω

V

CC

CP

RF

IF

VCO190-540T

VCO190-902U

18Ω

620pF

1.3nF

620pF

1nF

1.7kΩ

5.6kΩ

ADF4212L

8.2nF

13nF

R

SET

2.7kΩ

LOCK

DETECT

MUXOUT

RF

100pF

IF

IN

51Ω

51V

CLK

DATA

LE

100pF 100pF

SPI-COMPATIBLE SERIAL BUS

FREF

IN

REF

IN

51Ω

DECOUPLING CAPACITORS (22µF/10pF) ON V , V OF THE ADF4212L AND ON V OF THE VCOs

DD CC

P

HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 31. GSM Handset Receiver Local Oscillator Using the ADF4212L

Rev. B | Page 22 of 28

ADF4212L

MHz, I_CPof 10 mA (2.5 mA synthesizer I_CPmultiplied by the gain

factor of 4), VCO K_Dof 80 MHz/V (sensitivity of the M3500-1324

at an output of 2100 MHz), and a phase margin of 45 degrees.

WIDEBAND PLL

Many of the wireless applications for synthesizers and VCOs in

PLLs are narrow band in nature. These applications include the

various wireless standards such as GSM, DSC1800, CDMA, or

WCDMA. In each of these cases, the total tuning range for the

LO is less than 100 MHz. However, there are also wideband

applications where the LO can have up to an octave tuning

range. For example, cable television tuners have a total range

of about 400 MHz. Figure 32 shows an application where the

ADF4212L is used to control and program the Micronetics

M3500-1324. The loop filter was designed for an RF output of

2100 MHz, a loop bandwidth of 40 kHz, a PFD frequency of 1

In narrow-band applications, there is generally a small variation

in output frequency (generally less than 10%) and a small variation

in VCO sensitivity over the range (typically <10%). However, in

wideband applications, both of these parameters have a much

greater variation, which changes the loop bandwidth. This, in turn,

can affect stability and lock time. By changing the programma-

ble I_CP, it is possible to obtain compensation for these varying loop

conditions and to ensure that the loop is always operating close

to optimal conditions.

RF

OUT

12V

V

20V

DD

P

100pF

V

3kΩ

AD820

CC

1kΩ

100pF

18Ω

V 1 V 2

V

1

V

DD

2

DD

P

V_TUNE

M3500-1324

GND

OUT

20kΩ

CP

RF

1000pF 1000pF

FREF

IN

REF

IN

3.9nF

27nF

130pF

R

SET

51Ω

2.7kΩ

470Ω

ADF4212L

CLK

DATA

LE

LOCK

DETECT

SPI-COMPATIBLE SERIAL BUS

MUXOUT

100pF

RF

IN

51Ω

DECOUPLING CAPACITORS ON V

DDx

AND V OF THE ADF4212L, ON +V OF THE AD820,

Px

S

AND ON V

OF THE M3500-1324 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

CC

THE IF SECTION OF THE CIRCUIT HAS ALSO BEEN OMITTED TO SIMPLIFY THE SCHEMATIC.

Figure 32. Wideband PLL Circuit

Rev. B | Page 23 of 28

ADF4212L

three 8-bit bytes, enable the autobuffered mode, and then write

to the transmit register of the DSP. This last operation initiates

the autobuffer transfer.

INTERFACING

The ADF4212L has a simple SPI-compatible interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When latch enable (LE) goes high, the 22 bits that have

been clocked into the input register on each rising edge of CLK are

transferred to the appropriate latch. See Figure 2 for the timing

diagram and Table 6 for the latch truth table.

ADuC812

SCLOCK

MOSI

ADF4212L

CLK

DATA

LE

I/O PORTS

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 909 kHz or

one update every 1.1 μs, which is more than adequate for systems

that have typical lock times in hundreds of microseconds.

MUXOUT

(LOCK DETECT)

Figure 33. ADuC812 to ADF4212L Interface

ADuC812 Interface

ADSP-21xx

ADF4212L

Figure 33 shows the interface between the ADF4212L and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI (serial

port interface) master mode with CPHA = 0. To initiate the

operation, the I/O port driving LE is brought low. Each latch of

the ADF4212L needs a 24-bit word. This is accomplished by

writing three 8-bit bytes from the microconverter to the device.

When the third byte has been written, the LE input should be

brought high to complete the transfer.

SCLOCK

DT

CLK

DATA

LE

TFS

MUXOUT

(LOCK DETECT)

I/O FLAGS

Figure 34. ADSP-21xx to ADF4212L Interface

PCB DESIGN GUIDELINES FOR LEAD FRAME CHIP

SCALE PACKAGE

When first applying power to the ADF4212L, four writes (one

each to the R counter latch and the N counter latch for both the

IF and RF sides) are required for the output to become active.

The lands on the LFCSP (CP-20-1) are rectangular. The printed

circuit board (PCB) pad for these should be 0.1 mm longer than

the package land length and 0.05 mm wider than the package

land width. The land should be centered on the pad. This ensures

that the solder joint size is maximized. The bottom of the LFCSP

has a central thermal pad.

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed is 180 kHz.

The thermal pad on the PCB should be at least as large as the

exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

ADSP-2181 Interface

Figure 34 shows the interface between the ADF4212L and the

ADSP-21xx digital signal processor. As previously described,

the ADF4212L needs a 24-bit serial word for each latch write.

The easiest way to accomplish this with the ADSP-21xx family

is to use the autobuffered transmit mode of operation with

alternate framing. This provides a means for transmitting an

entire block of serial data before an interrupt is generated. Set

up the word length for eight bits and use three memory locations

for each 24-bit word. To program each 24-bit latch, store the

Thermal vias can be used on the PCB thermal pad to improve

thermal performance of the package. If vias are used, they

should be incorporated in the thermal pad at 1.2 mm pitch grid.

The via diameter should be between 0.3 mm and 0.33 mm, and

the via barrel should be plated with 1 oz copper to plug the via.

The user should connect the PCB thermal pad to PCB ground.

Rev. B | Page 24 of 28

ADF4212L

OUTLINE DIMENSIONS

6.60

6.50

6.40

20

11

10

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

COPLANARITY

0.10

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 35. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

0.60 MAX

4.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

15

16

20

1

5

0.50

BSC

PIN 1

INDICATOR

2.25

2.10 SQ

1.95

3.75

BCS SQ

EXPOSED

PAD

(BOTTOM VIEW)

10

6

11

0.75

0.60

0.50

0.25 MIN

TOP VIEW

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 36. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

Rev. B | Page 25 of 28

ADF4212L

ORDERING GUIDE

Model

ADF4212LBRU

Temperature Range

−40°C to +85°C

Package Description

20-Lead TSSOP

Package Option

RU-20

ADF4212LBRU-REEL

ADF4212LBRU-REEL7

ADF4212LBRUZ¹

ADF4212LBRUZ-RL¹

ADF4212LBRUZ-RL7¹

ADF4212LBCP

ADF4212LBCP-REEL

ADF4212LBCP-REEL7

ADF4212LBCPZ¹

20-Lead TSSOP

RU-20

20-Lead LFCSP_VQ

CP-20-1

ADF4212LBCPZ-RL¹

ADF4212LBCPZ-RL7¹

¹Z = RoHS Compliant Part.

Rev. B | Page 26 of 28

ADF4212L

NOTES

Rev. B | Page 27 of 28

ADF4212L

NOTES

registered trademarks are the property of their respective owners.

D02774-0-9/08(B)

Rev. B | Page 28 of 28


型号：	ADF4212LBCP-REEL7
厂家：	ADI
描述：	IC PLL FREQUENCY SYNTHESIZER, 2400 MHz, QCC20, 4 X 4 MM, MO-220VGGD-1, LFCSP-20, PLL or Frequency Synthesis Circuit
文件：	总28页 (文件大小：367K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF4212LBCP-REEL7 [ADI]

相关型号：

ADF4212LBCPZ-REEL

ADF4212LBCPZ-REEL7

ADF4212LBCPZ-RL7

ADF4212LBRU

ADF4212LBRU-REEL

ADF4212LBRU-REEL7

ADF4212LBRUZ

ADF4212LBRUZ-REEL

ADF4212LBRUZ-REEL7

ADF4212LBRUZ-RL

ADF4212LBRUZ-RL7

ADF4212_15