ADF4251BCP [ADI]

Dual Fractional-N/Integer-N Frequency Synthesizer; 双小数N /整数N频率合成器
ADF4251BCP
型号: ADF4251BCP
厂家: ADI    ADI
描述:

Dual Fractional-N/Integer-N Frequency Synthesizer
双小数N /整数N频率合成器

信号电路 锁相环或频率合成电路
文件: 总28页 (文件大小:425K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Dual Fractional-N/Integer-N  
Frequency Synthesizer  
ADF4251  
FEATURES  
GENERAL DESCRIPTION  
3.0 GHz Fractional-N/1.2 GHz Integer-N  
2.7 V to 3.3 V Power Supply  
Separate VP Allows Extended Tuning Voltage to 5 V  
Programmable Dual Modulus Prescaler  
RF: 4/5, 8/9  
IF: 8/9, 16/17, 32/33, 64/65  
Programmable Charge Pump Currents  
3-Wire Serial Interface  
Digital Lock Detect  
Power-Down Mode  
Programmable Modulus on Fractional-N Synthesizer  
Trade-Off Noise versus Spurious Performance  
Software and Hardware Power-Down  
The ADF4251 is a dual fractional-N/integer-N frequency  
synthesizer that can be used to implement local oscillators  
(LO) in the upconversion and downconversion sections of  
wireless receivers and transmitters. Both the RF and IF syn-  
thesizers consist of a low noise digital PFD (phase frequency  
detector), a precision charge pump, and a programmable refer-  
ence divider. The RF synthesizer has a -based fractional  
interpolator that allows programmable fractional-N division.  
The IF synthesizer has programmable integer-N counters. A  
complete PLL (phase-locked loop) can be implemented if the  
synthesizer is used with an external loop filter and VCO (volt-  
age controlled oscillator).  
Control of all the on-chip registers is via a simple 3-wire inter-  
face. The devices operate with a power supply ranging from  
2.7 V to 3.3 V and can be powered down when not in use.  
APPLICATIONS  
Base Stations for Mobile Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA,  
PHS)  
Wireless LANs  
Communications Test Equipment  
CATV Equipment  
FUNCTIONAL BLOCK DIAGRAM  
V
1
V
2
V
3
DV  
V 1  
V 2  
R
SET  
DD  
DD  
DD  
DD  
P
P
CE  
CP  
ADF4251  
REFERENCE  
4-BIT R  
2  
COUNTER  
REF  
PHASE  
IN  
DOUBLER  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
RF  
LOCK  
OUTPUT  
MUXOUT  
DETECT  
MUX  
RF  
RF  
A
IN  
FRACTIONAL N  
RF DIVIDER  
B
IN  
CLK  
DATA  
LE  
24-BIT  
DATA  
REGISTER  
INTEGER N  
IF DIVIDER  
IF  
IF  
B
IN  
FROM  
REFIN  
A
IN  
PHASE  
CHARGE  
PUMP  
CP  
FREQUENCY  
DETECTOR  
IF  
2  
15-BIT R  
DOUBLER  
COUNTER  
A
1
A
2
D
CP  
1
CP  
2
GND  
GND  
GND  
GND  
GND  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
(VDD1 = VDD2 = V 3 = DVDD = 3 V 10%, V 1 = V 2 = 5 V 10%, GND = 0 V,  
ADF4251–SPECIFICATIONS1 RSET = 2.7 k, dDBDm referred to 50 , TA = PTMIN toPTMAX, unless otherwise noted.)  
Parameter  
B Version  
Unit  
Test Conditions/Comments  
RF CHARACTERISTICS  
RF Input Frequency (RFINA, RFINB)2  
RF Input Sensitivity  
0.25/3.0  
10/0  
0.1/3.0  
30  
GHz min/max  
dBm min/max  
GHz min/max  
MHz max  
RF Input Frequency (RFINA, RFINB)2  
RF Phase Detector Frequency  
Allowable Prescaler Output Frequency  
Input Level = 8/0 dBm min/max  
Guaranteed by Design  
375  
MHz max  
IF CHARACTERISTICS  
IF Input Frequency (IFINA, IFINB)2  
IF Input Sensitivity  
50/1200  
10/0  
55  
MHz min/max  
dBm min/max  
MHz max  
IF Phase Detector Frequency  
Allowable Prescaler Output Frequency  
Guaranteed by Design  
150  
MHz max  
REFERENCE CHARACTERISTICS  
REFIN Input Frequency  
250  
MHz max  
For f < 10 MHz, use dc-coupled square  
wave (0 to VDD).  
REFIN Input Sensitivity  
0.5/VDD  
1
V p-p min/max AC-coupled. When dc-coupled, use  
0 to VDD max (CMOS compatible).  
REFIN Input Current  
REFIN Input Capacitance  
100  
10  
µA max  
pF max  
CHARGE PUMP  
RF ICP Sink/Source  
High Value  
4.375  
625  
5
625  
1
2
2
mA typ  
µA typ  
mA typ  
µA typ  
nA typ  
% typ  
See Table V  
See Table IX  
Low Value  
High Value  
Low Value  
IF ICP Sink/Source  
ICP Three-State Leakage Current  
RF Sink and Source Current Matching  
IF Sink and Source Current Matching  
0.5 V < VCP < VP 0.5  
% typ  
I
CP vs. VCP  
2
2
% typ  
% typ  
0.5 V < VCP < VP 0.5  
VCP = VP /2  
ICP vs. Temperature  
LOGIC INPUTS  
VINH, Input High Voltage  
1.35  
0.6  
1
V min  
V
INL, Input Low Voltage  
V max  
µA max  
pF max  
IINH/IINL, Input Current  
CIN Input Capacitance  
10  
LOGIC OUTPUTS  
VOH, Output High Voltage  
VOL, Output Low Voltage  
VDD 0.4  
0.4  
V min  
V max  
IOH = 0.2 mA  
IOL = 0.2 mA  
POWER SUPPLIES  
V
DD1, VDD2, VDD  
3
2.7/3.3  
V min/V max  
DVDD  
VDD1  
VDD1/5.5  
13  
10  
4
VP1, VP2  
V min/V max  
mA typ  
mA typ  
3
IDD  
RF + IF  
RF Only  
IF Only  
16 mA max  
13 mA max  
5.5 mA max  
mA typ  
Low Power Sleep Mode/Power-Down  
10  
pA typ  
RF NOISE AND SPURIOUS CHARACTERISTICS  
Noise Floor  
141  
dBc/Hz typ  
@ 20 MHz PFD Frequency  
@ VCO Output  
RFOUT = 1.8 GHz, PFD = 20 MHz  
RFOUT = 1.8 GHz, PFD = 20 MHz  
RFOUT = 1.8 GHz, PFD = 20 MHz  
See Typical Performance Characteristics  
In-Band Phase Noise Performance4  
Lowest Spur Mode  
90  
95  
103  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
Low Noise and Spur Mode  
Lowest Noise Mode  
Spurious Signals  
NOTES  
1Operating Temperature Range (B Version): 40°C to +85°C.  
2Use a square wave for frequencies less than FMIN  
.
3RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, VDD = 3 V, VP1 = 5 V, and VP2 = 3 V.  
4The in-band phase noise is measured with the EVAL-ADF4251EB2 Evaluation Board and the HP5500E Phase Noise Test System. The spectrum analyzer provides the  
REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). FOUT = 1.74 GHz, FREF = 20 MHz, N = 87, MOD = 100, Channel Spacing = 200 kHz, VDD = 3.3 V, and VP = 5 V.  
Specifications subject to change without notice.  
–2–  
REV. 0  
ADF4251  
TIMING CHARACTERISTICS*(VDD1 = VDD2 = VDD3 = DVDD = 3 V 10%, VP1 = VP2 = 5 V 10%, GND = 0 V, unless otherwise noted.)  
Limit at  
TMIN to TMAX  
(B Version)  
Parameter  
Unit  
Test Conditions/Comments  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
10  
10  
10  
25  
25  
10  
20  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
LE Setup Time  
DATA to CLOCK Setup Time  
DATA to CLOCK Hold Time  
CLOCK High Duration  
CLOCK Low Duration  
CLOCK to LE Setup Time  
LE Pulsewidth  
*Guaranteed by design but not production tested.  
t4  
t5  
CLOCK  
t2  
t3  
DB1  
DB23  
DATA  
DB22  
DB2  
DB0 (LSB)  
(CONTROL BIT C1)  
(CONTROL BIT C2)  
(MSB)  
t7  
LE  
t1  
t6  
LE  
Figure 1. Timing Diagram  
REV. 0  
–3–  
ADF4251  
ABSOLUTE MAXIMUM RATINGS1, 2  
NOTES  
1Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only and functional operation of  
the device at these or any other conditions above those listed in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
2This device is a high performance RF integrated circuit with an ESD rating  
of <2 kW, and it is ESD sensitive. Proper precautions should be taken for handling  
and assembly.  
(TA = 25°C, unless otherwise noted.)  
VDD1, VDD2, VDD3, DVDD to GND3 . . . . . . . . –0.3 V to +4 V  
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V  
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V  
VP1, VP2 to VDD  
1 . . . . . . . . . . . . . . . . . . . . . –3.3 V to +3.5 V  
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V  
Analog I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V  
Operating Temperature Range  
3GND = CPGND1, AGND1, DGND, AGND2, and CPGND2.  
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C  
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C  
LFCSP JA Thermal Impedance . . . . . . . . . . . . . . . . 122°C/W  
Soldering Reflow Temperature  
PIN CONFIGURATION  
Vapor Phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240°C  
IR Reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240°C  
CP  
1
18 CP  
17 DV  
16 IF  
2
GND  
PIN 1  
RF  
INDICATOR  
CP  
1 2  
GND  
DD  
RF A 3  
A
IN  
IN  
ADF4251  
15 IF  
B
RF B 4  
IN  
IN  
TOPVIEW  
A
1 5  
14 A  
13 R  
2
GND  
GND  
(Not to Scale)  
MUXOUT 6  
SET  
ORDERING GUIDE  
Model  
Temperature Range  
Package Option*  
ADF4251BCP  
ADF4251BCP-REEL  
ADF4251BCP-REEL7  
–40ºC to +85ºC  
–40ºC to +85ºC  
–40ºC to +85ºC  
CP-24  
CP-24  
CP-24  
*CP = Lead Frame Chip Scale Package  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection. Although the  
ADF4251 features proprietary ESD protection circuitry, permanent damage may occur on devices  
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended  
to avoid performance degradation or loss of functionality.  
–4–  
REV. 0  
ADF4251  
PIN FUNCTION DESCRIPTIONS  
Mnemonic  
CPRF  
Function  
RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.  
RF Charge Pump Ground  
CPGND1  
RFINA  
Input to the RF Prescaler. This small signal input is normally taken from the VCO.  
Complementary Input to the RF Prescaler  
RFINB  
AGND1  
Analog Ground for the RF Synthesizer  
MUXOUT  
REFIN  
CE  
This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference fre-  
quency to be accessed externally.  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of  
100 kW. This input can be driven from a TTL or CMOS crystal oscillator.  
Chip Enable. A Logic Low on this bit powers down the device and puts the charge pump outputs into three-state.  
A Logic High on this pin powers up the device, depending on the status of the software power-down bits.  
DGND  
CLK  
Digital Ground for the Fractional Interpolator  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the  
shift register on the CLK rising edge. This input is a high impedance CMOS input.  
DATA  
LE  
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a  
high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the  
seven latches, the latch being selected using the control bits.  
RSET  
Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship  
between ICP and RSET is:  
1.6875  
RSET  
ICP MIN  
=
Therefore, with RSET = 2.7 kW, ICP MIN = 0.625 mA.  
Ground for the IF Synthesizer  
AGND2  
IFINB  
IFINA  
DVDD  
Complementary Input to the IF Prescaler  
Input to the IF Prescaler. This small signal input is normally taken from the IF VCO.  
Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should  
be placed as close as possible to this pin. DVDD must have the same voltage as VDD1, VDD2, and VDD3.  
CPGND2  
CPIF  
IF Charge Pump Ground  
IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.  
VP2  
IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible  
to this pin. This voltage should be greater than or equal to VDD2.  
V
V
V
DD2  
DD3  
DD1  
Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as  
possible to this pin. VDD2 has a value 3 V 10ꢀ. VDD2 must have the same voltage as VDD1, VDD3, and DVDD  
Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close  
as possible to this pin. VDD3 has a value 3 V 10ꢀ. VDD3 must have the same voltage as VDD1, VDD2, and DVDD  
Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close  
as possible to this pin. VDD1 has a value 3 V 10ꢀ. VDD1 must have the same voltage as VDD2, VDD3, and DVDD  
.
.
.
VP1  
RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible  
to this pin. This voltage should be greater than or equal to VDD1.  
REV. 0  
–5–  
ADF4251  
V
1
V
2
V
3
DV  
V 1  
V 2  
R
SET  
DD  
DD  
DD  
DD  
P
P
CE  
CP  
ADF4251  
REFERENCE  
4-BIT R  
2  
COUNTER  
REF  
PHASE  
IN  
DOUBLER  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
RF  
LOCK  
OUTPUT  
MUXOUT  
DETECT  
MUX  
RF  
RF  
A
IN  
FRACTIONAL N  
RF DIVIDER  
B
IN  
CLK  
DATA  
LE  
24-BIT  
DATA  
REGISTER  
INTEGER N  
IF DIVIDER  
IF  
IF  
B
IN  
FROM  
REFIN  
A
IN  
PHASE  
CHARGE  
PUMP  
CP  
FREQUENCY  
DETECTOR  
IF  
2  
15-BIT R  
DOUBLER  
COUNTER  
A
1
A
2
D
CP  
1
CP  
2
GND  
GND  
GND  
GND  
GND  
Figure 2. Detailed Functional Block Diagram  
–6–  
REV. 0  
Typical Performance Characteristics–ADF4251  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
V
= 3V, V = 5V  
P
= 1.875mA  
V
= 3V, V = 5V  
DD  
DD P  
I
I
= 1.875mA  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
REFERENCE  
REFERENCE  
CP  
CP  
LEVEL = 4.2dBm  
LEVEL = 4.2dBm  
PFD FREQUENCY = 10MHz  
PFD FREQUENCY = 10MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
RBW = 10Hz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
RBW = 1kHz  
–50dBc@  
100kHz  
99.19dBc/Hz  
–400kHz  
–200kHz 1.7518GHz  
FREQUENCY  
200kHz  
400kHz  
–2kHz  
–1kHz  
1.7518GHz  
1kHz  
2kHz  
FREQUENCY  
TPC 1. Phase Noise Plot, Lowest Noise Mode,  
1.7518 GHz RFOUT, 10 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
TPC 4. Spurious Plot, Lowest Noise Mode,  
1.7518 GHz RFOUT, 10 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
0
0
V
= 3V, V = 5V  
P
= 1.875mA  
V
= 3V, V = 5V  
= 1.875mA  
DD  
DD P  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
I
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
I
REFERENCE  
REFERENCE  
CP  
CP  
PFD FREQUENCY = 10MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
LEVEL = 4.2dBm  
PFD FREQUENCY = 10MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
LEVEL = 4.2dBm  
RBW = 10Hz  
RBW = 1kHz  
–51dBc@  
100kHz  
–90.36dBc/Hz  
–2kHz  
–1kHz  
1.7518GHz  
FREQUENCY  
1kHz  
2kHz  
–400kHz  
–200kHz 1.7518GHz  
FREQUENCY  
200kHz  
400kHz  
TPC 2. Phase Noise Plot, Low Noise and Spur  
Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
TPC 5. Spurious Plot, Low Noise and Spur Mode,  
1.7518 GHz RFOUT, 10 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
0
0
V
= 3V, V = 5V  
P
= 1.875mA  
V
= 3V, V = 5V  
= 1.875mA  
DD  
DD P  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
I
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
I
REFERENCE  
REFERENCE  
CP  
CP  
PFD FREQUENCY = 10MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
LEVEL = 4.2dBm  
PFD FREQUENCY = 10MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
LEVEL = 4.2dBm  
RBW = 10Hz  
RBW = 1kHz  
–72dBc@  
100kHz  
–85.86dBc/Hz  
–2kHz  
–1kHz  
1.7518GHz  
FREQUENCY  
1kHz  
2kHz  
–400kHz  
–200kHz 1.7518GHz  
FREQUENCY  
200kHz  
400kHz  
TPC 3. Phase Noise Plot, Lowest Spur Mode,  
1.7518 GHz RFOUT, 10 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
TPC 6. Spurious Plot, Lowest Spur Mode,  
1.7518 GHz RFOUT, 10 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
TPCs 112 attained using EVAL-ADF4252EB1 Evaluation Board; measurements from HP8562E spectrum analyzer.  
REV. 0  
–7–  
ADF4251  
0
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
V
CP  
= 3V, V = 5V  
P
V
CP  
= 3V, V = 5V  
DD  
DD P  
I
= 1.875mA  
I
= 1.875mA  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
REFERENCE  
REFERENCE  
PFD FREQUENCY = 20MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
PFD FREQUENCY = 20MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
LEVEL = 4.2dBm  
LEVEL = 4.2dBm  
RBW = 10Hz  
RBW = 1kHz  
–53dBc@  
100kHz  
–102dBc/Hz  
–400kHz  
–200kHz 1.7518GHz  
FREQUENCY  
200kHz  
400kHz  
–2kHz  
–1kHz  
1.7518GHz  
1kHz  
2kHz  
FREQUENCY  
TPC 7. Phase Noise Plot, Lowest Noise Mode,  
1.7518 GHz RFOUT, 20 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
TPC 10. Spurious Plot, Lowest Noise Mode,  
1.7518 GHz RFOUT, 20 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
0
0
V
CP  
= 3V, V = 5V  
P
V
CP  
= 3V, V = 5V  
DD  
DD P  
I
= 1.875mA  
I
= 1.875mA  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
REFERENCE  
REFERENCE  
PFD FREQUENCY = 20MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
PFD FREQUENCY = 20MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
LEVEL = 4.2dBm  
LEVEL = 4.2dBm  
RBW = 10Hz  
RBW = 1kHz  
–63.2dBc@  
100kHz  
–93.86dBc/Hz  
–2kHz  
–1kHz  
1.7518GHz  
1kHz  
2kHz  
–400kHz  
–200kHz 1.7518GHz  
FREQUENCY  
200kHz  
400kHz  
FREQUENCY  
TPC 8. Phase Noise Plot, Low Noise and Spur  
Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
TPC 11. Spurious Plot, Low Noise and Spur Mode,  
1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz  
Channel Step Resolution  
0
0
V
CP  
= 3V, V = 5V  
P
V
CP  
= 3V, V = 5V  
DD  
DD P  
I
= 1.875mA  
I
= 1.875mA  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
REFERENCE  
REFERENCE  
PFD FREQUENCY = 20MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
PFD FREQUENCY = 20MHz  
CHANNEL STEP = 200kHz  
LOOP BANDWIDTH = 20kHz  
FRACTION = 59/100  
LEVEL = 4.2dBm  
LEVEL = 4.2dBm  
RBW = 10Hz  
RBW = 1kHz  
–72.33dBc@  
100kHz  
–89.52dBc/Hz  
–2kHz  
–1kHz  
1.7518GHz  
FREQUENCY  
1kHz  
2kHz  
–400kHz  
–200kHz 1.7518GHz  
FREQUENCY  
200kHz  
400kHz  
TPC 9. Phase Noise Plot, Lowest Spur Mode,  
1.7518 GHz RFOUT, 20 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
TPC 12. Spurious Plot, Lowest Spur Mode,  
1.7518 GHz RFOUT, 20 MHz PFD Frequency,  
200 kHz Channel Step Resolution  
–8–  
REV. 0  
ADF4251  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–70  
–75  
–80  
–85  
LOWEST SPUR MODE  
–90  
LOWEST NOISE MODE  
LOWEST SPUR MODE  
–95  
–100  
–105  
–110  
–115  
–120  
LOW NOISE AND SPUR MODE  
LOWEST NOISE MODE  
–110  
–120  
1.430  
1.435  
1.440  
FREQUENCY – GHz  
1.445  
1.450  
1.455  
1.460  
1.460  
1.460  
1.430  
1.435  
1.440  
1.445  
1.450  
1.455  
1.460  
FREQUENCY – GHz  
TPC 16. 400 kHz Spur vs. Frequency*  
TPC 13. In-Band Phase Noise vs. Frequency*  
–10  
–20  
–30  
–40  
–20  
–30  
–40  
–50  
LOWEST NOISE MODE  
–50  
–60  
LOWEST NOISE MODE  
LOWEST SPUR MODE  
–60  
–70  
–80  
–90  
–70  
–80  
–90  
–100  
–110  
–120  
–100  
LOWEST SPUR MODE  
–110  
1.430  
1.435  
1.440  
1.445  
1.450  
1.455  
1.460  
1.430  
1.435  
1.440  
1.445  
1.450  
1.455  
FREQUENCY – GHz  
FREQUENCY – GHz  
TPC 17. 600 kHz Spur vs. Frequency*  
TPC 14. 100 kHz Spur vs. Frequency*  
–20  
–30  
–20  
–30  
–40  
–40  
–50  
–50  
–60  
–60  
LOWEST NOISE MODE  
LOWEST SPUR MODE  
–70  
–70  
–80  
–80  
–90  
–90  
–100  
–110  
–120  
–100  
–110  
–120  
LOWEST NOISE MODE  
LOWEST SPUR MODE  
1.430  
1.435  
1.440  
1.445  
1.450  
1.455  
1.460  
1.430  
1.435  
1.440  
1.445  
1.450  
1.455  
FREQUENCY – GHz  
FREQUENCY – GHz  
TPC 18. 3 MHz Spur vs. Frequency*  
TPC 15. 200 kHz Spur vs. Frequency*  
*TPCs 1318: Across all fractional channel steps from f = 0/130 to f = 129/130.  
RFOUT = 1.45 GHz, Int Reg = 55, Ref = 26 MHz, and LBW = 40 kHz. TPCs 1324 attained using EVAL-ADF4252EB2 Evaluation Board.  
REV. 0  
–9–  
ADF4251  
–120  
–130  
–140  
–150  
–160  
–170  
–180  
0
V
= 3V  
DD  
P
V
= 3V  
–5  
–10  
–15  
–20  
–25  
–30  
PRESCALER = 4/5  
PRESCALER = 8/9  
–35  
0
10k  
100k  
1M  
10M  
1
2
3
4
5
6
PHASE DETECTOR FREQUENCY – Hz  
FREQUENCY – GHz  
TPC 22. Phase Noise (Referred to CP Output) vs.  
PFD Frequency, IF Side  
TPC 19. RF Input Sensitivity  
6
4
2
0
V
V
= 3V  
DD  
P
2 = 3V  
5
10  
15  
20  
25  
30  
35  
40  
V
= 3V  
DD  
P
V
1 = 5.5V  
0
–2  
–4  
–6  
0
0.5  
1.0 1.5 2.0  
3.0 3.5 4.0 4.5  
–V  
5.5  
2.5  
CP  
5.0  
–0.4  
0.1  
0.6  
1.1  
1.6  
V
IF INPUT FREQUENCY – GHz  
TPC 23. RF Charge Pump Output Characteristics  
TPC 20. IF Input Sensitivity  
6
4
2
–120  
–130  
–140  
–150  
–160  
V
V
= 3V  
DD  
P
= 5V  
V
V
= 3V  
DD  
P
2 = 3V  
0
–2  
–4  
–6  
–170  
–180  
0
0.5  
1.0  
1.5  
–V  
2.0  
3.0  
2.5  
10k  
100k  
1M  
10M  
V
PHASE DETECTOR FREQUENCY – Hz  
CP  
TPC 24. IF Charge Pump Output Characteristics  
TPC 21. Phase Noise (Referred to CP Output) vs.  
PFD Frequency, RF Side  
–10–  
REV. 0  
ADF4251  
CIRCUIT DESCRIPTION  
Reference Input Section  
REFIN = the reference input frequency, D = RF REFIN Doubler  
Bit, R = the preset divide ratio of the binary 4-bit program-  
mable reference counter (1 to 15), INT = the preset divide ratio of  
the binary 8-bit counter (31 to 255), MOD = the preset modulus  
ratio of binary 12-bit programmable FRAC counter (2 to 4095),  
and FRAC = the preset fractional ratio of the binary 12-bit  
programmable FRAC counter (0 to MOD).  
The reference input stage is shown in Figure 3. SW1 and SW2  
are normally closed switches. SW3 is normally open. When  
power-down is initiated, SW3 is closed and SW1 and SW2 are  
opened. This ensures that there is no loading of the REFIN pin  
on power-down.  
POWER-DOWN  
CONTROL  
RF N DIVIDER  
N = INT + FRAC/MOD  
100kꢂ  
FROM RF  
NC  
TO PFD  
N-COUNTER  
INPUT STAGE  
SW2  
REF  
IN  
NC  
TO R  
BUFFER  
XOEB  
COUNTER  
THIRD-ORDER  
FRACTIONAL  
SW1  
SW3  
INTERPOLATOR  
REF  
OUT  
NO  
FRAC  
INT  
MOD  
REG  
VALUE  
REG  
NC = NORMALLY CLOSED  
NO = NORMALLY OPEN  
Figure 3. Reference Input Stage  
RF and IF Input Stage  
The RF input stage is shown in Figure 4. The IF input stage is  
the same. It is followed by a two-stage limiting amplifier to  
generate the CML clock levels needed for the N counter.  
Figure 5. N Counter  
RF R Counter  
The 4-bit RF R counter allows the input reference frequency  
(REFIN) to be divided down to produce the reference clock to  
the RF PFD. Division ratios from 1 to 15 are allowed.  
1.6V  
BIAS  
GENERATOR  
V
1
DD  
2kꢂ  
2kꢂ  
IF R Counter  
The 15-bit IF R counter allows the input reference frequency  
(REFIN) to be divided down to produce the reference clock to  
the IF PFD. Division ratios from 1 to 32767 are allowed.  
RF  
RF  
A
B
IN  
IF Prescaler (P/P + 1)  
IN  
The dual modulus IF prescaler (P/P + 1), along with the IF A  
and B counters, enables the large division ratio, N, to be realized  
(N = PB + A). Operating at CML levels, it takes the clock from  
the IF input stage and divides it down to a manageable frequency  
for the CMOS IF A and CMOS IF B counters.  
A
GND  
Figure 4. RF Input Stage  
IF A and B Counters  
RF INT Divider  
The RF INT CMOS counter allows a division ratio in the PLL  
feedback counter. Division ratios from 31 to 255 are allowed.  
The IF A CMOS and IF B CMOS counters combine with the  
dual modulus IF prescaler to allow a wide ranging division ratio  
in the PLL feedback counter. The counters are guaranteed to  
work when the prescaler output is 150 MHz or less.  
INT, FRAC, MOD, and R Relationship  
The INT, FRAC, and MOD values, in conjunction with the  
RF R counter, make it possible to generate output frequencies  
that are spaced by fractions of the RF phase frequency detector  
(PFD). The equation for the RF VCO frequency (RFOUT) is  
Pulse Swallow Function  
The IF A and IF B counters, in conjunction with the dual modulus  
IF prescaler, make it possible to generate output frequencies  
that are spaced only by the reference frequency divided by R.  
See the Device Programming after Initial Power-Up section for  
examples. The equation for the IF VCO (IFOUT) frequency is  
Ê
FRACˆ  
RFOUT = FPFD ¥ INT +  
Á
˜
(1)  
MOD  
Ë
¯
IFOUT = P ¥ B + A ¥ F  
(3)  
(
[
)
]
PFD  
where RFOUT is the output frequency of external voltage controlled  
oscillator (VCO).  
where IFOUT = the output frequency of the external voltage controlled  
oscillator (VCO), P = the preset modulus of the IF dual modulus  
prescaler, B = the preset divide ratio of the binary 12-bit counter  
(3 to 4095), and A = the preset divide ratio of the binary 6-bit  
swallow counter (0 to 63). FPFD is obtained using Equation 2.  
1+ D  
R
(
)
(2)  
FPFD = REFIN  
¥
REV. 0  
–11–  
ADF4251  
Phase Frequency Detector (PFD) and Charge Pump  
The PFD takes inputs from the R counter and N counter and  
produces an output proportional to the phase and frequency  
difference between them. Figure 6 is a simplified schematic. The  
PFD includes a delay element that controls the width of the  
antibacklash pulse. This pulse ensures that there is no dead zone  
in the PFD transfer function and minimizes phase noise and  
reference spurs.  
Lock Detect  
MUXOUT can be programmed for two types of lock detect: digital  
and analog. Digital is active high. The N-channel open-drain  
analog lock detect should be operated with an external pull-up  
resistor of 10 kW nominal. When lock has been detected, this  
output will be high with narrow low going pulses.  
Hardware Power-Down/Chip Enable  
In addition to the software power-down methods described on  
pages 21 and 22, the ADF4251 also has a hardware power-  
down feature. This is accessed via the Chip Enable (CE) pin.  
When this pin is Logic High, the device is in normal operation.  
Bringing the CE pin Logic Low will power down the device.  
When this happens, the following events occur:  
1. All active dc current paths are removed.  
2. The RF and IF counters are forced to their load  
state conditions.  
3. The RF and IF charge pumps are forced into three-state mode.  
4. The digital lock detect circuitry is reset.  
U1  
HI  
D1  
UP  
Q1  
+IN  
CLR1  
CHARGE  
PUMP  
DELAY  
CP  
U3  
ELEMENT  
5. The RFIN and IFIN inputs are debiased.  
6. The REFIN input buffer circuitry is disabled.  
7. The serial interface input register remains active and capable  
of loading and latching data.  
CLR2  
D2  
HI  
DOWN  
Q2  
–IN  
Bringing the CE pin back up again to Logic High will reinstate  
normal operation, depending on the software power-down settings.  
U2  
Input Shift Register  
Figure 6. PFD Simplified Schematic  
MUXOUT and Lock Detect  
The output multiplexer on the ADF4251 allows the user to  
access various internal points on the chip. The state of MUXOUT  
is controlled by M4, M3, M2, and M1 in the Master Register.  
Table VI shows the full truth table. Figure 7 shows the MUXOUT  
section in block diagram format.  
Data is clocked in on each rising edge of CLK. The data is  
clocked in MSB first. Data is transferred from the input register  
to one of seven latches on the rising edge of LE. The destination  
latch is determined by the state of the three control bits (C2, C1,  
and C0) in the shift register. These are the three LSBs: DB2,  
DB1, and DB0, as shown in Figure 1. The truth table for these  
bits is shown in Table I. Table II shows a summary of how the  
registers are programmed.  
DV  
DD  
LOGIC LOW  
IF ANALOG LOCK DETECT  
IF R DIVIDER OUTPUT  
IF N DIVIDER OUTPUT  
RF ANALOG LOCK DETECT  
IF/RF ANALOG LOCK DETECT  
IF DIGITAL LOCK DETECT  
LOGIC HIGH  
Table I. Control Bit Truth Table  
C2  
C1  
C0  
Data Latch  
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
RF N Divider Reg  
RF R Divider Reg  
RF Control Reg  
Master Reg  
IF N Divider Reg  
IF R Divider Reg  
IF Control Reg  
MUXOUT  
MUX  
CONTROL  
RF R DIVIDER OUTPUT  
RF N DIVIDER OUTPUT  
THREE STATE OUTPUT  
RF DIGITAL LOCK DETECT  
RF/IF DIGITAL LOCK DETECT  
LOGIC HIGH  
LOGIC LOW  
D
GND  
Figure 7. MUXOUT Circuit  
–12–  
REV. 0  
ADF4251  
Table II. Register Summary  
RF N DIVIDER REG  
CONTROL  
BITS  
8-BIT RF INTEGER VALUE (INT)  
12-BIT RF FRACTIONAL VALUE (FRAC)  
DB23 DB22 DB21  
DB20 DB19 DB18  
N6 N5 N4  
DB17 DB16 DB15  
N3 N2 N1  
DB14 DB13 DB12  
F12 F11 F10  
DB11 DB10  
F9  
F8  
DB9  
F7  
DB8  
F6  
DB7  
F5  
DB6  
F4  
DB5  
F3  
DB4  
F2  
DB3  
F1  
DB2  
DB1  
DB0  
P1  
N8  
N7  
C3 (0) C2 (0) C1 (0)  
RF R DIVIDER REG  
CONTROL  
BITS  
4-BIT RF R COUNTER  
12-BIT INTERPOLATOR MODULUS VALUE (MOD)  
DB20 DB19  
P3 P2  
DB18 DB17 DB16 DB15 DB14 DB13  
R2  
DB12 DB11 DB10  
M8  
DB9  
M7  
DB8  
M6  
DB7  
M5  
DB6  
M4  
DB5  
M3  
DB4  
M2  
DB3  
M1  
DB2  
DB1  
DB0  
C3 (0)  
C2 (0) C1 (1)  
R4  
M12  
M11  
R3  
R1  
M10  
M9  
RF CONTROL REG  
RF CP  
CONTROL  
CURRENT  
SETTING  
RESERVED  
BITS  
DB15 DB14 DB13 DB12 DB11 DB10  
N3 T3 T2 T1 N2 CP2  
DB9  
CP1  
DB8  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
DB0  
0
P8  
N1  
P6  
P5  
P4  
C3 (0) C2 (1) C1 (0)  
MASTER REG  
CONTROL  
BITS  
MUXOUT  
DB10  
M4  
DB9  
DB8  
M2  
DB7  
M1  
DB6  
DB5  
P11  
DB4  
P10  
DB3  
P9  
DB2  
DB1  
DB0  
M3  
C3 (0) C2 (1) C1 (1)  
IF N DIVIDER REG  
CONTROL  
BITS  
12-BIT IF B COUNTER  
6-BIT IF A COUNTER  
IF PRESCALER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10  
DB9  
B1  
DB8  
A6  
DB7  
A5  
DB6  
A4  
DB5  
A3  
DB4  
A2  
DB3  
A1  
DB2  
DB1  
DB0  
P15  
P14  
P13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
C3 (1) C2 (0) C1 (0)  
IF R DIVIDER REG  
CONTROL  
BITS  
15-BIT IF R COUNTER  
DB18 DB17 DB16 DB15 DB14 DB13  
P16 R15 R14 R13 R12 R11  
DB12 DB11 DB10  
R10 R9 R8  
DB9  
R7  
DB8  
R6  
DB7  
R5  
DB6  
R4  
DB5  
R3  
DB4  
R2  
DB3  
R1  
DB2  
DB1  
DB0  
C3 (1) C2 (0) C1 (1)  
IF CONTROL REG  
RF PHASE  
RESYNC  
IF CP CURRENT  
SETTING  
CONTROL  
BITS  
RESERVED  
DB15 DB14 DB13  
DB12 DB11 DB10  
T7 PR1 CP3  
DB9  
CP2  
DB8  
CP1  
DB7  
P21  
DB6  
P20  
DB5  
P19  
DB4  
P18  
DB3  
P17  
DB2  
DB1  
DB0  
PR3  
PR2  
T8  
C3 (1) C2 (1) C1 (0)  
REV. 0  
–13–  
ADF4251  
Table III. RF N Divider Register Map  
CONTROL  
BITS  
8-BIT RF INTEGER VALUE (INT)  
12-BIT RF FRACTIONAL VALUE (FRAC)  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
P1  
N8  
N7  
N6  
N5  
N4  
N3  
N2  
N1  
F12  
F11  
F10  
F9  
F8  
F7  
F6  
F5  
F4  
F3  
F2  
F1  
C1 (0)  
C3 (0) C2 (0)  
F12  
F11  
F10  
F3  
F2  
0
0
1
1
.
F1  
0
1
0
1
.
FRACTIONAL VALUE (FRAC)  
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
..........  
..........  
..........  
..........  
..........  
..........  
..........  
..........  
0
0
0
0
.
.
.
1
0
1
P1  
RESERVED  
RESERVED  
2
3
0
.
.
.
.
.
0
.
0
.
4092  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
4093  
4094  
4095  
RF INTEGER  
VALUE (INT)*  
N8  
N7  
N6  
0
1
1
1
.
N5  
N4  
N3  
1
0
0
0
.
N2  
1
0
0
1
.
N1  
1
0
1
0
.
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
1
0
0
0
.
.
.
1
1
0
0
0
.
.
.
1
31  
32  
33  
34  
.
.
.
.
.
.
.
.
1
.
1
.
0
.
1
253  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
254  
255  
*WHEN P = 8/9, N  
= 91  
MIN  
–14–  
REV. 0  
ADF4251  
Table IV. RF R Divider Register Map  
CONTROL  
BITS  
12-BIT INTERPOLATOR MODULUS VALUE (MOD)  
4-BIT RF R COUNTER  
DB20 DB19 DB18 DB17 DB16 DB15  
DB14 DB13 DB12 DB11 DB10  
DB9  
M7  
DB8  
M6  
DB7  
M5  
DB6  
M4  
DB5  
M3  
DB4  
M2  
DB3  
M1  
DB2  
DB1  
DB0  
C3 (0)  
P3  
P2  
R4  
R3  
R2  
R1  
M12  
M11  
M10  
M9  
C2 (0) C1 (1)  
M8  
INTERPOLATOR MODULUS  
M12  
M11  
M10  
M3  
M2  
M1  
VALUE (MOD) DIVIDE RATIO  
0
0
0
.
.
.
1
0
0
0
.
.
.
1
0
0
0
.
.
.
1
..........  
..........  
..........  
..........  
..........  
..........  
..........  
0
0
1
.
.
.
1
1
1
0
.
.
.
0
0
1
0
.
.
.
0
2
P2  
RF REF  
IN  
DOUBLER  
3
4
.
0
1
DISABLED  
ENABLED  
.
.
4092  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
4093  
4094  
4095  
P3  
RF PRESCALER  
0
1
4/5  
8/9  
RF R COUNTER  
R4  
0
0
0
.
R3  
0
0
0
.
R2  
0
1
1
.
R1  
DIVIDE RATIO  
1
0
1
.
.
.
1
1
2
3
.
.
.
.
.
.
.
1
.
1
.
0
13  
1
1
1
1
1
1
0
1
14  
15  
REV. 0  
–15–  
ADF4251  
Table V. RF Control Register Map  
RF CP  
CONTROL  
BITS  
CURRENT  
SETTING  
RESERVED  
DB15 DB14 DB13 DB12  
DB11 DB10  
CP2  
DB9  
CP1  
DB8  
0
DB7  
P8  
DB6  
N1  
DB5  
P6  
DB4  
P5  
DB3  
P4  
DB2  
DB1  
DB0  
N3  
T3  
T2  
T1  
N2  
C2 (1) C1 (0)  
C3 (0)  
THESE BITS SHOULD  
EACH BE SET TO 0 FOR  
NORMAL OPERATION  
P4  
RF COUNTER  
RESET  
DISABLED  
ENABLED  
0
1
N3  
N2  
N1  
NOISE AND SPUR  
SETTING  
P5  
0
1
RF CP THREE-STATE  
DISABLED  
THREE-STATE  
0
0
1
0
0
1
0
1
1
LOWEST SPUR  
LOW NOISE AND SPUR  
LOWEST NOISE  
P6  
0
1
RF POWER-DOWN  
DISABLED  
ENABLED  
I
(mA)  
CP  
CP2  
CP1  
1.5k  
2.7k  
5.6k  
0
0
1
1
0
1
0
1
1.125  
3.375  
5.625  
7.7875  
0.625  
1.875  
3.125  
4.375  
0.301  
0.904  
1.506  
2.109  
P8  
0
1
RF PD POLARITY  
NEGATIVE  
POSITIVE  
–16–  
REV. 0  
ADF4251  
Table VI. Master Register Map  
CONTROL  
BITS  
MUXOUT  
DB10  
M4  
DB9  
M3  
DB8  
M2  
DB7  
M1  
DB6  
DB5  
P11  
DB4  
P10  
DB3  
P9  
DB2  
DB1  
DB0  
C3 (0)  
C2 (1) C1 (1)  
MUXOUT  
P9  
COUNTER RESET  
M4  
M1  
M3  
M2  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LOGIC LOW  
DISABLED  
ENABLED  
0
1
IF ANALOG LOCK DETECT  
IF R DIVIDER OUTPUT  
IF N DIVIDER OUTPUT  
RF ANALOG LOCK DETECT  
RF/IF ANALOG LOCK DETECT  
IF DIGITAL LOCK DETECT  
LOGIC HIGH  
P10  
CP THREE-STATE  
0
1
DISABLED  
THREE-STATE  
RF R DIVIDER OUTPUT  
RF N DIVIDER OUTPUT  
THREE-STATE OUTPUT  
LOGIC LOW  
P11  
POWER-DOWN  
0
1
DISABLED  
ENABLED  
RF DIGITAL LOCK DETECT  
RF/IF DIGITAL LOCK DETECT  
LOGIC HIGH  
LOGIC LOW  
RESERVED  
P12  
0
THIS BIT SHOULD BE SET TO “0” FOR  
NORMAL OPERATION.  
REV. 0  
–17–  
ADF4251  
Table VII. IF N Divider Register Map  
IF  
12-BIT IF B COUNTER*  
6-BIT IF A COUNTER*  
CONTROL  
BITS  
PRESCALER*  
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12  
DB11 DB10  
B3 B2  
DB9  
B1  
DB8  
A6  
DB7  
A5  
DB6  
A4  
DB5  
A3  
DB4  
A2  
DB3  
A1  
DB2  
DB1  
DB0  
DB20  
B12  
DB23 DB22  
P15  
P14  
DB21  
P13  
C2 (0) C1 (0)  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
C3 (1)  
P14  
P13  
PRESCALER VALUE  
0
0
1
1
0
1
0
1
8/9  
16/17  
32/33  
64/65  
A COUNTER  
DIVIDE RATIO  
A6  
A5  
..........  
A2  
A1  
0
0
0
0
.
0
0
0
0
.
..........  
..........  
..........  
..........  
..........  
..........  
..........  
..........  
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
1
.
1
.
0
.
0
.
P15  
IF CP GAIN  
60  
0
1
DISABLED  
ENABLED  
1
1
1
1
1
1
..........  
..........  
..........  
0
1
1
1
0
1
61  
62  
63  
B12  
B11  
B10  
B3  
B2  
B1  
B COUNTER DIVIDE RATIO  
0
0
.
0
0
.
0
0
.
..........  
..........  
..........  
..........  
..........  
..........  
0
1
.
1
0
.
1
0
.
3
4
.
.
.
.
.
.
.
.
.
1
.
1
.
1
.
1
.
0
.
0
.
4092  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
4093  
4094  
4095  
*N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER THAN OR EQUAL TO A FOR CONTIGUOUS VALUES OF N, NMIN IS (P2 – P) .  
–18–  
REV. 0  
ADF4251  
Table VIII. IF R Divider Register Map  
CONTROL  
15-BIT IF R COUNTER  
BITS  
DB18  
P16  
DB17 DB16 DB15  
DB14  
R12  
DB13 DB12  
R11 R10  
DB11 DB10  
DB9  
R7  
DB8  
R6  
DB7  
R5  
DB6  
R4  
DB5  
R3  
DB4  
R2  
DB3  
R1  
DB2  
DB1  
DB0  
C3 (1)  
R8  
R9  
R14  
R15  
R13  
C2 (0) C1 (1)  
R15  
R14  
R13  
R12  
..........  
..........  
..........  
..........  
..........  
..........  
..........  
..........  
..........  
R3  
0
0
0
1
.
R2  
0
1
1
0
.
R1  
1
0
1
0
.
DIVIDE RATIO  
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
1
0
2
0
3
0
4
0
.
.
.
.
.
.
.
.
1
.
0
.
0
.
.
16380  
32764  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
16381  
16382  
16383  
32765  
32766  
32767  
P16  
IF REF  
IN  
DOUBLER  
DISABLED  
ENABLED  
0
1
REV. 0  
–19–  
ADF4251  
Table IX. IF Control Register Map  
RF PHASE  
RESYNC  
IF CP CURRENT  
SETTING  
CONTROL  
BITS  
RESERVED  
DB15 DB14 DB13 DB12  
DB11 DB10  
CP3  
DB9  
CP2  
DB8  
CP1  
DB7  
P21  
DB6  
P20  
DB5  
P19  
DB4  
P18  
DB3  
P17  
DB2  
DB1  
DB0  
PR3  
PR2  
T8  
T7  
PR1  
C2 (1) C1 (0)  
C3 (1)  
THESE BITS  
SHOULD BE SET  
TO 0 FOR NORMAL  
OPERATION  
P17  
0
1
IF COUNTER RESET  
DISABLED  
ENABLED  
PR3  
0
1
PR2  
0
1
PR1  
0
1
RF PHASE RESYNC  
DISABLED  
ENABLED  
P18  
0
1
IF CP THREE-STATE  
DISABLED  
THREE-STATE  
P19  
0
1
IF POWER-DOWN  
DISABLED  
ENABLED  
I
(mA)  
CP  
IF CP3  
IF CP2  
IF CP1  
1.5k  
1.125  
2.25  
3.375  
4.5  
5.625  
6.75  
7.7875  
9
2.7k  
5.6k  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.625  
1.25  
1.875  
2.5  
3.125  
3.75  
4.375  
5.0  
0.301  
0.602  
0.904  
1.205  
1.506  
1.808  
2.109  
2.411  
P20  
0
1
IF LDP  
3
5
P21  
0
1
IF PD POLARITY  
NEGATIVE  
POSITIVE  
–20–  
REV. 0  
ADF4251  
RF N DIVIDER REGISTER  
(Address R0)  
RF CONTROL REGISTER  
(Address R2)  
With R0[2, 1, 0] set to [0, 0, 0], the on-chip RF N Divider register  
will be programmed. Table III shows the input data format for  
programming this register.  
With R2[2, 1, 0] set to [0, 1, 0], the on-chip RF control register  
will be programmed. Table V shows the input data format for  
programming this register. Upon initialization, DB15DB11  
should all be set to 0.  
8-Bit RF INT Value  
These eight bits control what is loaded as the INT value. This is  
used to determine the overall feedback division factor. It is used in  
Equation 1.  
Noise and Spur Setting  
The noise and spur setting (R2[15, 11, 06]) is a feature that  
allows the user to optimize his or her design either for improved  
spurious performance or for improved phase noise performance.  
When set to [0, 0, 0], the lowest spurs setting is chosen. Here,  
dither is enabled. This randomizes the fractional quantization  
noise so that it looks more like white noise than spurious noise.  
This means that the part is optimized for improved spurious  
performance. This operation would normally be used when the  
PLL closed-loop bandwidth is wide1 for fast-locking applications.  
A wide loop filter does not attenuate the spurs to a level that a  
narrow2 loop bandwidth would. When this bit is set to [0, 0, 1],  
the low noise and spur setting is enabled. Here, dither is disabled.  
This optimizes the synthesizer to operate with improved noise  
performance. However, the spurious performance is degraded in  
this mode compared to lowest spurs setting. To improve noise  
performance even further, another option is available that reduces  
the phase noise. This is the lowest noise setting [1, 1, 1]. As well  
as disabling the dither, it also ensures the charge pump is oper-  
ating in an optimum region for noise performance. This setting is  
extremely useful where a narrow loop filter bandwidth is available.  
The synthesizer ensures extremely low noise and the filter attenu-  
ates the spurs. The Typical Performance Characteristics (TPCs)  
give the user an idea of the trade-off in a typical WCDMA setup  
for the different noise and spur settings.  
12-Bit RF FRAC Value  
These 12 bits control what is loaded as the FRAC value into the  
fractional interpolator. This is part of what determines the overall  
feedback division factor. It is used in Equation 1. The FRAC  
value must be less than or equal to the value loaded into the  
MOD register.  
RF R DIVIDER REGISTER  
(Address R1)  
With R1[2, 1, 0] set to [0, 0, 1], the on-chip RF R Divider register  
will be programmed. Table IV shows the input data format for  
programming this register.  
RF Prescaler (P/P + 1)  
The RF dual-modulus prescaler (P/P +1), along with the INT,  
FRAC, and MOD counters, determine the overall division ratio  
from the RFIN to the PFD input. Operating at CML levels, it  
takes the clock from the RF input stage and divides it down to  
a manageable frequency for the CMOS counters. It is based on  
a synchronous 4/5 core (see Table IV).  
RF REFIN Doubler  
Setting this bit to 0 feeds the REFIN signal directly to the 4-bit  
RF R counter, disabling the doubler. Setting this bit to 1 multiplies  
the REFIN frequency by a factor of 2 before feeding into the 4-  
bit RF R counter. When the doubler is disabled, the REFIN  
falling edge is the active edge at the PFD input to the fractional-N  
synthesizer. When the doubler is enabled, both the rising and  
falling edges of REFIN become active edges at the PFD input.  
RF Counter Reset  
DB3 is the RF counter reset bit for the ADF4251. When this is  
1, the RF synthesizer counters are held in reset. For normal  
operation, this bit should be 0.  
RF Charge Pump Three-State  
This bit puts the charge pump into three-state mode when pro-  
grammed to a 1. It should be set to 0 for normal operation.  
When the doubler is enabled and lowest spur mode is chosen,  
the in-band phase noise performance is sensitive to the REFIN  
duty cycle. The phase noise degradation can be as much as 5 dB  
for REFIN duty cycles outside a 45% to 55% range. The phase  
noise is insensitive to REFIN duty cycle in the lowest noise mode  
and in low noise and spur mode. The phase noise is insensitive  
to REFIN duty cycle when the doubler is disabled.  
RF Power-Down  
DB5 on the ADF4251 provides the programmable power-down  
mode. Setting this bit to a 1 will perform a power-down on both  
the RF and IF sections. Setting this bit to 0 will return the RF  
and IF sections to normal operation. While in software power-  
down, the part will retain all information in its registers. Only  
when supplies are removed will the register contents be lost.  
4-Bit RF R Counter  
The 4-bit RF R counter allows the input reference frequency  
(REFIN) to be divided down to produce the reference clock to  
the phase frequency detector (PFD). Division ratios from 1 to  
15 are allowed.  
When a power-down is activated, the following events occur:  
1. All active RF dc current paths are removed.  
2. The RF synthesizer counters are forced to their load state  
conditions.  
3. The RF charge pump is forced into three-state mode.  
4. The RF digital lock detect circuitry is reset.  
5. The RFIN input is debiased.  
12-Bit Interpolator Modulus  
This programmable register sets the fractional modulus. This is  
the ratio of the PFD frequency to the channel step resolution on  
the RF output.  
6. The input register remains active and capable of loading and  
latching data.  
NOTES  
1Wide loop bandwidth is seen as a loop bandwidth greater than 1/10th of the  
RFOUT channel step resolution (FRES).  
2Narrow loop bandwidth is seen as a loop bandwidth less than 1/10th of the  
RFOUT channel step resolution (FRES).  
REV. 0  
–21–  
ADF4251  
RF Phase Detector Polarity  
IF CP Gain  
DB7 in the ADF4251 sets the RF phase detector polarity.  
When the VCO characteristics are positive, this should be set to 1.  
When they are negative, it should be set to 0.  
When set to 1, this bit changes the IF charge pump current  
setting to its maximum value. When the bit is set to 0, the charge  
pump current reverts back to its previous state.  
RF Charge Pump Current Setting  
IF Prescaler  
DB9 and DB10 set the RF charge pump current setting. This  
should be set to whatever charge pump current the loop filter  
has been designed with (see Table V).  
The dual-modulus prescaler (P/P + 1), along with the IF A and  
IF B counters, determine the overall division ratio, N, to be real-  
ized (N = PB + A) from the IFIN to the IF PFD input. Operating  
at CML levels, it takes the clock from the IF input stage and divides  
it down to a manageable frequency for the CMOS counters. It  
is based on a synchronous 4/5 core. See Equation 2 and Table VII.  
RF Test Modes  
These bits should be set to 0, 0, 0 for normal operation.  
MASTER REGISTER  
IF B and A Counter  
(Address R3)  
The IF A and IF B counters, in conjunction with the dual modu-  
lus prescaler, make it possible to generate output frequencies  
that are spaced only by the reference frequency (REFIN), divided  
by R. The equation for the IFOUT VCO frequency is given in  
Equation 2.  
With R3[2, 1, 0] set to 0, 1, 1, the on-chip master register will be  
programmed. Table VI shows the input data format for program-  
ming the Master Register.  
RF and IF Counter Reset  
DB3 is the counter reset bit for the ADF4251. When this is 1,  
both the RF and IF R, INT, and MOD counters are held in reset.  
For normal operation, this bit should be 0. Upon powering up, the  
DB3 bit needs to be disabled, the INT counter resumes counting  
in closealignment with the R counter. (The maximum error is  
one prescaler cycle).  
IF R DIVIDER REGISTER  
(Address R5)  
With R5[2, 1, 0] set to 1, 0, 1, the on-chip IF R divider register  
will be programmed. Table VIII shows the input data format for  
programming this register.  
IF REFIN Doubler  
Charge Pump Three-State  
Setting this bit to 0 feeds the REFIN signal directly to the 15-bit  
IF R counter. Setting this bit to 1 multiplies the REFIN  
frequency by a factor of 2 before feeding into the 15-bit IF R  
counter.  
This bit puts both the RF and IF charge pump into three-state  
mode when programmed to a 1. It should be set to 0 for normal  
operation.  
Power-Down  
15-Bit IF R Counter  
R3[3] on the ADF4251 provides the programmable power-down  
mode. Setting this bit to a 1 will perform a power-down on both  
the RF and IF sections. Setting this bit to 0 will return the RF  
and IF sections to normal operation. While in software power-  
down, the part will retain all information in its registers. Only  
when supplies are removed will the register contents be lost.  
The 15-bit IF R counter allows the input reference frequency  
(REFIN) to be divided down to produce the reference clock to  
the IF phase frequency detector (PFD). Division ratios from  
1 to 32767 are allowed.  
IF CONTROL REGISTER  
(Address R6)  
When a power-down is activated, the following events occur:  
With R6[2, 1, 0] set to 1, 1, 0, the on-chip IF control register  
will be programmed. Table IX shows the input data format for  
programming this register. Upon initialization, DB15DB11  
should all be set to 0.  
1. All active dc current paths are removed.  
2. The RF and IF counters are forced to their load state conditions.  
3. The RF and IF charge pumps are forced into three-state mode.  
4. The digital lock detect circuitry is reset.  
5. The RFIN input and IFIN input are debiased.  
6. The oscillator input buffer circuitry is disabled.  
7. The input register remains active and capable of loading and  
latching data.  
IF Counter Reset  
DB3 is the IF counter reset bit for the ADF4251. When this is  
1, the IF synthesizer counters are held in reset. For normal  
operation, this bit should be 0.  
MUXOUT Control  
The on-chip multiplexer is controlled by R3[107] on the  
ADF4251. Table VI shows the truth table.  
IF Charge Pump Three-State  
This bit puts the IF charge pump into three-state mode when pro-  
grammed to a 1. It should be set to 0 for normal operation.  
If the user updates the RF control register or the IF control  
register, the MUXOUT contents will be lost. To retrieve the  
MUXOUT signal, the user must write to the Master Register.  
IF Power-Down  
DB5 on the ADF4251 provides the programmable power-down  
mode. Setting this bit to a 1 will perform a power-down on the IF  
section. Setting this bit to 0 will return the section to normal  
operation. While in software power-down, the part will retain all  
information in its registers. Only when supplies are removed will  
the register contents be lost.  
IF N DIVIDER REGISTER  
(Address R4)  
With R4[2, 1, 0] set to [1, 0, 0], the on-chip IF N divider register  
will be programmed. Table VII shows the input data format for  
programming this register.  
–22–  
REV. 0  
ADF4251  
When a power-down is activated, the following events occur:  
and R6 are not programmed so that the rest of the IF circuitry  
remains in power-down.  
1. All active IF dc current paths are removed.  
2. The IF synthesizer counters are forced to their load state  
conditions.  
3. The IF charge pump is forced into three-state mode.  
4. The IF digital lock detect circuitry is reset.  
5. The IFIN input is debiased.  
DEVICE PROGRAMMING AFTER INITIAL POWER-UP  
After initially applying power to the supply pins, there are three  
ways to operate the device.  
RF and IF Synthesizers Operational  
All registers must be written to when powering up both the RF  
and IF synthesizer.  
6. The input register remains active and capable of loading and  
latching data.  
IF Phase Detector Polarity  
RF Synthesizer Operational, IF Power-Down  
It is necessary to write to registers R3, R2, R1, and R0 only  
when powering up the RF synthesizer only. The IF side will  
remain in power-down until registers R6, R5, R4, and R3 are  
written to.  
DB7 in the ADF4251 sets the IF phase detector polarity. When  
the VCO characteristics are positive, this should be set to 1.  
When they are negative, it should be set to 0.  
IF Charge Pump Current Setting  
DB8, DB9, and DB10 set the IF charge pump current setting.  
This should be set to whatever charge pump current the loop  
filter has been designed with (see Table VII).  
IF Synthesizer Operational, RF Power-Down  
It is necessary to write only to registers R6, R5, R4, and R3 when  
powering up the IF synthesizer only. The RF side will remain in  
power-down until registers R3, R2, R1, and R0 are written to.  
IF Test Modes  
These bits should be set to 0, 0 for normal operation.  
RF Synthesizer: An Example  
The RF synthesizer should be programmed as follows:  
RF Phase Resync  
Setting the Phase Resync Bits [15, 14, 11] to 1, 1, 1 enables  
the phase resync feature. With a fractional modulus of M, a  
fractional-N PLL can settle with any one of (2 ϫ ␲)/M valid  
phase offsets with respect to the reference input. This is different  
to integer-N (where the RF output always settles to the same  
static phase offset with respect to the input reference, which is  
zero ideally), but does not matter in most applications where all  
that is required is consistent frequency lock.  
Ê
Ë
FRACˆ  
RFOUT = INT +  
¥ FPFD  
Á
˜
(4)  
MOD  
¯
where RFOUT = the RF frequency output, INT = the integer division  
factor, FRAC = the fractionality, and MOD = the modulus.  
Ê
1+ Dˆ  
FPFD = REFIN  
¥
Á
˜
(5)  
R
Ë
¯
For applications where a consistent phase relationship between  
the output and reference is required (i.e., digital beamforming),  
the ADF4251 fractional-N synthesizer can be used with the phase  
resync feature enabled. This ensures that if the user programs  
the PLL to jump from frequency (and Phase) A to frequency  
(and Phase) B and back again to frequency A, the PLL will return  
to the original phase (Phase A).  
where REFIN = the reference frequency input, D = the RF  
REFIN Doubler Bit, and R = the RF reference division factor.  
For example, in a GSM 1800 system where 1.8 GHz RF frequency  
output (RFOUT) is required, a 13 MHz reference frequency input  
(REFIN) is available and a 200 kHz channel resolution (FRES) is  
required on the RF output.  
REF  
When enabled, it will activate every time the user programs  
register R0 or R1 to set a new output frequency. However, if a  
cycle slip occurs in the settling transient after the phase re-resync  
operation, the phase resync will be lost. This can be avoided by  
delaying the resync activation until the locking transient is close  
to its final frequency. In the IF R Divider register, Bits R5[173]  
are used to set a time interval from when the new channel is pro-  
grammed to the time the resync is activated. Although the time  
interval resolution available from the 15-bit IF R register is one  
REFIN clock cycle, IF R should be programmed to be a value that  
is an integer multiple of the programmed MOD value to set a  
time interval that is at least as long as the RF PLL loops lock time.  
IN  
MOD =  
FRES  
13 MHz  
MOD =  
= 65  
200 kHz  
So, from Equation 5:  
1+ 0  
1
FPFD = 13 MHz ¥  
= 13 MHz  
Ê
FRACˆ  
1.8 GHz = 13 MHz ¥ INT +  
Á
˜
65  
Ë
¯
where INT = 138 and FRAC = 30.  
IF Synthesizer: An Example  
The IF synthesizer should be programmed as follows:  
For example, if REFIN = 26 MHz, MOD = 130 to give 200 kHz  
output steps (FRES), and the RF loop has a settling time of 150 µs,  
then IF R should be programmed to 3900, as:  
26 MHz ¥150 ms = 3900  
IFOUT = P ¥ B + A ¥ F  
(6)  
(
[
)
]
PFD  
Note that if it is required to use the IF synthesizer with phase  
resync enabled on the RF synth, the IF synth must operate with  
a PFD frequency of 26 MHz/3900. In an application where the  
IF synth is not required, the user should ensure that registers R4  
where IFOUT = the output frequency of external voltage controlled  
oscillator (VCO), P = the IF prescaler, B = the B counter value,  
and A = the A counter value.  
Equation 5 applies in this example as well.  
REV. 0  
–23–  
ADF4251  
For example, in a GSM1800 system, where 540 MHz IF fre-  
quency output (IFOUT) is required, a 13 MHz reference frequency  
input (REFIN) is available and a 200 kHz channel resolution  
(FRES) is required on the IF output. The prescaler is set to 16/17.  
IF REFIN doubler is disabled.  
The modulus would be reprogrammed to 65 for GSM1800  
operation (13 MHz/65 = 200 kHz). It is important that the PFD  
frequency remains constant (13 MHz). This allows the user to  
design one loop filter that can be used in both setups without  
running into stability issues. It is the ratio of the RF frequency  
to the PFD frequency that affects the loop design. Keeping this  
relationship constant and instead changing the modulus factor,  
results in a stable filter.  
By Equation 5:  
1+ 0  
R
200 kHz = 13 MHz ¥  
Spurious Optimization and Fastlock  
As mentioned in the Noise and Spur Setting section, the part can  
be optimized for spurious performance. However, in fast-lock-  
ing applications, the loop bandwidth needs to be wide.  
Therefore, the filter does not provide much attenuation of the  
spurious. The programmable charge pump can be used to get  
around this issue. The filter is designed for a narrow loop band-  
width so that steady-state spurious specifications are met. This is  
designed using the lowest charge pump current setting. To  
implement fastlock during a frequency jump, the charge pump  
current is set to the maximum setting for the duration of the jump.  
This has the effect of widening the loop bandwidth, which im-  
proves lock time. When the PLL has locked to the new frequency,  
the charge pump is again programmed to the lowest charge pump  
current setting. This will narrow the loop bandwidth to its origi-  
nal cutoff frequency to allow for better attenuation of the  
spurious than the wide loop bandwidth.  
if R = 65.  
By Equation 6:  
540 MHz = 200 kHz ¥ 16 ¥ B + A  
(
[
)
]
if B = 168 and A = 12.  
Modulus  
The choice of modulus (MOD) depends on the reference signal  
(REFIN) available and the channel resolution (FRES) required at  
the RF output. For example, a GSM system with 13 MHz  
REFIN would set the modulus to 65. This means that the RF  
output resolution (FRES) is the 200 kHz (13 MHz/65) necessary  
for GSM.  
Reference Doubler and Reference Divider  
There is a reference doubler on-chip. This allows the input  
reference signal to be doubled. This is useful for increasing the  
PFD comparison frequency. Making the PFD frequency higher  
improves the noise performance of the system. Doubling the  
PFD frequency will usually result in an improvement in noise  
performance of 3 dB. It is important to note that the PFD can-  
not be operated above 30 MHz. This is due to a limitation in  
the speed of the -circuit of the N divider.  
Spurious SignalsPredicting Where They Will Appear  
Just as in integer-N PLLs, spurs will appear at PFD frequency  
offsets on either side of the carrier (and multiples of the PFD  
frequency). In a fractional-N PLL, spurs will also appear at  
frequencies equal to the RFOUT channel step resolution (FRES).  
The ADF4251 uses a high order fractional interpolator engine.  
This results in spurious signals also appearing at frequencies equal  
to 1/2 of the channel step resolution. For example, examine the  
GSM-1800 setup with a 26 MHz PFD and 200 kHz resolution.  
Spurs will appear at 26 MHz from the RF carrier (at an extremely  
low level due to filtering). Also, there will be spurs at 200 kHz from  
the RF carrier. Due to the fractional interpolator architecture  
used in the ADF4251, spurs will also appear at 100 kHz from  
the RF carrier. Harmonics of all spurs mentioned will also appear.  
With lowest spur setting enabled, the spurs will be attenuated  
into the noise floor.  
12-Bit Programmable Modulus  
Unlike most other fractional-N PLLs, the ADF4251 allows the  
user to program the modulus over a 12-bit range. This means  
that the user can set up the part in many different configurations  
for his or her application, when combined with the reference  
doubler and the 4-bit R counter.  
Take for example an application that requires 1.75 GHz RF and  
200 kHz channel step resolution. The system has a 13 MHz  
reference signal.  
One possible setup is feeding the 13 MHz directly to the PFD  
and programming the modulus to divide by 65. This would result  
in the required 200 kHz resolution.  
Prescaler  
The prescaler limits the INT value. With P = 4/5, NMIN = 31.  
With P = 8/9, NMIN = 91.  
Another possible setup is using the reference doubler to create  
26 MHz from the 13 MHz input signal. This 26 MHz is then  
fed into the PFD. The modulus is now programmed to divide by  
130. This also results in 200 kHz resolution. This would offer  
superior phase noise performance over the previous setup.  
The prescaler can also influence the phase noise performance.  
If INT < 91, a prescaler of 4/5 should be used. For applications  
where INT > 91, P = 8/9 should be used for optimum noise  
performance.  
Filter Design: ADIsimPLL  
The programmable modulus is also very useful for multistandard  
applications. If a dual-mode phone requires PDC and GSM1800  
standards, the programmable modulus is of huge benefit. PDC  
requires 25 kHz channel step resolution, whereas GSM1800  
requires 200 kHz channel step resolution. A 13 MHz reference  
signal could be fed directly to the PFD. The modulus would be  
programmed to 520 when in PDC mode (13 MHz /520 = 25 kHz).  
A filter design and analysis program is available to help users  
implement their PLL design. Visit www.analog.com/pll for a  
free download of the ADIsimPLL software. The software  
designs, simulates, and analyzes the entire PLL frequency  
domain and time domain response. Various passive and active  
filter architectures are allowed.  
–24–  
REV. 0  
ADF4251  
IF Side Not In Use  
If the IF side is not being used, the following pinout is recom-  
mended for the IF side:  
SCLOCK  
MOSI  
SCLK  
SDATA  
Pin No.  
Mnemonic  
GND2  
Description  
LE  
CE  
14  
15  
A
Short to all other ground pins.  
I/O PORTS  
IFINB  
IFINA  
CP_IF  
VP2  
Leave open circuit. (This is biased  
up to VDD/2 internally.)  
MUXOUT  
(LOCK DETECT)  
16  
19  
20  
21  
Leave open circuit. (This is biased  
up to VDD/2 internally.)  
ADuC812  
ADF4251  
Leave open circuit. (This is internally  
three-stated until power-up.)  
Figure 8. ADuC812 to ADF4251 Interface  
ADuC812 Interface  
Short to VP1. (VP1 is the RF CP  
supply.)  
Figure 8 shows the interface between the ADF4251 and the  
ADuC812 microconverter. Since the ADuC812 is based on  
an 8051 core, this interface can be used with any 8051-based  
microcontroller. The microconverter is set up for SPI Master  
mode with CPHA = 0. To initiate the operation, the I/O port  
driving LE is brought low. Each latch of the ADF4251 needs  
(at most) a 24-bit word. This is accomplished by writing three  
8-bit bytes from the microconverter to the device. When the third  
byte has been written, the LE input should be brought high to  
complete the transfer.  
V
DD2  
Short to VDD1 (VDD1 is the RF VDD  
supply.)  
INTERFACING  
The ADF4251 has a simple SPI compatible serial interface for  
writing to the device. SCLK, SDATA, and LE control the data  
transfer. When LE (Latch Enable) goes high, the 24 bits that have  
been clocked into the input register on each rising edge of SCLK  
will be transferred to the appropriate latch. See Figure 1 for the  
Timing Diagram and Table I for the Control Bit Truth Table.  
I/O port lines on the ADuC812 are also used to control power-  
down (CE input) and to detect lock (MUXOUT configured as  
lock detect and polled by the port input).  
The maximum allowable serial clock rate is 20 MHz. This means  
that the maximum update rate possible for the device is 833 kHz  
or one update every 1.2 µs. This is certainly more than adequate  
for systems that will have typical lock times in hundreds of  
microseconds.  
When operating in the mode described, the maximum SCLOCK  
rate of the ADuC812 is 4 MHz. This means that the maximum  
rate at which the output frequency can be changed will be 166 kHz.  
V
P
POWER-DOWN CONTROL  
S
V
DD  
ADG702  
IN  
V
RF  
IF  
DD  
OUT  
OUT  
D
GND  
100pF  
100pF  
V
V
DV  
V
CE  
CC  
DD  
DD  
P
18ꢂ  
18ꢂ  
18  
100pF  
18ꢂ  
100pF  
18ꢂ  
V
RF LOOP  
FILTER  
IF LOOP  
FILTER  
CC  
IF VCO  
GND  
IF CP  
RF CP  
RF VCO  
GND  
18  
R
SET  
2.7kꢂ  
ADF4251  
REF  
IN  
REFIN  
100pF  
100pF  
IF  
IF  
A
RF  
A
B
IN  
IN  
51ꢂ  
51ꢂ  
B
RF  
IN  
IN  
100pF  
100pF  
DECOUPLING CAPACITORS AND INTERFACE SIGNALS  
HAVE BEEN OMITTED FROM THE DIAGRAM IN THE  
INTERESTS OF GREATER CLARITY.  
Figure 9. Power-Down Circuit  
REV. 0  
–25–  
ADF4251  
Powerdown Circuit  
The attached circuit in Figure 10 shows how to shut down the  
ADF4251 and the accompanying RF and IF VCO. The  
ADG701 switch goes closed circuit when a Logic High is applied  
to the IN input. The low cost switch is available in SOT-23 and  
SOIC packages.  
SCLK  
DT  
SCLK  
SDATA  
TFS  
LE  
CE  
I/O FLAGS  
PCB DESIGN GUIDELINES FOR CHIP-SCALE  
PACKAGE  
MUXOUT  
(LOCK DETECT)  
The leads on the chip-scale package (CP-24) are rectangular. The  
printed circuit board pad for these should be 0.1 mm longer than  
the package land length and 0.05 mm wider than the package land  
width. The land should be centered on the pad. This will ensure  
that the solder joint size is maximized.  
ADF4251  
ADSP-21xx  
Figure 10. ADSP-21xx to ADF4251 Interface  
ADSP-2181 Interface  
The bottom of the chip-scale package has a central thermal pad.  
The thermal pad on the printed circuit board should be at least  
as large as this exposed pad. On the printed circuit board, there  
should be a clearance of at least 0.25 mm between the thermal  
pad and the inner edges of the pad pattern. This will ensure that  
shorting is avoided.  
Figure 10 shows the interface between the ADF4251 and the  
ADSP-21xx digital signal processor. Each latch of the ADF4251  
needs (at most) a 24-bit word. The easiest way to accomplish this  
using the ADSP-21xx family is to use the autobuffered transmit  
mode of operation with alternate framing. This provides a means  
for transmitting an entire block of serial data before an interrupt is  
generated. Set up the word length for eight bits and use three memory  
locations for each 24-bit word. To program each 24-bit latch, store  
the three 8-bit bytes, enable the autobuffered mode, and then write  
to the transmit register of the DSP. This last operation initiates the  
autobuffer transfer.  
Thermal vias may be used on the printed circuit board thermal pad  
to improve thermal performance of the package. If vias are used,  
they should be incorporated in the thermal pad at 1.2 mm pitch  
grid. The via diameter should be between 0.3 mm and 0.33 mm,  
and the via barrel should be plated with 1 oz copper to plug the via.  
V
VVCO  
V
V
VVCO  
DD  
P
P
R48  
0ꢂ  
R49  
0ꢂ  
R1  
20ꢂ  
R44  
6.3V  
6.3V  
6.3V  
6.3V  
6.3V  
0ꢂ  
6.3V  
VDD  
C9  
C11  
C5  
C29  
C7  
C3  
22F  
22F  
22F  
22F  
22F  
22F  
R43  
0ꢂ  
IF  
RF  
OUT  
OUT  
J7  
C8  
C10  
C12  
C6  
C30  
C4  
J6  
10pF  
10pF  
10pF  
10pF  
10pF  
10pF  
C15  
C27  
100pF  
100pF  
14  
VCC  
RF  
14  
VCC  
V 1  
V 2  
P
P
R12  
R22  
R17  
R20  
18ꢂ  
18ꢂ  
13kꢂ  
470ꢂ  
2
2
V
IN  
10  
OUT  
10  
RF  
V
CP  
CP  
IN  
OUT  
IF  
RF  
R13  
R21  
C16  
100pF  
C26  
100pF  
C20  
C19  
C18  
C23  
10nF  
C24  
C25  
18ꢂ  
18ꢂ  
VCO2  
VCO190–540T  
VCO1  
VCO190–1730T  
U1  
82pF  
2.2nF  
270pF  
100nF  
3.3nF  
R14  
R23  
ADF4251BCP  
18ꢂ  
R16  
R19  
18ꢂ  
7.5kꢂ  
270ꢂ  
CP  
1
R15  
R24  
GND  
51ꢂ  
51ꢂ  
RF  
A
B
IF  
A
IN  
IN  
C17  
C28  
REF  
J5  
100pF  
100pF  
IN  
RF  
T13  
IN  
C13  
1nF  
C14  
1nF  
C43  
C44  
100pF  
T16  
100pF  
R27  
R28  
10kꢂ  
10kꢂ  
5V  
3V  
MUXOUT  
V
R45  
R27  
DD  
R47  
R11  
0ꢂ  
2.7kꢂ  
0ꢂ  
51ꢂ  
R29  
A
1
GND  
10kꢂ  
3
D
LE  
R46  
GND  
O/P  
Y3  
0ꢂ  
D4  
DATA  
CLK  
A
2
2
GND  
4
B+  
GND  
CP  
2
GND  
C46  
C45  
10pF  
22F  
T14  
Figure 11. Typical PLL Circuit Schematic  
–26–  
REV. 0  
ADF4251  
OUTLINE DIMENSIONS  
24-Lead Frame Chip Scale Package [LFCSP]  
4 mm 4 mm Body  
(CP-24)  
Dimensions shown in millimeters  
0.60 MAX  
4.0  
0.25  
MIN  
BSC SQ  
PIN 1  
0.60 MAX  
INDICATOR  
1
19  
24  
18  
PIN 1  
0.50  
BSC  
INDICATOR  
3.75  
TOP  
BOTTOM  
VIEW  
VIEW  
BSC SQ  
0.50  
0.40  
0.30  
2.25  
6
13  
12  
7
1.70 SQ  
0.75  
2.50  
REF  
1.00 MAX  
0.65 NOM  
1.00  
0.90  
0.85  
12MAX  
0.05 MAX  
0.02 NOM  
0.25  
REF  
0.30  
0.23  
0.18  
COPLANARITY  
0.20 REF  
0.08  
SEATING  
PLANE  
COMPLIANTTO JEDEC STANDARDS MO-220-VGGD-2  
REV. 0  
–27–  
–28–  

相关型号:

ADF4251BCP-REEL

Dual Fractional-N/Integer-N Frequency Synthesizer
ADI

ADF4251BCP-REEL7

Dual Fractional-N/Integer-N Frequency Synthesizer
ADI

ADF4252

Dual Fractional-N/Integer-N Frequency Synthesizer
ADI

ADF4252BCP

Dual Fractional-N/Integer-N Frequency Synthesizer
ADI

ADF4252BCP

PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC24, MO-220-VGGD, LFCSP-24
ROCHESTER

ADF4252BCP-REEL

Dual Fractional-N/Integer-N Frequency Synthesizer
ADI

ADF4252BCP-REEL7

Dual Fractional-N/Integer-N Frequency Synthesizer
ADI

ADF4252BCP-REEL7

PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC24, MO-220-VGGD, LFCSP-24
ROCHESTER

ADF4252BCPZ

Dual Fractional-N/ Integer-N Frequency Synthesizer
ADI

ADF4252BCPZ

PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC24, MO-220-VGGD, LFCSP-24
ROCHESTER

ADF4252BCPZ-R7

PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC24, MO-220-VGGD, LFCSP-24
ROCHESTER

ADF4252BCPZ-R7

Dual Fractional-N/ Integer-N Frequency Synthesizer
ADI