ADF4355-3_技术文档

Microwave Wideband Synthesizer

with Integrated VCO

Data Sheet

ADF4355-3

FEATURES

GENERAL DESCRIPTION

RF output frequency range: 51.5625 MHz to 6600 MHz

Fractional-N synthesizer and integer-N synthesizer

High resolution 38-bit modulus

Low phase noise, voltage controlled oscillator (VCO)

Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output

All power supplies: 3.3 V

The ADF4355-3 allows the implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers when

used with an external loop filter and an external reference

frequency. A series of frequency dividers at the output provide

operation from 51.5625 MHz to 6600 MHz.

The ADF4355-3 has an integrated VCO with a fundamental

output frequency ranging from 3300 MHz to 6600 MHz. In

addition, the VCO frequency is connected to divide by 1, 2, 4, 8,

16, 32, or 64 circuits that allow the user to generate RF output

frequencies as low as 51.5625 MHz. For applications that require

isolation, the RF output stage can be muted. The mute function

is both pin- and software-controllable.

Logic compatibility: 1.8 V

Programmable dual modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

3-wire serial interface

Analog and digital lock detect

APPLICATIONS

Control of all on-chip registers is through a simple 3-wire interface.

The ADF4355-3 operates with analog, digital, charge pump, and

VCO power supplies ranging from 3.1515 V to 3.4485 V. The

ADF4355-3 also contains hardware and software power-down

modes.

Wireless infrastructure (W-CDMA, TD-SCDMA,

WiMAX, GSM, PCS, DCS, DECT)

Point to point/point to multipoint microwave links

Satellites/VSATs

Test equipment/instrumentation

Clock generation

FUNCTIONAL BLOCK DIAGRAM

AV

DV

V

R

V

VCO

V

AV

DD

CE

DD

P

SET

RF

MULTIPLEXER

MUXOUT

10-BIT R

COUNTER

÷2

DIVIDER

REF

A

B

IN

×2

DOUBLER

LOCK

DETECT

IN

C

1

2

REG

CLK

DATA

LE

DATA REGISTER

FUNCTION

LATCH

CHARGE

PUMP

CP

OUT

PHASE

COMPARATOR

V

TUNE

REF

V

VCO

CORE

BIAS

INTEGER

REG

FRACTION

REG

MODULUS

REG

REGVCO

RF

A+

A–

OUT

1/2/4/8

16/32/64

OUTPUT

STAGE

THIRD-ORDER

÷

FRACTIONAL

INTERPOLATOR

PDB

RF

N COUNTER

B+

B–

OUTPUT

STAGE

OUT

RF

OUT

MULTIPLEXER

SD

ADF4355-3

A

CP

A

GNDVCO

A

GND

GNDRF

Figure 1.

Rev. B

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADF4355-3

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 4 ..................................................................................... 22

Register 5 ..................................................................................... 23

Register 6 ..................................................................................... 24

Register 7 ..................................................................................... 26

Register 8 ..................................................................................... 27

Register 9 ..................................................................................... 27

Register 10................................................................................... 28

Register 11................................................................................... 28

Register 12................................................................................... 29

Register Initialization Sequence ............................................... 29

Frequency Update Sequence..................................................... 30

RF Synthesizer—A Worked Example ...................................... 30

Reference Doubler and Reference Divider ............................. 30

Spurious Optimization and Fast Lock..................................... 31

Optimizing Jitter......................................................................... 31

Spur Mechanisms ....................................................................... 31

Lock Time.................................................................................... 31

Applications Information .............................................................. 32

Direct Conversion Modulator .................................................. 32

Power Supplies............................................................................ 33

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Reference Input Section............................................................. 12

RF N Divider............................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump............ 13

MUXOUT and Lock Detect...................................................... 13

Input Shift Registers................................................................... 13

Program Modes .......................................................................... 14

VCO.............................................................................................. 14

Output Stage................................................................................ 14

Loop Filter ................................................................................... 14

Register Maps.................................................................................. 16

Register 0 ..................................................................................... 18

Register 1 ..................................................................................... 19

Register 2 ..................................................................................... 20

Register 3 ..................................................................................... 21

Printed Circuit Board (PCB) Design Guidelines for a Chip-

Scale Package .............................................................................. 33

Output Matching........................................................................ 33

Outline Dimensions....................................................................... 34

Ordering Guide .......................................................................... 34

REVISION HISTORY

8/2017—Rev. A to Rev. B

Changes to Figure 25...................................................................... 17

Changes to Reference Mode Section ........................................... 23

Changes to Negative Bleed Section.............................................. 24

Changes to Charge Pump Bleed Current Section...................... 25

Changes to Figure 34, Figure 35, and Register 8 Section.......... 27

Changes to Figure 37 and Register 11 Section ........................... 28

Changes to Frequency Update Sequence .................................... 30

Updated Outline Dimensions....................................................... 34

Changes to Ordering Guide .......................................................... 34

1/2016—Rev. 0 to Rev. A

Change to Integrated RMS Jitter Parameter, Unit Column,

Table 1 ................................................................................................ 4

Changes to Reference Input Section ............................................ 12

Changes to Table 6.......................................................................... 15

7/2015—Revision 0: Initial Version

Rev. B | Page 2 of 34

Data Sheet

ADF4355-3

SPECIFICATIONS

AV_DD= DV_DD= V_RF= V_P= V_VCO= V_REGVCO= 3.3 V 4.5%, A_GND= CP_GND= A_GNDVCO= SD_GND= A_GNDRF= 0 V, R_SET= 5.1 kΩ, dBm referred

to 50 Ω, T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

REF_INA/REF_INB CHARACTERISTICS

Input Frequency

REF_IN

For f < 10 MHz, ensure that the slew rate >

21 V/µs

Single-Ended Mode

Differential Mode

Doubler Enabled

Input Sensitivity

10

250

600

100

MHz

Doubler is set in Register 4, Bit DB26

Single-Ended Mode

0.4

AV_DD

1.8

V p-p

REF_INA biased at AV_DD/2; ac coupling

ensures AV_DD/2 bias

LVDS and LVPECL compatible, REF_INA/

REF_INB biased at 2.1 V; ac coupling ensures

2.1 V bias

Differential Mode

Input Capacitance

Single-Ended Mode

Differential Mode

Input Current

6.9

1.4

pF

µA

MHz

60

250

125

Single-ended reference programmed

Differential reference programmed

Phase Detector Frequency

CHARGE PUMP (CP)

Charge Pump Current, Sink/Source

High

I_CP

R_SET= 5.1 kΩ

4.8

0.3

5.1

3

1.5

mA

kΩ

%

Low

R_SETRange

Fixed

Current Matching

0.5 V ≤ V_CP¹≤ V_P− 0.5 V

V_CP¹= 2.5 V

1

I_CPvs. V_CP

I_CPvs. Temperature

LOGIC INPUTS

Input Voltage

High

1.8 V and 3.3 V compatible

V_INH

V_INL

I_INH/I_INL

C_IN

1.5

DV_DD

0.6

1

V

µA

pF

Low

Input Current

Input Capacitance

LOGIC OUTPUTS

Output Voltage

High

3.0

1.8

V_OH

DV_DD− 0.4

1.5

V

µA

3.3 V output selected

1.8 V output selected

I_OL²= 500 µA

Low

V_OL

I_OH

0.4

500

Output High Current

POWER SUPPLIES

Analog Power

AV_DD

3.1515

3.3

3.4485

V

3.3 V 4.5%

Digital Power, RF Supply, Charge Pump,

and VCO Supply Voltage

DV_DD, V_RF,

V_P, V_VCO

AV_DD

Voltages must equal AV_DD

Charge Pump Supply Current

DI_DD+ AI_DD

I_P

3.1

66

5

75

mA

3

Supply current drawn by DV_DDplus supply

current drawn by AV_DD

Output Dividers

See Table 6

VCO Supply Current

I_VCO

52

13/19/

25/31

70

20/27/

34/41

mA

RF_OUTA /RF_OUT

B

Supply Current

RF output stage is programmable;

RF_OUTB+/RF_OUTB− powered off

I

RF_OUTx±

Low Power Sleep Mode

1500

1950

µA

Hardware power-down

Software power-down

Rev. B | Page 3 of 34

ADF4355-3

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

RF OUTPUT CHARACTERISTICS

VCO Frequency Range

RF Output Frequency

VCO Sensitivity

Frequency Pushing (Open-Loop)

Frequency Pulling (Open-Loop)

Harmonic Content

3300

51.5625

6600

MHz

MHz/V

MHz

Fundamental VCO range

f_RF

K_V

63

22

0.54

Voltage standing wave ratio (VSWR) = 2:1

Second

−27

−22

−20

−12

8

dBc

dBm

Fundamental VCO output (RF_OUTA+)

Divided VCO output (RF_OUTA+)

Fundamental VCO output (RF_OUTA+)

Divided VCO output (RF_OUTA+)

RF_OUTA+ = 1 GHz. 7.5 nH inductor to V_RF

RF_OUTA+/RF_OUTA− = 4.4 GHz. 7.5 nH inductor

to V_RF

Third

RF Output Power⁴

3

RF Output Power Variation

Over Frequency

Level of Signal with Output Disabled

1

3

−60

−30

dB

dBm

RF_OUTA+/RF_OUTA− = 4.4 GHz

RF_OUTA+/RF_OUTA− = 1 GHz to 4.4 GHz

RF_OUTA+/RF_OUTA− = 1 GHz, VCO = 4 GHz

RF_OUTA+/RF_OUTA− = 4.4 GHz, VCO = 4.4 GHz

NOISE CHARACTERISTICS

Fundamental VCO Phase Noise

Performance

VCO noise in open-loop conditions

3.3 GHz Carrier

5.0 GHz Carrier

6.6 GHz Carrier

−113

−133

−135

−153

−110

−130

−132

−151

−107

−127

−129

−148

dBc/Hz

100 kHz offset from 3.3 GHz carrier

800 kHz offset from 3.3 GHz carrier

1 MHz offset from 3.3 GHz carrier

10 MHz offset from 3.3 GHz carrier

100 kHz offset from 5.0 GHz carrier

800 kHz offset from 5.0 GHz carrier

1 MHz offset from 5.0 GHz carrier

10 MHz offset from 5.0 GHz carrier

100 kHz offset from 6.6 GHz carrier

800 kHz offset from 6.6 GHz carrier

1 MHz offset from 6.6 GHz carrier

10 MHz offset from 6.6 GHz carrier

Normalized In-Band Phase Noise Floor

Fractional Channel⁵

−221

−223

−116

200

dBc/Hz

fs

Integer Channel⁶

Normalized 1/f Noise⁷

Integrated RMS Jitter

PN_{1_f}

10 kHz offset, normalized to 1 GHz

Spurious Signals due to Phase Frequency

Detector (PFD) Frequency

−85

dBc

¹V_CPis the voltage at the CP_OUTpin.

²I_OLis the output low current.

³T_A= 25°C; AV_DD= DV_DD= V_RF= V_VCO= V_P= 3.3 V; prescaler = 4/5; f_REF= 122.88 MHz; f_PFD= 61.44 MHz; and f_RF= 1650 MHz.

IN

⁴RF output power using the EV-ADF4355-3SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. Unused RF output

pins are terminated in 50 Ω.

⁵Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−221 + 10log(f_PFD) + 20logN. The value given is the lowest noise mode for the fractional channel.

⁶Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−223 + 10log(f_PFD) + 20logN. The value given is the lowest noise mode for the integer channel.

⁷The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f_RF

and at a frequency offset (f) is given by PN = P_{1_f}+ 10log(10 kHz/f) + 20log(f_RF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the

ADIsimPLL™ design tool.

)

Rev. B | Page 4 of 34

Data Sheet

ADF4355-3

TIMING CHARACTERISTICS

AV_DD= DV_DD=V_RF= V_P= V_VCO= 3.3 V 4.5%, A_GND= CP_GND= A_GNDVCO= SD_GND= A_GNDRF= 0 V, R_SET= 5.1 kΩ, dBm referred to 50 Ω, T_A= T_MIN

to T_MAX, unless otherwise noted.

Table 2. Write Timing

Parameter

Limit

Unit

Description

f_CLK

t₁

t₂

t₃

t₄

t₅

t₆

t₇

50

10

5

10

5

MHz max

ns min

SPI CLK frequency

LE setup time

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

20 or (2/f_PFD), whichever is longer

Write Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB3

DB2

(CONTROL BIT C3)

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB30

DATA

LE

(CONTROL BIT C4)

(CONTROL BIT C2)

t₇

t₁

t₆

Figure 2. Write Timing Diagram

Rev. B | Page 5 of 34

ADF4355-3

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 3.

Parameter¹

Rating

V_RF, DV_DD, AV_DDto GND

AV_DDto DV_DD

V_P, V_VCO, V_REGVCOto GND

CP_OUTto GND¹

Digital Input/Output Voltage to GND

Analog Input/Output Voltage to GND

REF_INA, REF_INB to GND

−0.3 V to +3.6 V

−0.3 V to +0.3 V

−0.3 V to +3.6 V

−0.3 V to V_P+ 0.3 V

−0.3 V to DV_DD+ 0.3 V

−0.3 V to AV_DD+ 0.3 V

2.1 V

The ADF4355-3 is a high performance RF integrated circuit

with an ESD rating of 2500 V and is ESD sensitive. Take proper

precautions for handling and assembly.

REF_INA to REF_INB

TRANSISTOR COUNT

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

−40°C to +105°C

−65°C to +125°C

150°C

The transistor count for the ADF4355-3 is 103,665 (CMOS) and

3214 (bipolar).

θ_JA, Thermal Impedance Pad Soldered

to GND

Reflow Soldering

27.3°C/W

ESD CAUTION

Peak Temperature

260°C

40 sec

Time at Peak Temperature

Electrostatic Discharge (ESD)

Charged Device Model

Human Body Model

500 V

2500 V

¹GND = A_GND= SD_GND= A_GNDRF= A_GNDVCO= CP_GND= 0 V.

Rev. B | Page 6 of 34

Data Sheet

ADF4355-3

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

DATA

LE

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

V

BIAS

REF

R

A

V

SET

ADF4355-3

TOP VIEW

(Not to Scale)

CE

GNDVCO

TUNE

AV

DD

V

P

OUT

V

A

V

REGVCO

CP

GNDVCO

VCO

CP

GND

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO A

.

GND

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

CLK

DATA

LE

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)

as the control bits. This input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that

is selected by the four LSBs.

2

3

4

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A

logic high on this pin powers up the device, depending on the status of the power-down bits.

5, 16

AV_DD

V_P

Analog Power Supplies. These pins range from 3.1515 V to 3.4485 V. Connect decoupling capacitors to the analog

ground plane as close to these pins as possible. AV_DDmust have the same value as DV_DD

.

6

7

Charge Pump Power Supply. V_Pmust have the same value as V_VCO. Connect decoupling capacitors to the ground

plane as close to this pin as possible.

Charge Pump Output. When enabled, this output provides I_CPto the external loop filter. The output of the loop

filter is connected to V_TUNEto drive the internal VCO.

CP_OUT

8

9

10

CP_GND

A_GND

V_RF

Charge Pump Ground. This output is the ground return pin for CP_OUT

.

Analog Ground. Ground return pin for AV_DD

.

Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin

as possible. V_RFmust have the same value as AV_DD. For optimum spurious performance, V_RFand DV_DDmust

originate from different regulators.

11

12

RF_OUTA+

RF_OUTA−

VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.

Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down

version is available.

13

14

A_GNDRF

RF_OUTB+

RF Output Stage Ground. This pin is the ground return for the RF output stage.

Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version

is available.

15

17

RF_OUTB−

V_VCO

Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a

divided down version is available.

Power Supply for the VCO. The voltage on this pin ranges from 3.1515 V to 3.4485 V. Connect decoupling

capacitors to the analog ground plane as close to this pin as possible.

18, 21

19

A_GNDVCO

V_REGVCO

VCO Ground. This pin is the ground return path for the VCO.

VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.

Connect this pin directly to V_VCO

.

20

V_TUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP_OUT

output voltage. The capacitance at this pin (V_TUNEinput capacitance) is 7 pF.

Rev. B | Page 7 of 34

ADF4355-3

Data Sheet

Pin No. Mnemonic

Description

22

23

R_SET

V_REF

Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.

Internal Compensation Node. V_REFis dc biased at half of the tuning range. Connect decoupling capacitors to the

ground plane as close to this pin as possible. The recommended capacitor values are 10 pF, 1 nF, and 4.7 µF.

24

V_BIAS

Reference Voltage. Connect decoupling capacitors to the ground plane as close to this pin as possible. The

recommended capacitor values are 10 pF, 1 nF, and 1 µF.

25, 32

C_REG1, C_REG

2

Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits, and have a

nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to A_GNDare required for these pins.

26

27

PDB_RF

DV_DD

RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software-controllable.

Digital Power Supply. This pin must be at the same voltage as AV_DD. Place decoupling capacitors to the ground

plane as close to this pin as possible. For optimum spurious performance, V_RFand DV_DDmust originate from

different regulators.

28

29

30

REF_INB

REF_INA

MUXOUT

Complementary Reference Input. If unused, ac-couple this pin to A_GND

Reference Input.

Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the

scaled reference frequency to be externally accessible.

.

31

SD_GND

EP

Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator.

Exposed Pad. The exposed pad must be connected to A_GND

.

Rev. B | Page 8 of 34

Data Sheet

ADF4355-3

TYPICAL PERFORMANCE CHARACTERISTICS

–50

–70

÷1

÷2

÷4

÷8

–70

÷16

÷32

÷64

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

OFFSET FREQUENCY (Hz)

FREQUENCY (Hz)

Figure 4. Open-Loop VCO Phase Noise, 3.3 GHz

Figure 7. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and Dividers,

VCO = 3.3 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 35 kHz

–50

–70

÷1

÷2

÷4

÷8

÷16

÷32

–70

÷64

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

OFFSET FREQUENCY (Hz)

FREQUENCY (Hz)

Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz

Figure 8. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and Dividers,

VCO = 5.0 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 35 kHz

–50

–70

–50

÷1

÷2

÷4

–70

÷8

÷16

÷32

÷64

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

OFFSET FREQUENCY (Hz)

FREQUENCY (Hz)

Figure 6. Open-Loop VCO Phase Noise, 6.6 GHz

Figure 9. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and Dividers,

VCO = 6.6 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 35 kHz

Rev. B | Page 9 of 34

ADF4355-3

Data Sheet

10

–40

–50

PFD = 61.44MHz

PFD = 30.72MHz

PFD = 15.36MHz

5

0

–60

–5

–70

–10

–15

–20

–25

–30

–80

–90

–40°C

+25°C

+105°C

–100

–110

0

1

2

3

4

5

6

0

1

2

3

4

5

6

FREQUENCY (GHz)

Figure 10. Output Power vs. Frequency, RF_OUTA+/RF_OUTA− (7.5 nH Inductors,

10 pF Bypass Capacitors, Board Losses De-Embedded)

Figure 13. Worst Case PFD Spur vs. Frequency, f_PFD= 15.36 MHz, 30.72 MHz,

and 61.44 MHz, Loop Filter = 35 kHz

10

–80

–90

SECOND HARMONIC

THIRD HARMONIC

0

–10

–20

–30

–40

–50

–60

–100

–110

–120

–130

–140

–150

–160

0

1

2

3

4

5

6

7

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

FREQUENCY (GHz)

Figure 11. RF_OUTA+/RF_OUTA− Harmonics vs. Frequency (7.5 nH Inductors,

10 pF Bypass Capacitors, Board Losses De-Embedded)

Figure 14. Spur Performance, GSM1800 Band, RF_OUTA+ = 1550.2 MHz, REF_IN

122.88 MHz, f_PFD= 61.44 MHz, Output Divide by 4 Selected, Loop Filter

Bandwidth = 35 kHz, Channel Spacing = 20 kHz

=

1.2

1kHz - 20MHz

12kHz - 20MHz

–80

–90

1.0

0.8

0.6

0.4

0.2

0

–100

–110

–120

–130

–140

–150

–160

0

1

2

3

4

5

6

7

OUTPUT FREQUENCY (GHz)

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 12. RMS Jitter vs. Output Frequency, f_PFD= 61.44 MHz, Loop Filter = 35 kHz

Figure 15. Spur Performance, W-CDMA Band, RF_OUTA+ = 2113.5 MHz, REF_IN

122.88 MHz, f_PFD= 61.44 MHz, Output Divide by 2 Selected, Loop Filter

Bandwidth = 35 kHz, Channel Spacing = 20 kHz

=

Rev. B | Page 10 of 34

Data Sheet

ADF4355-3

–80

5

4

–90

3

–100

–110

–120

–130

–140

–150

2

1

0

–1

–2

–3

–4

–5

–160

1k

10k

100k

1M

10M

100M

–150

0

150

300 450 600 750 900 1050 1200 1350

TIME (µs)

FREQUENCY (Hz)

Figure 17. Lock Time for 100 MHz Jump from 3300 MHz to 6600 MHz, Loop

Bandwidth = 3 kHz

Figure 16. Spur Performance, RF_OUTA+ = 2.591 GHz,

REF_IN= 122.88 MHz, f_PFD= 61.44 MHz, Output Divide-by-2 Selected,

Loop Filter Bandwidth = 35 kHz, Channel Spacing = 20 kHz

Rev. B | Page 11 of 34

ADF4355-3

Data Sheet

THEORY OF OPERATION

INT, FRACx, MODx, and R Counter Relationship

REFERENCE INPUT SECTION

The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in

conjunction with the R counter, make it possible to generate

output frequencies that are spaced by fractions of the PFD

frequency (f_PFD). For more information, see the RF Synthesizer—

A Worked Example section.

Figure 18 shows the reference input section of the ADF4355-3.

The reference input can accept both single-ended and differential

signals. Use the reference mode bit (Register 4, Bit DB9) to select

the signal. To use a differential signal on the reference input, program

this bit high. In this case, SW1 and SW2 are open, SW3 and SW4

are closed, and the current source that drives the differential pair

of transistors switches on. The differential signal is buffered, and

it is provided to an emitter coupled logic (ECL) to a CMOS

converter. When a single-ended signal is the reference, connect

the reference signal to REF_INA and program Bit DB9 in Register 4

to 0. In this case, SW1 and SW2 are closed, SW3 and SW4 are

open, and the current source that drives the differential pair of

transistors switches off. Single-ended mode results in lower integer

boundary spurs.

Calculate the RF VCO frequency (VCO_OUT) by

VCO_OUT= f_PFD× N

where:

(1)

VCO_OUTis the output frequency of the VCO (without using the

output divider).

f

_PFDis the frequency of the phase frequency detector.

N is the desired value of the feedback counter, N.

Calculate f_PFDby

REFERENCE

INPUT MODE

f

_PFD= REF_IN× ((1 + D)/(R × (1 + T)))

(2)

where:

85kꢀ

REF_INis the reference input frequency.

D is the REF_INdoubler bit.

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

SW2

BUFFER

SW1

SW3

TO

R COUNTER

MULTIPLEXER

T is the REF_INdivide by 2 bit (0 or 1).

AV

DD

N comprises

ECL TO CMOS

BUFFER

FRAC2

MOD2

MOD1

FRAC1

REF

A

IN

N  INT 

(3)

B

IN

where:

2.5kΩ

INT is the 16-bit integer value (23 to 32,767 for the 4/5

prescaler, and 75 to 65,535 for the 8/9 prescaler).

SW4

BIAS

GENERATOR

FRAC1 is the numerator of the primary modulus (0 to 16,777,215).

FRAC2 is the numerator of the 14-bit auxiliary modulus

(0 to 16,383).

Figure 18. Reference Input Stage

RF N DIVIDER

MOD2 is the programmable, 14-bit auxiliary fractional

modulus (2 to 16,383).

The RF N divider allows a division ratio in the PLL feedback path.

Determine the division ratio by the INT, FRAC1, FRAC2, and

MOD2 values that this divider comprises.

MOD1 is a 24-bit primary modulus with a fixed value of 2²⁴=

16,777,216.

FRAC2

RF N COUNTER

Equation 3 results in a very fine frequency resolution with no resid-

ual frequency error. Apply this formula using the following steps:

FRAC1 +

MOD2

N = INT +

TO

PFD

MOD1

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

1. Calculate N by dividing VCO_OUT/f_PFD. The integer value of

this number forms INT.

2. Subtract the INT value from the full N value.

3. Multiply the remainder by 2²⁴. The integer value of this

number forms FRAC1.

N COUNTER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

INT

REG

FRAC1

REG

FRAC2

VALUE

MOD2

VALUE

4. Calculate the MOD2 based on the channel spacing (f_CHSP) by

MOD2 = f_PFD/GCD(f_PFD, f_CHSP

where:

_CHSPis the desired channel spacing.

)

(4)

f

Figure 19. RF N Divider

GCD(f_PFD, f_CHSP) is the greatest common divider of the PFD

frequency and the channel spacing frequency.

Rev. B | Page 12 of 34

Data Sheet

ADF4355-3

SD

GND

5. Calculate FRAC2 by the following equation:

FRAC2 = ((N − INT) × 2²⁴− FRAC1)) × MOD2

(5)

(6)

THREE-STATE OUTPUT

SD

The FRAC2 and MOD2 fraction results in outputs with zero

frequency error for channel spacings when

GND

DGND

f

_PFD/GCD(f_PFD/f_CHSP) < 16,383

where:

_PFDis the frequency of the phase frequency detector.

GCD is a greatest common divider function.

_CHSPis the desired channel spacing.

R DIVIDER OUTPUT

N DIVIDER OUTPUT

MUX

CONTROL

MUXOUT

SD

to DV

DD

GND

f

DIGITAL LOCK DETECT

RESERVED

f

If zero frequency error is not required, the MOD1 and MOD2

denominators operate together to create a 38-bit resolution

modulus.

DGND

Figure 21. MUXOUT Block Diagram

If negative bleed is enabled, lock detect is not reliable for low

PFD frequencies.

INT N Mode

When FRAC1 and FRAC2 = 0, the synthesizer operates in

integer-N mode.

INPUT SHIFT REGISTERS

The ADF4355-3 digital section includes a 10-bit R counter, a

16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 14-bit

auxiliary fractional counter, and a 14-bit auxiliary modulus

counter. Data clocks into the 32-bit shift register on each rising

edge of CLK. The data clocks in MSB first. Data transfers from

the shift register to one of 13 latches on the rising edge of LE.

The state of the four control bits (C4, C3, C2, and C1) in the

shift register determines the destination latch. As shown in

Figure 2, the four least significant bits (LSBs) are DB3, DB2,

DB1, and DB0. The truth table for these bits is shown in Table 5.

Figure 24 and Figure 25 summarize the programing of the latches.

R Counter

The 10-bit R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 20 is a simplified schematic of

the phase frequency detector. The PFD includes a fixed delay

element that sets the width of the antibacklash pulse. This pulse

ensures that there is no dead zone in the PFD transfer function

and provides a consistent reference spur level. Set the phase

detector polarity to positive on this device because of the

positive tuning of the VCO.

Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits

Control Bits

C4

0

1

C3

0

1

0

1

C2

0

1

0

1

0

1

0

C1

0

1

0

1

0

1

0

1

0

1

0

1

0

Register

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

UP

HIGH

D1

Q1

U1

CLR1

+IN

CHARGE

PUMP

CP

U3

DELAY

DOWN

CLR2

D2 Q2

HIGH

U2

–IN

Figure 20. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4355-3 allows the user to access

various internal points on the chip. The M3, M2, and M1 bits in

Register 4 control the state of MUXOUT. Figure 21 shows the

MUXOUT section in block diagram form.

Rev. B | Page 13 of 34

ADF4355-3

Data Sheet

130

120

110

100

90

PROGRAM MODES

Table 5 and Figure 24 through Figure 38 show the program

modes that must be set up in the ADF4355-3.

The following settings in the ADF4355-3 are double buffered:

main fractional value (FRAC1), auxiliary modulus value (MOD2),

auxiliary fractional value (FRAC2), reference doubler, reference

divide by 2 (RDIV2), phase value, R counter value, and charge

pump current setting. Two events must occur before the

ADF4355-3 uses a new value for any of the double buffered

settings. First, the new value must latch into the device by writing

to the appropriate register, and second, a new write to Register 0

must be performed.

80

70

60

50

40

30

20

10

0

3.3

3.8

4.3

4.8

5.3

5.8

6.3

FREQUENCY (GHz)

For example, to ensure that the modulus value loads correctly,

every time the modulus value updates, Register 0 must be

written to. The RF divider select in Register 6 is also double

buffered, but only when DB14 of Register 4 is high.

Figure 22. K_Vvs. VCO Frequency

OUTPUT STAGE

The RF_OUTA+ and RF_OUTA− pins of the ADF4355-3 connect to

the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 23. In this scheme, the

ADF4355-3 contains internal 50 Ω resistors connected to the

VCO

The VCO core in the ADF4355-3 consists of four separate VCOs,

each of which uses 256 overlapping bands, which allows covering

a wide frequency range without a large VCO sensitivity (K_V) and

without resulting poor phase noise and spurious performance.

V

_RFpin. To optimize the power dissipation vs. the output

power requirements, the tail current of the differential pair is

programmable using Bits[DB5:DB4] in Register 6. Four current

levels can be set. These levels give the approximate output power

levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively,

using a 50 Ω resistor to V_RFand ac coupling into a 50 Ω load. For

accurate power levels, see the Typical Performance Characteristics

section. Add an external shunt inductor to provide higher power

levels; however, this is less wideband than the internal bias only.

Terminate the unused complementary output with a similar

circuit to the used output.

The correct VCO and band are chosen automatically by the VCO

and band select logic when Register 0 is updated and autocalibra-

tion is enabled. The VCO V_TUNEis disconnected from the output of

the loop filter and is connected to an internal reference voltage.

The R counter output is the clock for the band select logic. After

band selection, normal PLL action resumes. The nominal value

of K_Vis 63 MHz/V when the N divider is driven from the VCO

output, or the K_Vvalue is divided by D. D is the output divider

value if the N divider is driven from the RF output divider

(chosen by programming Bits[D23:D21] in Register 6).

V

RF

50Ω

A+

50Ω

RF

A–

The VCO shows the variation of K_Vas the tuning voltage, V_TUNE

varies within the band and from band to band. For wideband

applications covering a wide frequency range (and changing

output dividers), a value of 63 MHz/V provides the most accurate

K_V, because this value is closest to the average value. Figure 22

,

OUT

BUFFER/

DIVIDE BY

1/2/4/8/

VCO

16/32/64

shows how K_Vvaries with fundamental VCO frequency along with

an average value for the frequency band. Users may prefer this

figure when using narrow-band designs.

Figure 23. Output Stage

Another feature of the ADF4355-3 is that the supply current to

the output stages can shut down until the ADF4355-3 achieves

lock as measured by the digital lock detect circuitry. The mute until

lock detect (MTLD) bit (Bit DB11) in Register 6 enables this

function.

The RF_OUTB+/RF_OUTB− pins are duplicate outputs that can be

used independently or in addition to the RF_OUTA+/RF_OUTA− pins.

LOOP FILTER

Use only passive loop filters. For information on designing a

loop filter, use the ADIsimPLL design tool.

Rev. B | Page 14 of 34

Data Sheet

ADF4355-3

Table 6. Total I_DD(RF_OUT

Divide By

A

Refers to RF_OUTA+/RF_OUTA−)

RF_OUTOff RF_OUT= −4 dBm

49.4 mA

A

RF_OUTA

= −1 dBm

RF_OUTA

= +2 dBm

RF_OUTA = +5 dBm

I_VCOand I_P

49.4 mA

AI_DD, DI_DD, I_RF

1

2

4

8

16

32

64

91.8 mA

103.3 mA

113.6 mA

123.9 mA

132.1 mA

137.3 mA

141.4 mA

144.0 mA

106.5 mA

117.0 mA

127.5 mA

135.6 mA

140.8 mA

144.9 mA

147.4 mA

111.7 mA

122.8 mA

133.6 mA

141.8 mA

147.0 mA

151.1 mA

153.6 mA

116.9 mA

128.4 mA

139.8 mA

148.0 mA

153.3 mA

157.5 mA

160.0 mA

100.9 mA

110.8 mA

118.9 mA

124.0 mA

128.0 mA

130.4 mA

Rev. B | Page 15 of 34

ADF4355-3

Data Sheet

REGISTER MAPS

REGISTER 0

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1 C4(0) C3(0) C2(0) C1(0)

0

AC1

PR1

N16

REGISTER 1

CONTROL

BITS

DBR¹

RESERVED

24-BIT MAIN FRACTIONAL VALUE (FRAC1)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

0

C3(0) C2(0) C1(1)

C4(0)

0

REGISTER 2

CONTROL

BITS

DBR¹

1

14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)

DBR

14-BIT AUXILIARY MODULUS VALUE (MOD2)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

M14 M13 M12 M11 M10 M9

M8

M7

M6

M5

M4

M3

M2

M1

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

C3(0) C2(1) C1(0)

C4(0)

REGISTER 3

CONTROL

BITS

24-BIT PHASE VALUE (PHASE)

DBR¹

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(0) C2(1) C1(1)

P1 C4(0)

0

SD1

PR1 PA1 P24

P23 P22

P21

P20

P19

P18

P17

P16 P15

P14 P13

P12

P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

REGISTER 4

CONTROL

BITS

CURRENT

SETTING

DBR¹

RESERVED

MUXOUT

10-BIT R COUNTER

DBR¹

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(1) C2(0) C1(0)

U1 C4(0)

0

M3

M2

M1

RD2 RD1

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4

CP3 CP2 CP1 U6

U5

U4

U3

U2

REGISTER 5

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

C4(0) C3(1) C2(0)

C1(1)

REGISTER 6

AUX RF

OUTPUT

POWER

RF

OUTPUT

POWER

RF DIVIDER

SELECT²

CONTROL

BITS

RESERVED

CHARGE PUMP BLEED CURRENT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BL2

BL3

0

BL10 BL9

1

0

1

0

D13 D12 D11

D10

BL7

BL4

BL1

0

D8

0

D6

D5

D4

D3

D2

D1

BL8

BL6

BL5

C4(0) C3(1) C2(1) C1(0)

1

2

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.

Figure 24. Register Summary (Register 0 to Register 6)

Rev. B | Page 16 of 34

Data Sheet

ADF4355-3

REGISTER 7

LD

CYCLE

COUNT

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LD4

LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)

0

1

0

LE

0

LD5

LOL

REGISTER 8

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

C4(1) C3(0) C2(0) C1(0)

REGISTER 9

SYNTHESIZER

LOCK TIMEOUT

CONTROL

BITS

VCO BAND DIVISION

TIMEOUT

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC8 VC7 VC6

VC5 VC4 VC3 VC2 VC1 TL10 TL9

TL8

TL7

TL6

TL5

TL4

TL3

TL2

TL1

1

SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)

REGISTER 10

ADC

CLOCK DIVIDER

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

AD8 AD7 AD6

AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)

REGISTER 11

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

C4(1) C3(0) C2(1) C1(1)

0

REGISTER 12

CONTROL

BITS

RESERVED

RESYNC CLOCK

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P13 P12

P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1

0

1

0

1

0

P16 P15

C4(1) C3(1) C2(0) C1(0)

P14

Figure 25. Register Summary (Register 7 to Register 12)

Rev. B | Page 17 of 34

ADF4355-3

Data Sheet

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C4(0) C3(0) C2(0)

C1(0)

N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

0

AC1

PR1

N16

0

N15

0

...

N5

N4

N3

N2

N1

0

1

0

.

INTEGER VALUE (INT)

PR1 PRESCALER

0

.

0

.

0

.

0

1

.

NOT ALLOWED

0

1

4/5

8/9

0

NOT ALLOWED

0

NOT ALLOWED

.

...

0

1

.

0

1

.

1

0

.

1

0

.

0

1

0

.

NOT ALLOWED

0

23

0

24

VCO

AUTOCAL

AC1

.

...

1

0

1

0

1

65533

65534

65535

0

1

DISABLED

ENABLED

1

INT

= 75 WITH PRESCALER = 8/9

MIN

Figure 26. Register 0

Prescaler Value

The dual modulus prescaler (P/P + 1), along with the INT,

REGISTER 0

Control Bits

FRACx, and MODx counters, determines the overall division

ratio from the VCO output to the PFD input. The PR1 bit

(Bit DB20) in Register 0 sets the prescaler value.

With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 26

shows the input data format for programming this register.

Reserved

Operating at CML levels, the prescaler takes the clock from the

VCO output and divides it down for the counters. It is based on

a synchronous 4/5 core. The prescaler limits the INT value;

therefore, if P is 4/5, INT_MINis 23, and if P is 8/9, INT_MINis 75.

Bits[DB31:DB22] are reserved and must be set to 0.

Automatic Calibration (Autocal)

Write to Register 0 to enact (by default) the VCO automatic

calibration, and to choose the appropriate VCO and VCO

subband. Write 1 to the AC1 bit (Bit DB21) to enable the

automatic calibration, which is the recommended mode of

operation.

16-Bit Integer Value

The 16 INT bits (Bits[DB19:DB4]) set the INT value, which

determines the integer part of the feedback division factor. The

INT value is used in Equation 3 (see the RF Synthesizer—A

Worked Example section). All integer values from 23 to 32,767

are allowed for the 4/5 prescaler. For the 8/9 prescaler, the

minimum integer value is 75, and the maximum value is 65,535.

Set the AC1 bit to 0 to disable the automatic calibration, which

leaves the ADF4355-3 in the same band it is already in when

Register 0 is updated.

Disable the automatic calibration only for fixed frequency

applications, phase adjust applications, or very small (<10 kHz)

frequency jumps.

Rev. B | Page 18 of 34

Data Sheet

ADF4355-3

CONTROL

BITS

1

RESERVED

24-BIT MAIN FRACTIONAL VALUE (FRAC1)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1

C1(1)

C3(0) C2(0)

0

C4(0)

0

F24

F23

.......... F2

F1

MAIN FRACTIONAL VALUE (FRAC1)

0

.

0

.

..........

.........

0

1

.

0

1

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

16777212

16777213

16777214

16777215

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 27. Register 1

24-Bit Main Fractional Value

REGISTER 1

The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the

fraction that is input to the Σ-Δ modulator. This fraction, along

with the INT value, specifies the new frequency channel that

the synthesizer locks to, as shown in the RF Synthesizer—A

Worked Example section. FRAC1 values from 0 to (MOD1 − 1)

cover channels over a frequency range equal to the PFD

reference frequency.

Control Bits

With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 27

shows the input data format for programming this register.

Reserved

Bits[DB31:DB28] are reserved and must be set to 0.

Rev. B | Page 19 of 34

ADF4355-3

Data Sheet

CONTROL

BITS

14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2) DBR¹

14-BIT AUXILIARY MODULUS VALUE (MOD2) DBR¹

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

M14 M13 M12 M11 M10 M9

M8

M7

M6

M5

M4

M3

M2

M1

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

C3(0) C2(1) C1(0)

C4(0)

M14 M13 .......... M2

M1

0

1

0

1

.

MODULUS VALUE (MOD2)

F14

F13

.......... F2

F1

0

1

0

1

.

FRAC2 WORD

0

.

0

.

..........

.........

0

1

.

NOT ALLOWED

0

.

0

.

..........

.........

0

1

.

0

NOT ALLOWED

1

2

3

.

1

0

1

0

1

0

1

16380

16381

16382

16383

1

0

1

0

1

0

1

16381

16382

16383

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 28. Register 2

14-Bit Auxiliary Modulus Value (MOD2)

REGISTER 2

The 14-bit auxiliary modulus value (Bits[DB17:DB4]) sets the

auxiliary fractional modulus. Use MOD2 to correct any residual

error due to the main fractional modulus.

Control Bits

With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 28

shows the input data format for programming this register.

14-Bit Auxiliary Fractional Value (FRAC2)

The 14-bit auxiliary fractional value (Bits[DB31:DB18]) controls

the auxiliary fractional word. FRAC2 must be less than the

MOD2 value programmed in Register 2.

Rev. B | Page 20 of 34

Data Sheet

ADF4355-3

CONTROL

BITS

24-BIT PHASE VALUE (PHASE)

DBR¹

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(0) C2(1) C1(1)

0

SD1

PR1 PA1 P24

P23 P22

P21

P20

P19

P18

P17

P16 P15

P14 P13

P12

P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

P1 C4(0)

PHASE

ADJUST

PA1

P24

P23

0

.

.......... P2

P1

PHASE VALUE (PHASE)

0

1

DISABLED

ENABLED

0

.

..........

0

1

.

0

1

0

1

.

0

..........

.........

1

2

3

PHASE

PR1

.

RESYNC

.

0

1

DISABLED

ENABLED

.

1

0

1

0

1

0

1

16777212

16777213

16777214

16777215

SD LOAD

RESET

SD1

0

1

ON REGISTER 0 UPDATE

DISABLED

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 29. Register 3

For resync applications, enable the Σ-Δ modulator load reset in

Register 3 by setting DB30 to 0. Phase resync functions only

when FRAC2 = 0.

REGISTER 3

Control Bits

With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 29

shows the input data format for programming this register.

Phase Adjustment

To adjust the relative output phase of the ADF4355-3 on each

Register 0 update, set the PA1 bit (Bit DB28) to 1. This feature

differs from the resynchronization feature in that it is useful when

adjustments to phase are made continually in an application.

For this function, disable the VCO automatic calibration by

setting the AC1 bit (Bit DB21) in Register 0 to 1, and disable the

SD load reset by setting the SD1 bit (Bit DB30) in Register 3 to

1. Note that phase resync and phase adjustment cannot be used

simultaneously.

Reserved

Bit DB31 is reserved and must be set to 0.

SD Load Reset

When writing to Register 0, the Σ-Δ (SD) modulator resets. For

applications in which the phase is continually adjusted, this

reset may not be desirable; therefore, in these cases, the Σ-Δ

reset can be disabled by writing a 1 to the SD1 bit (Bit DB30).

Phase Resync

24-Bit Phase Value

To use the phase resynchronization feature, the PR1 bit (Bit DB29)

must be set to 1. If unused, the bit can be programmed to 0. The

phase resync timer must also be used in Register 12 to ensure

that the resynchronization feature is applied after the PLL settles to

the final frequency. If the PLL has not settled to the final frequency,

phase resync may not function correctly. Resynchronization is

useful in phased array and beam forming applications. It ensures

repeatability of output phase when programming the same

frequency. In phase critical applications that use frequencies

requiring the output divider (<3300 MHz), it is necessary to

feed the N divider with the divided VCO frequency as distinct

from the fundamental VCO frequency, which is achieved by

programming the D13 bit (Bit DB24) in Register 6 to 0, which

ensures divided feedback to the N divider.

The phase of the RF output frequency can be adjusted in 24-bit

steps; from 0° (0) to 360° (2²⁴− 1). For phase adjustment

applications, the phase is set by

(Phase Value/16,777,216) × 360°

(7)

When the phase value is programmed to Register 3, each

subsequent adjustment of Register 0 increments the phase by

the value in this equation.

Rev. B | Page 21 of 34

ADF4355-3

Data Sheet

CURRENT

SETTING

CONTROL

BITS

MUXOUT

10-BIT R COUNTER

DBR¹

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

0

M3

M2

M1 RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1 U6

U5

U4

U3

U2

U1

C3(1) C2(0) C1(0)

C4(0)

REFERENCE

RD2

COUNTER

RESET

DOUBLE BUFFERED

REGISTER 6, BITS[DB23:DB21]

U1

D1

U6

0

REFIN

SINGLE

DIFF

DOUBLER

0

1

DISABLED

ENABLED

0

1

DISABLED

ENABLED

0

1

DISABLED

1

ENABLED

RD1 REFERENCE DIVIDE BY 2

CP

I

(mA)

CP

U2

U5

LDP

THREE-STATE

CP4

CP3

CP2

CP1

5.1kΩ

0

1

DISABLED

ENABLED

0

1

1.8V

3.3V

0

1

DISABLED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.31

0.63

0.94

1.25

1.56

1.88

2.19

2.50

2.81

3.13

3.44

3.75

4.06

4.38

4.69

5.00

ENABLED

R10

R9

..........

R2

R1

R DIVIDER (R)

U4

0

PD POLARITY

NEGATIVE

POSITIVE

U3

POWER DOWN

0

.

0

.

..........

0

1

.

1

0

.

1

0

1

DISABLED

ENABLED

2

1

.

1

0

1

0

1

0

1

1020

1021

1022

1023

M3

0

M2

0

M1

0

OUTPUT

THREE-STATE OUTPUT

DV_DD

0

1

0

1

0

SD

GND

0

1

R DIVIDER OUTPUT

N DIVIDER OUTPUT

RESERVED

1

0

1

0

1

0

DIGITAL LOCK DETECT

RESERVED

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 30. Register 4

The maximum allowable reference frequency when the doubler

is enabled is 100 MHz.

REGISTER 4

Control Bits

RDIV2

With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 30

shows the input data format for programming this register.

Setting the RDIV2 bit (Bit DB25) to 1 inserts a divide by 2

toggle flip-flop between the R counter and PFD, which halves

the reference frequency to the PFD. This function provides a

50% duty cycle signal at the PFD input.

Reserved

Bits[DB31:DB30] are reserved and must be set to 0.

MUXOUT

10-Bit R Counter

The on-chip multiplexer (MUXOUT) is controlled by

Bits[DB29:DB27]. For additional details, see Figure 30.

The 10-bit R counter divides the input reference frequency

(REF_IN) to produce the reference clock to the PFD. Division

ratios range from 1 to 1023.

When changing frequency, that is, writing R0, MUXOUT must

not be set to the N divider output or the R divider output. If

needed, enable these functions after locking to the new frequency.

Double Buffer

The D1 bit (Bit DB14) enables or disables double buffering of

the RF divider select bits (Bits[DB23:DB21]) in Register 6. The

Program Modes section explains double buffering further.

Reference Doubler

Setting the RD2 bit (Bit DB26) to 0 feeds the REF_INsignal directly

to the 10-bit R counter, disabling the doubler. Setting this bit to

1 multiplies the reference frequency by a factor of 2 before feeding

it into the 10-bit R counter. When the doubler is disabled, the

REF_INfalling edge is the active edge at the PFD input to the

fractional synthesizer. When the doubler is enabled, both the rising

and falling edges of the reference frequency become active edges

at the PFD input.

Charge Pump Current Setting

The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump

current. Set this value to the charge pump current that the loop

filter is designed with (see Figure 30). For the lowest spurs, the

0.9 mA setting is recommended.

Rev. B | Page 22 of 34

Data Sheet

ADF4355-3

Reference Mode

When power-down activates, the following events occur:

The ADF4355-3 permits the use of either differential or single-

ended reference sources. For differential sources, set the reference

mode bit (Bit DB9) to 1, and for single-ended sources, set it to 0.

Single-ended mode results in lower integer boundary spurs. If

only a differential signal is available, REF_INB can be left floating

to get the integer boundary spur improvements (provided that

the frequency and power meets the single-ended requirements

shown in Table 1).

•

The synthesizer counters are forced to their load state

conditions.

The VCO powers down.

The charge pump is forced into three-state mode.

The digital lock detect circuitry resets.

The RF_OUTA+/RF_OUTA− and RF_OUTB+/RF_OUTB− output

stages are disabled.

The input registers remain active and capable of loading

and latching data.

•

Level Select

To assist with logic compatibility, MUXOUT is programmable to

two logic levels. Set the U5 bit (Bit DB8) to 0 to select 1.8 V

logic, and set it to 1 to select 3.3 V logic.

Charge Pump Three-State

Setting the U2 bit (Bit DB5) to 1 puts the charge pump into

three-state mode. Set DB5 to 0 for normal operation.

Phase Detector Polarity

Counter Reset

The U4 bit (Bit DB7) sets the phase detector polarity. Set DB7

to 1. Active filters are not supported.

The U1 bit (Bit DB4) resets the R counter, N counter, and VCO

band selection of the ADF4355-3. When DB4 is set to 1, the RF

synthesizer N counter and R counter and the VCO band

selection are reset. For normal operation, set DB4 to 0.

Power-Down

The U3 bit (Bit DB6) sets the programmable power-down mode.

Setting DB6 to 1 performs a power-down. Setting DB6 to 0 returns

the synthesizer to normal operation. In software power-down

mode, the ADF4355-3 retains all information in its registers. The

register contents are lost only if the supply voltages are removed.

REGISTER 5

The bits in Register 5 are reserved and must be programmed as

described in Figure 31, using a hexadecimal word of 0x00800005.

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C4(0) C3(1) C2(0)

0

1

0

1

0

C1(1)

Figure 31. Register 5 (0x00800005)

Rev. B | Page 23 of 34

ADF4355-3

Data Sheet

AUX RF

OUTPUT

POWER

RF

OUTPUT

POWER

RF DIVIDER

SELECT¹

CONTROL

BITS

RESERVED

CHARGE PUMP BLEED CURRENT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BL2

BL3

0

BL10 BL9

1

0

1

0

D13 D12 D11

D10

BL7

BL4

BL1

0

D8

0

D6

D5

D4

D3

D2

D1

BL8

BL6 BL5

C4(0) C3(1) C2(1) C1(0)

FEEDBACK

SELECT

D13

D2

D1

OUTPUT POWER

–4dBm

0

1

0

1

DIVIDED

1

0

1

–1dBm

FUNDAMENTAL

+2dBm

+5dBm

BLEED CURRENT

BL9

D12

D11

D10 RF DIVIDER SELECT

D3

0

RF OUT

0

1

DISABLED

ENABLED

0

1

0

1

0

1

0

1

0

1

0

1

0

÷1

DISABLED

ENABLED

÷2

MUTE TILL

LOCK DETECT

1

D8

÷4

0

1

MUTE DISABLED

MUTE ENABLED

÷8

GATED BLEED

BL10

D5

0

D4

0

AUXILARY OUTPUT POWER

÷16

÷32

÷64

–4dBm

–1dBm

+2dBm

+5dBm

0

1

DISABLED

ENABLED

0

1

0

1

D6

0

AUXILARY OUT

DISABLED

1

ENABLED

BL8

BL7

..........

BL2

BL1 BLEED CURRENT

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

(3.75µA)

(7.5µA)

.

1

0

1

0

1

0

1

252 (945µA)

253 (948.75µA)

254 (952.5µA)

255 (956.25µA)

1

BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT IS ENABLED, BIT DB14 OF REGISTER 4.

Figure 32. Register 6

Reserved

REGISTER 6

Bits[DB28:DB25] are reserved and must be set to 1010.

Control Bits

With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 32

shows the input data format for programming this register.

Feedback Select

D13 (Bit DB24) selects the feedback from the output of the

VCO to the N counter. When D13 is set to 1, the signal is taken

directly from the VCO. When this bit is set to 0, the signal is

taken from the output of the output dividers. The dividers

enable coverage of the wide frequency band (51.5625 MHz to

6.6 GHz). When the divider is enabled and the feedback signal is

taken from the output, the RF output signals of two separately

configured PLLs are in phase. Divided feedback is useful in

some applications where the positive interference of signals is

required to increase the power.

Reserved

Bit DB31 is reserved and must be set to 0.

Gated Bleed

Bleed currents can improve phase noise and spurs. However,

due to a potential impact on lock time, the gated bleed bit, BL10

(Bit DB30), if set to 1, ensures bleed currents are not switched

on until the digital lock detect asserts logic high. Note that this

function requires digital lock detection to be enabled.

Negative Bleed

Divider Select

Use of constant negative bleed is recommended for most

applications because it improves the linearity of the charge

pump, leading to lower noise and spurious performance than

leaving constant negative bleed off. To enable negative bleed,

write 1 to BL9 (Bit DB29), and to disable negative bleed, write 0

to BL9 (Bit DB29). Use negative bleed only when operating in

fractional-N mode, that is, FRAC1 or FRAC2 not equal to 0.

D12 to D10 (Bits[DB23:DB21]) select the value of the RF output

divider (see Figure 32). These bits are buffered by a write to

Register 0 when Bit DB14 of Register 4 is high.

Rev. B | Page 24 of 34

Data Sheet

ADF4355-3

Charge Pump Bleed Current

Reserved

BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed

current added to the charge pump output. This current

optimizes the phase noise and spurious levels from the device.

Bit DB10 is reserved and must be set to 0.

Auxiliary RF Output Enable

Bit DB9 enables or disables the auxiliary frequency RF output

(RF_OUTB+/RF_OUTB−). When DB9 is set to 1, the auxiliary

frequency RF output is enabled. When DB9 is set to 0, the

auxiliary RF output is disabled.

Calculate the optimal bleed setting using Equation 8 and

Equation 9.

If f_PFD≤ 80 MHz,

Auxiliary RF Output Power

Bleed Value = Floor(39 × (f_PFD/61.44 MHz) × (I_CP/0.9 mA)) (8)

If f_PFD> 80 MHz and ≤ 100 MHz,

Bits[DB8:DB7] set the value of the auxiliary RF output power

level.

Bleed Value = Floor(42 × (I_CP/0.9 mA))

If f_PFD> 100 MHz, disable bleed current using DB29.

where:

(9)

RF Output Enable

Bit DB6 enables or disables the primary RF output (RF_OUTA+/

RF_OUTA−). When DB6 is set to 0, the primary RF output is

disabled; when DB6 is set to 1, the primary RF output is

enabled.

Floor() is a function to round down to the nearest integer value.

Bleed Value is the value programmed to Bits[DB20:DB13].

f_PFDis the PFD frequency.

Output Power

I_CPis the value of charge pump current setting, Bits[DB13:DB10] of

Register 4.

Bits[DB5:DB4] set the value of the primary RF output power level.

Reserved

Bit DB12 is reserved and must be set to 0.

Mute Till Lock Detect

When D8 (Bit DB11) is set to 1, the supply current to the RF

output stage is shut down until the device achieves lock, as

determined by the digital lock detect circuitry.

Rev. B | Page 25 of 34

ADF4355-3

Data Sheet

LD

CYCLE

COUNT

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LD4

LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)

0

1

0

LE

0

LD5

LOL

LOCK DETECT MODE

LD1

FRACTIONAL-N

0

1

INTEGER-N (2.9ns)

LD3 LD2

FRACTIONAL-N LD PRECISION

0

1

0

1

0

1

5.0ns

6.0ns

8.0ns

12.0ns

LE

LE SYNCHRONIZATION

LOL LOSS OF LOCK MODE

DISABLED

ENABLED

0

1

0

1

LE SYNCED TO REFIN

LD5 LD4

LOCK DETECT CYCLE COUNT

0

1

0

1

0

1

1024

2048

4096

8192

Figure 33. Register 7

Loss of Lock (LOL) Mode

REGISTER 7

Set LOL (Bit DB7) to 1 when the application is a fixed frequency

application in which the reference (REF_IN) is likely to be removed,

such as a clocking application. The standard lock detect circuit

assumes that REF_INis always present; however, this may not be

the case with clocking applications. To enable this functionality,

set Bit DB7 to 1. Loss of lock mode does not function reliably

when using differential REF_INmode.

Control Bits

With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 33

shows the input data format for programming this register.

Reserved

Bits[DB31:DB29] and Bits[DB27:DB26] are reserved and must

be set to 0. Bit DB28 is reserved and must be set to 1.

LE Sync

Fractional-N Lock Detect Precision (LDP)

When set to 1, Bit DB25 ensures that the load enable (LE) edge

is synchronized internally with the rising edge of the reference

input frequency. This synchronization prevents the rare event of

reference and RF dividers loading at the same time as a falling

edge of reference frequency, which can lead to longer lock times.

LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect

circuitry in fractional-N mode. LDP is available at 5.0 ns, 6.0 ns,

8.0 ns, or 12.0 ns. If bleed currents are used, use 12.0 ns.

Lock Detect Mode (LDM)

If LD1 (Bit DB4) is set to 0, each reference cycle is set by the

fractional-N lock detect precision as described in the

Fractional-N Lock Detect Count (LDC) section. If DB4 is

set to 1, each reference cycle is 2.9 ns long, which is more

appropriate for integer-N applications.

Reserved

Bits[DB24:DB10] are reserved and must be set to 0.

Fractional-N Lock Detect Count (LDC)

LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive

cycles counted by the lock detect circuitry before asserting lock

detect high. See Figure 33 for details.

Rev. B | Page 26 of 34

Data Sheet

ADF4355-3

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

C4(1) C3(0) C2(0) C1(0)

Figure 34. Register 8 (0x1A69A6B8)

SYNTHESIZER

LOCK TIMEOUT

CONTROL

BITS

VCO BAND DIVISION

TIMEOUT

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC8 VC7 VC6

VC5 VC4 VC3 VC2 VC1 TL10 TL9

TL8

TL7

TL6

TL5

TL4

TL3

TL2

TL1

1

SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)

SL5

SL4

..........

SL2

SL1 SLC WAIT

0

.

0

.

..........

0

1

.

1

0

.

1

TL10

TL9

..........

TL2

TL1 TIMEOUT

2

0

.

0

.

..........

0

1

.

1

0

.

1

.

2

.

1

0

1

0

1

0

1

28

29

30

31

.

1

0

1

0

1

0

1

1020

1021

1022

1023

VC8

VC7

..........

VC2

VC1 VCO BAND DIV

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

1

0

1

0

1

0

1

252

253

254

255

Figure 35. Register 9

VCO Band Division

REGISTER 8

VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band

division clock. Determine the value of this clock by

The bits in this register are reserved and must be programmed as

shown in Figure 34, using a hexadecimal word of 0x1A69A6B8.

VCO Band Div = ceiling(f^PFD/2,400,000)

REGISTER 9

Timeout

For a worked example and more information, see the Lock

Time section.

TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the

VCO band selection.

Control Bits

Synthesizer Lock Timeout

With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 35

shows the input data format for programming this register.

SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout

value. This value allows the V_TUNEforce to settle on the V_TUNEpin.

The value must be 20 μs. Calculate the value using Equation 10:

Reserved Bits

Bits[DB13:DB9]) are reserved and must be set to 0b11111.

Synthesizer Lock Timeout > (20 ꢀs × f_PFD)/Timeout

(10)

Rev. B | Page 27 of 34

ADF4355-3

Data Sheet

ADC

CLOCK DIVIDER

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)

0

1

0

AE1 ADC

0

1

DISABLED

ENABLED

AE2 ADC CONVERSION

0

1

DISABLED

ENABLED

AD8

AD7

..........

AD2 AD1 ADC CLK DIV

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

1

0

1

0

1

0

1

252

253

254

255

Figure 36. Register 10

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

C4(1) C3(0) C2(1) C1(1)

0

Figure 37. Register 11 (0x0081200B)

Choose the ADC_CLK_DIV value such that

ADC_CLK_DIV = ceiling(((f^PFD/100,000) − 2)/4)

REGISTER 10

Control Bits

(11)

With Bits[C4:C1] set to 1010, Register 10 is programmed.

Figure 36 shows the input data format for programming this

register.

where ceiling() is a function to round up to the nearest integer.

For example, for f_PFD= 61.44 MHz, set ADC_CLK_DIV = 154

so that the ADC clock frequency is 99.417 kHz. If ADC_CLK_DIV

is greater than 255, set it to 255.

Reserved

Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to

11, and all other bits in this range must be set to 0.

ADC Conversion Enable

AE2 (Bit DB5) ensures that the ADC performs a conversion

when a write to Register 10 is performed. It is recommended to

enable this mode.

ADC Conversion Clock (ADC_CLK_DIV)

An on-board analog-to-digital converter (ADC) is connected to

a temperature sensor. It determines the V_TUNEsetpoint relative

to the ambient temperature of the ADF4355-3 environment.

The ADC ensures that the initial tuning voltage in any application

is chosen correctly to avoid any temperature drift issues.

ADC Enable

AE1 (Bit DB4), when set to 1, powers up the ADC for the

temperature dependent V_TUNEcalibration. It is recommended to

always use this function.

The ADC uses a clock that is equal to the output of the R

counter (or the PFD frequency) divided by ADC_CLK_DIV.

REGISTER 11

The bits in this register are reserved and must be programmed

as described in Figure 37, using a hexadecimal word of

0x0081200B.

AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On

power-up, the R counter is not programmed; however, in these

power-up cases, it defaults to R = 1.

Rev. B | Page 28 of 34

Data Sheet

ADF4355-3

CONTROL

BITS

RESERVED

RESYNC CLOCK

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P13 P12

P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1

C1(0)

C3(1) C2(0)

0

1

0

1

0

P16 P15

C4(1)

P14

P16

0

.

P15

...

P5

P4

P3

P2

P1

RESYNC CLOCK

0

.

...

0

.

0

.

0

.

0

1

.

0

1

0

.

NOT ALLOWED

1

2

...

0

.

0

.

1

.

0

1

.

1

0

.

1

0

.

0

1

0

.

22

23

24

...

1

0

1

0

1

65533

65534

65535

Figure 38. Register 12

14. Register 0.

REGISTER 12

Control Bits

For f_PFD> 75 MHz (initially lock with halved f_PFD), use the

following sequence:

With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 38

shows the input data format for programming this register.

1. Register 12.

2. Register 11.

Phase Resync Clock Divider Value

3. Register 10.

4. Register 4 (with the R divider doubled to halve f_PFD).

5. Register 9.

6. Register 8.

7. Register 7.

P16 to P1 (Bits[DB31:DB16]) set the timeout counter for

activation of phase resync. This value must be set such that a

the resync happens immediately after (and not before) the PLL

achieves lock after reprogramming.

Calculate the timeout value using the following equation:

8. Register 6.

Timeout Value = Phase Resync Clock/f_PFD

Reserved

(12)

9. Register 5.

10. Register 4 (with the R divider doubled to halve f_PFD).

11. Register 3.

12. Register 2 (for halved f_PFD).

13. Register 1 (for halved f_PFD).

14. Wait >16 ADC_CLK cycles. For example, if ADC_CLK =

Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB8 must be set

to 1, but all other bits in this range must be set to 0.

REGISTER INITIALIZATION SEQUENCE

99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10

section for more information.

15. Register 0 (for halved f_PFD; autocalibration enabled).

16. Register 4 (with the R divider set for desired f_PFD).

17. Register 2 (for desired f_PFD).

At initial power-up, after the correct application of voltages to

the supply pins, the ADF4355-3 registers must be programmed

in sequence. For f ≤ 75 MHz, use the following sequence:

1. Register 12.

2. Register 11.

3. Register 10.

4. Register 9.

18. Register 1 (for desired f_PFD).

19. Register 0 (for desired f_PFD; autocalibration disabled).

5. Register 8.

6. Register 7.

7. Register 6.

8. Register 5.

9. Register 4.

10. Register 3.

11. Register 2.

12. Register 1.

13. Wait >16 ADC_CLK cycles. For example, if ADC_CLK =

99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10

section for more information.

Rev. B | Page 29 of 34

ADF4355-3

Data Sheet

For example, in a universal mobile telecommunication system

(UMTS) where 2112.8 MHz RF frequency output (RF_OUT) is

required, a 122.88 MHz reference frequency input (REF_IN) is

available. Note that the ADF4355-3 VCO operates in the

frequency range of 3.3 GHz to 6.6 GHz. Therefore, RF divider

FREQUENCY UPDATE SEQUENCE

Frequency updates require updating the auxiliary modulator

(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,

and the integer value (INT) in Register 0. It is recommended to

perform a temperature dependent V_TUNEcalibration by updating

Register 10 first. Therefore, for f_PFD≤ 75 MHz, the sequence

must be as follows:

of 2 must be used (VCO frequency = 4225.6 MHz, RF_OUT

=

VCO frequency/RF divider = 4225.6 MHz/2 = 2112.8 MHz).

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 39).

1. Register 10.

2. Register 2.

In this example, the 122.88 MHz reference signal is divided by 2

3. Register 1.

to generate an f_PFDvalue of 61.44 MHz. The desired channel

spacing is 200 kHz.

4. Wait >16 ADC_CLK cycles. For example, if ADC_CLK =

99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10

section for more information.

5. Register 0.

f_PFD

RF

OUT

PFD

VCO

÷2

For f_PFD> 75 MHz (initially lock with halved f_PFD), the sequence

must be as follows:

N

DIVIDER

1. Register 10.

Figure 39. Loop Closed Before Output Divider

2. Register 4 (RDivider doubled for halved f_PFD).

3. Register 2 (for halved f_PFD).

The worked example is as follows:

4. Register 1 (for halved f_PFD).

•

N = VCO_OUT/f_PFD= 4225.6 MHz/61.44 MHz =

68.7760416666666667

INT = int(VCO frequency/f_PFD) = 68

FRAC = 0.7760416666666667

5. Wait >16 ADC_CLK cycles. For example, if ADC_CLK =

99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10

section for more information.

6. Register 0 (for halved f_PFD; autocalibration enabled).

7. Register 4 (RDivider set for desired f_PFD).

8. Register 2 (for desired f_PFD).

•

MOD1 = 16,777,216

FRAC1 = int(MOD1 × FRAC) = 13,019,817

Remainder = 0.6666666667 or 2/3

MOD2 = f_PFD/GCD(f_PFD/f_CHSP) = 61.44 MHz/GCD(61.44 MHz/

200 kHz) = 1536

9. Register 1 (for desired f_PFD).

10. Register 0 (for desired f_PFD; autocalibration disabled).

•

FRAC2 = remainder × 1536 = 1024

The frequency change occurs only when writing to Register 0.

RF SYNTHESIZER—A WORKED EXAMPLE

From Equation 14,

Use the following equations to program the ADF4355-3

synthesizer:

f

_PFD= (122.88 MHz × (1 + 0)/2) = 61.44 MHz

(15)

(16)

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/2²⁴))/2

FRAC2

MOD2

MOD1

FRAC1+

where:

INT = 68

FRAC1 = 13,019,817

FRAC2 = 1024

MOD2 = 1536

INT +

RF_OUT

where:

=

× (f_PFD)/RF Divider

(13)

RF_OUTis the RF frequency output.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality.

MOD2 is the auxiliary modulus.

MOD1 is the fixed 24-bit modulus.

RF Divider is the output divider that divides down the VCO

frequency.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system, increase the PFD frequency. Doubling the PFD

frequency typically improves noise performance by 3 dB.

f

_PFD= REF_IN× ((1 + D)/(R × (1 + T)))

(14)

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

where:

REF_INis the reference frequency input.

D is the RF REF_INdoubler bit.

R is the RF reference division factor.

T is the reference divide by 2 bit (0 or 1).

Rev. B | Page 30 of 34

Data Sheet

ADF4355-3

SPURIOUS OPTIMIZATION AND FAST LOCK

LOCK TIME

Narrow loop bandwidths can filter unwanted spurious signals,

but these bandwidths usually have a long lock time. A wider

loop bandwidth achieves faster lock times but may lead to

increased spurious signals inside the loop bandwidth.

The PLL lock time divides into a number of settings. All of

these settings are modeled in the ADIsimPLL design tool.

Much faster lock times than those detailed in this data sheet are

possible; contact Analog Devices, Inc., for more information.

OPTIMIZING JITTER

Synthesizer Lock Timeout

For lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of in-band noise from

the PLL. Set the PLL filter bandwidth such that the in-band noise

of the PLL intersects with the open-loop noise of the VCO,

minimizing the contribution of both to the overall noise.

The synthesizer lock timeout ensures that the VCO calibration

DAC, which forces V_TUNE, settles to a steady value for the band

select circuitry.

The timeout and synthesizer lock timeout variables programmed

in Register 9 select the length of time the DAC is allowed to

settle to the final voltage before the VCO calibration process

continues to the next phase, which is VCO band selection. The

PFD frequency is used as the clock for this logic, and the

duration is set by

Use the ADIsimPLL design tool for this task.

SPUR MECHANISMS

This section describes the two different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4355-3.

(Timeout × Synthesizer Lock Timeout)/f_PFD

The calculated time must be greater than or equal to 20 µs.

VCO Band Selection

(17)

Integer Boundary Spurs

One mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (the purpose of a

fractional-N synthesizer), spur sidebands appear on the VCO

output spectrum at an offset frequency that corresponds to the

beat note or the difference in frequency between an integer

multiple of the reference and the VCO frequency. These spurs

are attenuated by the loop filter and are more noticeable on

channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth (thus

the name, integer boundary spurs).

Use the PFD frequency again as the clock for the band selection

process. Calculate this value by

f_PFD/(VCO Band Selection × 16) < 150 kHz

(18)

The band selection takes 11 cycles of the previously calculated

value. Calculate the duration by

11 × (VCO Band Selection × 16)/f_PFD

(19)

PLL Low-Pass Filter Settling Time

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth. The settling time is also modeled

in the ADIsimPLL design tool.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop may cause a problem. Feedthrough of

low levels of on-chip reference switching noise, through the

prescaler back to the VCO, can result in reference spur levels

as high as −80 dBc.

The total lock time for changing frequencies is the sum of the

three separate times (synthesizer lock, VCO band selection, and

PLL settling time), all of which are modeled in the ADIsimPLL

design tool.

Rev. B | Page 31 of 34

ADF4355-3

Data Sheet

APPLICATIONS INFORMATION

The LO ports of the ADL5375 can be driven differentially from

the complementary RF_OUTA+/RF_OUTA− outputs of the ADF4355-3.

A differential drive gives better second-order distortion perfor-

mance than a single-ended LO driver and eliminates the use of

a balun to convert from a single-ended LO input to the more

desirable differential LO input for the ADL5375.

DIRECT CONVERSION MODULATOR

Direct conversion architectures are used to implement base station

transmitters. Figure 40 shows how to use Analog Devices devices to

implement such a system.

The circuit block diagram shows the AD9761 TxDAC® being

used with the ADL5375. The use of a dual integrated DAC, such

as the AD9761, ensures minimum error contribution (over

temperature) from this portion of the signal chain.

The ADL5375 accepts LO drive levels from −6 dBm to +6 dBm.

The optimum LO power can be software programmed on the

ADF4355-3, which allows levels from −4 dBm to +5 dBm from

each output.

The local oscillator (LO) is implemented using the ADF4355-3.

The low-pass filter was designed using the ADIsimPLL design

tool for a PFD of 61.44 MHz and a closed-loop bandwidth of

20 kHz.

The RF output is designed to drive a 50 Ω load; however, it

must be ac-coupled, as shown in Figure 40. If the I and Q inputs

are driven in quadrature by 2 V p-p signals, the resulting output

power from the ADL5375 modulator is approximately 2 dBm.

51Ω

REFIO

IOUTA

IOUTB

LOW-PASS

FILTER

MODULATED

DIGITAL

DATA

AD9761

TxDAC

QOUTA

QOUTB

LOW-PASS

FILTER

FSADJ

51Ω

2kΩ

V_VCO

LOCK

DETECT

V_DD

16

100nF

25

100nF

2

32

17

26 10

6

5

27

4

30

C

_REG1

C_REG

V_VCO

PDB_RFV_RF

MUXOUT

V_PAV _DDDV_DDAV _DDCE

1nF 1nF

ADL5375

IBBP

FREF_IN

29

REF_IN

A

B

RF_OUTB+ 14

IBBN

V_OUT

RF_OUTB–

FREF_IN

15

28

REF_IN

7.5nH

1

2

3

CLK

DATA

LE

1nF

LOIP

LOIN

11

12

RF_OUTA+

RF_OUTA–

QUADRATURE

PHASE

SPLITTER

LPF

ADF4355-3

RFOUT

DSOP

V_TUNE20

CP_OUT

3.3kΩ

QBBP

QBBN

22 R_SET

7

5.1kΩ

33nF

1500pF

390pF

1kΩ

V_REGVCO

V_BIAS

24

CP_GNDSD_GNDA_GNDA_GNDRFA_GNDVCO

31 13 18 21

V_REF

23

8

9

19

10pF

0.1µF 10pF

10pF

0.1µF

Figure 40. Direct Conversion Modulator

Rev. B | Page 32 of 34

Data Sheet

ADF4355-3

Take care with the RF output traces to minimize discontinuities

and ensure the best signal integrity. Via placement and grounding

are critical.

POWER SUPPLIES

The ADF4355-3 contains four multiband VCOs that together cover

an octave range of frequencies. To ensure best performance, it is

vital to connect a low noise regulator, such as the ADM7150, to

the V_VCOpin. Connect the same regulator to V_VCO, V_REGVCO, V_RF,

and V_P.

OUTPUT MATCHING

The low frequency output can simply be ac-coupled to the next

circuit, if desired; however, if higher output power is required,

use a pull-up inductor to increase the output power level.

For the 3.3 V supply pins, use one or two ADM7150 regulators.

Figure 42 shows the recommended connections.

V

RF

7.5nH

100pF

PRINTED CIRCUIT BOARD (PCB) DESIGN

GUIDELINES FOR A CHIP-SCALE PACKAGE

RF

A+

OUT

50Ω

The lands on the 32-lead lead frame chip-scale package are rectan-

gular. The PCB pad for these lands must be 0.1 mm longer than the

package land length and 0.05 mm wider than the package land

width. Center each land on the pad to maximize the solder joint size.

Figure 41. Optimum Output Stage

When differential outputs are not needed, terminate the unused

output or combine it with both outputs using a balun.

The bottom of the chip-scale package has a central exposed thermal

pad. The thermal pad on the PCB must be at least as large as the

exposed pad. On the PCB, there must be a minimum clearance of

0.25 mm between the thermal pad and the inner edges of the

pad pattern. This clearance ensures the avoidance of shorting.

For lower frequencies below 2 GHz, it is recommended to use a

100 nH inductor on the RF_OUTA+/RF_OUTA− pins.

The RF_OUTA+/RF_OUTA− pins are a differential circuit. Provide

each output with the same (or similar) components where

possible, such as the same shunt inductor value, bypass

capacitor, and termination.

To improve the thermal performance of the package, use thermal

vias on the PCB thermal pad. If vias are used, incorporate them

into the thermal pad at the 1.2 mm pitch grid. The via diameter

must be between 0.3 mm and 0.33 mm, and the via barrel must

be plated with 1 oz. of copper to plug the via.

The auxiliary frequency output, RF_OUTB+/RF_OUTB−, can be

treated the same as the RF_OUTA+/RF_OUTA− output. If unused,

leave both RF_OUTB+/RF_OUTB− pins open.

For a microwave PLL and VCO synthesizer, such as the ADF4355-3,

take care with the board stack-up and layout. Do not use FR4

material because it is too lossy above 3 GHz. Instead, Rogers 4350,

Rogers 4003, or Rogers 3003 dielectric material is suitable.

V

= 6.0V

V

= 3.3V

OUT

IN

OUT

VIN

EN

VOUT

C

IN

C

ADM7150

1µF

ON

1µF

LOCK

DETECT

100nF

OFF

REF

BYP

25

C_REG

10

V_VCOV_PV_RF

5

26

17

6

27

4

32

C_REG

16

30

C

BYP

VREG

REF_SENSE

2

1

MUXOUT

DV_DDAV_DDCE PDB_RF

AV_DD

1µF

1nF 1nF

C

10µF

REG

FREF_IN

GND

29

REF_IN

A

RF_OUTB+ 14

V_OUT

RF_OUTB–

15

28 REF_INB

7.5nH

1

2

3

CLK

DATA

LE

1nF

11

12

RF_OUTA+

RF_OUTA–

ADF4355-3

V

= 6.0V

V

= 3.3V

IN

OUT

VIN

VOUT

V_TUNE

20

7

C

1µF

IN

C

1µF

OUT

ADM7150

1kΩ

ON

EN

CP_OUT

22 R_SET

OFF

5.1kΩ

47nF

REF

2700pF

680pF

BYP

C

1µF

BYP

360kΩ

VREG

REF_SENSE

CP_GNDSD_GNDA_GNDA_GNDRFA_GNDVCO

31 13 18 21

V_REGVCOV_REFV_BIAS

19 23 24

C

10µF

REG

8

9

GND

10pF

0.1µF 10pF

0.1µF

Figure 42. Power Supplies

Rev. B | Page 33 of 34

ADF4355-3

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

S

INDIC ATOR AREA OPTION

(SEE DETAIL A)

25

32

24

1

0.50

BSC

3.75

3.60 SQ

3.55

EXPOSED

PAD

17

8

16

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.

Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height

(CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADF4355-3BCPZ

ADF4355-3BCPZ-RL7

EV-ADF4355-3SD1Z

Temperature Range

−40°C to +105°C

Package Description

Package Option

32-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-32-12

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D13345-0-8/17(B)

Rev. B | Page 34 of 34


型号：	ADF4355-3
厂家：	ADI
描述：	Microwave Wideband Synthesizer with Integrated VCO
文件：	总34页 (文件大小：819K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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