ADF4360-6BCPZRL7_技术文档

Integrated Synthesizer and VCO

ADF4360-6

FEATURES

GENERAL DESCRIPTION

Output frequency range: 1050 MHz to 1250 MHz

Divide-by-2 output

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Integer-N synthesizer

Programmable dual-modulus prescaler 8/9, 16/17, 32/33

Programmable output power level

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

The ADF4360-6 is a fully integrated integer-N synthesizer and

voltage-controlled oscillator (VCO). The ADF4360-6 is de-

signed for a center frequency of 1150 MHz. In addition, a di-

vide-by-2 option is available, whereby the user receives an RF

output of between 525 MHz and 625 MHz.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging from

3.0 V to 3.6 V and can be powered down when not in use.

APPLICATIONS

Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)

Test equipment

Wireless LANs

CATV equipment

FUNCTIONAL BLOCK DIAGRAM

AV

DV

CE

R

SET

DD

ADF4360-6

MUXOUT

MULTIPLEXER

14-BIT R

COUNTER

REF

IN

LOCK

DETECT

MUTE

CLK

DATA

LE

24-BIT

FUNCTION

LATCH

24-BIT

DATA REGISTER

CHARGE

PUMP

CP

PHASE

COMPARATOR

V

VCO

TUNE

C

N

C

INTEGER

REGISTER

RF

A

B

OUT

VCO

CORE

OUTPUT

STAGE

13-BIT B

COUNTER

OUT

LOAD

5-BIT A

COUNTER

PRESCALER

P/P+1

N = (BP + A)

÷2

DIVSEL = 1

DIVSEL = 2

CPGND

AGND

DGND

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADF4360-6

TABLE OF CONTENTS

Specifications..................................................................................... 3

VCO ............................................................................................. 10

Output Stage................................................................................ 11

Latch Structure ........................................................................... 12

Power-Up..................................................................................... 16

Control Latch.............................................................................. 18

N Counter Latch......................................................................... 19

R Counter Latch ......................................................................... 19

Applications..................................................................................... 20

Direct Conversion Modulator .................................................. 20

Fixed Frequency LO................................................................... 21

Interfacing ................................................................................... 21

PCB Design Guidelines for Chip Scale Package........................... 22

Output Matching........................................................................ 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description........................................................................... 9

Reference Input Section............................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

PFD and Charge Pump................................................................ 9

MUXOUT and Lock Detect...................................................... 10

Input Shift Register..................................................................... 10

REVISION HISTORY

12/04—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Specifications................................................................ 3

Changes to Timing Characteristics................................................ 5

Changes to Power-Up Section ...................................................... 16

Added Table 10 ............................................................................... 16

Added Figure 16.............................................................................. 16

Changes to Ordering Guide .......................................................... 23

Updated Outline Dimensions....................................................... 23

11/03—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADF4360-6

SPECIFICATIONS¹

AV_DD= DV_DD= V_VCO= 3.3 V 10%; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

B Version

Unit

Conditions/Comments

REF_INCHARACTERISTICS

REF_INInput Frequency

10/250

MHz min/max

For f < 10 MHz, use a dc-coupled CMOS-compatible

square wave, slew rate > 21 V/µs.

REF_INInput Sensitivity

0.7/AV_DD

0 to AV_DD

5.0

V p-p min/max

V max

pF max

AC-coupled.

CMOS compatible.

REF_INInput Capacitance

REF_INInput Current

PHASE DETECTOR

Phase Detector Frequency²

CHARGE PUMP

100

µA max

8

MHz max

I_CPSink/Source³

With R_SET= 4.7 kΩ.

High Value

Low Value

R_SETRange

2.5

mA typ

kΩ

nA typ

% typ

0.312

2.7/10

0.2

2

1.5

I_CPThree-State Leakage Current

Sink and Source Current Matching

I_CPvs. V_CP

I_CPvs. Temperature

LOGIC INPUTS

1.25 V ≤ V_CP≤ 2.5 V.

V_CP= 2.0 V.

2

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

C_IN, Input Capacitance

LOGIC OUTPUTS

V_OH, Output High Voltage

I_OH, Output High Current

V_OL, Output Low Voltage

POWER SUPPLIES

AV_DD

1.5

0.6

1

V min

V max

µA max

pF max

3.0

DV_DD– 0.4

500

0.4

V min

µA max

V max

CMOS output chosen.

I_OL= 500 µA.

3.0/3.6

AV_DD

10

2.5

19.0

V min/V max

DV_DD

V_VCO

AI_DD

4

mA typ

µA typ

4

DI_DD

4, 5

I_VCO

I_CORE= 10 mA.

RF output stage is programmable.

4

I_RFOUT

3.5 to 11.0

7

Low Power Sleep Mode⁴

RF OUTPUT CHARACTERISTICS⁵

VCO Output Frequency

VCO Sensitivity

1050/1250

32

400

6

15

MHz min/max

MHz/V typ

µs typ

MHz/V typ

kHz typ

I_CORE= 10 mA.

Lock Time⁶

To within 10 Hz of final frequency.

Into 2.00 VSWR load.

Frequency Pushing (Open Loop)

Frequency Pulling (Open Loop)

Harmonic Content (Second)

Harmonic Content (Third)

Output Power^{5, 7}

−13

−19

dBc typ

−13.5/−4.5 dBm typ

Programmable in 3 dB steps. See Table 7.

Output Power Variation

VCO Tuning Range

3

dB typ

V min/max

For tuned loads, see the Output Matching section.

1.25/2.5

Rev. A | Page 3 of 24

ADF4360-6

Parameter

B Version

Unit

Conditions/Comments

NOISE CHARACTERISTICS⁵

VCO Phase-Noise Performance⁸

−110

−132

−141

−147

−172

−163

−147

−88

dBc/Hz typ

Degrees typ

dBc typ

@ 100 kHz offset from carrier.

@ 1 MHz offset from carrier.

@ 3 MHz offset from carrier.

@ 10 MHz offset from carrier.

@ 25 kHz PFD frequency.

@ 200 kHz PFD frequency.

@ 8 MHz PFD frequency.

@ 1 kHz offset from carrier.

100 Hz to 100 kHz.

Synthesizer Phase-Noise Floor⁹

In-Band Phase Noise^{10, 11}

RMS Integrated Phase Error¹²

0.64

−65

Spurious Signals due to PFD Frequency^{11, 13}

Level of Unlocked Signal with MTLD Enabled

−44

dBm typ

¹Operating temperature range is –40°C to +85°C.

²Guaranteed by design. Sample tested to ensure compliance.

³I_CPis internally modified to maintain constant loop gain over the frequency range.

⁴T_A= 25°C; AV_DD= DV_DD= V_VCO= 3.3 V; P = 32.

⁵These characteristics are guaranteed for VCO core power = 10 mA.

⁶Jumping from 1.0 GHz to 1.25 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

⁷Using 50 Ω resistors to V_VCO, into a 50 Ω load. For tuned loads, see the Output Matching section.

⁸The noise of the VCO is measured in open-loop conditions.

⁹The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).

¹⁰The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF_INfor the

synthesizer; offset frequency = 1 kHz.

11

f

= 10 MHz; f_PFD= 200 kHz; N = 5000; Loop B/W = 10 kHz.

= 10 MHz; f_PFD= 1 MHz; N = 1000; Loop B/W = 25 kHz.

REFIN

12

REFIN

¹³The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF_INfor

the synthesizer; f_REFOUT= 10 MHz @ 0 dBm.

Rev. A | Page 4 of 24

ADF4360-6

TIMING CHARACTERISTICS¹

AV_DD= DV_DD= V_VCO= 3.3 V 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T_A= T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

Limit at T_MINto T_MAX(B Version)

Unit

Test Conditions/Comments

LE Setup Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

20

10

25

10

20

ns min

DATA to CLOCK Setup Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Setup Time

LE Pulse Width

¹See the Power-Up section for the recommended power-up procedure for this device.

t₄

t₅

CLOCK

t₂

t₃

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

DB22

DB2

DATA

LE

t₇

t₁

t₆

LE

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

ADF4360-6

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 3.

Parameter

AV_DDto GND¹

Rating

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rat-

ing only; functional operation of the device at these or any

other conditions above those indicated in the operational sec-

tions of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to V_DD+ 0.3 V

AV_DDto DV_DD

V_VCOto GND

V_VCOto AV_DD

Digital I/O Voltage to GND

Analog I/O Voltage to GND

REF_INto GND

Operating Temperature Range

Maximum Junction Temperature

CSP θ_JAThermal Impedance

(Paddle Soldered)

(Paddle Not Soldered)

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

This device is a high performance RF integrated circuit with an

ESD rating of <1 kV and it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

150°C

50°C/W

88°C/W

TRANSISTOR COUNT

215°C

220°C

12543 (CMOS) and 700 (Bipolar).

¹GND = AGND = DGND = 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-

trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation

or loss of functionality.

Rev. A | Page 6 of 24

ADF4360-6

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

IDENTIFIER

CPGND

AV

1

2

3

4

5

6

18 DATA

17 CLK

DD

ADF4360-6

TOP VIEW

(Not to Scale)

AGND

16 REF

IN

RF

A

B

15 DGND

OUT

14

13

C

R

N

V

VCO

SET

Figure 3. Pin Configuration

Table 4. Pin Functional Descriptions

Pin No.

Mnemonic Description

1

2

CPGND

AV_DD

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AV_DDmust have the same value as DV_DD.

3, 8 to 11, 22 AGND

Analog Ground. This is the ground return path of the prescaler and VCO.

4

5

6

RF_OUT

V_VCO

A

VCO Output. The output level is programmable from −4.5 dBm to −13.5 dBm. See the Output Matching section

for a description of the various output stages.

VCO Complementary Output. The output level is programmable from −4.5 dBm to −13.5 dBm. See the Output

Matching section for a description of the various output stages.

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. V_VCOmust have the same value as AV_DD.

B

7

12

13

V_TUNE

C_C

R_SET

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.

Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.

Connecting a resistor between this pin and CP_GNDsets the maximum charge pump output current for the syn-

thesizer. The nominal voltage potential at the R_SETpin is 0.6 V. The relationship between I_CPand R_SETis

11.75

R_SET

I_CPmax

=

Where R_SET= 4.7 kΩ, I_CPmax= 2.5 mA.

14

15

16

C_N

DGND

REF_IN

Internal Compensation Node. This pin must be decoupled to V_VCOwith a 10 µF capacitor.

Digital Ground.

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and a dc equivalent input resistance of

100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

17

18

19

20

21

23

24

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches, and the relevant latch is selected using the control bits.

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally.

Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DV_DDmust have the same value as AV_DD.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

Taking the pin high powers up the device depending on the status of the power-down bits.

DATA

LE

MUXOUT

DV_DD

CE

CP

Charge Pump Output. When enabled, this provides I_CPto the external loop filter, which in turn drives the internal VCO.

Rev. A | Page 7 of 24

ADF4360-6

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

V

= 3V, V

= 3V

VCO

DD

I

= 2.5mA

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 10kHz

RES. BANDWIDTH = 30Hz

VIDEO BANDWIDTH = 30Hz

SWEEP = 1.9SECONDS

–40 AVERAGES = 10

–50

–70

–80

1

–90

2

–100

–110

–120

–130

–140

–150

–160

–170

–87.5dBc/Hz

–60

–70

–80

–90

3

4

1k

10k

100k

1M

10M

–2kHz

–1kHz

1150MHz

1kHz

2kHz

FREQUENCY OFFSET (Hz)

Figure 7. Close-In Phase Noise at 1150 MHz (200 kHz Channel Spacing)

Figure 4. Open-Loop VCO Phase Noise

–70

–75

–80

–85

0

V

I

= 3V, V

= 2.5mA

= 3V

VCO

DD

–10

–20

–30

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 10kHz

RES. BANDWIDTH = 3kHz

VIDEO BANDWIDTH = 3kHz

SWEEP = 140ms

–90

–95

–100

–40 AVERAGES = 100

–50

–105

–110

–115

–120

–125

–130

–135

–140

–145

–73.7dBc

–60

–70

–80

–90

–150

100

1k

10k

100k

1M

10M

–200kHz

–100kHz

1150MHz

100kHz

200kHz

FREQUENCY OFFSET (Hz)

Figure 8. Reference Spurs at 1150 MHz

(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)

Figure 5. VCO Phase Noise, 1150 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth

–70

–75

–80

–85

0

–10

–20

–30

–40

–50

V

= 3V, V

= 2.5mA

= 3V

VCO

DD

I

CP

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 25kHz

RES. BANDWIDTH = 30kHz

VIDEO BANDWIDTH = 30kHz

SWEEP = 50ms

–90

–95

–100

AVERAGES = 100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–73.3dBc/Hz

–60

–70

–80

–90

–150

100

1k

10k

100k

1M

10M

–1MHz

–0.5MHz

1150MHz

0.5MHz

1MHz

FREQUENCY OFFSET (Hz)

Figure 9. Reference Spurs at 1150 MHz

(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)

Figure 6. VCO Phase Noise, 575 MHz,

Divide-by-2 Enabled, 200 kHz PFD, 10 kHz Loop Bandwidth

Rev. A | Page 8 of 24

ADF4360-6

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 10. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

N = BP + A

13-BIT B

COUNTER

TO PFD

LOAD

PRESCALER

P/P+1

FROM VCO

LOAD

5-BIT A

MODULUS

CONTROL

POWER-DOWN

CONTROL

COUNTER

N DIVIDER

100kΩ

SW2

NC

TO R COUNTER

REF

Figure 11. A and B Counters

IN

NC

SW1

BUFFER

R COUNTER

SW3

NO

The 14-bit R counter allows the input reference frequency to

be divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

Figure 10. Reference Input Stage

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B

counters, enables the large division ratio, N, to be realized

(N = BP + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the VCO and divides it down to a

manageable frequency for the CMOS A and B counters. The

prescaler is programmable. It can be set in software to 8/9,

16/17, or 32/33 and is based on a synchronous 4/5 core. There is

a minimum divide ratio possible for fully contiguous output

frequencies; this minimum is determined by P, the prescaler

value, and is given by (P²− P).

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter

(N = BP + A) and produces an output proportional to the phase

and frequency difference between them. Figure 12 is a simpli-

fied schematic. The PFD includes a programmable delay ele-

ment that controls the width of the antibacklash pulse. This

pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. Two

bits in the R counter latch, ABP2 and ABP1, control the width of

the pulse (see Table 9).

A AND B COUNTERS

V

P

CHARGE

PUMP

The A and B CMOS counters combine with the dual-modulus

prescaler to allow a wide range division ratio in the PLL feed-

back counter. The counters are specified to work when the pre-

scaler output is 300 MHz or less. Thus, with a VCO frequency of

2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is

not valid.

UP

HI

D1

Q1

U1

R DIVIDER

CLR1

Pulse Swallow Function

PROGRAMMABLE

DELAY

CP

U3

The A and B counters, in conjunction with the dual-modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

VCO frequency equation is

ABP1

ABP2

CLR2

U2

DOWN

HI

D2

Q2

( )

f_VCO=[ P × B + A]× f_REFIN/R

N DIVIDER

CPGND

where:

f_VCOis the output frequency of the VCO.

P is the preset modulus of the dual-modulus prescaler (8/9,

16/17, and so on).

B is the preset divide ratio of the binary 13-bit counter (3 to 8191).

A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).

f_REFINis the external reference frequency oscillator.

R DIVIDER

N DIVIDER

CP OUTPUT

Figure 12. PFD Simplified Schematic and Timing (In Lock)

Rev. A | Page 9 of 24

ADF4360-6

Table 5. C2 and C1 Truth Table

MUXOUT AND LOCK DETECT

Control Bits

The output multiplexer on the ADF4360 family allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. The full truth table is shown in Table 7. Figure 13 shows

the MUXOUT section in block diagram form.

Data Latch

C2

0

C1

0

1

Control Latch

R Counter

1

0

1

N Counter (A and B)

Test Mode Latch

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital and analog. Digital lock detect is active high. When LDP

in the R counter latch is set to 0, digital lock detect is set high

when the phase error on three consecutive phase detector cycles

is less than 15 ns.

VCO

The VCO core in the ADF4360 family uses eight overlapping

bands, as shown in Figure 14, to allow a wide frequency range to

be covered without a large VCO sensitivity (K_V) and resultant

poor phase noise and spurious performance.

With LDP set to 1, five consecutive cycles of less than 15 ns

phase error are required to set the lock detect. It stays set high

until a phase error of greater than 25 ns is detected on any sub-

sequent PD cycle.

The correct band is chosen automatically by the band select

logic at power-up or whenever the N counter latch is updated. It

is important that the correct write sequence be followed at

power-up. This sequence is

The N-channel open-drain analog lock detect should be oper-

ated with an external pull-up resistor of 10 kΩ nominal. When a

lock has been detected, this output is high with narrow low-

going pulses.

1. R counter latch

2. Control latch

3. N counter latch

DV

DD

During band select, which takes five PFD cycles, the VCO V_TUNE

is disconnected from the output of the loop filter and connected

to an internal reference voltage.

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

3.5

3.0

2.5

MUXOUT

MUX

CONTROL

2.0

1.5

DGND

Figure 13. MUXOUT Circuit

INPUT SHIFT REGISTER

1.0

0.5

0

The ADF4360 family’s digital section includes a 24-bit input

shift register, a 14-bit R counter, and an 18-bit N counter

comprised of a 5-bit A counter and a 13-bit B counter. Data is

clocked into the 24-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from the

shift register to one of four latches on the rising edge of LE. The

destination latch is determined by the state of the two control

bits (C2, C1) in the shift register. These are the two LSBs—DB1,

DB0—as shown in Figure 2.

900

1000

1100

1200

1300

1400

FREQUENCY (MHz)

Figure 14. Frequency vs. V_TUNE, ADF4360-6

The R counter output is used as the clock for the band select logic

and should not exceed 1 MHz.A programmable divider is provided

at the R counter input to allow division by 1, 2, 4, or 8 and is con-

trolled by Bits BSC1 and BSC2 in the R counter latch.Where the

required PFD frequency exceeds 1 MHz, the divide ratio should be

set to allow enough time for correct band selection.

The truth table for these bits is shown in Table 5. Table 6 shows

a summary of how the latches are programmed. Note that the

test mode latch is used for factory testing and should not be

programmed by the user.

After band selection, normal PLL action resumes. The nominal

value of K_Vis 32 MHz/V, or 16 MHz/V if divide-by-2 operation has

been selected (by programming DIV2 [DB22] high in the N

counter latch). The ADF4360 family contains linearization circuitry

to minimize any variation of the product of I_CPand K_V.

Rev. A | Page 10 of 24

ADF4360-6

The operating current in the VCO core is programmable in four

steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by

Bits PC1 and PC2 in the control latch.

If the outputs are used individually, the optimum output stage

consists of a shunt inductor to V_DD.

Another feature of the ADF4360 family is that the supply current

to the RF output stage is shut down until the part achieves lock as

measured by the digital lock detect circuitry. This is enabled by the

mute-till-lock detect (MTLD) bit in the control latch.

OUTPUT STAGE

The RF_OUTA and RF_OUTB pins of the ADF4360 family are con-

nected to the collectors of an NPN differential pair driven by

buffered outputs of the VCO, as shown in Figure 15. To allow

the user to optimize the power dissipation versus the output

power requirements, the tail current of the differential pair is

programmable via Bits PL1 and PL2 in the control latch. Four

current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.

These levels give output power levels of −13.5 dBm, −10.5 dBm,

−7.5 dBm, and −4.5 dBm, respectively, using a 50 Ω resistor to

RF

A

RF

B

OUT

BUFFER/

DIVIDE BY 2

VCO

V_DDand ac coupling into a 50 Ω load. Alternatively, both out-

puts can be combined in a 1 + 1:1 transformer or a 180° micro-

strip coupler (see the Output Matching section).

Figure 15. Output Stage ADF4360-6

Rev. A | Page 11 of 24

ADF4360-6

LATCH STRUCTURE

Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed.

Table 6. Latch Structure

CONTROL LATCH

OUTPUT

POWER

LEVEL

CORE

POWER

LEVEL

PRESCALER

VALUE

CURRENT

SETTING 2

CURRENT

SETTING 1

MUXOUT

CONTROL

BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2

P1

PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP

PDP

M3

M2

M1

CR

PC2 PC1 C2 (0) C1 (0)

N COUNTER LATCH

CONTROL

BITS

13-BIT B COUNTER

5-BIT A COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DIVSEL DIV2 CPG B13 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

RSV A5

A4

A3

A2

A1 C2 (1) C1 (0)

R COUNTER LATCH

ANTI-

BACKLASH

PULSE

BAND

SELECT

CLOCK

CONTROL

BITS

14-BIT REFERENCE COUNTER

WIDTH

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (1)

Rev. A | Page 12 of 24

ADF4360-6

Table 7. Control Latch

OUTPUT

POWER

LEVEL

CORE

POWER

LEVEL

PRESCALER

VALUE

CURRENT

SETTING 2

CURRENT

SETTING 1

MUXOUT

CONTROL

BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P2

P1

PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP

PDP

M3

M2

M1

CR

PC2 PC1 C2 (0) C1 (0)

PC2

CORE POWER LEVEL

PC1

0

1

5mA

0

1

0

1

10mA

15mA

20mA

I

(mA)

PHASE DETECTOR

PDP POLARITY

CPI6

CPI3

CPI5

CPI2

CPI4

CPI1

CP

4.7kΩ

COUNTER

0

1

NEGATIVE

POSITIVE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.31

0.62

0.93

1.25

1.56

1.87

2.18

2.50

CR

OPERATION

0

1

NORMAL

R, A, B COUNTERS

HELD IN RESET

CHARGE PUMP

OUTPUT

NORMAL

CP

0

1

THREE-STATE

CP GAIN

CPG

0

1

CURRENT SETTING 1

CURRENT SETTING 2

MUTE-TILL-LOCK DETECT

DISABLED

ENABLED

MTLD

0

1

M3

0

M2

0

M1

0

1

OUTPUT

THREE-STATE OUTPUT

DIGITAL LOCK DETECT

(ACTIVE HIGH)

PL2

PL1

OUTPUT POWER LEVEL

CURRENT

POWER INTO 50Ω (USING 50Ω TO V

)

VCO

0

1

0

1

0

1

3.5mA

5.0mA

7.5mA

11.0mA

–13.5dBm

–10.5dBm

–7.5dBm

–4.5dBm

0

1

0

1

N DIVIDER OUTPUT

DV

DD

R DIVIDER OUTPUT

N-CHANNEL OPEN-DRAIN

LOCK DETECT

1

0

1

SERIAL DATA OUTPUT

DGND

1

0

1

CE PIN

PD2

X

0

1

PD1

X

0

1

MODE

0

1

ASYNCHRONOUS POWER-DOWN

NORMAL OPERATION

ASYNCHRONOUS POWER-DOWN

SYNCHRONOUS POWER-DOWN

P2

0

P1

0

PRESCALER VALUE

8/9

0

1

0

1

16/17

32/33

Rev. A | Page 13 of 24

ADF4360-6

Table 8. N Counter Latch

CONTROL

BITS

13-BIT B COUNTER

5-BIT A COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DIVSEL DIV2 CPG B13 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

RSV A5

A4

A3

A2

A1 C2 (1) C1 (0)

THIS BIT IS NOT USED

BY THE DEVICE AND

IS A DON'T CARE BIT.

A COUNTER

A5

A4

..........

A2

A1

DIVIDE RATIO

0

.

1

0

.

1

..........

0

1

.

0

1

0

1

0

1

.

0

1

0

1

0

1

2

3

.

28

29

30

31

B13

B12

B11

B3

B2

0

1

.

0

1

B1

0

1

0

1

.

0

1

0

1

B COUNTER DIVIDE RATIO

NOT ALLOWED

3

.

8188

8189

8190

8191

0

.

1

0

.

1

0

.

1

..........

0

1

.

1

F4 (FUNCTION LATCH)

FASTLOCK ENABLE

CP GAIN OPERATION

0

1

CHARGE PUMP CURRENT SETTING 1

IS PERMANENTLY USED

CHARGE PUMP CURRENT SETTING 2

IS PERMANENTLY USED

N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.

B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY

2

ADJACENT VALUES OF (N

×

F

), AT THE OUTPUT, N

IS (P –P).

MIN

REF

DIVIDE-BY-2

DIV2

0

1

FUNDAMENTAL OUTPUT

DIVIDE-BY-2

DIVIDE-BY-2 SELECT (PRESCALER INPUT)

DIVSEL

0

1

FUNDAMENTAL OUTPUT SELECTED

DIVIDE-BY-2 SELECTED

Rev. A | Page 14 of 24

ADF4360-6

Table 9. R Counter Latch

ANTI-

BACKLASH

PULSE

BAND

SELECT

CLOCK

CONTROL

BITS

14-BIT REFERENCE COUNTER

WIDTH

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (0) C1 (1)

R14

0

R13

R12

R3

0

1

.

1

R2

0

1

0

.

0

1

R1

DIVIDE RATIO

0

.

1

0

.

1

..........

0

1

0

1

.

0

1

0

1

2

3

4

.

0

.

TEST MODE

BIT SHOULD

BE SET TO 0

FOR NORMAL

OPERATION.

THESE BITS ARE NOT

USED BY THE DEVICE

AND ARE DON'T CARE

BITS.

.

1

16380

16381

16382

16383

ABP2

ABP1

ANTIBACKLASH PULSE WIDTH

0

1

0

1

0

1

3.0ns

1.3ns

6.0ns

3.0ns

LDP

0

LOCK DETECT PRECISION

THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1

BSC2

BSC1

BAND SELECT CLOCK DIVIDER

0

1

0

1

0

1

2

4

8

Rev. A | Page 15 of 24

ADF4360-6

During initial power-up, a write to the control latch powers up

the part and the bias currents of the VCO begin to settle. If

these currents have not settled to within 10% of their steady-

state value and if the N counter latch is then programmed, the

VCO may not be able to oscillate at the desired frequency,

which does not allow the band select logic to choose the correct

frequency band, and the ADF4360-6 may not achieve lock. If

the recommended interval is inserted, and the N counter latch

is programmed, the band select logic can choose the correct

frequency band, and the part locks to the correct frequency.

POWER-UP

Power-Up Sequence

The correct programming sequence for the ADF4360-6 after

power-up is:

1. R counter latch

2. Control latch

3. N counter latch

Initial Power-Up

The duration of this interval is affected by the value of the ca-

pacitor on the C_Npin (Pin 14). This capacitor is used to reduce

the close-in noise of the ADF4360-6 VCO. The recommended

value of this capacitor is 10 µF. Using this value requires an in-

terval of ≥ 5 ms between the latching in of the control latch bits

and latching in of the N counter latch bits. If a shorter delay is

required, this capacitor can be reduced. A slight phase noise

penalty is incurred by this change, which is explained further in

Table 10.

Initial power-up refers to programming the part after the

application of voltage to the AV_DD, DV_DD, V_VCO, and CE pins. On

initial power-up, an interval is required between programming

the control latch and programming the N counter latch. This

interval is necessary to allow the transient behavior of the

ADF4360-6 during initial power-up to have settled.

Table 10. C_NCapacitance vs. Interval and Phase Noise

C_NValue

Recommended Interval between Control Latch and N Counter Latch

Open-Loop Phase Noise @ 10 kHz Offset

10 µF

440 nF

≥ 5 ms

≥ 600 µs

−88 dBc

−87 dBc

POWER-UP

CLOCK

R COUNTER

LATCH DATA

CONTROL

LATCH DATA

N COUNTER

LATCH DATA

DATA

LE

REQUIRED INTERVAL

CONTROL LATCH WRITE TO

N COUNTER LATCH WRITE

Figure 16. ADF4360-6 Power-Up Timing

Rev. A | Page 16 of 24

ADF4360-6

Hardware Power-Up/Power-Down

Software Power-Up/Power-Down

If the part is powered down via the hardware (using the CE pin)

and powered up again without any change to the N counter

register during power-down, the part locks at the correct fre-

quency because the part is already in the correct frequency

band. The lock time depends on the value of capacitance on the

C_Npin, which is <5 ms for 10 µF capacitance. The smaller ca-

pacitance of 440 nF on this pin enables lock times of <600 µs.

If the part is powered down via the software (using the control

latch) and powered up again without any change to the N

counter latch during power-down, the part locks at the correct

frequency because the part is already in the correct frequency

band. The lock time depends on the value of capacitance on the

C_Npin, which is <5 ms for 10 µF capacitance. The smaller ca-

pacitance of 440 nF on this pin enables lock times of <600 µs.

The N counter value cannot be changed while the part is in

power-down because the part may not lock to the correct fre-

quency on power-up. If it is updated, the correct programming

sequence for the part after power-up is to the R counter latch,

followed by the control latch, and finally the N counter latch,

with the required interval between the control latch and N

counter latch, as described in the Initial Power-Up section.

The N counter value cannot be changed while the part is in

power-down because the part may not lock to the correct fre-

quency on power-up. If it is updated, the correct programming

sequence for the parts after power-up is to the R counter latch,

followed by the control latch, and finally the N counter latch,

with the required interval between the control latch and N

counter latch, as described in the Initial Power-Up section.

Rev. A | Page 17 of 24

ADF4360-6

Charge Pump Currents

CONTROL LATCH

CPI3, CPI2, and CPI1 in the ADF4360 family determine

Current Setting 1.

With (C2, C1) = (0, 0), the control latch is programmed. Table 7

shows the input data format for programming the control latch.

CPI6, CPI5, and CPI4 determine Current Setting 2. See the

truth table in Table 7.

Prescaler Value

In the ADF4360 family, P2 and P1 in the control latch set the

prescaler values.

Output Power Level

Bits PL1 and PL2 set the output power level of the VCO. See the

truth table in Table 7

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable power-

down modes.

Mute-Till-Lock Detect

DB11 of the control latch in the ADF4360 family is the mute-till-

lock detect bit. This function, when enabled, ensures that the RF

outputs are not switched on until the PLL is locked.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into Bit PD1, with

the condition that PD2 has been loaded with a 0. In the pro-

grammed synchronous power-down, the device power-down is

gated by the charge pump to prevent unwanted frequency

jumps. Once the power-down is enabled by writing a 1 into

Bit PD1 (on the condition that a 1 has also been loaded to PD2),

the device goes into power-down on the second rising edge of

the R counter output, after LE goes high. When the CE pin is

low, the device is immediately disabled regardless of the state of

PD1 or PD2.

CP Gain

DB10 of the control latch in the ADF4360 family is the charge

pump gain bit. When it is programmed to 1, Current Setting 2 is

used. When it is programmed to 0, Current Setting 1 is used.

Charge Pump Three-State

This bit puts the charge pump into three-state mode when

programmed to a 1. It should be set to 0 for normal operation.

Phase Detector Polarity

When a power-down is activated (either synchronous or

asynchronous mode), the following events occur:

The PDP bit in the ADF4360 family sets the phase detector

polarity. The positive setting enabled by programming a 1 is

used when using the on-chip VCO with a passive loop filter or

with an active noninverting filter. It can also be set to 0, which is

required if an active inverting loop filter is used.

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load

state conditions.

MUXOUT Control

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

The on-chip multiplexer is controlled by M3, M2, and M1.

See the truth table in Table 7.

Counter Reset

• The RF outputs are debiased to a high impedance state.

• The reference input buffer circuitry is disabled.

DB4 is the counter reset bit for the ADF4360 family. When this

is 1, the R counter and the A, B counters are reset. For normal

operation, this bit should be 0.

• The input register remains active and capable of loading and

Core Power Level

latching data.

PC1 and PC2 set the power level in the VCO core. The recom-

mended setting is 10 mA. See the truth table in Table 7.

Rev. A | Page 18 of 24

ADF4360-6

N COUNTER LATCH

R COUNTER LATCH

With (C2, C1) = (1, 0), the N counter latch is programmed.

Table 8 shows the input data format for programming the

N counter latch.

With (C2, C1) = (0, 1), the R counter latch is programmed.

Table 9 shows the input data format for programming the

R counter latch.

A Counter Latch

R Counter

A5 to A1 program the 5-bit A counter. The divide range is

0 (00000) to 31 (11111).

R1 to R14 set the counter divide ratio. The divide range is

1 (00......001) to 16383 (111......111).

Reserved Bits

Antibacklash Pulse Width

DB7 is a spare bit that is reserved. It should be programmed to 0.

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

B Counter Latch

B13 to B1 program the B counter. The divide range is 3

(00.....0011) to 8191 (11....111).

DB18 is the lock detect precision bit. This bit sets the number of

reference cycles with less than 15 ns phase error for entering the

locked state. With LDP at 1, five cycles are taken; with LDP at 0,

three cycles are taken.

Overall Divide Range

The overall divide range is defined by ((P × B) + A), where P is

the prescaler value.

Test Mode Bit

DB19 is the test mode bit (TMB) and should be set to 0. With

TMB = 0, the contents of the test mode latch are ignored and

normal operation occurs as determined by the contents of the

control latch, R counter latch, and N counter latch. Note that

test modes are for factory testing only and should not be pro-

grammed by the user.

CP Gain

DB21 of the N counter latch in the ADF4360 family is the

charge pump gain bit. When this is programmed to 1, Current

Setting 2 is used.When programmed to 0, Current Setting 1 is used.

This bit can also be programmed through DB10 of the control

latch. The bit always reflects the latest value written to it, whether

this is through the control latch or the N counter latch.

Band Select Clock

These bits set a divider for the band select logic clock input. The

output of the R counter is by default the value used to clock the

band select logic, but if this value is too high (>1 MHz), a

divider can be switched on to divide the R counter output to a

smaller value (see Table 9).

Divide-by-2

DB22 is the divide-by-2 bit.When set to 1, the output divide-by-2

function is chosen.When it is set to 0, normal operation occurs.

Divide-by-2 Select

DB23 is the divide-by-2 select bit. When programmed to 1, the

divide-by-2 output is selected as the prescaler input. When set

to 0, the fundamental is used as the prescaler input. For exam-

ple, using the output divide-by-2 feature and a PFD frequency

of 200 kHz, the user needs a value of N = 5,500 to generate

550 MHz. With the divide-by-2 select bit high, the user may

keep N = 2,750.

Reserved Bits

DB23 to DB22 are spare bits that are reserved. They should be

programmed to 0.

Rev. A | Page 19 of 24

ADF4360-6

APPLICATIONS

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to

implement base station transmitters. Figure 17 shows how ADI

parts can be used to implement such a system.

The LO ports of the AD8349 can be driven differentially from

the complementary RF_OUTA and RF_OUTB outputs of the

ADF4360-6. This gives better performance than a single-ended

LO driver and eliminates the often necessary use of a balun to

convert from a single-ended LO input to the more desirable

differential LO inputs for the AD8349. The typical rms phase

noise (100 Hz to 100 kHz) of the LO in this configuration is 1.07°.

The circuit block diagram shows the AD9761 TxDAC® being

used with the AD8349. The use of dual integrated DACs, such

as the AD9761 with its specified 0.02 dB and 0.004 dB gain

and offset matching characteristics, ensures minimum error

contribution (over temperature) from this portion of the

signal chain.

The AD8349 accepts LO drive levels from −10 dBm to 0 dBm.

The optimum LO power can be software programmed on the

ADF4360-6, which allows levels from −13.5 dBm to −4.5 dBm

from each output.

The local oscillator is implemented using the ADF4360-6. The

low-pass filter was designed using ADIsimPLL™ for a channel

spacing of 200 kHz and an open-loop bandwidth of 10 kHz.

The RF output is designed to drive a 50 Ω load but must be ac-

coupled, as shown in Figure 17. If the I and Q inputs are driven

in quadrature by 2 V p-p signals, the resulting output power

from the modulator is approximately 2 dBm.

REFIO

IOUTA

LOW-PASS

FILTER

IOUTB

MODULATED

DIGITAL

DATA

AD9761

TxDAC

QOUTA

QOUTB

LOW-PASS

FILTER

FSADJ

2kΩ

LOCK

V

DETECT

VCO

DD

2

VPS1

VPS2

IBBP

IBBN

6

21

23

20

10µF

V

CE MUXOUT

DD

7

TUNE

CP

V

DV

AV

VCO

DD

6.8kΩ

14

16

C

100pF

N

24

1nF 1nF

FREF

REF

IN

12nF

1nF

330pF

51Ω

17 CLK

TO

RF PA

AD8349

3.9kΩ

QBBP

QBBN

ADF4360-6

18

DATA

LE

V

VCO

19

12

C

47nH

2.7pF

7.5nH

13

R

LOIP

LOIN

SET

1nF

RF

A

B

4

5

OUT

PHASE

SPLITTER

4.7kΩ

CPGND

1

AGND

DGND

RF

OUT

3

8

9

10 11 22 15

Figure 17. Direct Conversion Modulator

Rev. A | Page 20 of 24

ADF4360-6

ADuC812 Interface

FIXED FREQUENCY LO

Figure 19 shows the interface between the ADF4360 family and

the ADuC812 MicroConverter®. Because the ADuC812 is based

on an 8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4360 family

needs a 24-bit word, which is accomplished by writing three

8-bit bytes from the MicroConverter to the device. After the

third byte has been written, the LE input should be brought

high to complete the transfer.

Figure 18 shows the ADF4360-6 used as a fixed frequency LO at

1.08 GHz. The low-pass filter was designed using ADIsimPLL

for a channel spacing of 8 MHz and an open-loop bandwidth of

40 kHz. The maximum PFD frequency of the ADF4360-6 is

8 MHz. Because using a larger PFD frequency allows the use of

a smaller N, the in-band phase noise is reduced to as low as

possible, –102 dBc/Hz. The 40 kHz bandwidth is chosen to be

just greater than the point at which the open-loop phase noise

of the VCO is –102 dBc/Hz, thus giving the best possible inte-

grated noise. The typical rms phase noise (100 Hz to 100 kHz)

of the LO in this configuration is 0.3°. The reference frequency is

from a 16 MHz TCXO from Fox; thus, an R value of 2 is pro-

grammed. Taking into account the high PFD frequency and its

effect on the band select logic, the band select clock divider is

enabled. In this case, a value of 8 is chosen. A very simple pull-up

resistor and dc blocking capacitor complete the RF output stage.

SCLOCK

MOSI

SCLK

SDATA

ADuC812

LE

ADF4360-x

I/O PORTS

CE

MUXOUT

(LOCK DETECT)

LOCK

V

DETECT

VCO

VDD

6

21

DV

2

23

20

Figure 19. ADuC812 to ADF4360-x Interface

10µF

V

CE MUXOUT

7

TUNE

CP

V

AV

DD

VCO

DD

14

16

C

N

24

1nF 1nF

FOX

801BE-160

16MHz

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and detect lock (MUXOUT configured as lock

detect and polled by the port input). When operating in the

described mode, the maximum SCLOCK rate of the ADuC812

is 4 MHz. This means that the maximum rate at which the out-

put frequency can be changed is 166 kHz.

REF

IN

27.0nF

5.6nF

51Ω

390Ω

17 CLK

ADF4360-6

18

19

12

DATA

LE

V

VCO

C

51Ω

100pF

13

R

SET

1nF

RF

A

B

4

5

OUT

4.7kΩ

CPGND

1

AGND

DGND

RF

OUT

ADSP-2181 Interface

3

8

9

10 11 22 15

Figure 20 shows the interface between the ADF4360 family and

the ADSP-21xx digital signal processor. The ADF4360 family

needs a 24-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

autobuffered transmit mode of operation with alternate fram-

ing. This provides a means for transmitting an entire block of

serial data before an interrupt is generated.

Figure 18. Fixed Frequency LO

INTERFACING

The ADF4360 family has a simple SPI®-compatible serial inter-

face for writing to the device. CLK, DATA, and LE control the

data transfer. When LE goes high, the 24 bits that have been

clocked into the appropriate register on each rising edge of CLK

are transferred to the appropriate latch. See Figure 2 for the

timing diagram and Table 5 for the latch truth table.

SCLOCK

SCLK

MOSI

TFS

SDATA

LE

ADF4360-x

ADSP-21xx

I/O PORTS

CE

MUXOUT

(LOCK DETECT)

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible is 833 kHz or

one update every 1.2 µs. This is certainly more than adequate

for systems that have typical lock times in hundreds of micro-

seconds.

Figure 20. ADSP-21xx to ADF4360-x Interface

Set up the word length for 8 bits and use three memory loca-

tions for each 24-bit word. To program each 24-bit latch, store

the 8-bit bytes, enable the autobuffered mode, and write to the

transmit register of the DSP. This last operation initiates the

autobuffer transfer.

Rev. A | Page 21 of 24

ADF4360-6

Experiments have shown that the circuit shown in Figure 22

provides an excellent match to 50 Ω over the operating range of

the ADF4360-6. This gives approximately −3 dBm output power

across the frequency range of the ADF4360-6. Both single-

ended architectures can be examined using the EVAL-

ADF4360-6EB1 evaluation board.

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The leads on the chip scale package (CP-24) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package lead length and 0.05 mm wider than

the package lead width. The lead should be centered on the pad

to ensure that the solder joint size is maximized.

V

VCO

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern to ensure that short-

ing is avoided.

47nH

2.7pF

7.5nH

RF

OUT

50Ω

Figure 22. Optimum ADF4360-6 Output Stage

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias

are used, they should be incorporated into the thermal pad at a

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm, and the via barrel should be plated with 1 ounce

of copper to plug the via.

If the user does not need the differential outputs available on

the ADF4360-6, the user may either terminate the unused out-

put or combine both outputs using a balun. The circuit in

Figure 23 shows how best to combine the outputs.

V

VCO

The user should connect the printed circuit thermal pad to

AGND. This is internally connected to AGND.

7.5nH

47nH

6.8nH

RF

A

B

OUT

10pF

2.7pF

7.5nH

OUTPUT MATCHING

50Ω

There are a number of ways to match the output of the

ADF4360-6 for optimum operation; the most basic is to use a

50 Ω resistor to V_VCO. A dc bypass capacitor of 100 pF is con-

nected in series as shown in Figure 21. Because the resistor is

not frequency dependent, this provides a good broadband

match. The output power in this circuit typically gives −4.5 dBm

output power into a 50 Ω load.

6.8nH

OUT

2.7pF

Figure 23. Balun for Combining ADF4360-6 RF Outputs

The circuit in Figure 23 is a lumped-lattice-type LC balun. It

is designed for a center frequency of 1.15 GHz and outputs

5.0 dBm at this frequency. The series 6.8 nH inductor is used to

tune out any parasitic capacitance due to the board layout from

each input, and the remainder of the circuit is used to shift the

output of one RF input by +90° and the second by −90°, thus

combining the two. The action of the 7.5 nH inductor and the

2.7 pF capacitor accomplishes this. The 47 nH is used to provide

an RF choke to feed the supply voltage, and the 10 pF capacitor

provides the necessary dc block. To ensure good RF perform-

ance, the circuits in Figure 22 and Figure 23 are implemented

with Coilcraft 0402/0603 inductors and AVX 0402 thin-film

capacitors.

V

VCO

51Ω

100pF

RF

OUT

50Ω

Figure 21. Simple ADF4360-6 Output Stage

A better solution is to use a shunt inductor (acting as an RF

choke) to V_VCO.This gives a better match and, therefore, more

output power. Additionally, a series inductor is added after the

dc bypass capacitor to provide a resonant LC circuit. This tunes

the oscillator output and provides approximately 10 dB addi-

tional rejection of the second harmonic. The shunt inductor

needs to be a relatively high value (>40 nH).

Alternatively, instead of the LC balun shown in Figure 23, both

outputs may be combined using a 180° rat-race coupler.

Rev. A | Page 22 of 24

ADF4360-6

OUTLINE DIMENSIONS

0.60 MAX

4.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

1

24

19

18

0.50

BSC

PIN 1

INDICATOR

*

2.45

2.30 SQ

2.15

TOP

3.75

EXPOSED

VIEW

BSC SQ

PA D

(BOTTOMVIEW)

0.50

0.40

0.30

6

13

7

12

0.23 MIN

2.50 REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

*

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 24. 24-Lead Lead Frame Chip Scale Package [VQ_LFCSP]

4 mm × 4 mm Body, Very Thin Quad (CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADF4360-6BCP

ADF4360-6BCPRL

ADF4360-6BCPRL7

ADF4360-6BCPZ¹

ADF4360-6BCPZRL¹

ADF4360-6BCPZRL7¹

EVAL-ADF4360-6EB1

Temperature Range

−40°C to +85°C

Frequency Range

Package Option

1050 MHz to 1250 MHz

CP-24-2

Evaluation Board

¹Z = Pb-free model.

Rev. A | Page 23 of 24

ADF4360-6

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©

registered trademarks are the property of their respective owners.

C04440–0–12/04(A)

Rev. A | Page 24 of 24


型号：	ADF4360-6BCPZRL7
厂家：	ADI
描述：	Integrated Synthesizer and VCO 集成的合成器和VCO
文件：	总24页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF4360-6BCPZRL7 [ADI]

相关型号：

ADF4360-7

ADF4360-7BCP

ADF4360-7BCP

ADF4360-7BCPRL

ADF4360-7BCPRL7

ADF4360-7BCPRL7

ADF4360-7BCPZ

ADF4360-7BCPZRL

ADF4360-7BCPZRL7

ADF4360-8

ADF4360-8BCP

ADF4360-8BCPRL