ADF4360-8BCPZ [ADI]
Integrated Synthesizer and VCO;
| 型号： | ADF4360-8BCPZ |
| 厂家： | 
ADI |
| 描述： | Integrated Synthesizer and VCO 电信 信息通信管理 电信集成电路 |
| 文件： | 总24页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated Synthesizer and VCO
Data Sheet
ADF4360-8
FEATURES
GENERAL DESCRIPTION
Output frequency range: 65 MHz to 400 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
The ADF4360-8 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). The ADF4360-8 center
frequency is set by external inductors. This allows a frequency
range of between 65 MHz to 400 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
Digital lock detect
Hardware and software power-down mode
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DV
R
CE
DD
DD
SET
ADF4360-8
MUXOUT
MULTIPLEXER
14-BIT R
COUNTER
REF
IN
LOCK
DETECT
MUTE
CLK
DATA
LE
24-BIT
FUNCTION
LATCH
24-BIT
DATA REGISTER
CHARGE
PUMP
CP
PHASE
COMPARATOR
V
V
VCO
TUNE
L1
L2
C
C
C
N
RF
RF
A
B
OUT
OUT
VCO
CORE
OUTPUT
STAGE
13-BIT B
COUNTER
N = B
AGND
DGND
CPGND
Figure 1.
Rev. D
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Tel: 781.329.4700
Technical Support
©2004-2016 Analog Devices, Inc. All rights reserved.
www.analog.com
ADF4360-8
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
MUXOUT and Lock Detect...................................................... 10
Input Shift Register .................................................................... 11
VCO ............................................................................................. 11
Output Stage................................................................................ 12
Latch Structure ........................................................................... 13
Power-Up..................................................................................... 17
Control Latch.............................................................................. 19
N Counter Latch......................................................................... 20
R Counter Latch ......................................................................... 20
Applications Information.............................................................. 21
Choosing the Correct Inductance Value................................. 21
Fixed Frequency LO................................................................... 21
Interfacing ................................................................................... 22
PCB Design Guidelines for Chip Scale Package........................... 22
Output Matching........................................................................ 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 10
Reference Input Section............................................................. 10
N Counter.................................................................................... 10
R Counter .................................................................................... 10
PFD and Charge Pump.............................................................. 10
REVISION HISTORY
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
5/2016—Rev. C to Rev. D
Changed ADF4360 Family to ADF4360-8 and
ADSP-21xx to ADSP-2181 ........................................... Throughout
Changes to Figure 3.......................................................................... 7
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
01/2005—Rev. 0 to Rev. A
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Figure 20...................................................................... 12
Added Power-Up Section.............................................................. 17
Deleted Power-Up Section ............................................................ 22
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
11/2012—Rev. B to Rev. C
Changes to Table 1............................................................................ 4
Changes to Table 3 ............................................................................ 6
Updated Outline Dimensions ....................................................... 24
10/2004—Revision 0: Initial Version
2/2012—Rev. A to Rev. B
Changes to Figure 3 and Table 4 ..................................................... 7
Changes to Output Matching Section.......................................... 23
Rev. D | Page 2 of 24
Data Sheet
ADF4360-8
SPECIFICATIONS1
AVDD = DVDD = VVCO = 3.3 V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
B Version
Unit
Test Conditions/Comments
REFIN CHARACTERISTICS
REFIN Input Frequency
10/250
MHz min/max
For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew
rate > 21 V/µs.
REFIN Input Sensitivity
0.7/AVDD
0 to AVDD
5.0
V p-p min/max AC-coupled.
V max
CMOS-compatible.
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency2
CHARGE PUMP
pF max
µA max
±±0
8
MHz max
ICP Sink/Source3
With RSET = 4.7 kΩ.
High Value
Low Value
RSET Range
ICP Three-State Leakage
Current
2.5
mA typ
mA typ
kΩ
0.312
2.7/10
0.2
nA typ
Sink and Source Current
Matching
2
% typ
1.25 V ≤ VCP ≤ 2.5 V.
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
1.5
2
% typ
% typ
1.25 V ≤ VCP ≤ 2.5 V.
VCP = 2.0 V.
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
IOH, Output High Current
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
1.5
0.±
±1
3.0
V min
V max
µA max
pF max
DVDD − 0.4
500
0.4
V min
µA max
V max
CMOS output chosen.
IOL = 500 µA.
3.0/3.±
AVDD
AVDD
5
V min/V max
DVDD
VVCO
4
AIDD
mA typ
mA typ
mA typ
mA typ
µA typ
4
DIDD
2.5
4, 5
IVCO
12.0
3.5 to 11.0
7
ICORE = 5 mA.
RF output stage is programmable.
4
IRFOUT
Low Power Sleep Mode4
RF OUTPUT CHARACTERISTICS5
Maximum VCO Output Frequency
400
MHz
ICORE = 5 mA. Depending on L. See the
Choosing the Correct Inductance Value section.
Minimum VCO Output Frequency ±5
MHz
VCO Output Frequency
88/108
MHz min/max
L1, L2 = 270 nH. See the Choosing the Correct Inductance Value
section for other frequency values.
VCO Frequency Range
VCO Sensitivity
1.2
2
Ratio
MHz/V typ
FMAX/FMIN
L1, L2 = 270 nH. See the Choosing the Correct Inductance Value
section for other sensitivity values.
To within 10 Hz of final frequency.
Lock Time±
400
µs typ
Frequency Pushing (Open Loop)
0.24
MHz/V typ
Rev. D | Page 3 of 24
ADF4360-8
Data Sheet
Parameter
B Version
10
−1±
−21
−9/0
−14/−9
±3
1.25/2.5
Unit
Test Conditions/Comments
Frequency Pulling (Open Loop)
Harmonic Content (Second)
Harmonic Content (Third)
Output Power5, 7
Output Power5, 8
Output Power Variation
VCO Tuning Range
Hz typ
Into 2.00 VSWR load.
dBc typ
dBc typ
dBm typ
dBm typ
dB typ
Using tuned load, programmable in 3 dB steps; see Table 7.
Using 50 Ω resistors to VVCO, programmable in 3 dB steps; see Table 7.
V min/max
NOISE CHARACTERISTICS5
VCO Phase Noise Performance9
−120
−139
−140
−142
−1±0
−150
−142
−215
−102
0.09
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Degrees typ
dBc typ
At 100 kHz offset from carrier.
At 800 kHz offset from carrier.
At 3 MHz offset from carrier.
At 10 MHz offset from carrier.
At 200 kHz PFD frequency.
At 1 MHz PFD frequency.
Synthesizer Phase Noise Floor10
At 8 MHz PFD frequency.
Phase Noise Figure of Merit10
In-Band Phase Noise11, 12
RMS Integrated Phase Error13
Spurious Signals due to PFD
Frequency12, 14
At 1 kHz offset from carrier.
100 Hz to 100 kHz.
−75
Level of Unlocked Signal with
MTLD Enabled
−70
dBm typ
1 Operating temperature range is –40°C to +85°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 ICP is internally modified to maintain constant loop gain over the frequency range.
4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V.
5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
± Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7 For more detail on using tuned loads, see the Output Matching section.
8 Using 50 Ω resistors to VVCO, into a 50 Ω load.
9 The noise of the VCO is measured in open-loop conditions.
10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The
phase noise figure of merit subtracts 10 log (PFD frequency).
11 The phase noise is measured with the EV-ADF43±0-8EB1Z evaluation board and the HP 85±2E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
12
f
f
= 10 MHz; fPFD = 200 kHz; N = 1000; loop bandwidth = 10 kHz.
= 10 MHz; fPFD = 1 MHz; N = 120; loop bandwidth = 100 kHz.
REFIN
13
REFIN
14 The spurious signals are measured with the EV-ADF43±0-8EB1Z evaluation board and the HP 85±2E spectrum analyzer. The spectrum analyzer provides the REFIN for
the synthesizer; fREFOUT = 10 MHz at 0 dBm.
Rev. D | Page 4 of 24
Data Sheet
ADF4360-8
TIMING CHARACTERISTICS1
AVDD = DVDD = VVCO = 3.3 V 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN to TMAX (B Version)
Unit
Test Conditions/Comments
LE setup time
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
1 Refer to the Power-Up section for the recommended power-up procedure for this device.
t4
t5
CLOCK
t2
t3
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DB2
DATA
LE
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. D | Page 5 of 24
ADF4360-8
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum Rat-
ings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
Rating
AVDD to GND1
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to + 85°C
−65°C to +150°C
150°C
AVDD to DVDD
VVCO to GND
VVCO to AVDD
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
CSP θJA Thermal Impedance
Paddle Soldered
TRANSISTOR COUNT
12543 (CMOS) and 700 (Bipolar)
ESD CAUTION
50°C/W
88°C/W
260°C
Paddle Not Soldered
Lead Temperature, Soldering Reflow
1 GND = AGND = DGND = 0 V.
Rev. D | Page 6 of 24
Data Sheet
ADF4360-8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
IDENTIFIER
CPGND 1
18 DATA
AV
2
3
4
17 CLK
16 REF
DD
AGND
IN
ADF4360-8
TOP VIEW
RF
A
15
DGND
OUT
RF
B 5
6
14 C
13 R
OUT
V
N
VCO
SET
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO AGND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
CPGND
AVDD
Description
1
2
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. AVDD must have the same value as DVDD.
3, 8, 11, 22
4
AGND
Analog Ground. This is the ground return path of the prescaler and VCO.
RFOUT
RFOUT
VVCO
A
VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
description of the various output stages.
VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching
section for a description of the various output stages.
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. VVCO must have the same value as AVDD.
5
6
B
7
9
VTUNE
L1
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.
An external inductor to AGND should be connected to this pin to set the ADF4360-8 output frequency. L1 and L2
need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10
L2
An external inductor to AGND should be connected to this pin to set the ADF4360-8 output frequency. L1 and L2
need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12
13
CC
RSET
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer.
The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
11.75
RSET
ICPmax
where RSET = 4.7 kΩ, ICPmax = 2.5 mA.
14
15
16
CN
DGND
REFIN
Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor.
Digital Ground.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17
18
19
CLK
DATA
LE
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit
shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, and the relevant latch is selected using the control bits.
20
21
MUXOUT
DVDD
This multiplexer output lets either the lock detect, the scaled RF, or the scaled reference frequency be accessed externally.
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DVDD must have the same value as AVDD.
23
24
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn drives the internal VCO.
Exposed Pad. The exposed pad must be connected to AGND.
CP
EP
Rev. D | Page 7 of 24
ADF4360-8
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–40
0
–10
–20
–30
–40
–50
V
= 3.3V, V
= 3.3V
VCO
DD
= 2.5mA
–50
–60
REFERENCE
LEVEL = –2.5dBm
I
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2SECONDS
AVERAGES = 20
–70
–80
–90
–100
–110
–120
–130
–140
–150
–60
–70
–80
–90
–84dBc
100
1k
10k
100k
1M
10M
–1.1MHz
–0.55MHz
65MHz
0.55MHz
1.1MHz
FREQUENCY OFFSET (Hz)
Figure 4. Open-Loop VCO Phase Noise, L1, L2 = 560 nH
Figure 7. Reference Spurs at 65 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
–70
–75
–80
–85
–90
–95
–100
–40
–50
–60
–70
–80
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–90
–100
–110
–120
–130
–140
–150
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 5. VCO Phase Noise, 65 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
Figure 8. Open-Loop VCO Phase Noise, L1, L2 = 110 nH
0
–70
V
= 3.3V, V
= 3.3V
VCO
DD
= 2.5mA
–75
–80
REFERENCE
LEVEL = –2.5dBm
–10
–20
–30
–40
–50
I
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9SECONDS
AVERAGES = 20
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–60
–70
–80
–90
–107.4dBc/Hz
–2kHz
–1kHz
65MHz
1kHz
2kHz
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 6. Close-In Phase Noise at 65 MHz (1 MHz Channel Spacing)
Figure 9. VCO Phase Noise, 160 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
Rev. D | Page 8 of 24
Data Sheet
ADF4360-8
0
–10
–20
–30
–40
–50
–70
–75
–80
–85
–90
–95
–100
V
= 3.3V, V
= 3.3V
VCO
DD
= 2.5mA
REFERENCE
LEVEL = 1dBm
I
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9SECONDS
AVERAGES = 20
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–60
–70
–80
–90
–109.4dBc/Hz
–2kHz
–1kHz
160MHz
1kHz
2kHz
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 13. VCO Phase Noise, 400 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
Figure 10. Close-In Phase Noise at 160 MHz (1 MHz Channel Spacing)
0
0
V
= 3.3V, V
= 3.3V
VCO
DD
= 2.5mA
V
= 3.3V, V
= 3.3V
VCO
DD
= 2.5mA
REFERENCE
LEVEL = 0dBm
–10
–20
–30
–40
–50
I
CP
REFERENCE
LEVEL = 1dBm
–10
–20
–30
–40
–50
I
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9SECONDS
AVERAGES = 20
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2SECONDS
AVERAGES = 20
–60
–70
–80
–90
–60
–70
–80
–90
–76dBc
–103.4dBc/Hz
–2kHz
–1kHz
400MHz
1kHz
2kHz
–1.1MHz
–0.55MHz
160MHz
0.55MHz
1.1MHz
Figure 14. Close-In Phase Noise at 400 MHz (1 MHz Channel Spacing)
Figure 11. Reference Spurs at 160 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
0
–40
V
= 3.3V, V
= 3.3V
VCO
DD
= 2.5mA
–50
–60
REFERENCE
LEVEL = 0dBm
–10
–20
–30
–40
–50
I
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2SECONDS
AVERAGES = 20
–70
–80
–90
–100
–110
–120
–130
–140
–150
–60
–70
–80
–90
–77dBc
–1.1MHz
–0.55MHz
400MHz
0.55MHz
1.1MHz
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 12. Open-Loop VCO Phase Noise, L1, L2 = 18 nH
Figure 15. Reference Spurs at 400 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
Rev. D | Page 9 of 24
ADF4360-8
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
V
P
CHARGE
PUMP
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
UP
HI
D1
Q1
U1
R DIVIDER
CLR1
POWER-DOWN
CONTROL
PROGRAMMABLE
DELAY
CP
U3
100k
SW2
NC
ABP1
ABP2
TO R COUNTER
REF
IN
NC
SW1
BUFFER
CLR2
U2
DOWN
HI
D2
Q2
SW3
NO
N DIVIDER
Figure 16. Reference Input Stage
CPGND
N COUNTER
R DIVIDER
N DIVIDER
CP OUTPUT
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is re-
ferred to as the B counter. It makes it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The VCO frequency equation is
Figure 17. PFD Simplified Schematic and Timing (In Lock)
fVCO B fREFIN /R
MUXOUT AND LOCK DETECT
where:
The output multiplexer on the ADF4360-8 allows the user to
access various internal points on the chip. The state of MUX-
OUT is controlled by M3, M2, and M1 in the function latch.
The full truth table is shown in Table 7. Figure 18 shows the
MUXOUT section in block diagram form.
f
VCO is the output frequency of the VCO.
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
REFIN is the external reference frequency oscillator.
f
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
DV
DD
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
MUXOUT
MUX
CONTROL
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 17 is a simpli-
fied schematic. The PFD includes a programmable delay ele-
ment that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function, and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width
of the pulse (see Table 9).
DGND
Figure 18. MUXOUT Circuit
Rev. D | Page 10 of 24
Data Sheet
ADF4360-8
The correct band is chosen automatically by the band select logic
at power-up or whenever the N counter latch is updated. It is
important that the correct write sequence be followed at power-
up. This sequence is
Lock Detect
MUXOUT can be programmed for one type of lock detect. Dig-
ital lock detect is active high. When LDP in the R counter latch
is set to 0, digital lock detect is set high when the phase error on
three consecutive phase detector cycles is less than 15 ns.
1. R counter latch
2. Control latch
3. N counter latch
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
INPUT SHIFT REGISTER
3.5
3.0
2.5
2.0
The digital section of the ADF4360-8 includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
1.5
1.0
0.5
0
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
80
85
90
95
100
105
110
115
FREQUENCY (MHz)
Figure 19. Frequency vs. VTUNE, ADF4360-8, L1 and L2 = 270 nH
Table 5. C2 and C1 Truth Table
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8,
and is controlled by the BSC1 bit and the BSC2 bit in the R
counter latch. Where the required PFD frequency exceeds
1 MHz, the divide ratio should be set to allow enough time for
correct band selection.
Control Bits
C2
0
0
1
1
C1
0
1
0
1
Data Latch
Control Latch
R Counter
N Counter (B)
Test Modes Latch
VCO
After band selection, normal PLL action resumes. The value of
KV is determined by the value of inductors used (see the Choos-
ing the Correct Inductance Value section). The ADF4360-8
contains linearization circuitry to minimize any variation of the
product of ICP and KV.
The VCO core in the ADF4360-8 uses eight overlapping bands,
as shown in Figure 19, to allow a wide frequency range to be
covered without a large VCO sensitivity (KV) and resultant poor
phase noise and spurious performance.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
Rev. D | Page 11 of 24
ADF4360-8
Data Sheet
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360-8 are connected
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 20. To allow the user to
optimize the power dissipation vs. the output power require-
ments, the tail current of the differential pair is programmable
via Bits PL1 and PL2 in the control latch. Four current levels
may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give
output power levels of −9 dBm, −6 dBm, −3 dBm, and 0 dBm,
respectively, using the correct shunt inductor to VDD and ac
coupling into a 50 Ω load. Alternatively, both outputs can be
combined in a 1 + 1:1 transformer or a 180° microstrip coupler
(see the Output Matching section).
Another feature of the ADF4360-8 is that the supply current
to the RF output stage is shut down until the device achieves lock,
as measured by the digital lock detect circuitry. This is enabled by
the Mute-Till-Lock Detect (MTLD) bit in the control latch.
RF
OUT
A
RF B
OUT
VCO
BUFFER
Figure 20. Output Stage ADF4360-8
Rev. D | Page 12 of 24
Data Sheet
ADF4360-8
LATCH STRUCTURE
Table 6 shows the three on-chip latches for the ADF4360-8. The two LSBs decide which latch is programmed.
Table 6. Latch Structure
CONTROL LATCH
OUTPUT
POWER
LEVEL
CORE
POWER
LEVEL
CURRENT
SETTING 2
CURRENT
SETTING 1
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP
PDP
M3
M2
M1
CR
PC2 PC1 C2 (0) C1 (0)
N COUNTER LATCH
CONTROL
BITS
13-BIT B COUNTER
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CPG B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
RSV RSV RSV RSV RSV RSV C2 (1) C1 (0)
RSV RSV
R COUNTER LATCH
ANTI-
BACKLASH
PULSE
BAND
SELECT
CLOCK
CONTROL
BITS
14-BIT REFERENCE COUNTER
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (1)
Rev. D | Page 13 of 24
ADF4360-8
Data Sheet
Table 7. Control Latch
OUTPUT
POWER
LEVEL
CORE
POWER
LEVEL
CURRENT
SETTING 2
CURRENT
SETTING 1
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP
PDP
M3
M2
M1
CR
PC2 PC1 C2 (0) C1 (0)
PC2
CORE POWER LEVEL
PC1
0
0
1
1
2.5mA
5mA
7.5mA
10mA
0
1
0
1
I
(mA)
PHASE DETECTOR
PDP POLARITY
CPI6
CPI3
CPI5
CPI2
CPI4
CPI1
CP
4.7k
COUNTER
0
1
NEGATIVE
POSITIVE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
CR
OPERATION
0
1
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
CP
0
1
THREE-STATE
CP GAIN
CPG
0
1
CURRENT SETTING 1
CURRENT SETTING 2
MUTE-TIL-LOCK DETECT
DISABLED
ENABLED
MTLD
0
1
M3
0
0
M2
0
0
M1
0
1
MUXOUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
PL2
PL1
OUTPUT POWER LEVEL
CURRENT
(USING TUNED LOAD)
(USING 50 TO V
)
VCO
0
0
1
1
0
1
0
1
3.5mA
5.0mA
7.5mA
11.0mA
–9dBm
–6dBm
–3dBm
0dBm
–19dBm
–15dBm
–12dBm
–9dBm
0
0
1
1
0
1
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
NOT USED
NOT USED
1
1
1
1
0
0
1
1
0
1
0
1
DGND
CE PIN
PD2
X
X
0
1
PD1
MODE
0
1
1
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
Rev. D | Page 14 of 24
Data Sheet
ADF4360-8
Table 8. N Counter Latch
CONTROL
BITS
13-BIT B COUNTER
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV CPG B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
RSV RSV RSV RSV RSV RSV C2 (1) C1 (0)
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
B13
B12
B11
B3
B2
0
0
1
1
.
.
.
0
0
1
1
B1
0
1
0
1
.
.
.
0
1
0
1
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
8188
8189
8190
8191
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
.
.
1
1
1
1
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN OPERATION
0
0
0
1
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
N = B; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
2
ADJACENT VALUES OF (N F
), AT THE OUTPUT, N
IS (P –P).
MIN
REF
Rev. D | Page 15 of 24
ADF4360-8
Data Sheet
Table 9. R Counter Latch
ANTI-
BACKLASH
PULSE
BAND
SELECT
CLOCK
CONTROL
BITS
14-BIT REFERENCE COUNTER
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (0) C1 (1)
R14
0
0
R13
R12
R3
0
0
0
1
.
.
.
1
1
1
1
R2
0
1
1
0
.
.
.
0
0
1
1
R1
DIVIDE RATIO
1
2
3
4
.
.
.
16380
16381
16382
16383
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
1
0
1
0
.
.
.
0
1
0
1
0
TEST MODE
BIT SHOULD
BE SET TO 0
0
.
.
FOR NORMAL
OPERATION.
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
.
1
1
1
1
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH
0
0
1
1
0
1
0
1
3.0ns
1.3ns
6.0ns
3.0ns
LDP
0
LOCK DETECT PRECISION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
0
0
1
1
0
1
0
1
1
2
4
8
Rev. D | Page 16 of 24
Data Sheet
ADF4360-8
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency band,
and the ADF4360-8 may not achieve lock. If the recommended
interval is inserted, and the N counter latch is programmed, the
band select logic can choose the correct frequency band, and
the device locks to the correct frequency.
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-8 after
power-up is
1. R counter latch
2. Control latch
3. N counter latch
The duration of this interval is affected by the value of the
capacitor on the CN pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-8 VCO. The
recommended value of this capacitor is 10 μF. Using this value
requires an interval of ≥15 ms between the latching in of the
control latch bits and latching in of the N counter latch bits. If a
shorter delay is required, the capacitor can be reduced. A slight
phase noise penalty is incurred by this change, which is further
explained in Table 10.
Initial Power-Up
Initial power-up refers to programming the device after the
application of voltage to the AVDD, DVDD, VVCO, and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-8 during initial power-up to settle.
During initial power-up, a write to the control latch powers up
the device, and the bias currents of the VCO begin to settle. If
Table 10. CN Capacitance vs. Interval and Phase Noise
Open-Loop Phase Noise at 10 kHz Offset
CN
Recommended Interval Between
Value
Control Latch and N Counter Latch L1 and L2 = 18.0 nH
L1 and L2 = 110.0 nH
−97 dBc/Hz
−96 dBc/Hz
L1 and L2 = 560.0 nH
−99 dBc/Hz
−98 dBc/Hz
10 μF
440 nF
≥15 ms
−100 dBc/Hz
−99 dBc/Hz
≥ 600 μs
POWER-UP
CLOCK
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
DATA
LE
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
Figure 21. ADF4360-8 Power-Up Timing
Rev. D | Page 17 of 24
ADF4360-8
Data Sheet
Hardware Power-Up/Power-Down
Software Power-Up/Power-Down
If the device is powered down via the hardware (using the CE
pin) and powered up again without any change to the N counter
register during power-down, the device locks at the correct
frequency, because the device is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <15 ms for 10 μF capacitance. The smaller
capacitance of 440 nF on this pin enables lock times of <600 μs.
If the device is powered down via the software (using the con-
trol latch) and powered up again without any change to the N
counter latch during power-down, the device locks at the cor-
rect frequency, because the device is already in the correct fre-
quency band. The lock time depends on the value of capaci-
tance on the CN pin, which is <15 ms for 10 μF capacitance. The
smaller capacitance of 440 nF on this pin enables lock times of
<600 μs.
The N counter value cannot be changed while the device is in
power-down, since the device may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the device after power-up is the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
The N counter value cannot be changed while the device is in
power-down, because the device may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the device after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
Rev. D | Page 18 of 24
Data Sheet
ADF4360-8
Charge Pump Currents
CONTROL LATCH
CPI3, CPI2, and CPI1 in the ADF4360-8 determine
Current Setting 1.
With (C2, C1) = (0, 0), the control latch is programmed. Table 7
shows the input data format for programming the control latch.
CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in Table 7.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
Output Power Level
Bits PL1 and PL2 set the output power level of the VCO. See the
truth table in Table 7.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1,
with the condition that PD2 has been loaded with a 0. In the
programmed synchronous power-down, the device power-
down is gated by the charge pump to prevent unwanted
frequency jumps. Once the power-down is enabled by writing a
1 into Bit PD1 (on the condition that a 1 has also been loaded to
PD2), the device goes into power-down on the second rising
edge of the R counter output, after LE goes high. When the
CE pin is low, the device is immediately disabled, regardless
of the state of PD1 or PD2.
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360-8 is the Mute-Till-
Lock Detect bit. This function, when enabled, ensures that the
RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360-8 is the Charge
Pump Gain bit. When it is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used.
When a power-down is activated (either synchronous or
asynchronous mode), the following events occur:
Charge Pump Three-State
This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
Phase Detector Polarity
The PDP bit in the ADF4360-8 sets the phase detector polarity.
The positive setting enabled by programming a 1 is used when
using the on-chip VCO with a passive loop filter or with an
active non-inverting filter. It can also be set to 0, which is re-
quired if an active inverting loop filter is used.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF outputs are de-biased to a high impedance state.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Table 7.
Counter Reset
DB4 is the counter reset bit for the ADF4360-8. When this is 1,
the R counter and the A, B counters are reset. For normal oper-
ation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The recom-
mended setting is 5 mA. See the truth table in Table 7.
Rev. D | Page 19 of 24
ADF4360-8
Data Sheet
N COUNTER LATCH
R COUNTER LATCH
Table 8 shows the input data format for programming the
N counter latch.
With (C2, C1) = (0, 1), the R counter latch is programmed.
Table 9 shows the input data format for programming the
R counter latch.
Reserved Bits
R Counter
DB2 to DB7 are spare bits and have been designated as
reserved. They should be programmed to 0.
R1 to R14 set the counter divide ratio. The divide range is
1 (00...001) to 16383 (111...111).
B Counter Latch
Antibacklash Pulse Width
B13 to B1 program the B counter. The divide range is 3
(00...0011) to 8191 (11...111).
DB16 and DB17 set the antibacklash pulse width.
Overall Divide Range
Lock Detect Precision
The overall VCO feedback divide range is defined by B.
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with less than 15 ns phase error for entering the
locked state. With LDP at 1, five cycles are taken; with LDP at 0,
three cycles are taken.
CP Gain
DB21 of the N counter latch in the ADF4360-8 is the charge
pump gain bit. When it is programmed to 1, Current Setting 2 is
used. When programmed to 0, Current Setting 1 is used. This bit
can also be programmed through DB10 of the control latch. The bit
always reflects the latest value written to it, whether this is through
the control latch or the N counter latch.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs, as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be
programmed by the user.
Band Select Clock
These bits set a divider for the band select logic clock input.
The output of the R counter is, by default, the value used to
clock the band select logic; if this value is too high (>1 MHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Table 9).
Reserved Bits
DB23 to DB22 are spare bits that have been designated as
reserved. They should be programmed to 0.
Rev. D | Page 20 of 24
Data Sheet
ADF4360-8
APPLICATIONS INFORMATION
12
10
CHOOSING THE CORRECT INDUCTANCE VALUE
The ADF4360-8 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 22 shows a graph of both minimum
and maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors
should be placed at right angles to one another.
8
6
4
2
0
The lowest center frequency of oscillation possible is approxi-
mately 65 MHz, which is achieved using 560 nH inductors. This
relationship can be expressed by
0
100
200
300
400
500
600
INDUCTANCE (nH)
Figure 23. Tuning Sensitivity (in MHz/V) vs. Inductance (nH)
1
FO
2π 9.3 pF
0.9 nH LEXT
FIXED FREQUENCY LO
Figure 24 shows the ADF4360-8 used as a fixed frequency LO at
200 MHz. The low-pass filter was designed using ADIsimPLL
for a channel spacing of 2 MHz and an open-loop bandwidth of
100 kHz. The maximum PFD frequency of the ADF4360-8 is
8 MHz. Since using a larger PFD frequency allows the use of a
smaller N, the in-band phase noise is reduced to as low as pos-
sible, −109 dBc/Hz. The typical rms phase noise (100 Hz to
100 kHz) of the LO in this configuration is 0.09°. The reference
frequency is from a 16 MHz TCXO from Fox; thus, an R value of
2 is programmed. Taking into account the high PFD frequency
and its effect on the band select logic, the band select clock
divider is enabled. In this case, a value of 8 is chosen. A very
simple shunt inductor and dc-blocking capacitor complete the RF
output stage.
where FO is the center frequency and LEXT is the external induct-
ance.
450
400
350
300
250
200
150
100
50
0
LOCK
V
V
DETECT
0
100
200
300
400
500
600
VCO
VDD
INDUCTANCE (nH)
Figure 22. Output Center Frequency vs. External Inductor Value
6
21
DV
2
23
20
10F
V
CE MUXOUT
7
TUNE
CP
AV
DD
V
VCO
DD
15k
14
16
C
N
24
The approximate value of capacitance at the midpoint of the
center band of the VCO is 9.3 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 23 shows a graph of the tuning sensitivity (in MHz/V)
vs. the inductance (nH). It can be seen that as the inductance
increases, the sensitivity decreases. This relationship can be
derived from the equation above; that is, since the inductance
has increased, the change in capacitance from the varactor has
less of an effect on the frequency.
1nF 1nF
FOX
801BE-160
16MHz
REF
IN
680pF
47pF
22nF
51
17 CLK
6.8k
ADF4360-8
18
19
12
DATA
LE
V
VCO
C
C
56nH 56nH
100pF
13
R
SET
1nF
RF
A
B
4
5
OUT
4.7k
CPGND
1
AGND DGND L1 L2
RF
OUT
9
3
8
11 22 15
10
100pF
68nH
470
470
68nH
Figure 24. Fixed Frequency LO
Rev. D | Page 21 of 24
ADF4360-8
Data Sheet
ADSP-2181 Interface
INTERFACING
Figure 26 shows the interface between the ADF4360-8 and the
ADSP-2181 digital signal processor. The ADF4360-8 needs a
24-bit serial word for each latch write. The easiest way to ac-
complish this using the ADSP-2181 is to use the autobuffered
transmit mode of operation with alternate framing. This pro-
vides a means for transmitting an entire block of serial data
before an interrupt is generated.
The ADF4360-8 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that have been clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz, or
one update every 1.2 μs. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.
SCLOCK
SCLK
MOSI
TFS
SDATA
LE
ADF4360-8
ADSP-2181
I/O PORTS
ADuC812 Interface
CE
MUXOUT
(LOCK DETECT)
Figure 25 shows the interface between the ADF4360-8 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based mi-
crocontrollers. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360-8 needs a
24-bit word, which is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. After the third byte has
been written, the LE input should be brought high to complete
the transfer.
Figure 26. ADSP-2181 to ADF4360-8 Interface
Set up the word length for 8 bits and use three memory loca-
tions for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
SCLOCK
MOSI
SCLK
The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm long-
er than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
SDATA
ADuC812
LE
ADF4360-8
I/O PORTS
CE
MUXOUT
(LOCK DETECT)
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that short-
ing is avoided.
Figure 25. ADuC812 to ADF4360-8 Interface
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and detect lock (MUXOUT configured as lock
detect and polled by the port input). When operating in the
described mode, the maximum SCLOCK rate of the ADuC812
is 4 MHz. This means that the maximum rate at which the
output frequency can be changed is 166 kHz.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias
are used, they should be incorporated into the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
Rev. D | Page 22 of 24
Data Sheet
ADF4360-8
The recommended value of this inductor changes with the VCO
center frequency. A graph of the optimum inductor value vs.
frequency is shown in Figure 29.
OUTPUT MATCHING
There are a number of ways to match the output of the
ADF4360-8 for optimum operation; the most basic is to use a
50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is
connected in series, as shown in Figure 27. Because the resistor
is not frequency dependent, this provides a good broadband
match. The output power in the circuit below typically gives
−9 dBm output power into a 50 Ω load.
300
250
200
150
V
VCO
51Ω
100
50
0
100pF
RF
OUT
50Ω
Figure 27. Simple ADF4360-8 Output Stage
0
100
200
300
400
5000
CENTRE FREQUENCY (MHz)
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and, therefore, more
output power.
Figure 29. Optimum ADF4360-8 Shunt Inductor
Both complementary architectures can be examined using the
EV-ADF4360-8EB1Z evaluation board. If the user does not
need the differential outputs available on the ADF4360-8, the
user should either terminate the unused output or combine
both outputs using a balun. Alternatively, instead of the LC
balun, both outputs may be combined using a 180° rat-race
coupler.
Experiments have shown that the circuit shown in Figure 28
provides an excellent match to 50 Ω over the operating range of
the ADF4360-8. This gives approximately 0 dBm output power
across the specific frequency range of the ADF4360-8 using the
recommended shunt inductor, followed by a 100 pF dc blocking
capacitor.
V
VCO
L
100pF
RF
OUT
50Ω
Figure 28. Optimum ADF4360-8 Output Stage
Rev. D | Page 23 of 24
ADF4360-8
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
PIN 1
INDICATOR
24
1
19
18
0.50
BSC
2.40
2.30 SQ
2.20
EXPOSED
PAD
6
13
12
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
0.30
0.25
0.20
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 30. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm x 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Frequency Range
Package Description
Package Option
CP-24-14
CP-24-14
ADF43±0-8BCPZ
ADF43±0-8BCPZRL
ADF43±0-8BCPZRL7 −40°C to +85°C
EV-ADF43±0-8EB1Z
−40°C to +85°C
−40°C to +85°C
±5 MHz to 400 MHz 24-Lead Lead Frame Chip Scale Package [LFCSP]
±5 MHz to 400 MHz 24-Lead Lead Frame Chip Scale Package [LFCSP]
±5 MHz to 400 MHz 24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-24-14
1Z = RoHS Compliant Part.
©2004-2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04763-0-5/16(D)
Rev. D | Page 24 of 24
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