ADF5902WCCPZ-RL7_技术文档

24 GHz, ISM Band, Multichannel

FMCW Radar Transmitter

Data Sheet

ADF5902

FEATURES

APPLICATIONS

24 GHz to 24.25 GHz VCO (industrial, scientific, and medical

(ISM) radio band)

Automotive radars

Industrial radars

2-channel 24 GHz power amplifier with 8 dBm output

Single-ended outputs

2-channel muxed outputs with mute function

Programmable output power

LO output buffer

RF frequency range: 24 GHz to 24.25 GHz

Power control detector

Auxiliary 8-bit ADC

High and low speed FMCW ramp generation

25-bit fixed modulus allows subhertz frequency resolution

PFD frequencies up to 110 MHz

Normalized phase noise floor of −222 dBc/Hz

Programmable charge pump currents

5ꢀC temperature sensor

Microwave radar sensors

GENERAL DESCRIPTION

The ADF5902 is a 24 GHz transmitter (Tx) monolithic microwave

integrated circuit (MMIC) with an on-chip, 24 GHz voltage

controlled oscillator (VCO). The VCO features a fractional-N

frequency synthesizer with waveform generation capability with

programmable grid array (PGA) and dual transmitter channels

for radar systems. The on-chip, 24 GHz VCO generates the

24 GHz signal for the two transmitter channels and the local

oscillator (LO) output. Each transmitter channel contains a

power control circuit. There is also an on-chip temperature

sensor.

Control of all the on-chip registers is through a simple, 4-wire

serial peripheral interface (SPI).

4-wire SPI

ESD performance

HBM: 2000 V

CDM: 250 V

The ADF5902 comes in a compact, 32-lead, 5 mm × 5 mm

LFCSP package.

Qualified for automotive applications

FUNCTIONAL BLOCK DIAGRAM

TX_AHI

DVDD

RF_AHI

AHI

VCO_AHI

CP_AHI

R

SET

C1

C2

VREG

REGULATOR

BIAS

ADF5902

CLK

DATA

LE

32-BIT

DATA

REGISTER

GND

DVDD

RDIV

MUXOUT

ADC OUTPUT

READBACK

CONTROL

NDIV

DOUT

FREQUENCY COUNTER

RAMP

STATUS

CE

VCO

CAL

ADC

TX

1

2

OUT

REF

IN

+

R DIVIDER

N DIVIDER

PHASE

CHARGE

PUMP

FREQUENCY

DETECTOR

–

÷2

OUT

ADC

TEMPERATURE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

ATEST

SENSOR

ADC

RAMP

GENERATION

TX_DATA

FMCW RAMP GENERATION PLL

V

CP

LO

TUNE

GND

OUT

Figure 1.

Rev. 0

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADF5902

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 6 ..................................................................................... 22

Register 7 ..................................................................................... 23

Register 8 ..................................................................................... 24

Register 9 ..................................................................................... 24

Register 10................................................................................... 25

Register 11................................................................................... 25

Register 12................................................................................... 26

Register 13................................................................................... 27

Register 14................................................................................... 28

Register 15................................................................................... 29

Register 16................................................................................... 30

Register 17................................................................................... 30

Applications Information.............................................................. 31

Initialization Sequence .............................................................. 31

Recalibration Sequence ............................................................. 32

Temperature Sensor ................................................................... 33

RF Synthesis: a Worked Example............................................. 33

Reference Doubler...................................................................... 33

Frequency Measurement Procedure........................................ 34

Waveform Generation ............................................................... 34

Waveform Deviations and Timing........................................... 34

Ramp and Modulation............................................................... 35

Application of the ADF5902 in FMCW Radar ...................... 37

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 39

Automotive Products................................................................. 39

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 11

Reference Input Section............................................................. 11

RF INT Divider........................................................................... 11

INT, FRAC, and R Relationship ............................................... 11

R Counter .................................................................................... 11

PFD and Charge Pump.............................................................. 11

Input Shift Register..................................................................... 11

Program Modes .......................................................................... 12

Register Maps.................................................................................. 13

Register 0 ..................................................................................... 16

Register 1 ..................................................................................... 17

Register 2 ..................................................................................... 18

Register 3 ..................................................................................... 19

Register 4 ..................................................................................... 20

Register 5 ..................................................................................... 21

REVISION HISTORY

12/2018—Revision 0: Initial Version

Rev. 0 | Page 2 of 39

Data Sheet

ADF5902

SPECIFICATIONS

AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = CP_AHI = 3.3 V 5ꢀ, GND = 0 V, dBm referred to 50 Ω, T_A= T_MAXto T_MIN, unless

otherwise noted. The operating temperature range is −40°C to +105°C.

Table 1.

Parameter

Min

24

Typ

Max

24.25

2.5

Unit

Test Conditions/Comments

OPERATING CONDITIONS

RF Frequency Range

VCO CHARACTERISTICS

V_TUNE

GHz

0.5

V

V_TUNEImpedance

VCO Phase Noise Performance

At 100 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

Amplitude Noise

Static Pulling VCO Frequency (f_VCO) Change vs.

Load

Dynamic Pulling Transmitter On or Off Switch

Change

Dynamic Pulling Transmitter to Transmitter

Switch Change

Pushing f_VCOChange vs. AHI Change

Spurious Level Harmonics

Spurious Level Nonharmonics

POWER SUPPLIES

100

kΩ

Closed-loop, 10 kHz loop filter

−88

−108

−128

−150

2

dBc/Hz

dBc/Hz At 1 MHz offset

MHz

Open-loop into 2:1 voltage standing wave ratio

(VSWR) load

Open-loop

10

5

Open-loop

5

MHz/V

dBc

−30

<−70

AHI, TX_AHI, RF_AHI, VCO_AHI, DVDD, CP_AHI

3.135

3.3

3.465

12

V

1

Total Current (I_TOTAL

)

190

1.2

mA

μA

Software Power-Down Mode

Hardware Power-Down Mode

TRANSMITTER OUTPUT

Output Power

Output Impedance

On to Off Isolation

Transmitter to Transmitter Isolation

Power-Up/Power-Down Time

LO OUTPUT

200

2

8

dBm

Ω

dB

ns

50

30

25

200

Single transmitter output switched on to off

Output Power

Output Impedance

On to Off Isolation

−7

−1

50

35

+5

dBm

Ω

dB

PHASE FREQUENCY DETECTOR (PFD)

Phase Detector Frequency²

CHARGE PUMP

Charge Pump Current (I_CP) Sink and Source

Current

110

MHz

mA

Programmable

High Value

4.48

R_SET= 5.1 kΩ; R_SETis a resistor to ground that sets

the maximum charge pump output current

Low Value

Absolute Accuracy

R_SETRange

I_CPTristate Leakage Current

Sink and Source Matching

I_CPvs. V_CP

280

2.5

5.1

1

2

μA

%

kΩ

nA

%

R_SET= 5.1 kΩ

5.049

5.151

Sink and source current

0.5 V < charge pump voltage (V_CP) < CP_AHI − 0.6 V

0.5 V < V_CP< CP_AHI − 0.6 V

V_CP= CP_AHI/2

%

I_CPvs. Temperature

2

%

Rev. 0 | Page 3 of 39

ADF5902

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

Normalized Phase Noise Floor, Fractional-N

−222

−120

dBc/Hz PLL loop bandwidth (BW) = 1 MHz

Mode³

4

Normalized 1/f Noise (PN_{1_f}

TEMPERATURE SENSOR

Analog Accuracy

)

dBc/Hz Measured at 10 kHz offset, normalized to 1 GHz

5

°C

Following one point calibration

Digital Accuracy

Sensitivity

6.4

mV/°C

ANALOG-TO-DIGITAL CONVERTER (ADC)

Resolution

8

Bits

LSB

mV

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Least Significant Bit (LSB)

REF_INCHARACTERISITICS

REF_INInput Frequency

1

7.4

10

260

MHz

−5 dBm minimum to +9 dBm maximum biased

at AHI/2 (ac coupling ensures 1.8 ÷ 2 bias); for

frequencies < 10 MHz, use a dc-coupled, CMOS-

compatible square wave with a slew rate > 25 V/μs

REF_INInput Capacitance²

REF_INInput Current

LOGIC INPUTS

Input Voltage

1.2

100

pF

μA

High (V_IH)

1.4

V

Low (V_IL)

Input Current (I_INH, I_INL

Input Capacitance (C_IN)²

0.6

1

10

V

μA

pF

)

LOGIC OUTPUTS

Output Voltage

5

High (V_OH

)

DVDD −

0.4

V

Low (V_OL

Output Current

High (I_OH

Low (I_OL

)

0.4

)

500

μA

)

¹Following the initialization sequence described in the Initialization Sequence section, T_A= 25°C, AHI = 3.3 V, f_REFIN= 100 MHz, and RF = 24.025 GHz.

²Guaranteed by design. Sample tested to ensure compliance.

³This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(f_PFD) + 20 logN) to calculate

in-band phase noise performance as seen at the VCO output.

⁴The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f_RF)

and at an offset frequency (f) is given by PN = PN_{1_f}+ 10 log(10 kHz/f) + 20 log(f_RF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

⁵DVDD selected from the IO level bit (Bit DB11 in Register 3).

Rev. 0 | Page 4 of 39

Data Sheet

ADF5902

TIMING SPECIFICATIONS

Write Timing Specifications

AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = CP_AHI = 3.3 V 5ꢀ, GND = 0 V, dBm referred to 50 Ω, T_A= T_MINto T_MAX, unless

otherwise noted. The operating temperature range is −40°C to +105°C.

Table 2.

Parameter

Limit at T_MINto T_MAX

Unit

Description

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

20

10

25

10

20

10

15

ns min

ns max

LE setup time

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

LE setup time to DOUT

CLK setup time to DOUT

t₄

t₅

CLK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTRO BIT C1)

DB30

DATA

LE

DB31 (MSB)

7

1

6

DB31

(MSB)

DOUT

DB30

DB1

DB0

8

9

Figure 2. Write Timing Diagram

500µA

I

OL

TO DOUT AND

MUXOUT PINS

DVDD/2

C

L

10pF

500µA

I

OH

Figure 3. Load Circuit for DOUT/MUXOUT Timing, C_L= 10 pF

Rev. 0 | Page 5 of 39

ADF5902

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

The ADF5902 is a high performance RF integrated circuit with

an ESD rating of 2 kV and is ESD sensitive. Take proper

precautions for handling and assembly.

Parameter

Rating

AHI to GND

AHI to TX_AHI

AHI to RF_AHI

AHI to VCO_AHI

AHI to DVDD

AHI to CP_AHI

V_TUNEto GND

Digital Input/Output Voltage to GND

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Reflow Soldering

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to +3.6 V

−0.3 V to DVDD + 0.3 V

−40°C to +105°C

−65°C to +150°C

150°C

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 4. Thermal Resistance

1

2

Package Type

CP-32-12³

θ_JA

θ_JC

26.86

Unit

48.18

°C/W

¹θ_JAis the natural convection junction-to-ambient thermal resistance

measured in a one cubic foot sealed enclosure.

²θ_JCis the junction-to-case thermal resistance.

³Test Condition 1: thermal impedance simulated values are based on use of a

PCB with the thermal impedance pad soldered to GND.

Peak Temperature

260°C

40 sec

Time at Peak Temperature

Electrostatic Discharge (ESD)

Charged Device Model (CDM)

Human Body Model (HBM)

ESD CAUTION

250 V

2000 V

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. 0 | Page 6 of 39

Data Sheet

ADF5902

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

1

2

3

4

5

6

7

8

24 DOUT

23

22 DATA

21 CLK

20 CE

TX

1

LE

OUT

GND

ADF5902

TOP VIEW

(Not to Scale)

TX_AHI

GND

19

TX_DATA

TX

2

18 VREG

17 DVDD

OUT

GND

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO GND.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3, 6, 8, 10, GND

12, 13

RF Ground. Tie all GND pins together.

2

TX_OUT

1

24 GHz Transmitter Output 1.

4, 5

TX_AHI

Voltage Supply for the Transmitter Section. Connect decoupling capacitors (0.1 ꢀF, 1 nF, and 10 pF) to the

ground plane as close as possible to this pin. TX_AHI must be the same value as AHI.

7

9

11

14

TX_OUT

ATEST

LO_OUT

2

24 GHz Transmitter Output 2.

Analog Test Output Pin.

LO Output.

Voltage Supply for the RF Section. Connect decoupling capacitors (0.1 ꢀF, 1 nF, and 10 pF) to the ground

plane as close as possible to this pin. RF_AHI must be the same value as AHI.

RF_AHI

15

REF_IN

Reference Input. This pin is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input

resistance of 100 kΩ. See Figure 17. This input can be driven from a TTL or CMOS crystal oscillator, or it can

be ac-coupled.

16

17

AHI

Voltage Supply for the Analog Section. Connect decoupling capacitors (0.1 ꢀF, 1 nF, and 10 pF) to the

ground plane as close as possible to this pin.

Digital Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors (0.1 ꢀF,

1 nF, and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI.

DVDD

18

19

VREG

TX_DATA

Internal 1.8 V Regulator Output. Connect a 220 nF capacitor to ground as close as possible to this pin.

Transmit Data Pin. This pin controls some of the ramping functionality. Synchronize the rising edge of the

TX_DATA signal to the rising edge of REF_IN.

20

21

CE

CLK

Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device.

Serial Clock Input. This serial clock input clocks in the serial data to the registers. The data is latched into the

32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

22

23

DATA

LE

Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a

high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded to one of the

18 latches with the latch selected via the control bits.

24

25

26

DOUT

MUXOUT

R_SET

Serial Data Output.

Multiplexer Output. This multiplexer output allows various internal signals to be accessed externally.

Resistor Setting Pin. Connecting a 5.1 kΩ resistor between this pin and GND sets an internal current. The

nominal voltage potential at the R_SETpin is 0.62 V.

27

28

CP_AHI

CP_OUT

Charge Pump Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors

(0.1 ꢀF, 1 nF, and 10 pF) to the ground plane as close as possible to this pin. CP_AHI must be the same value

as AHI.

Charge Pump Output. When the charge pump is enabled, this output provides I_CPto the external loop

filter, which, in turn, drives the VCO.

Rev. 0 | Page 7 of 39

ADF5902

Data Sheet

Pin No.

29

Mnemonic

V_TUNE

Description

Control Input to the VCO. This voltage determines the output.

30

VCO_AHI

Voltage Supply for the VCO Section. Connect decoupling capacitors (0.1 ꢀF, 1 nF, and 10 pF) to the ground

plane as close as possible to this pin. VCO_AHI must be the same value as AHI.

31

32

C1

C2

EP

Decoupling Capacitor 1. Place a 47 nF capacitor to ground as close as possible to this pin.

Decoupling Capacitor 2. Place a 220 nF capacitor to ground as close as possible to this pin.

Exposed Pad. The exposed pad must be connected to GND.

Rev. 0 | Page 8 of 39

Data Sheet

ADF5902

TYPICAL PERFORMANCE CHARACTERISTICS

12

6

4

10

8

2

0

6

–2

–4

–6

–8

–40°C

+25°C

+105°C

–40°C

+25°C

+105°C

Tx1

4

Tx2

OUTSIDE OF SPECIFIED RANGE

2

OUTSIDE OF SPECIFIED RANGE

0

23.95

24.00

24.05

24.10

24.15

24.20

24.25

24.30

23.95

24.00

24.05

24.10

24.15

24.20

24.25

24.30

OUTPUT FREQUENCY (GHz)

Figure 5. Transmitter (Tx) Output Power vs. Output Frequency

Figure 8. LO Output Power vs. Output Frequency

12

10

8

24.250

24.200

24.150

24.100

24.050

24.000

6

4

3.135V

3.300V

3.465V

–40°C

+25°C

+105°C

2

OUTSIDE OF SPECIFIED RANGE

0

23.95

24.00

24.05

24.10

24.15

24.20

24.25

24.30

0

100

200

300

400

500

600

OUTPUT FREQUENCY (GHz)

TIME (µs)

Figure 6. Transmitter 1 (Tx1) Output Power Variation vs. Output Frequency

with Temperature and Supply

Figure 9. Triangular Ramp with Delay

24.250

24.200

24.150

24.100

24.050

24.000

15

–40°C

10

+25°C

+105°C

5

0

–5

–10

–15

–20

0

10

20

30

40

50

60

70

80

90

100

0

100

200

300

400

500

600

TIME (µs)

Tx AMPLITUDE CALIBRATION REFERENCE CODE

Figure 7. Transmitter (Tx) Output Power vs. Transmitter (Tx) Amplitude

Calibration Reference Code

Figure 10. Dual Triangular Ramp

Rev. 0 | Page 9 of 39

ADF5902

Data Sheet

4

3

24.300

24.250

24.200

24.150

24.100

24.050

2

1

0

PUMP UP SETTING 7

PUMP DOWN SETTING 7

–1

–2

–3

–4

–5

OUTSIDE OF SPECIFIED RANGE

24.000

0

0.5

1.0

1.5

2.0

2.5

3.0

100

200

300

400

500

600

CHARGE PUMP VOLTAGE (V)

TIME (µs)

Figure 14. Charge Pump Output Characteristics, CP_AHI = 3.3 V, at 25°C

Figure 11. Sawtooth Ramp

–40

3.5

3.0

2.5

2.0

1.5

1.0

0.5

25°C,AHI = 3.3V, I = 2.24mA

CP

300kHz LOOP BW FILTER, f_PFD= 100MHz

–60

–80

–100

–120

–140

–160

–40°C

+25°C

+105°C

0

100

1k

10k

100k

1M

10M

100M

24.00

24.05

24.10

24.15

24.20

24.25

FREQUENCY OFFET (Hz)

OUTPUT FREQUENCY (MHz)

Figure 15. Closed-Loop Phase Noise on Transmitter 1 at 24.125 GHz

Figure 12. V_TUNEFrequency Range

250

0

–10

1.8

–20

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

200

150

100

50

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

1k

0

10k

100k

1M

10M

FREQUENCY OFFSET (Hz)

TEMPERATURE (ºC)

Figure 13. Open-Loop Phase Noise on Transmitter 1 Output at 24.125 GHz

Figure 16. ATEST Voltage and ADC Code vs. Temperature

Rev. 0 | Page 10 of 39

Data Sheet

ADF5902

THEORY OF OPERATION

R DIVIDER

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 17. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This configuration ensures that there is no loading of

the REF_INpin on power-down.

5-BIT

R

REF

IN

×2

DOUBLER

TO PFD/

CAL BLOCK

COUNTER

÷2

DIVIDER

Figure 19. Reference Divider

POWER-DOWN

CONTROL

R COUNTER

1

100kΩ

NC

The 5-bit R counter allows the input reference frequency (REF_IN)

to be divided down to supply the reference clock to the PFD

and VCO calibration block. Division ratios from 1 to 32 are

allowed.

SW2

1

NC

REF

IN

TO R COUNTER

BUFFER

SW1

SW3

2

NO

PFD AND CHARGE PUMP

1

2

NC = NORMALLY CLOSED

NO = NORMALLY OPEN

The PFD receives inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 20 shows a simplified sche-

matic of the PFD.

Figure 17. Reference Input Stage

RF INT DIVIDER

The RF INT counter allows a division ratio in the RF feedback

counter. Division ratios from 75 to 4095 are allowed.

UP

HIGH

D1

Q1

U1

CLR1

INT, FRAC, AND R RELATIONSHIP

+IN

Generate the RF VCO frequency (RF_OUT) using the INT and

FRAC values in conjunction with the R counter, as follows:

CHARGE

PUMP

CP

U3

DELAY

DOWN

RF_OUT= f_PFD× (INT + (FRAC/2²⁵)) × 2

where:

RF_OUTis the output frequency of the internal VCO.

_PFDis the phase frequency detector (PFD) frequency.

(1)

CLR2

D2 Q2

HIGH

–IN

f

U2

INT is the preset divide ratio of the binary 12-bit counter

(75 to 4095).

Figure 20. PFD Simplified Schematic

FRAC is the numerator of the fractional division (0 to 2²⁵− 1).

The PFD includes a fixed delay element that sets the width of the

antibacklash pulse, which is typically 1 ns. This pulse ensures that

there is no dead zone in the PFD transfer function and provides

a consistent reference spur level.

f

_PFD= REF_IN× ((1 + D)/(R × (1 + T)))

(2)

where:

REF_INis the reference input frequency.

D is the REF_INdoubler bit (0 or 1).

R is the preset divide ratio of the binary, 5-bit, programmable

reference counter (1 to 32).

INPUT SHIFT REGISTER

The ADF5902 digital section includes a 5-bit RF R counter,

a 12-bit RF N counter, and a 25-bit FRAC counter. Data is

clocked to the 32-bit input shift register on each rising edge of

CLK. The data is clocked in MSB first. Data is transferred from

the input shift register to one of 18 latches on the rising edge of

LE. The destination latch is determined by the state of the five

control bits (C5, C4, C3, C2, and C1) in the input shift register.

These are the five LSBs (DB4, DB3, DB2, DB1, and DB0,

respectively), as shown in Figure 2. Table 6 shows the truth table

for these bits. Figure 21 and Figure 22 show a summary of how

the latches are programmed.

T is the REF_INdivide by 2 bit (0 or 1).

25

RF N DIVIDER

N = INT + FRAC/2

TO PFD/

CAL BLOCK

FROM RF

INPUT STAGE

N COUNTER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

INT

FRAC

VALUE

Figure 18. RF N Divider

Rev. 0 | Page 11 of 39

ADF5902

Data Sheet

value is latched into the device by writing to the appropriate

register. Second, a new write must be performed on Register R5.

PROGRAM MODES

Table 6 and Figure 24 through Figure 42 show how to set up the

program modes in the ADF5902.

For example, updating the fractional value can involve a write to

the 13 LSB bits in Register R6 and the 12 MSB bits in Register R5.

Write to Register R6 first, followed by the write to Register R5.

The frequency change begins after the write to Register R5.

Double buffering ensures that the bits written to in Register R6

do not take effect until after the write to Register R5.

Several settings in the ADF5902 are double buffered. These

include the LSB fractional value, R counter value (R divider),

reference doubler, clock divider, RDIV2, and MUXOUT. This

means that two events must occur before the device uses a new

value for any of the double buffered settings. First, the new

Table 6. C5, C4, C3, C2, and C1 Truth Table

Control Bits

C5 (DB4)

C4 (DB3)

C3 (DB2)

C2 (DB1)

C1 (DB0)

Register

R0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

R17

Rev. 0 | Page 12 of 39

Data Sheet

ADF5902

REGISTER MAPS

REGISTER 0 (R0)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0)

C4(0) C3(0) C2(0) C1(0)

0

1

REGISTER 1 (R1)

CONTROL

BITS

RESERVED

Tx AMP CAL REF CODE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)

1

0

1

REGISTER 2 (R2)

ADC

AVERAGE

CONTROL

RESERVED

ADC CLOCK DIVIDER

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

AS

AA0 AA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C5(0) C4(0) C3(0) C2(1) C1(0)

REGISTER 3 (R3)

CONTROL

BITS

1

RESERVED

READBACK CONTROL

MUXOUT DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

M3 M2 M1 M0 IOL RC5 RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)

0

1

0

1

0

1

REGISTER 4 (R4)

CONTROL

BITS

RAMP STATUS/ANALOG TEST BUS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AB14 AB13 AB12 AB11 AB10

0

AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)

REGISTER 5 (R5)

CONTROL

RESERVED

INTEGER WORD

FRAC MSB WORD

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

RON N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

F24 F23

F22 F21

F20 F19

F18 F17 F16 F15 F14 F13 C5(0) C4(0) C3(1) C2(0) C1(1)

REGISTER 6 (R6)

CONTROL

BITS

1

DBR

RESERVED

FRAC LSB WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 C5(0) C4(0) C3(1) C2(1) C1(0)

¹DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.

0

Figure 21. Register Summary (Register 0 to Register 6)

Rev. 0 | Page 13 of 39

ADF5902

Data Sheet

REGISTER 7 (R7)

CONTROL

BITS

1

R DIVIDER DBR

1

RESERVED

CLOCK DIVIDER

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

RD2

RD

R4

R3

R2

R1

R0 C5(0)

C4(0) C3(1) C2(1) C1(1)

C1D3 C1D2 C1D1 C1D0

0

MR

1

C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4

REGISTER 8 (R8)

CONTROL

BITS

FREQENCY CAL DIVIDER

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

FC9 FC8 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)

REGISTER 9 (R9)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C5(0) C4(1) C3(0) C2(0) C1(1)

REGISTER 10 (R10)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

C5(0) C4(1) C3(0) C2(1) C1(0)

REGISTER 11 (R11)

RAMP

MODE

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SFT

0

SDR

0

RM1 RM0

0

CR C5(0) C4(1) C3(0) C2(1) C1(1)

REGISTER 12 (R12)

1

DBR

RESERVED

CHARGE PUMP

CURRENT

CONTROL

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CC3 CC2 CC1 CC0 CTRI

C5(0) C4(1) C3(1) C2(0) C1(0)

0

1

0

1

0

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.

Figure 22. Register Summary (Register 7 to Register 12)

Rev. 0 | Page 14 of 39

Data Sheet

ADF5902

REGISTER 13 (R13)

CONTROL

BITS

CLOCK DIVIDER 2

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

LES CDM1 CDM0 C2D11C2D10 C2D9 C2D8 C2D7 C2D6 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CDS1 CDS0 C5(0) C4(1) C3(1) C2(0) C1(1)

REGISTER 14 (R14)

DEVIATION

SEL

CONTROL

BITS

RESERVED

DEVIATION OFFSET

DEVIATION WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

TDI

DW10 DW9 DW8 DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 C5(0)

C4(1) C3(1) C2(1) C1(0)

TRC

0

DS1 DS0 DO3 DO2 DO1 DO0 DW15 DW14 DW13 DW12 DW11

REGISTER 15 (R15)

STEP

SEL

CONTROL

BITS

RESERVED

STEP WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

SS1 SS0 SW19 SW18 SW17 SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 C5(0) C4(1) C3(1) C2(1) C1(1)

REGISTER 16 (R16)

DELAY

SELECT

CONTROL

BITS

RESERVED

DELAY START WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DSL1 DSL0 TR1 RD DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0 C5(1) C4(0) C3(0) C2(0) C1(0)

0

REGISTER 17 (R17)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C5(1) C4(0) C3(0) C2(0) C1(1)

0

Figure 23. Register Summary (Register 13 to Register 17)

Rev. 0 | Page 15 of 39

ADF5902

Data Sheet

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0)

C4(0) C3(0) C2(0) C1(0)

0

1

PLO PUP LO

0

1

POWER DOWN LO

POWER UP LO

PTx1 PUP Tx1

0

1

POWER DOWN Tx1

POWER UP Tx1

PTx2 PUP Tx2

0

1

POWER DOWN Tx2

POWER UP Tx2

PADC PUP ADC

0

1

POWER DOWN ADC

POWER UP ADC

Tx2C Tx2 AMP CAL

0

1

NORMAL OPERATION

Tx2 AMP CAL

VCAL VCO CAL

NORMAL OPERATION

VCO FULL CAL

0

1

Tx1C Tx1 AMP CAL

0

1

NORMAL OPERATION

Tx1 AMP CAL

PVCO PUP VCO

0

1

POWER DOWN VCO

POWER UP VCO

Figure 24. Register 0 (R0)

VCO Calibration

REGISTER 0

Bit DB9 provides the control bit for frequency calibration of the

VCO. Set this bit to 0 for normal operation. Setting this bit to 1

performs a VCO frequency and amplitude calibration. Bit DB9

is shown as VCO CAL in Figure 24.

Control Bits

With Bits[C5:C1] set to 00000, Register R0 is programmed.

Figure 24 shows the input data format for programming this

register.

Power-Up ADC

Reserved

Bit DB8 provides the power-up bit for the ADC. Setting this bit

to 0 performs a power-down of the ADC. Setting this bit to 1

performs a power-up of the ADC. Bit DB8 is shown as PUP ADC

in Figure 24.

Bits[DB31:DB13] are reserved and must be set as shown in

Figure 24.

Transmitter 2 (Tx2) Amplitude Calibration

Bit DB12 provides the control bit for amplitude calibration of

the Tx2 output. Set this bit to 0 for normal operation. Setting

this bit to 1 performs an amplitude calibration of the Tx2

output. Bit DB12 is shown as Tx2 AMP CAL in Figure 24.

Power-Up Tx2 Output

Bit DB7 provides the power-up bit for the Tx2 output. Setting

this bit to 0 performs a power-down of the Tx2 output. Setting

this bit to 1 performs a power-up of the Tx2 output. Only one

transmitter output can be powered up at any time, either Tx1

(DB6) or Tx2 (DB7). Bit DB7 is shown as PUP Tx2 in Figure 24.

Tx1 Amplitude Calibration

Bit DB11 provides the control bit for amplitude calibration of

the Tx1 output. Set this bit to 0 for normal operation. Setting

this bit to 1 performs an amplitude calibration of the Tx1

output. Bit DB11 is shown as Tx1 AMP CAL in Figure 24.

Power-Up Tx1 Output

Bit DB6 provides the power-up bit for the Tx1 output. Setting

this bit to 0 performs a power-down of the Tx1 output. Setting

this bit to 1 performs a power-up of the Tx1 output. Only one

Tx output can be powered up at any time, either Tx1 (DB6) or

Tx2 (DB7). Bit DB6 is shown as PUP Tx1 in Figure 24.

Power-Up VCO

Bit DB10 provides the power-up bit for the VCO. Setting this bit

to 0 performs a power-down of the VCO. Setting this bit to 1

performs a power-up of the VCO. Bit DB10 is shown as PUP

VCO in Figure 24.

Power-Up LO Output

Bit DB5 provides the power-up bit for the LO output. Setting

this bit to 0 performs a power-down of the LO output. Setting

this bit to 1 performs a power-up of the LO output. Bit DB5 is

shown as PUP LO in Figure 24.

Rev. 0 | Page 16 of 39

Data Sheet

ADF5902

CONTROL

BITS

Tx AMP CAL REF CODE

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)

1

0

1

TAR7 TAR6 .......... TAR1 TAR0

Tx AMP CAL REF CODE

0

.

0

.

..........

.........

0

1

.

0

1

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

252

253

254

255

Figure 25. Register 1 (R1)

Transmitter Amplitude Calibration Reference Code

REGISTER 1

Bits[DB12:DB5] set the transmitter amplitude calibration

reference code for the two transmitter outputs during

calibration. Calibrate the output power on the transmitter

outputs from −20 dBm to 8 dBm by setting the transmitter

amplitude calibration reference code (see Figure 7).

Bits[DB12:DB5] are shown as Tx AMP CAL REF CODE

in Figure 25.

Control Bits

With Bits[C5:C1] set to 00001, Register R1 is programmed.

Figure 25 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB13] are reserved and must be set as shown in

Figure 25.

Rev. 0 | Page 17 of 39

ADF5902

Data Sheet

ADC

AVERAGE

CONTROL

BITS

RESERVED

ADC CLOCK DIVIDER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

AS

AA0 AA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C5(0) C4(0) C3(0) C2(1) C1(0)

AS

0

ADC START

AC7 AC6

AC1

AC0

ADC CLOCK DIVIDER

.

NORMAL OPERATION

START ADC CONVERSION

0

.

0

.

0

1

.

1

0

.

1

.

1

2

.

AA1 AA0

ADC AVERAGE

.

0

1

0

1

0

1

2

3

4

1

0

1

0

1

0

1

124

125

126

127

Figure 26. Register 2 (R2)

ADC Start

REGISTER 2

Bit DB15 starts the ADC conversion. Setting this bit to 1 starts

an ADC conversion.

Control Bits

With Bits[C5:C1] set to 00010, Register R2 is programmed.

Figure 26 shows the input data format for programming this

register.

ADC Average

Bits[DB14:DB13] program the ADC average, which is the

number of averages of the ADC output (see Figure 26).

Reserved

Bits[DB31:DB16] are reserved and must be set as shown in

Figure 26.

ADC Clock Divider

Bits[DB12:DB5] program the clock divider, which is used as the

sampling clock for the ADC (see Figure 26). The output of the

R divider block clocks the ADC clock divider. Program a

divider value to ensure the ADC sampling clock is 1 MHz.

Rev. 0 | Page 18 of 39

Data Sheet

ADF5902

CONTROL

BITS

MUXOUT DBR¹

RESERVED

READBACK CONTROL

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

M3 M2

M1

M0

IOL RC5 RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)

M3 M2 M1 M0

MUXOUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

TRISTATE OUTPUT

LOGIC HIGH

LOGIC LOW

R DIVIDER OUTPUT

N DIVIDER OUTPUT

RESERVED

READBACK CONTROL

RC5 RC4 RC3 RC2 RC1 RC0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NONE

0

1

REGISTER 0

REGISTER 1

REGISTER 2

REGISTER 3

REGISTER 4

REGSITER 5

REGISTER 6

REGISTER 7

REGISTER 8

REGISTER 9

REGISTER 10

REGISTER 11

REGISTER 12

REGISTER 13 SEL = 0

REGISTER 14 SEL = 0

RESERVED

CAL BUSY

RESERVED

R DIVIDER/2

N DIVIDER/2

RESERVED

RAMP STATUS TO MUXOIUT

REGISTER 15 SEL = 0

REGISTER 16 SEL = 0

REGISTER 17

1

DBR = DOUBLE-BUFFERED REGISTER.

IOL

0

IO LEVEL

0

.

0

.

1

.

0

.

0

.

1

.

RESERVED

1.8V LOGIC OUTPUTS

3.3V LOGIC OUTPUTS

ADC READBACK

RESERVED

0

1

0

1

.

1

0

1

0

FREQ READBACK

.

0

1

.

RESERVED

REGISTER 13 SEL = 1

0

1

0

1

REGISTER 14 SEL = 1

REGISTER 15 SEL = 1

REGISTER 16 SEL = 1

REGISTER 13 SEL = 2

REGISTER 14 SEL = 2

REGISTER 15 SEL = 2

REGISTER 16 SEL = 2

REGISTER 13 SEL = 3

REGISTER 14 SEL = 3

REGISTER 15 SEL = 3

REGISTER 16 SEL = 3

RESERVED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Figure 27. Register 3 (R3)

MUXOUT Control

REGISTER 3

Bits[DB15:DB12] control the on-chip multiplexer of the

ADF5902. See Figure 27 for the truth table.

Control Bits

With Bits[C5:C1] set to 00011, Register R3 is programmed.

Figure 27 shows the input data format for programming this

register.

Input/Output (I/O) Level

Bit DB11 controls the DOUT logic levels. Setting this bit to 0

sets the DOUT logic level to 1.8 V. Setting this bit to 1 sets the

DOUT logic level to 3.3 V.

Reserved

Bits[DB31:DB16] are reserved and must be set as shown in

Figure 27.

Readback Control

Bits[DB10:DB5] control the readback data to DOUT on the

ADF5902. See Figure 27 for the truth table.

Rev. 0 | Page 19 of 39

ADF5902

Data Sheet

CONTROL

BITS

RESERVED

RAMP STATUS/ANALOG TEST BUS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)

0

AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0

ANALOG TEST BUS

0

1

0

1

0

0x0000

0x00C0

0x0100

0x0503

0x0903

NONE

RAMP COMPLETE TO MUXOUT

RAMP DOWN TO MUXOUT

TEMPERATURE SENSOR TO ATEST

TEMPERATURE SENSOR TO ADC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Figure 28. Register 4 (R4)

Ramp Status/Analog Test Bus

REGISTER 4

Bits[DB19:DB5] control the analog test bus and the ramp status

to MUXOUT (see Figure 28).

Control Bits

With Bits[C5:C1] set to 00100, Register R4 is programmed.

Figure 28 shows the input data format for programming this

register.

The analog test bus allows access to internal test signals for the

temperature sensor which can be connected to the ATEST pin

or the internal ADC.

Reserved

Setting Bits DB[19:5] to 0 (no value) sets the ATEST pin to high

impedance.

Bits[DB31:DB20] are reserved and must be set as shown in

Figure 28.

For ramp status outputs on MUXOUT, the MUXOUT bits in

Register R3 (Bits[DB15:DB12]) must be set to 1111 to access

these modes.

Rev. 0 | Page 20 of 39

Data Sheet

ADF5902

CONTROL

BITS

RESERVED

INTEGER WORD

FRAC MSB WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

RON N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

F24 F23

F22 F21

F20 F19

F18 F17 F16 F15 F14 F13 C5(0) C4(0) C3(1) C2(0) C1(1)

N11

0

N10

...

N4

N3

N2

0

.

N1

0

1

.

N0

0

1

0

.

INTEGER WORD

FRAC MSB WORD

(FRAC)*

F24

F23

.......... F14

F13

0

.

0

.

0

.

NOT ALLOWED

0

NOT ALLOWED

0

.

0

.

..........

.........

0

1

.

0

1

0

1

.

0

NOT ALLOWED

1

.

...

2

0

.

0

.

1

.

0

1

.

1

0

.

0

1

0

.

NOT ALLOWED

3

0

75

.

0

76

.

...

.

1

0

1

0

1

4093

4094

4095

1

0

1

0

1

0

1

4092

4093

4094

4095

1

R1

RAMP ON

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN

0

1

RAMP DISABLED

RAMP ENABLED

REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2¹³

.

Figure 29. Register 5 (R5)

When using the TX_DATA pin to trigger the ramp off in

continuous ramp modes, the ramp stops at the initial frequency,

a write to Register R6 is not required. When using the TX_

DATA pin in single ramp modes, a write to Register R6 is not

required prior to repeating the single ramp function.

REGISTER 5

Control Bits

With Bits[C5:C1] set to 00101, Register R5 is programmed.

Figure 29 shows the input data format for programming this

register.

12-Bit Integer Value (INT)

Reserved

These 12 bits (Bits[DB28:DB17]) set the INT value, which

determines the integer part of the RF division factor. This INT

value is used in Equation 5. See the RF Synthesis: a Worked

Example section for more information. All integer values from 75

to 4095 are allowed.

Bits[DB31:DB30] are reserved and must be set as shown in

Figure 29.

Ramp On

When Bit DB29 is set to 1, the ramp is started. When Bit DB29

is set to 0, the ramp function is disabled.

12-Bit MSB Fractional Value (FRAC)

In continuous ramp modes, the ramp stops when Bit DB29 is

set to 0. For applications that require the ramp to stop at the

initial frequency, a write to Register R6 is required prior to

disabling the ramp function. In single ramp modes, a write to

Register R6 is required prior to repeating the single ramp

function.

Bits[DB16:DB5], together with Bits[DB17:DB5] (FRAC LSB

word) in Register R6, control what is loaded as the FRAC value

into the fractional interpolator. This FRAC value partially

determines the overall RF division factor. It is also used in

Equation 1. These 12 bits are the most significant bits (MSB) of

the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB word)

in Register R6 are the least significant bits (LSB). See the RF

Synthesis: a Worked Example section for more information.

Rev. 0 | Page 21 of 39

ADF5902

Data Sheet

CONTROL

BITS

1

DBR

RESERVED

FRAC LSB WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F12

F11 F10

F9

F8

F7

F6

F5

F4

F3

F2 F1

F0 C5(0) C4(0) C3(1) C2(1) C1(0)

FRAC LSB WORD

(FRAC)*

F12

F11

.......... F1

F0

0

.

0

.

..........

.........

0

1

.

0

1

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

8188

8189

8190

8191

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN

REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2

1

13

DBR = DOUBLE-BUFFERED REGISTER.

.

Figure 30. Register 6 (R6)

13-Bit LSB FRAC Value

REGISTER 6

These 13 bits (Bits[DB17:DB5]), together with Bits[DB16:DB5]

(FRAC MSB word) in Register R5, control what is loaded as the

FRAC value into the fractional interpolator. This FRAC value

partially determines the overall RF division factor. It is also used

in Equation 1. These 13 bits are the least significant bits (LSB)

of the 25-bit FRAC value, and Bits[DB16:DB5] (FRAC MSB

word) in Register R5 are the most significant bits (MSB). See

the RF Synthesis: a Worked Example section for more

information.

Control Bits

With Bits[C5:C1] set to 00110, Register R6 is programmed.

Figure 30 shows the input data format for programming

this register.

Reserved

Bits[DB31:DB18] are reserved and must be set as shown in

Figure 30.

Rev. 0 | Page 22 of 39

Data Sheet

ADF5902

CONTROL

BITS

DBR¹

RESERVED

CLOCK DIVIDER

R DIVIDER DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RD2 RD R4 R3 R2 R1 R0 C5(0)

C4(0) C3(1) C2(1) C1(1)

0

C1D3 C1D2 C1D1 C1D0

0

MR

1

C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4

MR

0

MASTER RESET

RD2 RDIV2

DISABLED

ENABLED

0

1

DISABLED

ENABLED

1

REF

DOUBLER

RD

C1D11 C1D10 .......... C1D2 C1D0

CLOCK DIVIDER (CLK₁)

0

1

DISABLED

ENABLED

0

.

0

.

..........

.........

0

1

.

0

1

0

1

.

0

1

2

R4

R3

R1

R0

R DIVIDER (R)

R2

3

.

0

.

0

.

0

1

.

1

0

.

1

0

.

2

.

1

0

1

0

1

0

1

4092

4093

4094

4095

.

1

0

1

0

1

0

1

28

29

30

31

1

¹DBR = DOUBLE-BUFFERED REGISTER.

Figure 31. Register 7 (R7)

Divide by 2 (RDIV2)

REGISTER 7

Setting the DB11 bit to 1 inserts a divide by 2 toggle flip flop

between the R counter and VCO calibration block.

Control Bits

With Bits[C5:C1] set to 00111, Register R7 is programmed.

Figure 31 shows the input data format for programming

this register.

Reference Doubler

Setting DB10 to 0 feeds the REF_INsignal directly to the 5-bit

R counter, disabling the doubler. Setting this bit to 1 multiplies

the REF_INfrequency by a factor of 2 before the REF_INsignal is

fed to the 5-bit R counter. When the doubler is disabled, the

REF_INfalling edge is the active edge at the PFD input to the

fractional synthesizer. When the doubler is enabled, both the

rising and falling edges of REF_INbecome active edges at the

PFD input.

Reserved

Bits[DB31:DB26] are reserved and must be set as shown in

Figure 31.

Master Reset

Bit DB25 provides a master reset bit for the device. Setting this

bit to 1 performs a reset of the device and all register maps.

Setting this bit to 0 returns the device to normal operation.

When the reference doubler is enabled, for optimum phase

noise performance, it is recommended to only use charge pump

current settings of 0b0000 to 0b0111, that is, 0.28 mA to 2.24 mA

in Register 12. In this case, the best practice is to design the loop

filter for a charge pump current of 1.12 mA or 1.4 mA and then

use the programmable charge pump current to adjust the

frequency response.

Clock Divider

Bits[DB23:DB12] controls the clock divider (CLK₁) value (see

Figure 31). The CLK₁value sets a divider for the VCO frequency

calibration. Load the divider such that PFD frequency (f_PFD)/

CLK₁is less than or equal to 25 kHz.

For example, for f_PFD= 50 MHz, set CLK₁= 2048 so that f_PFD

CLK₁< 25 kHz.

/

The maximum allowable REF_INfrequency when the doubler is

enabled is 50 MHz.

The CLK₁value is also used to determine the duration of the

time step in ramp mode. See the Ramp and Modulation section

for more information.

5-Bit R Divider

The 5-bit R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the VCO calibration block. Division ratios from 1 to 31 are

allowed.

Rev. 0 | Page 23 of 39

ADF5902

Data Sheet

CONTROL

BITS

FREQENCY CAL DIVIDER

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FC9 FC8 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)

0

1

0

FREQUENCY CAL

FC9 FC8

...

FC4 FC3 FC2 FC1 FC0

DIVIDER

0

.

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

0

1

2

...

.

...

1

0

1

0

1

1021

1023

1024

Figure 32. Register 8 (R8)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C5(0) C4(1) C3(0) C2(0) C1(1)

Figure 33. Register 9 (R9 0x2A20B929)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C5(0) C4(1) C3(0) C2(0) C1(1)

0

1

0

1

0

1

0

1

0

1

0

1

Figure 34. Register 9 (R9 0x2800B929)

frequency calibration divider is less than or equal to 100 kHz

(see Figure 32).

REGISTER 8

Control Bits

REGISTER 9

With Bits[C5:C1] set to 01000, Register R8 is programmed.

Figure 32 shows the input data format for programming this

register.

The bits in Register 9 are reserved and must be programmed as

shown in Figure 32 using a hexadecimal word of 0x2A20B929,

prior to the VCO calibration.

Reserved

The bits in Register 9 must be programmed as described in

Figure 32, using a hexadecimal word of 0x2800B929 for normal

operation.

Bits[DB31:DB15] are reserved and must be set as shown in

Figure 32.

Frequency Calibration Divider

See the Applications Information section for more information.

Bits[DB14:DB5] set a divider for the VCO frequency calibration

clock. Load the divider such that the PFD frequency (f_PFD)/

Rev. 0 | Page 24 of 39

Data Sheet

ADF5902

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

C5(0) C4(1) C3(0) C2(1) C1(0)

Figure 35. Register 10 (R10 0x1D32A64A)

RAMP

MODE

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SDR SFT RM1 RM0 CR C5(0) C4(1) C3(0) C2(1) C1(1)

0

CR CNTR RESET

0

1

DISABLED

ENABLED

SDR SD RESET

0

1

ENABLED

DISABLED

SING FULL TRI

DISABLED

SFT

0

1

ENABLED

RM1 RM0 RAMP MODE

0

1

0

1

0

1

CONTINUOUS SAWTOOTH

SINGLE SAWTOOTH BURST

CONTINUOUS TRIANGULAR

SINGLE RAMP BURST

Figure 36. Register 11 (R11)

Single Full Triangle

REGISTER 10

When Bit DB9 is set to 1, the single full triangle function is

enabled. When Bit DB9 is set to 0, this function is disabled. To

use the single full triangle function, ramp mode (Register 11,

Bits DB[8:7]) must be set to 0b11, single sawtooth burst. For

more information, see the Ramp and Modulation section.

The bits in Register 10 are reserved and must be programmed

as shown in Figure 35 using a hexadecimal word of 0x1D32A64A.

REGISTER 11

Control Bits

With Bits[C5:C1] set to 01011, Register R11 is programmed.

Figure 36 shows the input data format for programming this

register.

Ramp Mode

Bits[DB8:DB7] determine the type of generated waveform (see

Figure 36). For more information, see the Ramp and

Modulation section.

Reserved

Bits[DB31:DB12], Bit DB10, and Bit DB6 are reserved and must

be set as shown in Figure 36.

Counter Reset

Bit DB5 provides a counter reset bit for the counters. Setting

this bit to 1 performs a counter reset of the device counters.

Setting this bit to 0 returns the device to normal operation.

Bit DB5 is shown as CNTR RESET in Figure 36.

SD Reset

For most applications, set Bit DB11 to 0. When this bit is set to 0,

the Σ-Δ (SD) modulator is reset on each write to Register R5. If

it is not required that the SD modulator be reset on each write to

Register R5, set this bit to 1.

Rev. 0 | Page 25 of 39

ADF5902

Data Sheet

1

DBR

RESERVED

CHARGE PUMP

CURRENT

CONTROL

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CC3 CC2 CC1 CC0

CTRI

0

1

0

1

0

C5(0) C4(1) C3(1) C2(0) C1(0)

CP

CTRI

TRISTATE

0

1

DISABLED

ENABLED

I

(mA)

CP

CC3

CC2

CC1

CC0

5.1kΩ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.28

0.56

0.84

1.12

1.40

1.68

1.96

2.24

2.52

2.80

3.08

3.36

3.64

3.92

4.20

4.48

1

DBR = DOUBLE-BUFFERED REGISTER.

Figure 37. Register 12 (R12)

Charge Pump Current Setting

REGISTER 12

Bits[DB20:DB17] set the charge pump current (see Figure 37). Set

these bits to the charge pump current that the loop filter is

designed with. The best practice is to design the loop filter for a

charge pump current of 2.24 mA or 2.52 mA and then use the

programmable charge pump current to adjust the frequency

response. See the Reference Doubler section for information on

setting the charge pump current when the doubler is enabled.

Control Bits

With Bits[C5:C1] set to 01100, Register R12 is programmed.

Figure 37 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB21] and Bit DB16 are reserved and must be set as

shown in Figure 37.

Charge Pump Tristate

When Bit DB15 is set to 1, the charge pump is placed in tristate

mode. For normal charge pump operation, set this bit to 0.

Rev. 0 | Page 26 of 39

Data Sheet

ADF5902

CONTROL

BITS

CLOCK DIVIDER 2

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

LES CDM1 CDM0 C2D11C2D10 C2D9 C2D8 C2D7 C2D6 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CDS1 CDS0 C5(0) C4(1) C3(1) C2(0) C1(1)

LES

0

LE SEL

LE FROM PIN

LE SYNC WITH REF

1

CDS1 CDS0

CLK DIV SEL

IN

0

LOAD CLK DIV 0

0

1

0

1

LOAD CLK DIV 1

LOAD CLK DIV 2

LOAD CLK DIV 3

CDM1 CDM0 CLOCK DIVIDER MODE

0

1

0

1

0

1

CLOCK DIVIDER OFF

RESERVED

FREQ MEASUREMENT

RAMP DIVIDER

C2D11C2D10

C2D1 C2D0

CLOCK DIVIDER 2 (CLK₂)

0

.

0

.

...

0

1

.

0

1

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

4092

4093

4094

4095

Figure 38. Register 13 (R13)

Clock Divider Mode

REGISTER 13

Bits[DB20:DB19] are used to enable ramp divider mode. When

using any of the ramp modes, set Bits[CDM1:CDM0] to 11.

Otherwise, set these bits to 0b00.

Control Bits

With Bits[C5:C1] set to 01101, Register R13 is programmed.

Figure 38 shows the input data format for programming this

register.

12-Bit Clock Divider (CLK₂) Value

Bits[DB18:DB7] program the clock divider (CLK₂) timer when

the device operates in ramp mode (see the Ramp and

Modulation section).

Reserved

Bits[DB31:DB22] are reserved and must be set as shown in

Figure 38.

Clock Divider Select

LE Select

Bits[DB6:DB5] select the segment of the ramp CLK₂is used (see

Figure 38). For more information, see the Ramp and Modulation

section. Bits[DB6:DB5] are shown as CLK DIV SEL in Figure 38.

In some applications, it is necessary to synchronize the LE pin

with the reference signal. To perform this synchronization,

Bit DB21 must be set to 1. Synchronization is performed

internally on the device.

Rev. 0 | Page 27 of 39

ADF5902

Data Sheet

DEVIATION

SEL

CONTROL

BITS

DEVIATION OFFSET

DEVIATION WORD

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

TDI DW10 DW9 DW8 DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 C5(0)

C4(1) C3(1) C2(1) C1(0)

TRC

0

DS1 DS0 DO3 DO2 DO1 DO0 DW15 DW14 DW13 DW12 DW11

TDI Tx_DATA INV

0

1

DISABLED

DW15 DW14 ...

DW1 DW0

DEVIATION WORD

ENABLED

0

.

1

.

...

1

.

1

.

32,767

.

TX RAMP CLK

DO3 DO3 DO1 DO0 DEV OFFSET

TRC

0

1

0

3

2

...

0

.

0

.

0

1

.

0

1

0

.

0

1

2

.

0

1

CLK DIV

Tx_DATA PIN

...

0

1

0

1

0

...

1

.

1

.

1

0

.

1

0

1

.

–1

–2

.

0

1

0

1

0

1

7

8

9

3

–

...

0

.

1

0

–32,768

DS1

DS0

DEVIATION SEL

0

1

0

1

0

1

LOAD DEVIATION 0

LOAD DEVIATION 1

LOAD DEVIATION 2

LOAD DEVIATION 3

Figure 39. Register 14 (R14)

TX_DATA Ramp Clock

REGISTER 14

When Bit DB30 is set to 0, the clock divider clock is used to

clock the ramp. When Bit DB30 is set to 1, the TX_DATA pin

is used to clock the ramp.

Control Bits

With Bits[C5:C1] set to 01110, Register R14 is programmed.

Figure 39 shows the input data format for programming this

register.

Deviation Select

Bits[DB26:DB25] select the deviation word to be loaded (see

Figure 39).

Reserved

Bits[DB29:DB27] are reserved and must be set as shown in

Figure 39.

4-Bit Deviation Offset Word

Bits DB[24:21] determine the deviation offset word. The

deviation offset word affects the deviation resolution (see the

Ramp and Modulation section).

TX_DATA Invert

When Bit DB31 is set to 0, events triggered by TX_DATA occur

on the rising edge of the TX_DATA pulse. When Bit DB31 is set

to 1, events triggered by TX_DATA occur on the falling edge of

the TX_DATA pulse.

16-Bit Deviation Word

Bits[DB20:DB5] determine the signed deviation word in twos

complement format. The deviation word defines the deviation

step (see the Ramp and Modulation section).

Rev. 0 | Page 28 of 39

Data Sheet

ADF5902

STEP

SEL

CONTROL

BITS

RESERVED

STEP WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

SS1 SS0 SW19 SW18 SW17 SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 C5(0) C4(1) C3(1) C2(1) C1(1)

SS1 SS0

STEP SEL

...

SW19 SW18

SW1 SW0

STEP WORD

0

1

0

1

0

1

LOAD STEP 0

LOAD STEP 1

LOAD STEP 2

LOAD STEP 3

0

.

0

.

...

0

1

.

0

1

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

1,048,572

1,048,573

1,048,574

1,048,575

Figure 40. Register 15 (R15)

Step Select

REGISTER 15

Bits[DB26:DB25] select the step word to be loaded (see Figure 40).

Control Bits

With Bits[C5:C1] set to 01111, Register R15 is programmed.

Figure 40 shows the input data format for programming this

register.

20-Bit Step Word

Bits[DB22:DB3] determine the step word. The step word is the

number of steps in the ramp (see the Ramp and Modulation

section).

Reserved

Bits[DB31:DB27] are reserved and must be set as shown in

Figure 40.

Rev. 0 | Page 29 of 39

ADF5902

Data Sheet

CONTROL

BITS

RESERVED

DEL SEL

DELAY START WORD

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

DSL1 DSL0

0

TR1

RD

DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0 C5(1) C4(0) C3(0) C2(0) C1(0)

DS11 DS10

...

DS1

DS0

DELAY START WORD

0

.

0

.

...

0

1

.

0

1

0

1

.

0

1

2

TR1 TX DATA TRIGGER

3

0

1

DISABLED

ENABLED

.

1

0

1

0

1

0

1

4092

4093

4094

4095

DSL1 DSL0

DELAY SELECT

0

1

0

1

0

1

LOAD DELAY 0

LOAD DELAY 1

LOAD DELAY 2

LOAD DELAY 3

RD

RAMP DEL

0

1

DISABLED

ENABLED

Figure 41. Register 16 (R16)

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C5(1) C4(0) C3(0) C2(0) C1(1)

0

Figure 42. Register 17 (R17)

When Bit DB20 is set to 0, this function is disabled.

REGISTER 16

Control Bits

When activating continuous triangular or continuous sawtooth

ramps, a pulse applied to the TX_DATA pin is required after

Bit DB29 of Register 5 is toggled high. To stop the continuous

triangular or sawtooth ramps, a TX_DATA pulse is required

after Bit DB29 of Register 5 is toggled low.

With Bits[C5:C1] set to 10000, Register R16 is programmed.

Figure 41 shows the input data format for programming this

register.

Reserved

When Bit DB20 is set to 0, this function is disabled.

Bits[DB31:DB25], Bits[DB22:DB21], and Bits[DB18:DB17] are

reserved and must be set as shown in Figure 41.

Ramp Delay

When Bit DB19 is set to 1, the delay between ramps function is

enabled. When Bit DB19 is set to 0, this function is disabled.

Delay Select

Bits[DB24:DB23] select the delay word to be loaded.

TX_DATA Trigger

12-Bit Delay Word

Bits[DB16:DB5] determine the delay word. The delay word

determines the duration of the ramp start delay.

When Bit DB20 is set to 1, a logic high on the TX_DATA pin

activates the ramp in conjunction with Bit DB29 of Register 5.

Synchronize the active edge of the pulse applied to the TX_

DATA pin to the rising edge of the REF_INreference input.

REGISTER 17

The bits in Register 17 are reserved and must be programmed

as described in Figure 42 using a hexadecimal word of

0x00000011.

The pulse duration applied to the TX_DATA pin must be a

minimum width of 4 × 1/f_PFD, where f_PFDis the phase frequency

detector (PFD) frequency.

Rev. 0 | Page 30 of 39

Data Sheet

ADF5902

APPLICATIONS INFORMATION

This sequence locks the VCO to 24.025 GHz with a 100 MHz

reference. The ramp-up rate is 200 MHz at 144 μs. The ramp-

down rate is 200 MHz at 9 μs.

INITIALIZATION SEQUENCE

After powering up the device, administer the programming

sequence shown in Table 7.

Table 7. Initialization Sequence

Step

Register

Hexadecimal Code

0x02000007

0x0000002B

0x0000000B

0x0018000D

0x1D32A64A

0x2A20B929

0x40003E88

0x800FE520

Description

1

2

3

4

5

6

7

8

R7

Master reset

Reset the counters

Enable counters

Enable ramp divider

R11

R13

R10

R9

Reserved

VCO calibration setup

Set the VCO frequency calibration divider clock to 100 kHz

Power up the device and LO

R8

R0

Delay of 10 μs

9

10

11

12

13

14

15

16

R7

R6

R5

R4

R3

R2

R1

R0

0x01800827

0x00000006

0x01E38005

0x00000004

0x01897803

0x00020642

0xFFF7FFE1

0x800FE720

PFD = 50 MHz, CLK₁= 2048

Set the LSB FRAC = 0

N = 241.175

Set the ATEST pin to high impedance

Sets the I/O level to 3.3 V, CAL_BUSY to MUXOUT

Set ADC clock to 1 MHz

Set the transmitter amplitude level

Start the VCO frequency calibration

Delay of 1200 μs

17

18

R0

0x800FE560

0x800FED60

Turn Tx1 on, Tx2 off, and LO on

Tx1 amplitude calibration

Delay of 500 μs

19

20

R0

0x800FE5A0

0x800FF5A0

Turn Tx1 off, Tx2 on, and LO on

Tx2 amplitude calibration

Delay of 500 μs

21

22

23

24

25

26

27

28

R17

R16

R15

R14

0x00000011

0x00000010

0x0000120F

0x0200012F

0x0400120F

0x0600012F

0x012038EE

0x033C720E

Reserved

Ramp delay register

Load step register with STEP_SEL = 0, step word is 144

Load step register with STEP_SEL = 1, step word is 9

Load step register with STEP_SEL = 2, step word is 144

Load step register with STEP_SEL = 3, step word is 9

Load deviation register with DEV_SEL = 0, DEV = 455, DEV offset = 9

Load deviation register with DEV_SEL = 1, dev word= −1820, DEV

offset = 9

29

30

R14

0x052038EE

0x73C720E

Load deviation register with DEV_SEL = 2, dev word = 455, dev offset = 9

Load deviation register with DEV_SEL = 3, dev word = −1820 dev

offset = 9

31

32

33

34

35

36

37

38

R13

R12

R9

R7

R6

R5

R4

0x0018050D

0x0018052D

0x0018054D

0x0018056D

0x004F000C

0x2800B929

0x0100A027

0x00000006

0x00F04005

0x00002004

0x0189F803

Load the clock register with CLK DIV SEL = 0, CLK2_0 = 10

Load the clock register with CLK DIV SEL = 1, CLK2_1 = 10

Load the clock register with CLK DIV SEL = 2, CLK2_2 = 10

Load the clock register with CLK DIV SEL = 3, CLK2_3 = 10

Charge pump current = 2.24 mA

Normal Operation

PFD = 100 MHz, CLK₁= 10

Set the LSB FRAC = 0

INT =120, MSB FRAC = 512; lock to 24.025 GHz

Ramp down to MUXOUT

39

40

41

R3

I/O voltage level to 3.3 V

Delay of 100 μs

42

R11

0x0000010B

Select ramp mode

Rev. 0 | Page 31 of 39

ADF5902

Data Sheet

temperature can be monitored using the temperature sensor

(see the Temperature Sensor section).

RECALIBRATION SEQUENCE

The ADF5902 can be recalibrated after the initialization sequence

is complete and the device is powered up. The recalibration

sequence must be run for every 10°C temperature change. The

Table 8. Recalibration Sequence

Step Number from

Initialization Sequence

Register

R0

Hexadecimal Code

0x800FE500

0x2A20B929

0x01800827

0x00000006

0x01E38005

0x00000004

0x01897803

0x00020642

0xFFF7FFE1

0x800FE700

Description

Turn Tx1 off, Tx2 off and LO off

Reserved

PFD = 50 MHz, CLK₁= 2048

Set the LSB FRAC = 0

6

9

R9

R7

R6

R5

R4

R3

R2

R1

10

11

12

13

14

15

N = 241.175

Set the ATEST pin to high impedance

I/O level to 3.3 V, CAL_BUSY to MUXOUT

Set ADC clock to 1 MHz

Set the transmitter amplitude level

Start the VCO frequency calibration

R0

Delay of 1200 μs

17

18

R0

0x800FE560

0x800FED60

Turn Tx1 on, Tx2 off, and LO on

Tx1 amplitude calibration

Delay of 500 μs

19

20

R0

0x800FE5A0

0x800FF5A0

Turn Tx1 off, Tx2 on, and LO on

Tx2 amplitude calibration

Delay of 500 μs

36

37

38

39

R9

R7

R6

R5

0x2800B929

0x0100A027

0x00000006

0x00F04005

Reserved

PFD set to 100 MHz, CLK_DIV1 = 10

Set the LSB FRAC = 0

Set INT word to 120, set MSB FRAC = 512; lock to

24.025 GHz

40

41

R4

R3

0x00002004

0x0189F803

Ramp down to MUXOUT

I/O voltage level to 3.3 V

Delay of 100 μs

42

R11

0x0000010B

Select ramp mode

Rev. 0 | Page 32 of 39

Data Sheet

ADF5902

RF SYNTHESIS: A WORKED EXAMPLE

TEMPERATURE SENSOR

The following equation governs how to program the ADF5902:

RF_OUT= (INT + (FRAC/2²⁵)) × f_REF× 2

(5)

where:

RF_OUTis the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

The ADF5902 has an on-chip temperature sensor that can be

accessed on the ATEST pin or as a digital word on DOUT

following an ADC conversion. The temperature sensor operates

over the full operating temperature range of −40°C to +105°C.

The accuracy can be improved by performing a one-point

calibration at room temperature and storing the result in

memory.

f

_REF= REF_IN× ((1 + D)/(R × (1 + T)))

(6)

With the temperature sensor on the analog test bus and test bus

connected to the ATEST pin (Register 4 set to 0x0000A064), the

ATEST voltage can be converted to temperature with the

following equation:

where:

REF_INis the reference frequency input.

D is the reference doubler bit, DB10 in Register R7 (0 or 1).

R is the reference division factor.





V_ATEST V_OFF

Temperature (^C) 

(3)

T is the reference divide by 2 bit, DB11 in Register R7 (0 or 1).

V_GAIN

For example, in a system where a 24.125 GHz RF frequency

output (RF_OUT) is required and a 100 MHz reference frequency

input (REF_IN) is available, f_REFis set to 50 MHz.

where:

V

_ATESTis the voltage on the ATEST pin.

_OFF= 0.699 V, the offset voltage.

_GAIN= 6.4 × 10⁻³, the voltage gain.

From Equation 6,

f

_REF= (100 MHz × (1 + 0)/(1 × (1 + 1)) = 50 MHz

From Equation 5,

24.125 GHz = 50 MHz × (N + FRAC/2²⁵) × 2

The temperature sensor result can be converted to a digital

word with the ADC and readback on DOUT with the following

sequence:

1. Write 0x00012064 to Register R4 to connect the analog test

bus to the ADC and the temperature sensor to the analog

test bus.

2. Write 0x0002A802 to Register R2 to start the ADC

conversion.

3. Write 0x0189FAC3 to Register R3 to set the ADC output

data to DOUT.

4. Read back DOUT.

Calculating the N and FRAC values,

N = int(RF_OUT/(f_REF× 2)) = 241

FRAC = F_MSB× 2¹³+ F_LSB

F

_MSB= int(((RF_OUT/(f_REF× 2)) − N) × 2¹²) = 1024

_LSB= int(((((RF_OUT/(f_REF× 2)) − N) × 2¹²) − F_MSB) × 2¹³) = 0

where:

F_MSBis the 12-bit MSB FRAC value in Register R5.

F_LSBis the 13-bit LSB FRAC value in Register R6.

5. Write 0x00002064 to Register R4 to reset Register R4 to the

initial value.

int() makes an integer of the argument in parentheses.

6. Write 0x00020642 to Register R2 to reset Register R2 to the

initial value.

REFERENCE DOUBLER

The on-chip reference doubler allows the input reference signal to

be doubled. This doubling is useful for increasing the PFD compar-

ison frequency. Doubling the PFD frequency typically improves

the noise performance of the system by 3 dB.

Convert the DOUT word to temperature with the following

equation:



ADC V_LSB



V_OFF



Temperature (^C) 

(4)

V_GAIN

where:

ADC is the ADC code read back on DOUT.

V

_LSB= 7.33 mV, the ADC LSB voltage.

_OFF= 0.699 V, the offset voltage.

_GAIN= 6.4 × 10⁻³, the voltage gain.

Rev. 0 | Page 33 of 39

ADF5902

Data Sheet

FREQUENCY MEASUREMENT PROCEDURE

Use the following procedure to measure the output locked

frequency of the ADF5902:

1. In Register R3, set the readback control bits

(Bits[DB10:DB5]) to 26.

2. Read back the frequency counter value on DOUT and

record this value as Frequency 1 (see Figure 3).

3. In Register R7, set the CLK1 bits (Bits[DB23:DB12]) to

1808.

TIME

Figure 44. Single Triangular Burst

4. In Register R13, set the CLK2 bits (Bits[DB18:DB7]) to 10.

5. In Register R5, set the ramp on bit (Bit DB29) to 0.

6. In Register R13, Set the clock divider mode bits

(Bits[DB20:DB19]) to 2.

7. Allow a minimum delay of 428 μs (CLK_DIV/f_PFD(sec)).

8. In Register R3, set the readback control bits

(Bits[DB10:DB5]) to 26.

TIME

Figure 45. Single Sawtooth Burst

9. Read back the frequency counter value on DOUT and

record this value as Frequency 2.

Where Frequency 1 > Frequency 2,

Frequency Counter Value Delta = (2¹⁶− Frequency 1) +

Frequency 2.

TIME

Where Frequency 2 > Frequency 1,

Figure 46. Continuous Sawtooth Ramp

Frequency Counter Value Delta = Frequency 2 − Frequency 1.

10. Calculate the output frequency using the following formula:

Output Frequency = (Frequency Counter Value Delta/

CLK_DIV) × f_PFD× N_DIV× 2

where:

CLK_DIV= ((CLK₂× 2¹²) + CLK₁).

TIME

f

N

_PFD= f_REF/R_DIV

.

Figure 47. Continuous Triangular Ramp

_DIV= INT value + (FRAC value/(2²⁵)).

WAVEFORM DEVIATIONS AND TIMING

11. Set Register R13 and Register R7 back to the original

settings and enable the ramp function in Register R5 if

required.

TIMER

f_DEV

WAVEFORM GENERATION

The ADF5902 is capable of generating five types of waveforms

in the frequency domain: single ramp burst, single triangular

burst, single sawtooth burst, continuous sawtooth ramp, and

continuous triangular ramp. Figure 43 through Figure 47 show

the types of waveforms available.

TIME

Figure 48. Waveform Timing

The key parameters that define a ramp are



Frequency deviation

Time per step

Number of steps

TIME

Figure 43. Single Ramp Burst

Rev. 0 | Page 34 of 39

Data Sheet

ADF5902

Frequency Deviation

There are numerous ramp shapes available (see the Waveform

Generation section). Depending on the chosen shape, some or

all of the ramp slopes must be programmed. Figure 49 shows

what must be programmed for each shape. The slope being

programmed is controlled by

The frequency deviation for each frequency hop is set by

f

_DEV= (f_PFD/2²⁵) × (DEV × 2^DEV_OFFSET

where:

_PFDis the PFD frequency.

DEV is a 16-bit word (Bits[DB20:DB5] in Register R14).

)

(7)

f



CLK DIV SEL (Register R13, Bits[DB6:DB5]).

DEV SEL (Register R14, Bits[DB26:DB25]).

Step SEL (Register R15, Bits[DB26:DB25]).

DEV_OFFSET is a 4-bit word (Bits[DB24:DB21] in Register R14).

Time per step

Typically, each register must be written multiple times, one time

for each slope.

The time between each frequency hop is set by

Timer = CLK₁× CLK₂× (1/f_PFD

)

(8)

The frequency deviation for each step of a slope is set by

where:

f

_DEV= (f_PFD/2²⁵) × (DEV × 2^DEV_OFFSET

)

CLK₁and CLK₂are the 12-bit clock values (12-bit CLK₁divider in

Register R7 and 12-bit CLK₂divider in Register R13).

where:

f

_DEVis the frequency deviation of a step.

Bits[DB20:DB19] in Register R13 must be set to 11 for ramp

divider.

f

_PFDis the PFD frequency.

DEV is the deviation value (Register R14, Bits[DB20:DB5]).

DEV_OFFSET is the deviation offset (Register R14,

Bits[DB24:DB21]).

f

_PFDis the PFD frequency.

Either CLK₁or CLK₂must be greater than 1, that is, CLK₁=

CLK₂= 1 is not allowed.

The time for each step of a slope is set by

Number of Steps

Timer = CLK₁× CLK₂× (1/f_PFD

where:

Timer is the time per step.

)

A 20-bit step value (Bits[DB24:DB5] in Register R15) defines

the number of frequency hops that take place. The INT value

cannot be incremented by more than 2⁸= 256 from its starting

value.

CLK₁is the CLK₁value (Register R7, Bits[23:12]).

CLK₂is the CLK₂value (Register R13, Bits[18:7]).

RAMP AND MODULATION

CLK₁is common to all slopes.

All ramps are generated according to the scheme shown in

Figure 49. The total ramp is separated into four sections. Each

section consists of a delay section and a slope section. Each

slope is made up of one or more steps. Each step has a

programmed frequency deviation and step time.

The number of steps per slope is programmed in Register R15,

Bits[DB24:DB5].

When programming the registers for a ramp, write the registers

in descending order. Then write to Register R5 to enable the

ramp (Register R5, Bit DB29 = 1) must be last.

Rev. 0 | Page 35 of 39

ADF5902

Data Sheet

DELAY 1

DELAY 3

DELAY 0

DELAY 2

DELAY 0

TIME

SLOPE 3

STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b11

STEP WORD (REG 15, BITS[DB24:DB5]) = X

DEV SELECT (REG 14, BITS[DB26:DB25]) = 0b11

DEV OFFSET (REG 14, BITS[DB24:DB21]) = X

DEV WORD (REG 14, BITS[DB20:DB5]) = –X (NOTE: NEGATIVE)

DELAY 0

CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11

DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b00

RAMP DELAY (REG 16, BITS[DB19]) = 1

DELAY WORD (REG 16, BITS[DB16:DB5]) = X

CLK DIVIDER (REG 13, BITS[DB18:DB7]) = X

2

CLK DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b11

2

DELAY 3

DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b11

RAMP DELAY (REG 16, BITS[DB19]) = 1

SLOPE 0

STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b00

STEP WORD (REG 15, BITS[DB24:DB5]) = X

DELAY WORD (REG 16, BITS[DB16:DB5]) = X

SLOPE 2

STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b10

STEP WORD (REG 15, BITS[DB24:DB5]) = X

DEV SELECT (REG 14, BITS[DB26:DB25]) = 0b00

DEV OFFSET (REG 14, BITS[DB24:DB21]) = X

DEV WORD (REG 14, BITS[DB20:DB5]) = X

DELAY 2

DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b10

RAMP DELAY (REG 16, BITS[DB19]) = 1

DELAY WORD (REG 16, BITS[DB16:DB5]) = X

DEV SELECT (REG 14, BITS[DB22:DB25]) = 0b10

DEV OFFSET (REG 14, BITS[DB24:DB21]) = X

DEV WORD (REG 14, BITS[DB20:DB5]) = X

CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11

CLK2 DIVIDER (REG 13, BITS[DB18:DB7]) = X

CLK2 DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b00

CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11

SLOPE 1

CLK DIVIDER (REG 13, BITS[DB18:DB7]) = X

STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b01

STEP WORD (REG 15, BITS[DB24:DB5]) = X

2

CLK DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b10

2

DEV SELECT (REG 14, BITS[DB26:DB25]) = 0b01

DEV OFFSET (REG 14, BITS[DB24:DB21]) = X

DEV WORD (REG 14, BITS[DB20:DB5]) = –X (NOTE: NEGATIVE)

DELAY 1

DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b01

RAMP DELAY (REG 16, BITS[DB19]) = 1

DELAY WORD (REG 16, BITS[DB16:DB5]) = X

CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11

CLK DIVIDER (REG 13, BITS[DB18:DB7]) = X

2

CLK DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b01

2

NOTES

- ALL DELAYS ARE OPTIONAL.

- SINGLE RAMP BURST:

- DELAY 0 TO DELAY 3 ARE ENABLED BY REG 16, BITS[DB19].

- RAMP MODE (R11BITS[DB8:DB7]) MUST BE SET TO 0b11.

- SLOPE 0 MUST BE PROGRAMMED.

- CONTINUOUS SAWTOOTH RAMP:

- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b00.

- SLOPE 0 AND 2 MUST BE PROGRAMMED (EVEN

IF SLOPE 0 AND SLOPE 2 ARE THE SAME).

- SINGLE TRIANGULAR RAMP:

- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b11.

- SLOPE 0 AND SLOPE 1 MUST BE PROGRAMMED.

- SING FULL TRI (REG 11, BIT[DB9]) = 1.

- CONTINUOUS TRIANGULAR RAMP:

- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b10.

- SLOPE 0, SLOPE 1, SLOPE 2, AND SLOPE 3 MUST BE PROGRAMMED.

- WHEN PROGRAMMING SLOPE 1 OR SLOPE 3, DEV WORD

MUST BE NEGATIVE TO DECREASE THE FREQUENCY.

- SINGLE SAWTOOTH RAMP:

- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b01.

- SLOPE 0 MUST BE PROGRAMMED.

- NEGATIVE VALUES ARE TWOS COMPLEMENT BINARY.

- X = DON’T CARE.

Figure 49. Ramp Sections

Rev. 0 | Page 36 of 39

Data Sheet

ADF5902

Ramp Complete and Ramp-Down Signals to MUXOUT

External Control of Ramp Steps

Figure 50 shows the ramp complete signal on MUXOUT.

The internal ramp clock can be bypassed and each step can be

triggered by a pulse on the TX_DATA pin. This process allows

transparent control of each step. Enable this feature by setting

Bit DB30 in Register R14 to 1.

RF

TIME

OUT

TIME

TX_DATA

TIME

Figure 50. Ramp Complete Signal on MUXOUT

To activate this function, set Bits[DB15:DB12] in Register R3

to 1111, and set Bits[DB19:DB5] in Register R4 to 0x00C0.

Figure 52. External Control of Ramp Steps

Figure 51 shows the ramp-down signal on MUXOUT.

APPLICATION OF THE ADF5902 IN FMCW RADAR

Figure 53 shows the application of the ADF5902 in a frequency

modulated continuous wave (FMCW) radar system.

In the FMCW radar system, the ADF5902 generates the

sawtooth or triangle ramps necessary for this type of radar to

operate.

TIME

The ADF5902 CP_OUTpin controls the V_TUNEpin on the ADF5902

transmitter MMIC and thus the frequency of the VCO and the

transmitter output signal on TX_OUT1 or TX_OUT2. The LO signal

from the ADF5902 is fed to the LO input on the ADF5904.

The ADF5904 downconverts the signal from the four receiver

antennas to baseband with the LO signal from the transmitter

MMIC.

TIME

Figure 51. Ramp-Down Signal on MUXOUT

To activate this function, set Bits[DB15:DB12] in Register R3

to 1111, and set Bits[DB19:DB5] in Register R4 to 0x0100.

The downconverted baseband signals from the four receiver

channels on the ADF5904 are fed to the ADAR7251 4-channel,

continuous time, Σ-Δ ADC.

A digital signal processor (DSP) follows the ADC to handle the

target information processing.

Rev. 0 | Page 37 of 39

ADF5902

Data Sheet

LOOP FILTER

CP

V

TUNE

OUT

TX

1

2

OUT

ADF5902

OUT

LO

OUT

LO_IN

RX1_RF

RX2_RF

RX3_RF

RX4_RF

DSP

ADAR7251

Rx BASEBAND

ADF5904

Figure 53. FMCW Radar with the ADF5902

Rev. 0 | Page 38 of 39

Data Sheet

ADF5902

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

25

32

TIONS

INDIC ATOR AREA OP

(SEE DETAIL A)

24

1

0.50

BSC

3.75

3.60 SQ

3.55

EXPOSED

PAD

17

8

16

9

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5

Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height

(CP-32-12)

ORDERING GUIDE

Model¹

ADF5902WCCPZ

ADF5902WCCPZ-RL7

EV-ADF5902SD1Z

Temperature Range

−40°C to +105°C

Package Description

Package Option

CP-32-12

32-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

¹Z = RoHS Compliant Part.

AUTOMOTIVE PRODUCTS

The ADF5902W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

registered trademarks are the property of their respective owners.

D16746-0-12/18(0)

Rev. 0 | Page 39 of 39


型号：	ADF5902WCCPZ-RL7
厂家：	ADI
描述：	24 GHz, ISM Band, Multichannel FMCW Radar Transmitter ISM频段
文件：	总39页 (文件大小：498K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF5902WCCPZ-RL7 [ADI]

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