ADF7023-JBCPZ-RL_技术文档

High Performance, Low Power, ISM Band

FSK/GFSK/MSK/GMSK Transceiver IC

ADF7023-J

SPORT mode support

FEATURES

High speed synchronous serial interface to Tx and Rx Data

for direct interfacing to processors and DSPs

Packet management support

Highly flexible for a wide range of packet formats

Insertion/detection of preamble/sync word/CRC/address

Manchester and 8b/10b data encoding and decoding

Data whitening

Smart wake mode

Current saving low power mode with autonomous receiver

wake up, carrier sense, and packet reception

Downloadable firmware modules

Image rejection calibration, fully automated (patent

pending)

128-bit AES encryption/decryption with hardware

acceleration and key sizes of 128 bits, 192 bits, and

256 bits

Ultralow power, high performance transceiver

Frequency bands: 902 MHz to 958 MHz

Data rates supported: 1 kbps to 300 kbps

2.2 V to 3.6 V power supply

Single-ended and differential power amplifiers (PAs)

Low IF receiver with programmable IF bandwidths

100 kHz, 150 kHz, 200 kHz, 300 kHz

Receiver sensitivity (BER)

−116 dBm at 1.0 kbps, 2FSK, GFSK

−107.5 dBm at 38.4 kbps, 2FSK, GFSK

−106.5 dBm at 50 kbps, 2FSK, GFSK

−105 dBm at 100 kbps, 2FSK, GFSK

−104 dBm at 150 kbps, GFSK, GMSK

−103 dBm at 200 kbps, GFSK, GMSK

−100.5 dBm at 300 kbps, GFSK, GMSK

Very low power consumption

Reed-Solomon error correction with hardware acceleration

240-byte packet buffer for Tx/Rx data

Efficient SPI control interface with block read/write access

Integrated battery alarm and temperature sensor

Integrated RC and 32.768 kHz crystal oscillator

On-chip, 8-bit ADC

12.8 mA in PHY_RX mode (maximum front-end gain)

11.9 mA in PHY_RX mode (AGC off, ADC off)

24.1 mA in PHY_TX mode (10 dBm output, single-ended PA)

0.75 μA in PHY_SLEEP mode (32 kHz RC oscillator active)

1.28 μA in PHY_SLEEP mode (32 kHz XTAL oscillator active)

0.33 μA in PHY_SLEEP mode (Deep Sleep Mode 1)

RF output power of −20 dBm to +13.5 dBm (single-ended PA)

RF output power of −20 dBm to +10 dBm (differential PA)

Patented fast settling automatic frequency control (AFC)

Digital received signal strength indication (RSSI)

Integrated PLL loop filter and Tx/Rx switch

Fast automatic voltage controlled oscillator (VCO) calibration

Automatic synthesizer bandwidth optimization

On-chip, low power, custom 8-bit processor

Radio control

5 mm × 5 mm, 32-lead, LFCSP package

APPLICATIONS

Smart metering

IEEE 802.15.4g

Home automation

Process and building control

Wireless sensor networks (WSNs)

Wireless healthcare

Packet management

Smart wake mode

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADF7023-J

TABLE OF CONTENTS

Features .............................................................................................. 1

Interrupts in Sport Mode .......................................................... 46

ADF7023-J Memory Map ............................................................. 47

BBRAM........................................................................................ 47

Modem Configuration RAM (MCR) ...................................... 47

Program ROM ............................................................................ 47

Program RAM ............................................................................ 47

Packet RAM ................................................................................ 48

SPI Interface .................................................................................... 49

General Characteristics ............................................................. 49

Command Access....................................................................... 49

Status Word ................................................................................. 49

Command Queuing ................................................................... 50

Memory Access........................................................................... 51

Low Power Modes .......................................................................... 54

Example Low Power Modes...................................................... 57

Low Power Mode Timing Diagrams........................................ 59

WUC Setup ................................................................................. 60

Firmware Timer Setup............................................................... 61

Downloadable Firmware Modules............................................... 62

Writing a Module to Program RAM........................................ 62

Image Rejection Calibration Module ...................................... 62

AES Encryption and Decryption Module............................... 62

Reed-Solomon Coding Module ............................................... 62

Radio Blocks.................................................................................... 64

Frequency Synthesizer............................................................... 64

Crystal Oscillator........................................................................ 65

Modulation.................................................................................. 65

RF Output Stage.......................................................................... 66

PA/LNA Interface....................................................................... 66

Receive Channel Filter............................................................... 66

Image Channel Rejection .......................................................... 66

Automatic Gain Control (AGC)............................................... 66

RSSI .............................................................................................. 67

2FSK/GFSK/MSK/GMSK Demodulation............................... 69

Clock Recovery........................................................................... 71

Applications....................................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

General Description......................................................................... 4

Specifications..................................................................................... 6

RF and Synthesizer Specifications.............................................. 6

Transmitter Specifications........................................................... 7

Receiver Specifications ................................................................ 9

Timing and Digital Specifications............................................ 12

Auxilary Block Specifications ................................................... 13

General Specifications ............................................................... 14

Timing Specifications ................................................................ 15

Absolute Maximum Ratings.......................................................... 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 19

Terminology .................................................................................... 26

Radio Control.................................................................................. 27

Radio States ................................................................................. 27

Initialization ................................................................................ 29

Commands .................................................................................. 30

Automatic State Transitions ...................................................... 32

State Transition and Command Timing.................................. 33

Sport Mode...................................................................................... 35

Packet Structure in Sport Mode ............................................... 35

Sport Mode in Transmit ............................................................ 35

Sport Mode in Receive............................................................... 35

Transmit Bit Latencies in Sport Mode..................................... 35

Packet Mode .................................................................................... 38

Preamble ...................................................................................... 38

Sync Word ................................................................................... 39

Payload......................................................................................... 40

CRC .............................................................................................. 41

Postamble..................................................................................... 42

Transmit Packet Timing ............................................................ 42

Data Whitening .......................................................................... 43

Manchester Encoding ................................................................ 43

8b/10b Encoding ........................................................................ 43

Interrupt Generation...................................................................... 44

Recommended Receiver Settings for

2FSK/GFSK/MSK/GMSK ......................................................... 71

Peripheral Features......................................................................... 73

Analog-to-Digital Converter .................................................... 73

Temperature Sensor ................................................................... 73

Rev. 0 | Page 2 of 100

ADF7023-J

Test DAC ......................................................................................73

Transmit Test Modes ..................................................................73

Silicon Revision Readback.........................................................73

Applications Information...............................................................74

Application Circuit .....................................................................74

Host Processor Interface ............................................................74

PA/LNA Matching ......................................................................75

Command Reference ......................................................................77

Register Maps ..................................................................................78

BBRAM Register Description ...................................................80

MCR Register Description.........................................................90

Packet RAM Register Description............................................97

Outline Dimensions........................................................................98

Ordering Guide ...........................................................................98

REVISION HISTORY

5/11—Revision 0: Initial Version

Rev. 0 | Page 3 of 100

ADF7023-J

FUNCTIONAL BLOCK DIAGRAM

ADCIN_ATB3

IRQ

IRQ_GP3

4kB ROM

MAC

FSK

ASK

CTRL

LNA

DEMOD

RFIO_1P

RSSI/

LOGAMP

CS

8-BIT RISC

PROCESSOR

8-BIT

ADC

2kB RAM

RFIO_1N

MISO

SCLK

MOSI

CDR

AFC

AGC

SPI

256 BYTE

PACKET

RAM

PA

64 BYTE

BBRAM

26MHz OSC

LOOP

FILTER

CHARGE

PUMP

GPIO

DIVIDER

PA

RFO2

PFD

256 BYTE

MCR RAM

TEST

DAC

1

DIVIDER

GPIO

f_DEV

PA RAMP

PROFILE

WAKE-UP CONTROL

TIMER UNIT

GAUSSIAN

FILTER

CLOCK

DIVIDER

Σ-∆

MODULATOR

ADF7023-J

ANALOG

TEST

TEMP

SENSOR

BATTERY

MONITOR

32kHz

OSC

32kHz

RCOSC

26MHz

OSC

BIAS

CREGRFx CREGVCO CREGSYNTH CREGDIGx RBIAS

GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27.

XOSC32KN_ATB2 XOSC32KP_GP5_ATB1 XOSC26N XOSC26P

1

Figure 1.

GENERAL DESCRIPTION

The ADF7023-J is a very low power, high performance, highly

integrated 2FSK/GFSK/MSK/GMSK transceiver designed for

operation in the 902 MHz to 958 MHz frequency band, which

covers the ARIB Standard T96 band at 950 MHz. Data rates

from 1 kbps to 300 kbps are supported.

calibration can be stored in nonvolatile memory for use on

subsequent power-ups of the transceiver.

The ADF7023-J operates with a power supply range of 2.2 V to

3.6 V and has very low power consumption in both Tx and Rx

modes, enabling long lifetimes in battery-operated systems while

maintaining excellent RF performance. The device can enter a

low power sleep mode in which the configuration settings are

retained in the battery backup random access memory (BBRAM).

The transmit RF synthesizer contains a VCO and a low noise

fractional-N phase locked loop (PLL) with an output channel

frequency resolution of 400 Hz. The VCO operates at twice the

fundamental frequency to reduce spurious emissions. The receive

and transmit synthesizer bandwidths are automatically, and

independently, configured to achieve optimum phase noise,

modulation quality, and settling time. The transmitter output

power is programmable from −20 dBm to +13.5 dBm, with

automatic PA ramping to meet transient spurious specifications.

The part possesses both single-ended and differential PAs, which

allow for Tx antenna diversity.

The ADF7023-J features an ultralow power, on-chip,

communications processor. The communications processor,

which is an 8-bit RISC processor, performs the radio control,

packet management, and smart wake mode (SWM) functionality.

The communications processor eases the processing burden of

the companion processor by integrating the lower layers of a

typical communication protocol stack. The communications

processor also permits the download and execution of firmware

modules. Available modules include image rejection (IR)

calibration, advanced encryption standard (AES) encryption,

and Reed-Solomon coding. These firmware modules are included

in the Applications Software, which is available online at

ftp://ftp.analog.com/pub/RFL/ADF7023/.

The receiver is exceptionally linear, achieving an IP3 specification

of −12.2 dBm and −11.5 dBm at maximum gain and minimum

gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm

at maximum gain and minimum gain, respectively. The receiver

achieves an interference blocking specification of 66 dB at a

2 MHz offset and 74 dB at a 10 MHz offset. Thus, the part

is extremely resilient to the presence of interferers in spectrally

noisy environments. The receiver features a novel, high speed,

AFC loop, allowing the PLL to find and correct any RF frequency

errors in the recovered packet. A patent pending image rejection

calibration scheme is available by downloading the image rejection

calibration firmware module to program RAM. The algorithm

does not require the use of an external RF source nor does it

require any user intervention once initiated. The results of the

The communications processor provides a simple command-based

radio control interface for the host processor. A single-byte command

transitions the radio between states or performs a radio function.

The communications processor provides support for generic

packet formats. The packet format is highly flexible and fully

programmable, thereby ensuring its compatibility with proprietary

packet profiles. In transmit mode, the communications processor

can be configured to add preamble, sync word, and CRC to the

Rev. 0 | Page 4 of 100

ADF7023-J

payload data stored in packet RAM. In receive mode, the

communications processor can detect and interrupt the host

processor on reception of preamble, sync word, address, and CRC

and store the received payload to packet RAM. The ADF7023-J

uses an efficient interrupt system comprising MAC level interrupts

and PHY level interrupts that can be individually set. The payload

data plus the 16-bit CRC can be encoded/decoded using

Manchester or 8b/10b encoding. Alternatively, data whitening

and dewhitening can be applied.

also be triggered by the host processor. For systems requiring

very accurate wake-up timing, a 32 kHz oscillator can be used

to drive the wake-up timer. Alternatively, the internal RC oscillator

can be used, which gives lower current consumption in sleep.

The ADF7023-J features an AES engine with hardware

acceleration that provides 128-bit block encryption and

decryption with key sizes of 128 bits, 192 bits, and 256 bits.

Both electronic code book (ECB) and Cipher Block Chaining

Mode 1 (CBC Mode 1) are supported. The AES engine can be

used to encrypt/decrypt packet data and can be used as a stand-

alone engine for encryption/decryption by the host processor.

The AES engine is enabled on the ADF7023-J by downloading

the AES firmware module to program RAM.

The SWM allows the ADF7023-J to wake up autonomously from

sleep using the internal wake-up timer without intervention from

the host processor. After wake-up, the ADF7023-J is controlled

by the communications processor. This functionality allows

carrier sense, packet sniffing, and packet reception while the

host processor is in sleep, thereby reducing overall system current

consumption. The smart wake mode can wake the host processor

on an interrupt condition. These interrupt conditions can be

configured to include the reception of valid preamble, sync

word, CRC, or address match. Wake-up from sleep mode can

An on-chip, 8-bit ADC provides readback of an external analog

input, the RSSI signal, or an integrated temperature sensor. An

integrated battery voltage monitor raises an interrupt flag to the

host processor whenever the battery voltage drops below a user-

defined threshold.

Rev. 0 | Page 5 of 100

ADF7023-J

SPECIFICATIONS

V_DD= VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, GND = 0 V, T_A= T_MINto T_MAX, unless otherwise noted. Typical specifications are at

V_DD= 3 V and T_A= 25°C.

RF AND SYNTHESIZER SPECIFICATIONS

Table 1.

Parameter

Min Typ

Max Unit

Test Conditions/Comments

RF CHARACTERISTICS

Frequency Range

PHASE-LOCKED LOOP

Channel Frequency Resolution

Phase Noise at Offset of

600 kHz

800 kHz

600 kHz

800 kHz

1 MHz

2 MHz

10 MHz

VCO Calibration Time

Synthesizer Settling Time

902

958

MHz

Hz

396.7

PA output power = 10 dBm, RF frequency = 950 MHz

−116.3

−119.4

−113.8

−117.2

−126

−131

−142

142

dBc/Hz 130 kHz closed-loop bandwidth¹

dBc/Hz 130 kHz closed-loop bandwidth

dBc/Hz 223 kHz closed-loop bandwidth²

dBc/Hz 223 kHz closed-loop bandwidth

dBc/Hz

μs

56

μs

Frequency synthesizer settles to within 5 ppm of the target

frequency within this time following the VCO calibration,

transmit, and receive, 2FSK/GFSK/MSK/GMSK

Integer Boundary Spurious³

(26 MHz × N) + 0.1 MHz

N = 35 or 36

−39

−79

dBc

Using 130 kHz synthesizer bandwidth, integer boundary spur at

910 MHz (26 MHz × 35), inside synthesizer loop bandwidth

Using 130 kHz synthesizer bandwidth, integer boundary spur at

910 MHz (26 MHz × 35), outside synthesizer loop bandwidth

(26 MHz × N) + 1.0 MHz

CRYSTAL OSCILLATOR

Crystal Frequency

Recommended Load Capacitance

Maximum Crystal ESR

Pin Capacitance

26

MHz

pF

Ω

pF

μs

Parallel load resonant crystal

7

18

1800

2.1

310

388

26 MHz crystal with 18 pF load capacitance

Capacitance for XOSC26P and XOSC26N

26 MHz crystal with 7 pF load capacitance

26 MHz crystal with 18 pF load capacitance

Start-Up Time

μs

¹130 kHz closed-loop bandwidth recommended for T96/15.4 g, 50 kbps and 100 kbps data rates (see Table 31).

²223 kHz closed-loop bandwidth recommended for T96/15.4 g, 200 kbps data rate (see Table 31).

³As the 26 MHz XTAL is fixed, integer boundary spurs occur at 910 MHz and 936 MHz (N = 35 and N = 36).

Rev. 0 | Page 6 of 100

ADF7023-J

TRANSMITTER SPECIFICATIONS

Table 2.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

DATA RATE

2FSK/GFSK/MSK/GMSK

Data Rate Resolution

MODULATION ERROR RATIO (MER)¹

10 kbps to 49.5 kbps

49.6 kbps to 129.5 kbps

129.6 kbps to 179.1 kbps

179.2 kbps to 239.9 kbps

240 kbps to 300 kbps

MODULATION ERROR RATIO 15.4 g DATA RATES

50 kbps

1

300

kbps

bps

100

RF frequency = 957.2 MHz, GFSK

Modulation index = 1

Modulation index = 0.5

With T96 look-up table (LUT)²

Modulation index = 1

25.4

25.3

23.9

23.3

23

dB

25.4

28.9

25.9

24.3

dB

100 kbps

200 kbps

100 kbps

Modulation index = 1

Modulation index = 0.5

MODULATION

2FSK/GFSK/MSK/GMSK Frequency Deviation 0.1

Deviation Frequency Resolution

Gaussian Filter Bandwidth-Time (BT) Product

SINGLE-ENDED PA

409.5 kHz

Hz

100

0.5

Maximum Power³

13.5

dBm

Programmable, separate PA and LNA

match⁴

Minimum Power

Transmit Power Variation vs. Temperature

−20

0.5

dBm

dB

From −40°C to +85°C, RF frequency =

958.0 MHz

Transmit Power Variation vs. V_DD

Transmit Power Flatness

1

dB

From 2.2 V to 3.6 V, RF frequency = 958.0 MHz

From 902 MHz to 928 MHz and 950 MHz to

958 MHz

Programmable Step Size

−20 dBm to +13.5 dBm

DIFFERENTIAL PA

0.5

dB

Programmable in 63 steps

Programmable

Maximum Power³

10

−20

1

dBm

dB

Minimum Power

Transmit Power Variation vs. Temperature

From −40°C to +85°C, RF frequency =

958.0 MHz

Transmit Power Variation vs. V_DD

Transmit Power Flatness

2

1

dB

From 2.2 V to 3.6 V, RF frequency = 958.0 MHz

From 902 MHz to 928 MHz and 950 MHz to

958 MHz

Programmable Step Size

−20 dBm to +10 dBm

0.5

dB

Programmable in 63 steps

Rev. 0 | Page 7 of 100

ADF7023-J

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

SPURIOUS EMISSIONS

Measured as per TELEC T-245 for T96

compliance, 950 MHz to 958 MHz band,

single-ended PA with combined output. For

spurious emissions compliance in the

1.8845 GHz to 1.9196 GHz frequency band,

a seventh-order PA harmonic filter is used.

This has an insertion loss of up to 1.5 dB.

30 MHz to 710 MHz

710 MHz to 945 MHz

945 MHz to 950 MHz

958 MHz to 960 MHz

960 MHz to 1 GHz

−65

−63

−66

dBm/100 kHz

dBm/1 MHz

dBm/100 kHz

−60.7

dBm/100 kHz DR = 100 kbps, MI = 1, n = 2, f_C= 957.3 MHz

−64

−72

−76

−69

−66

−69

dBm/100 kHz

dBm/1 MHz

1 GHz to 1.215 GHz

1.215 GHz to 1.8845 GHz

1.8845 GHz to 1.9196 GHz⁵

1.9196 GHz to 3 GHz

3 GHz to 5 GHz

OPTIMUM PA LOAD IMPEDANCE

Single-Ended PA in Transmit Mode

f_RF= 915 MHz

50.8 + j10.2

38.5 + j5.9

Ω

f_RF= 954MHz

Single-Ended PA in Receive Mode

f_RF= 915 MHz

f_RF= 954 MHz

PA Impedance in Rx mode

9.4 − j124

8.8 − j118.5

Ω

Differential PA in Transmit Mode

Load impedance between RFIO_1P and

RFIO_1N to ensure maximum output power

f_RF= 915 MHz

f_RF= 954 MHz

20.5 + j36.4

28.1 + j17.3

Ω

¹MER is a measure of signal to noise ratio at optimal eye sampling point.

²Optimized PLL bandwidth settings vs. data rate defined in Table 31.

³Measured as the maximum unmodulated power.

⁴A combined single-ended PA and LNA match can reduce the maximum achievable output power by up to 1 dB.

⁵This includes the second harmonic.

Rev. 0 | Page 8 of 100

ADF7023-J

RECEIVER SPECIFICATIONS

Table 3.

Parameter

Min Typ

Max Unit Test Conditions/Comments

2FSK/MSK INPUT SENSITIVITY, BIT ERROR RATE (BER)

At BER = 1E − 3, RF frequency = 915 MHz,

LNA and PA matched separately¹

1.0 kbps

−116

−111

dBm Frequency deviation = 4.8 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 9.6 kHz,

IF filter bandwidth = 100 kHz

10 kbps

38.4 kbps

−107.5

dBm Frequency deviation = 20 kHz,

IF filter bandwidth = 100 kHz

50 kbps

−106.5

−105

dBm Frequency deviation = 12.5 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 25 kHz,

IF filter bandwidth = 100 kHz

100 kbps

150 kbps

−104

dBm Frequency deviation = 37.5 kHz,

IF filter bandwidth = 150 kHz

200 kbps

−103

dBm Frequency deviation = 50 kHz,

IF filter bandwidth = 200 kHz

300 kbps

−100.5

dBm Frequency deviation = 75 kHz,

IF filter bandwidth = 300 kHz

GFSK/GMSK INPUT SENSITIVITY, BER

At BER = 1E − 3, RF frequency = 954 MHz,

LNA and PA matched separately¹

50 kbps

−107.4

−105

dBm Frequency deviation = 25 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 50 kHz,

IF filter bandwidth = 100 kHz

100 kbps

−106

dBm Frequency deviation = 40 kHz,

IF filter bandwidth = 100 kHz

200 kbps

−102

dBm Frequency deviation = 100 kHz,

IF filter bandwidth = 200 kHz

200 kbps

−103.3

dBm Frequency deviation = 80 kHz,

IF filter bandwidth = 200 kHz

2FSK/MSK INPUT SENSITIVITY, PACKET ERROR RATE (PER)

At PER = 1%, RF frequency = 915 MHz,

LNA and PA matched separately,²

packet length = 128 bits, packet mode

1.0 kbps

9.6 kbps

38.4 kbps

50 kbps

−115.5

−110.6

−106

dBm Frequency deviation = 4.8 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 9.6 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 20 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 12.5 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 25 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 37.5 kHz,

IF filter bandwidth = 150 kHz

dBm Frequency deviation = 50 kHz,

IF filter bandwidth = 200 kHz

dBm Frequency deviation = 75 kHz,

IF filter bandwidth = 300 kHz

−104.3

−102.6

−101

100 kbps

150 kbps

200 kbps

300 kbps

−99.1

−97.9

Rev. 0 | Page 9 of 100

ADF7023-J

Parameter

Min Typ

Max Unit Test Conditions/Comments

GFSK/GMSK INPUT SENSITIVITY, PER

At PER = 1%, RF frequency = 954 MHz,

LNA and PA matched separately,

packet length = 20 octets, packet mode

50 kbps

−104.1

dBm Frequency deviation = 25 kHz,

IF filter bandwidth = 100 kHz

100 kbps

−101.1

−102.2

−98.5

dBm Frequency deviation = 50 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 40 kHz,

IF filter bandwidth = 100 kHz

dBm Frequency deviation = 100 kHz,

IF filter bandwidth = 200 kHz

100 kbps

200 kbps

−99.5

dBm Frequency deviation = 80 kHz,

IF filter bandwidth = 200 kHz

LNA AND MIXER, INPUT IP3

Receiver LO frequency (f_LO) = 914.8 MHz,

f

_SOURCE1= f_LO+ 0.4 MHz, f_SOURCE2= f_LO+ 0.7 MHz

Minimum LNA Gain

Maximum LNA Gain

−11.5

−12.2

dBm

LNA AND MIXER, INPUT IP2

Receiver LO frequency (f_LO) = 920.8 MHz,

_SOURCE1= f_LO+ 1.1 MHz, f_SOURCE2= f_LO+ 1.3 MHz

f

Maximum LNA Gain, Maximum Mixer Gain

Minimum LNA Gain, Minimum Mixer Gain

LNA AND MIXER, 1 dB COMPRESSION POINT

Maximum LNA Gain, Maximum Mixer Gain

Minimum LNA Gain, Minimum Mixer Gain

ADJACENT CHANNEL REJECTION

18.5

27

dBm

RF frequency = 915 MHz

−21.9

−21

dBm

CW Interferer

Desired signal at −87 dBm, CW interferer

power level increased until BER = 62⁻⁶,

image calibrated

200 kHz Offset

38

dB

IF BW = 100 kHz, wanted signal:

f_DEV= 25 kHz, DR = 50 kbps

+400 kHz Offset

−400 kHz Offset

51

33/39

dB

Uncalibrated/internal calibration; using an

IF of 200 kHz, −400 kHz is the image frequency

CO-CHANNEL REJECTION

−6

dB

Desired signal at −87 dBm,

data rate = 50 kbps,

frequency deviation = 25 kHz,

RF frequency = 954 MHz

BLOCKING

RF Frequency = 954 MHz

Desired signal 3 dB above the input

sensitivity level, data rate = 50 kbps,

CW interferer power level increased until

BER = 10⁻³(see the Typical Performance

Characteristics section for blocking at other

offsets and IF bandwidths), image calibrated

2 MHz

10 MHz

60 MHz

65

72

76

dB

IMAGE CHANNEL ATTENUATION

Measured as image attenuation at the

IF filter output, carrier wave interferer at

400 kHz below the channel frequency,

100 kHz IF filter bandwidth

954 MHz

36/43.8

dB

Uncalibrated/calibrated

Rev. 0 | Page 10 of 100

ADF7023-J

Parameter

AFC

Min Typ

Max Unit Test Conditions/Comments

Accuracy

1

kHz

Maximum Pull-In Range

Achievable pull-in range dependent on

discriminator bandwidth and modulation

300 kHz IF Filter Bandwidth

200 kHz IF Filter Bandwidth

150 kHz IF Filter Bandwidth

100 kHz IF Filter Bandwidth

PREAMBLE LENGTH

150

100

75

kHz

50

Minimum number of preamble bits to

ensure the minimum PER across the full

input power range (see Table 41)

AFC Off, AGC Lock on Sync Word Detection

38.4 kbps

300 kbps

Sync word length 24 bits

Sync word tolerance = 0

Sync word tolerance = 1

8

24

Bits

AFC On, AFC and AGC Lock on Preamble Detection

9.6 kbps

38.4 kbps

50 kbps

100 kbps

150 kbps

200 kbps

300 kbps

46

44

50

52

54

58

64

Bits

AFC On, AFC and AGC Lock on Sync Word Detection

38.4 kbps

300 kbps

Sync word length 24 bits

Sync word tolerance = 0

Sync word tolerance = 1

14

32

Bits

RSSI

Range at Input

Linearity

−97 to −26

2

3

dBm

dB

Absolute Accuracy

SATURATION (MAXIMUM INPUT LEVEL)

2FSK/GFSK/MSK/GMSK

LNA INPUT IMPEDANCE

Receive Mode

12

dBm

f_RF= 915 MHz

75.9 −

j32.3

74.6 −

j32.5

Ω

f_RF= 954 MHz

Transmit Mode

f_RF= 915 MHz

f_RF= 954 MHz

7.7 + j8.6

7.7 + j8.9

Ω

Rx SPURIOUS EMISSIONS²

Maximum < 1 GHz

Maximum > 1 GHz

−66

−62

dBm At antenna input, unfiltered conductive

¹Sensitivity for combined matching network case is typically 1 dB less than separate matching networks.

²Follow the matching and layout guidelines to achieve the relevant ARIB-T96/TELEC T-245 specifications.

Rev. 0 | Page 11 of 100

ADF7023-J-J

TIMING AND DIGITAL SPECIFICATIONS

Table 4.

Parameter

Min

Typ Max

Unit Test Conditions/Comments

Rx AND Tx TIMING PARAMETERS

See the State Transition and Command

Timing section for more details

PHY_ON to PHY_RX (on CMD_PHY_RX)

PHY_ON to PHY_TX (on CMD_PHY_TX)

300

296

μs

Includes VCO calibration and synthesizer

settling

Includes VCO calibration and synthesizer

settling, does not include PA ramp-up

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_INH/I_INL

Input Capacitance, C_IN

LOGIC OUTPUTS

0.7 × V_DD

V

μA

pF

0.2 × V _DD

1

10

Output High Voltage, V_OH

Output Low Voltage, V_OL

GPIO Rise/Fall

GPIO Load

Maximum Output Current

ATB OUTPUTS

V_DD− 0.4

V

ns

pF

mA

I_OH= 500 μA

I_OL= 500 μA

0.4

5

10

5

Used for external PA and LNA control

ADCIN_ATB3 and ATB4

Output High Voltage, V_OH

Output Low Voltage, V_OL

Maximum Output Current

XOSC32KP_GP5_ATB1 and XOSC32KN_ATB2

Output High Voltage, V_OH

Output Low Voltage, V_OL

Maximum Output Current

1.8

0.1

0.5

V

mA

V_DD

0.1

5

V

mA

Rev. 0 | Page 12 of 100

ADF7023-J

AUXILARY BLOCK SPECIFICATIONS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

32 kHz RC OSCILLATOR

Frequency

Frequency Accuracy

Frequency Drift

32.768

1.5

kHz

%

After calibration

After calibration at 25°C

Temperature Coefficient

Voltage Coefficient

Calibration Time

32 kHz XTAL OSCILLATOR

Frequency

0.14

4

1

%/°C

%/V

ms

32.768

630

kHz

ms

Start-Up Time

32.768 kHz crystal with 7 pF load capacitance

WAKE UP CONTROLLER (WUC)

Hardware Timer

Wake-Up Period

Firmware Timer

61 × 10⁻⁶

1

1.31 × 10⁵

2¹⁶

sec

Wake-Up Period

Hardware Firmware counter counts of the number of

periods

hardware wake-ups, resolution of 16 bits

ADC

Resolution

DNL

INL

8

Bits

LSB

μs

1

From 2.2 V to 3.6 V, T_A= 25°C

Conversion Time

Input Capacitance

BATTERY MONITOR

Absolute Accuracy

Alarm Voltage Setpoint

Alarm Voltage Step Size

Start-Up Time

Current Consumption

TEMPERATURE SENSOR

Range

1

12.4

pF

45

62

mV

V

mV

μs

1.7

2.7

5-bit resolution

When enabled

100

30

μA

−40

+85

°C

Resolution

0.3

With averaging

Accuracy of Single Temperature

Readback

+7/−4

°C

Overtemperature range −40°C to +85°C

(calibrated at +25°C)

Overtemperature range −36°C to +84°C

(calibrated at +25°C)

Overtemperature range −12°C to +79°C

(calibrated at +25°C)

4

3

Rev. 0 | Page 13 of 100

ADF7023-J

GENERAL SPECIFICATIONS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TEMPERATURE RANGE, T_A

VOLTAGE SUPPLY

V_DD

−40

+85

°C

2.2

3.6

V

Applied to VDDBAT1 and VDDBAT2

TRANSMIT CURRENT CONSUMPTION

In the PHY_TX state, single-ended PA matched to 50 Ω,

differential PA matched to 100 Ω, separate single-ended PA

and LNA match, combined differential PA and LNA match

Single-Ended PA, 915 MHz

−10 dBm

0 dBm

10 dBm

10.3

13.3

24.1

32.1

mA

13.5 dBm

Differential PA, 915 MHz

−10 dBm

0 dBm

5 dBm

10 dBm

9.3

12

16.7

28

mA

POWER MODES

PHY_SLEEP (Deep Sleep Mode 2)

0.18

0.33

0.75

1.28

1

μA

mA

Sleep mode, wake-up configuration values (BBRAM) not

retained

Sleep mode, wake-up configuration values (BBRAM)

retained

WUC active, RC oscillator running, wake-up configuration

values retained (BBRAM)

WUC active, 32 kHz crystal running, wake-up configuration

values retained (BBRAM)

Device in PHY_OFF state, 26 MHz oscillator running, digital

and synthesizer regulators active, all register values retained

Device in PHY_ON state, 26 MHz oscillator running, digital,

synthesizer, VCO, and RF regulators active, baseband filter

calibration performed, all register values retained

PHY_SLEEP (Deep Sleep Mode 1)

PHY_SLEEP (RCO Wake Mode)

PHY_SLEEP (XTO Wake Mode)

PHY_OFF

PHY_ON

1

PHY_RX (ADC, AGC Off)

PHY_RX (ADC, AGC On)

SMART WAKE MODE

11.9

12.8

mA

Device in PHY_Rx state, ADC off, manual AGC gain

Device in PHY_RX state

Average current consumption

21.78

11.75

μA

Autonomous reception every 1 sec, with receive dwell

time of 1.25 ms, using RC oscillator, data rate = 38.4 kbps

Autonomous reception every 1 sec, with receive dwell

time of 0.5 ms, using RC oscillator, data rate = 300 kbps

Rev. 0 | Page 14 of 100

ADF7023-J

TIMING SPECIFICATIONS

V_DD= VDDBAT1 = VDDBAT2 = 3 V 10ꢀ, V_GND= GND = 0 V, T_A= T_MINto T_MAX, unless otherwise noted.

Table 7. SPI Interface Timing

Parameter

Limit

Unit

Test Conditions/Comments

CS falling edge to MISO setup time (TRX active)

CS low to SCLK setup time

SCLK high time

SCLK low time

SCLK period

SCLK falling edge to MISO delay

MOSI to SCLK rising edge setup time

MOSI to SCLK rising edge hold time

SCLK falling edge to CS hold time

CS high time

t₁

15

ns max

ns min

ns max

ns min

μs typ

ns max

t₂

85

t₃

t₄

t₅

t₆

t₇

t₈

t₉

85

170

10

5

85

t₁₁

t₁₂

t₁₃

t₁₄

270

310

20

CS low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, T_A= 25°C

SCLK rise time

SCLK fall time

20

Timing Diagrams

CS

t₁₁

t₂

t₃t₄

t₅

t₁₃

t₁₄

t₉

SCLK

t₁

t₆

MISO

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 7

BIT 0

X

BIT 7

t₈

t₇

MOSI

7

6

5

4

3

2

1

0

7

Figure 2. SPI Interface Timing

CS

t₉

7

6

5

4

3

2

1

0

SCLK

t₁₂

t₆

t₁

MISO

X

SPI STATE

SLEEP

WAKE UP

SPI READY

CS

Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready T12 After Falling Edge of

)

Rev. 0 | Page 15 of 100

ADF7023-J

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted. Connect the exposed paddle

of the LFCSP package to ground.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 8.

Parameter

Rating

VDDBAT1, VDDBAT2 to GND

Operating Temperature Range

Industrial

Storage Temperature Range

Maximum Junction Temperature

LFCSP θ_JAThermal Impedance

Reflow Soldering

−0.3 V to +3.96 V

−40°C to +85°C

−65°C to +125°C

150°C

This device is a high performance, RF integrated circuit with an

ESD rating of <2 kV; it is ESD sensitive. Take proper precautions

for handling and assembly.

26°C/W

Peak Temperature

Time at Peak Temperature

260°C

40 sec

ESD CAUTION

Rev. 0 | Page 16 of 100

ADF7023-J

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CREGRF1

RBIAS

CREGRF2

RFIO_1P

RFIO_1N

RFO2

1

2

3

4

5

6

7

8

24 CS

23

22 SCLK

21 MISO

MOSI

ADF7023-J

TOP VIEW

(Not to Scale)

20

19

18

IRQ_GP3

GP2

GP1

EPAD

VDDBAT2

NC

17 GP0

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT EXPOSED PAD TO GND.

Figure 4. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CREGRF1

Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

2

3

RBIAS

CREGRF2

External Bias Resistor. A 36 kΩ resistor with 2% tolerance should be used.

Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

4

5

6

7

RFIO_1P

RFIO_1N

RFO2

LNA Positive Input in Receive Mode. PA positive output in transmit mode with differential PA.

LNA Negative Input in Receive Mode. PA negative output in transmit mode with differential PA.

Single-Ended PA Output.

Power Supply Pin Two. Decoupling capacitors to the ground plane should be placed as close as

possible to this pin.

VDDBAT2

8

9

NC

CREGVCO

No Connect.

Regulator Voltage for the VCO. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

10

11

VCOGUARD

CREGSYNTH

Guard/Screen for VCO. This pin should be connected to Pin 9.

Regulator Voltage for the Synthesizer. A 220 nF capacitor should be placed between this pin and

ground for regulator stability and noise rejection.

12

CWAKEUP

External Capacitor for Wake-Up Control. A 150 nF capacitor should be placed between this pin and

ground.

13

14

15

XOSC26P

XOSC26N

DGUARD

The 26 MHz reference crystal should be connected between this pin and XOSC26N.

The 26 MHz reference crystal should be connected between this pin and XOSC26P.

Internal Guard/Screen for the Digital Circuitry. A 220 nF capacitor should be placed between this pin

and ground.

16

CREGDIG1

Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this

pin and ground for regulator stability and noise rejection. This can be achieved by shorting it to

Pin 15 and sharing the capacitor to ground.

17

18

19

20

GP0

GP1

GP2

IRQ_GP3

Digital GPIO Pin 0.

Digital GPIO Pin 1.

Digital GPIO Pin 2.

Interrupt Request, Digital GPIO Test Pin 3. An RC filter should be placed between this pin and the

host processor. Recommended values are R = 1.1 kΩ and C = 1.5 nF.

Rev. 0 | Page 17 of 100

ADF7023-J

Pin No.

21

22

23

24

Mnemonic

Description

MISO

SCLK

MOSI

CS

Serial Port Master In/Slave Out.

Serial Port Clock.

Serial Port Master Out/Slave In.

Chip Select (Active Low). A pull-up resistor of 100 kΩ to V_DDis recommended to prevent the host

processor from inadvertently waking the ADF7023-J from sleep.

25

26

GP4

CREGDIG2

Digital GPIO Test Pin 4.

Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this

pin and ground for regulator stability and noise rejection.

27

28

29

30

XOSC32KP_GP5_ATB1

XOSC32KN_ATB2

VDDBAT1

Digital GPIO Test Pin 5. A 32 kHz watch crystal can be connected between this pin and

XOSC32KN_ATB2. Analog Test Pin 1.

A 32 kHz watch crystal can be connected between this pin and XOSC32KP_GP5_ATB1. Analog Test

Pin 2.

Digital Power Supply Pin One. Decoupling capacitors to the ground plane should be placed as close

as possible to this pin.

Analog-to-Digital Converter Input. Can be configured as an external PA enable signal. Analog Test

Pin 3.

ADCIN_ATB3

31

32

ATB4

ADCVREF

Analog Test Pin 4. Can be configured as an external LNA enable signal.

ADC Reference Output. A 220 nF capacitor should be placed between this pin and ground for

adequate noise rejection.

EPAD

The exposed package paddle must be connected to GND.

Rev. 0 | Page 18 of 100

ADF7023-J

TYPICAL PERFORMANCE CHARACTERISTICS

32

30

28

26

24

22

20

18

16

14

12

10

8

14

12

10

8

6

4

2

–40°C, 3.6V

–40°C, 1.8V

+85°C, 3.6V

+85°C, 1.8V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.4V

–40°C, 1.8V

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.4V

+85°C, 1.8V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.4V

+25°C, 1.8V

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

6

0

4

8

12 16 20 24 28 32 36 40 44 48 52 56 60 64

PA SETTING

OUTPUT POWER (dBm)

Figure 8. Differential PA at 915 MHz: Supply Current vs. Output Power,

Temperature, and V_DD(Minimum Recommended V_DD= 2.2 V, 1.8 V Operation

Shown for Robustness)

Figure 5. Single-Ended PA at 915 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V_DD(Minimum Recommended V_DD= 2.2 V, 1.8 V

Operation Shown for Robustness)

36

34

10

0

–40°C, 3.6V

–40°C, 1.8V

+85°C, 3.6V

+85°C, 1.8V

32

30

28

26

24

22

20

18

16

14

12

10

8

–10

–20

PA RAMP = 1

PA RAMP = 2

–30

PA RAMP = 3

PA RAMP = 4

PA RAMP = 5

–40

PA RAMP = 6

PA RAMP = 7

–50

–60

6

0

50

100 150 200 250 300 350 400 450 500

TIME (µs)

OUTPUT POWER (dBm)

Figure 9. PA Ramp-Up at Data Rate = 38.4 kbps for

Each PA_RAMP Setting, Differential PA

Figure 6. Single-Ended PA at 915 MHz: Supply Current vs. Output Power,

Temperature, and V_DD(Minimum Recommended V_DD= 2.2 V, 1.8 V Operation

Shown for Robustness)

12

10

8

10

0

6

4

–10

–20

–30

–40

–50

–60

2

0

–40°C, 3.6V

–40°C, 3.0V

–2

–40°C, 2.4V

–40°C, 1.8V

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.4V

+85°C, 1.8V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.4V

+25°C, 1.8V

–4

–6

PA RAMP = 1

PA RAMP = 2

PA RAMP = 3

PA RAMP = 4

PA RAMP = 5

PA RAMP = 6

PA RAMP = 7

–8

–10

–12

–14

–16

–18

–20

0

50

100 150 200 250 300 350 400 450 500

TIME (µs)

0

4

8

12 16 20 24 28 32 36 40 44 48 52 56 60 64

PA LEVEL SETTING

Figure 10. PA Ramp-Down at Data Rate = 38.4 kbps for

Each PA_RAMP Setting, Differential PA

Figure 7. Differential PA at 915 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V_DD(Minimum Recommended V_DD= 2.2 V, 1.8 V

Operation Shown for Robustness)

Rev. 0 | Page 19 of 100

ADF7023-J

5

0

10

0

–5

OUTPUT POWER (FUNDAMENTAL)

OUTPUT POWER IDEAL

P1dB

–10

–20

–30

–40

–50

–60

–10

–15

–20

–25

–30

–35

–40

PA RAMP = 4

PA RAMP = 5

PA RAMP = 6

PA RAMP = 7

P1dB = –21dBm

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75

TIME (µs)

–40

–35

–30

–25

–20

–15

LNA INPUT POWER (dBm)

Figure 11. PA Ramp-Up at Data Rate = 300 kbps for

Each PA_RAMP Setting, Differential PA

Figure 14. LNA/Mixer 1 dB Compression Point, V_DD= 3.0 V, Temperature =

25°C, RF Frequency = 915 MHz, LNA Gain = Low, Mixer Gain = Low

20

10

0

OUTPUT POWER (FUNDAMENTAL)

OUTPUT POWER IDEAL

P1dB

15

10

5

–10

–20

–30

–40

–50

–60

PA RAMP = 4

PA RAMP = 5

PA RAMP = 6

PA RAMP = 7

0

–5

P1dB = –21.9dBm

–10

–40

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75

TIME (µs)

–35

–30

–25

–20

–15

LNA INPUT POWER (dBm)

Figure 12. PA Ramp-Down at Data Rate = 300 kbps for

Each PA_RAMP Setting, Differential PA

Figure 15. LNA/Mixer 1 dB Compression Point, V_DD= 3.0 V, Temperature =

25°C, RF Frequency = 915 MHz, LNA Gain = High, Mixer Gain = High

15

10

0

–10

–20

–30

–40

–50

–60

5

3.6V, +25°C

1.8V, +25°C

3.6V, +85°C

1.8V, +85°C

3.6V, –40°C

1.8V, –40°C

0

–5

–10

–15

–20

–25

–30

–35

–40

–45

IIP3 = –11.5dBm

–70

–80

–90

–100

–110

–120

–130

FUNDAMENTAL TONE

IM3 TONE

FUNDAMENTAL 1/1 SLOPE FIT

IM3 3/1 SLOPE FIT

–50

–45

–40

–35

–30

–25

–20

–15

–10

LNA INPUT POWER (dBm)

FREQUENCY OFFSET (kHz)

Figure 13. Transmit Spectrum at 928 MHz, GFSK, Data Rate = 300 kbps,

Frequency Deviation = 75 kHz (Minimum Recommended V_DD= 2.2 V, 1.8 V

Operation Shown for Robustness)

Figure 16. LNA/Mixer IIP3, V_DD= 3.0 V, Temperature = 25°C, RF Frequency =

915 MHz, LNA Gain = Low, Mixer Gain = Low, Source 1 Frequency =

(915 + 0.4) MHz, Source 2 Frequency = (915+ 0.7) MHz

Rev. 0 | Page 20 of 100

ADF7023-J

80

70

60

50

40

30

20

10

0

20

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

MODULATED

INTERFERER

CARRIER WAVE

INTERFERER

IIP3 = –12.2dBm

FUNDAMENTAL TONE

IM3 TONE

FUNDAMENTAL 1/1 SLOPE FIT

IM3 3/1 SLOPE FIT

–10

–50

–45

–40

–35

–30

–25

–20

–15

–10

LNA INPUT POWER (dBm)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 20. Receiver Wideband Blocking at 915 MHz, Data Rate = 38.4 kbps

Figure 17. LNA/Mixer IIP3, V_DD= 3.0 V, Temperature = 25°C,

RF Frequency = 915 MHz, LNA Gain = High, Mixer Gain = High,

Source 1 Frequency = (915 + 0.4) MHz, Source 2 Frequency = (915+ 0.7) MHz

10

80

70

60

100kHz

0

150kHz

200kHz

300kHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

50

MODULATED

INTERFERER

CARRIER WAVE

INTERFERER

40

30

20

10

0

–10

–20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

FREQUENCY OFFSET (MHz)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 18. IF Filter Profile vs. IF Bandwidth, V_DD= 3.0 V, Temperature = 25°C

Figure 21. Receiver Wideband Blocking at 915 MHz, Data Rate = 100 kbps

10

70

60

50

1.8V, –40°C

2.4V, –40°C

3.0V, –40°C

3.6V, –40°C

1.8V, +25°C

2.4V, +25°C

3.0V, +25°C

3.6V, +25°C

1.8V, +85°C

2.4V, +85°C

3.0V, +85°C

3.6V, +85°C

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

40

MODULATED

INTERFERER

30

CARRIER WAVE

INTERFERER

20

10

0

–10

–20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

FREQUENCY OFFSET (MHz)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 19. IF Filter Profile vs. V_DDand Temperature, 100 kHz IF Filter

Bandwidth

Figure 22. Receiver Wideband Blocking at 915 MHz, Data Rate = 300 kbps

Rev. 0 | Page 21 of 100

ADF7023-J

60

55

50

45

40

35

30

25

20

15

10

5

80

70

60

50

40

30

20

10

0

–5

–10

–15

–20

CW INTERFERER

MODULATED INTERFERER

25°C, 3.0V

–60 –50 –40 –30 –20 –10

BLOCKER FREQUENCY OFFSET (MHz)

–10

–2.0 –1.6 –1.2 –0.8 –0.4

0

0.4

0.8

1.2

1.6

2.0

0

10 20 30 40 50 60

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 23. Receiver Wideband Blocking at 954 MHz, Data Rate = 50 kbps,

Frequency Deviation = 25 kHz, Carrier Wave Interferer, P_WANTED= P_SENS+ 3 dB

Figure 26. Receiver Close-In Blocking at 915 MHz, Data Rate = 150 kbps,

IF Filter Bandwidth = 150 kHz, Image Calibrated

70

60

50

40

30

20

10

0

60

55

50

45

40

35

30

25

20

15

10

5

0

–5

–10

CW INTERFERER

–15

25°C, 3.0V

0.6 0.8 1.0

BLOCKER FREQUENCY OFFSET (MHz)

MODULATED INTERFERER

–10

–1.0 –0.8 –0.6 –0.4 –0.2

–20

0

0.2

0.4

–2.0 –1.6 –1.2 –0.8 –0.4

0

0.4

0.8

1.2

1.6

2.0

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 27. Receiver Close-In Blocking at 915 MHz, Data Rate = 200 kbps,

IF Filter Bandwidth = 200 kHz, Image Calibrated

Figure 24. Receiver Close-In Blocking at 954 MHz, Data Rate = 50 kbps,

IF Filter Bandwidth = 100 kHz, Image Calibrated, CW Interferer, P_WANTED

P_SENS+ 3 dB

=

60

55

50

45

40

35

30

25

20

15

10

5

60

50

40

30

20

10

0

–5

–10

CW INTERFERER

–15

MODULATED INTERFERER

25°C, 3.0V

0.6 0.8 1.0

BLOCKER FREQUENCY OFFSET (MHz)

–20

–1.0 –0.8 –0.6 –0.4 –0.2

–2.0 –1.6 –1.2 –0.8 –0.4

0

0.4

0.8

1.2

1.6

2.0

0

0.2

0.4

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 28. Receiver Close-In Blocking at 915 MHz, Data Rate = 300 kbps,

IF Filter Bandwidth = 300 kHz, Image Calibrated

Figure 25. Receiver Close-In Blocking at 954 MHz, Data Rate = 100 kbps,

IF Filter Bandwidth = 100 kHz, Image Calibrated, CW Interferer, P_WANTED

P_SENS+ 3 dB

=

Rev. 0 | Page 22 of 100

ADF7023-J

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–95

–100

–105

–110

–115

–120

BIT ERROR RATE (1E-3)

CALIBRATED

PACKET ERROR RATE (1%)

UNCALIBRATED

–1.0 –0.8 –0.6 –0.4 –0.2

0

0.2

0.4

0.6

0.8

1.0

0

50

100

150

200

250

300

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

DATA RATE (kbps)

Figure 29. Image Attenuation with Calibrated and Uncalibrated Images,

915 MHz, IF Filter Bandwidth = 100 kHz, V_DD= 3.0 V, Temperature = 25°C

Figure 32. Bit Error Rate Sensitivity (at BER = 1E − 3) and Packet Error Rate

Sensitivity (at PER = 1%) vs. Data Rate, GFSK, V_DD= 3.0 V,

Temperature = 25°C

100

0

1kbps

100kHz BW

150kHz BW

10kbps

90

–10

38.4kbps

50kbps

100kbps

200kbps

300kbps

200kHz BW

300kHz BW

–20

80

70

60

50

40

30

20

10

0

–30

–40

–50

–60

–70

–80

–90

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

–1.0 –0.8 –0.6 –0.4 –0.2

0

0.2

0.4

0.6

0.8

1.0

APPLIED RECEIVER POWER (dBm)

OFFSET FROM LO FREQUENCY (MHz)

Figure 33. Packet Error Rate vs. RF Input Power and Data Rate, FSK/GFSK,

928 MHz, Preamble Length = 64 Bits, V_DD= 3.0 V, Temperature = 25°C

Figure 30. IF Filter Profile with Calibrated Image vs. IF Filter Bandwidth,

921 MHz, V_DD= 3.0 V, Temperature = 25°C

–96.0

–96.5

–98

915MHz, –40°C

915MHz, +25°C

915MHz, +85°C

–99

–100

–101

–102

–103

–104

–97.0

+25°C

+85°C

–97.5

–98.0

–40°C

–98.5

–99.0

–99.5

–100.0

1.8

3.6

1.8

3.0

(V)

3.6

V

(V)

V

DD

Figure 34. Receiver Sensitivity (Packet Error Rate at 1%) vs. V_DD

Temperature, and RF Frequency, Data Rate = 300 kbps, GFSK, Frequency

Deviation = 75 kHz, IF Bandwidth = 300 kHz

,

Figure 31. Receiver Sensitivity (Bit Error Rate at 1E − 3) vs. V_DD, Temperature,

and RF Frequency, Data Rate = 300 kbps, GFSK, Frequency Deviation =

75 kHz, IF Bandwidth = 300 kHz

Rev. 0 | Page 23 of 100

ADF7023-J

>1%

<1%

10

9

8

7

6

5

4

3

2

1

0

CODED, PML = 0x0A,

SYNC. TOL. = 0

2.00

1.75

CODED, PML = 0x0A,

SYNC. TOL. = 1

1.50

CODED, PML = 0x07,

SYNC. TOL. = 2

1.25

UNCODED, PML = 0x0A,

SYNC. TOL. = 0

1.00

0.75

0.50

0.25

0

–0.25

–0.50

–0.75

–1.00

–1.25

–1.50

–1.75

–2.00

2.1dB

3.5dB

4.1dB

–107

–106

–105

–104

–103

–102

–101

–100

–99

–140–120–100 –80 –60 –40 –20

0

20 40 60 80 100 120 140

Rx INPUT POWER (dBm)

RF FREQUENCY ERROR (kHz)

Figure 38. AFC On: Packet Error Rate vs. RF Frequency Error and Data Rate

Error, AFC On, Data Rate = 300 kbps, Frequency Deviation = 75 kHz, GFSK,

AGC_LOCK_MODE = Lock After Preamble

Figure 35. Receiver PER Using Reed Solomon (RS) Coding; RF Frequency =

928 MHz, GFSK, Data Rate = 100 kbps, Frequency Deviation = 50 kHz, Packet

Length = 28 Bytes (Uncoded); Reed Solomon Configuration: n = 38,

k = 28, t = 5, PML = Preamble Match Level Register

0

–20

–30

10

8

100kbps

150kbps

200kbps

300kbps

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–40

6

–50

4

–60

2

–70

0

–80

–2

–4

–6

–8

–10

–90

IDEAL RSSI

MEAN RSSI

MEAN RSSI ERROR

MAX POSITIVE RSSI ERROR

MAX NEGATIVE RSSI ERROR

–100

–110

–120

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

INPUT POWER (dBm)

RF FREQUENCY ERROR (kHz)

Figure 36. AFC On: Receiver Sensitivity (at PER = 1%) vs. RF Frequency Error,

GFSK, 915 MHz, AFC Enabled (Ki = 7, Kp = 3), AFC Mode = Lock After

Preamble, IF Bandwidth = 100 kHz (at 100 kbps), 150 kHz (at 150 kbps),

200 kHz (at 200 kbps), and 300 kHz (at 300 kbps), Preamble Length = 64 Bits

Figure 39. RSSI (via CMD_GET_RSSI) vs. RF Input Power, 950 MHz, GFSK, Data

Rate = 38.4 kbps, Frequency Deviation = 20 kHz, IF Bandwidth = 100 kHz,

100 RSSI Measurements at Each Input Power Level

>1%

<1%

–20

–30

10

8

2.00

1.75

IDEAL RSSI

MEAN RSSI

MEAN RSSI ERROR

MAX POSITIVE RSSI ERROR

MAX NEGATIVE RSSI ERROR

1.50

–40

6

1.25

1.00

–50

4

0.75

–60

2

0.50

0.25

–70

0

–0.25

–0.50

–0.75

–1.00

–1.25

–1.50

–1.75

–2.00

–80

–2

–4

–6

–8

–10

–90

–100

–110

–120

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

–40 –35 –30 –25 –20 –15 –10 –5

0

5

10 15 20 25 30 35 40

INPUT POWER (dBm)

RF FREQUENCY ERROR (kHz)

Figure 40. RSSI (via Automatic End of Packet RSSI Measurement) vs. RF Input

Power, 950 MHz, GFSK, Data Rate = 300 kbps, Frequency Deviation = 75 kHz,

IF Bandwidth = 300 kHz, AGC_CLOCK_DIVIDE = 15, 100 RSSI Measurements

at Each Input Power Level

Figure 37. AFC Off: Packet Error Rate vs. RF Frequency Error and Data Rate

Error, AFC Off, Data Rate = 300 kbps, Frequency Deviation = 75 kHz, GFSK,

AGC_LOCK_MODE = Lock After Preamble

Rev. 0 | Page 24 of 100

ADF7023-J

6

4

300kbps

200kbps

150kbps

100kbps

50kbps

1

38.4kbps

9.6kbps

2

0

–2

–4

–6

–1

0

1

2

3

4

5

6

7

8

9

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

SAMPLE NUMBER

INPUT POWER (dBm)

Figure 44. Receiver Eye Diagram Measured Using the Test DAC,

RF Frequency = 915 MHz, RF Input Power = −80 dBm,

Data Rate = 100 kbps, Frequency Deviation = 50 kHz

Figure 41. Mean RSSI Error (via Automatic End of Packet RSSI Measurement)

vs. RF Input Power vs. Data Rate; RF Frequency = 950 MHz, GFSK, 100 RSSI

Measurements at Each Input Power Level

–90

–91

–92

–93

–94

–95

–96

–97

–98

220

–20

–30

10

8

IFBW = 100kHz

IFBW = 200kHz

DISC BW (kHz)

IDEAL RSSI

MEAN RSSI

210

200

190

180

170

160

150

140

130

120

110

100

90

80

70

60

50

40

30

20

4.0

(WITH POLYNOMIAL CORRECTION)

–40

6

–50

4

–60

2

–99

–100

–101

–102

–103

–104

–105

–106

–107

–108

–109

–110

–70

0

–80

–2

–4

–6

–8

–10

–90

–100

–110

–120

MEAN RSSI ERROR

(WITH POLYNOMIAL CORRECTION)

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

MODULATION INDEX

INPUT POWER (dBm)

Figure 45. Rx Sensitivity vs. Modulation Index, Data Rate = 50 kbps,

MOD = GFSK, F_DEV(MI ꢀ 2 5 kHz), Data = PRBS9, BER = 1E − 3,

Figure 42. RSSI With and Without Cosine Polynomial Correction (via

Automatic End of Packet RSSI Measurement), 100 RSSI Measurements at

Each Input Power Level

=

Bits = 1E + 6, V_BAT= 3.0 V, Temperature = 25°C

–90

–91

–92

–93

–94

–95

–96

–97

–98

240

230

220

210

200

190

180

170

160

150

140

130

120

110

100

90

80

70

IFBW = 100kHz

IFBW = 200kHz

DISC BW (kHz)

60

MEAN (°C)

50

40

30

20

10

–99

–100

–101

–102

–103

–104

–105

–106

–107

–108

–109

–110

ERROR + 3

σ

(°C)

0

–10

–20

–30

–40

ERROR – 3

80

70

60

50

40

2.0

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

MODULATION INDEX

Figure 46. Rx Sensitivity vs. Modulation Index, Data Rate = 100 kbps,

MOD = GFSK (0.5), F_DEV(MI ꢀ 50 kHz), Data = PRBS9, BER = 1E − 3,

Bits = 2E + 5, V_BAT= 3.0 V, Temperature = 25°C

Figure 43. Temperature Sensor Readback vs. Die Temperature, Readback

Value Converted to °C via Formula in the Temperature Sensor Section

=

Rev. 0 | Page 25 of 100

ADF7023-J

TERMINOLOGY

ADC

Analog-to-digital converter

MSK

Minimum shift keying, 2FSK with modulation index = 0.5

AGC

NOP

No operation

Automatic gain control

AFC

PA

Automatic frequency control

Power amplifier

Battmon

Battery monitor

PFD

Phase frequency detector

BBRAM

PHY

Physical layer

Battery backup random access memory

CBC

RCO

RC oscillator

Cipher block chaining

CRC

RISC

Cyclic redundancy check

Reduced instruction set computer

DR

Data rate

RSSI

Receive signal strength indicator

ECB

Rx

Receive

Electronic code book

ECC

SAR

Error checking code

Successive approximation register

2FSK

SWM

Smart wake mode

Two-level frequency shift keying

GFSK

Tx

Transmit

Two-level Gaussian frequency shift keying

GMSK

VCO

Gaussian minimum shift keying, GFSK with modulation index = 0.5

Voltage controlled oscillator

LO

WUC

Local oscillator

Wake-up controller

MAC

XOSC

Media access control

Crystal oscillator

MCR

Modem configuration random access memory

MER

Modulation error ratio

Rev. 0 | Page 26 of 100

ADF7023-J

RADIO CONTROL

The ADF7023-J has five radio states designated PHY_SLEEP,

PHY_OFF, PHY_ON, PHY_TX, and PHY_RX. The host processor

can transition the ADF7023-J between states by issuing single

byte commands over the SPI interface. The various commands

and states are illustrated in Figure 47. The communications

processor handles the sequencing of various radio circuits and

critical timing functions, thereby simplifying radio operation

and easing the burden on the host processor.

PHY_TX

In the PHY_TX state, the synthesizer is enabled and calibrated.

The power amplifier is enabled, and the device transmits at the

channel frequency defined by the CHANNEL_FREQ[23:0]

setting (Address 0x109 to Address 0x10B). The state is entered by

issuing the CMD_PHY_TX command. The device automatically

transmits the transmit packet stored in the packet RAM. After

transmission of the packet, the PA is disabled, and the device

automatically returns to the PHY_ON state and can, optionally,

generate an interrupt.

RADIO STATES

PHY_SLEEP

In sport mode, the device transmits the data present on the GP2

pin as described in the Sport Mode section. The host processor

must issue the CMD_PHY_ON command to exit the PHY_TX

state when in sport mode.

In this state, the device is in a low power sleep mode. To enter

the state, issue the CMD_PHY_SLEEP command, either from

the PHY_OFF or PHY_ON state. To wake the radio from the

CS

state, set the pin low or use the wake-up controller (32.768 kHz

PHY_RX

RC or 32.768 kHz crystal) to wake the radio from this state. The

wake-up timer should be set up before entering the PHY_SLEEP

state. If retention of BBRAM contents is not required, Deep

Sleep Mode 2 can be used to further reduce the PHY_SLEEP

state current consumption. Deep Sleep Mode 2 is entered by

issuing the CMD_HW_RESET command. The options for

the PHY_SLEEP state are detailed in Table 10.

In the PHY_RX state, the synthesizer is enabled and calibrated.

The ADC, RSSI, IF filter, mixer, and LNA are enabled. The

radio is in receive mode on the channel frequency defined by

the CHANNEL_FREQ[23:0] setting (Address 0x109 to

Address 0x10B).

After reception of a valid packet, the device returns to the

PHY_ON state and can, optionally, generate an interrupt.

In sport mode, the device remains in the PHY_RX state

until the CMD_PHY_ON command is issued.

PHY_OFF

In the PHY_OFF state, the 26 MHz crystal, the digital regulator,

and the synthesizer regulator are powered up. All memories are

fully accessible. The BBRAM registers must be valid before exiting

this state.

Current Consumption

The typical current consumption in each state is detailed

in Table 10.

PHY_ON

In the PHY_ON state, along with the crystal, the digital regulator,

the synthesizer regulator, the VCO, and the RF regulators are

powered up. A baseband filter calibration is performed when

this state is entered from the PHY_OFF state if the BB_CAL bit

in the MODE_CONTROL register (Address 0x11A) is set. The

device is ready to operate, and the PHY_TX and PHY_RX states

can be entered.

Table 10. Current Consumption in ADF7023-J Radio States

State

Current (Typical)

Conditions

PHY_SLEEP (Deep Sleep Mode 2)

0.18 μA

Wake-up timer off, BBRAM contents not retained, entered by

issuing CMD_HW_RESET

PHY_SLEEP (Deep Sleep Mode 1)

PHY_SLEEP (RCO Mode )

PHY_SLEEP (XTO Mode )

PHY_OFF

PHY_ON

PHY_TX

0.33 μA

0.75 μA

1.28 μA

1.0 mA

24.1 mA

12.8 mA

Wake-up timer off, BBRAM contents retained

Wake-up timer on using a 32 kHz RC oscillator, BBRAM contents retained

Wake-up timer on using a 32 kHz XTAL oscillator, BBRAM contents retained

10 dBm, single-ended PA, 950 MHz

PHY_RX

Rev. 0 | Page 27 of 100

ADF7023-J

COLD START

(BATTERY APPLIED)

WUC TIMEOUT

CMD_HW_RESET

(FROM ANY STATE)

CS LOW

CMD_CONFIG_DEV

PHY_OFF

PHY_SLEEP

CMD_PHY_SLEEP

CONFIGURE

CMD_RAM_LOAD_INIT

CMD_RAM_LOAD_DONE

PROGRAM RAM

CONFIG

C

M

C

M

D

_

P

D

_

H

Y

_

P

H

O

Y

_

N

O

F

2

PROGRAM RAM

4

CMD_AES

CMD_BB_CAL

CMD_CONFIG_DEV

CMD_GET_RSSI

AES

IF FILTER CAL

CONFIGURE

CMD_IR_CAL

IR CALIBRATION

REED-SOLOMON

PHY_ON

5

CMD_RS

MEASURE RSSI

3

RX_EOF

TX_EOF

1

RX_TO_TX_AUTO_TURNAROUND

TX_TO_RX_AUTO_TURNAROUND

PHY_TX

PHY_RX

CMD_PHY_TX

CMD_PHY_RX

CMD_PHY_TX

CMD_PHY_RX

1

2

TRANSMIT AND RECEIVE AUTOMATIC TURNAROUND MUST BE ENABLED BY BITS RX_TO_TX_AUTO_TURNAROUND AND

TX_TO_RX_AUTO_TURNAROUND (0x11A: MODE_CONTROL).

AES ENCRYPTION/DECRYPTION, IMAGE REJECTION CALIBRATION, AND REED SOLOMON CODING ARE AVAILABLE ONLY IF THE NECESSARY

FIRMWARE MODULE HAS BEEN DOWNLOADED TO THE PROGRAM RAM.

3

4

5

THE END OF FRAME (EOF) AUTOMATIC TRANSITIONS ARE DISABLED IN SPORT MODE.

CMD_AES REFERS TO THE THREE AVAILABLE AES COMMANDS: CMD_AES_ENCRYPT, CMD_AES_DECRYPT, AND CMD_AES_DECRYPT_INIT.

CMD_RS REFERS TO THE THREE AVAILABLE REED SOLOMON COMMANDS: CMD_RS_ENCODE_INIT, CMD_RS_ENCODE,

AND CMD_RS_DECODE.

KEY

TRANSITION INITIATED BY HOST PROCESSOR

AUTOMATIC TRANSITION BY COMMUNICATIONS PROCESSOR

COMMUNICATIONS PROCESSOR FUNCTION

DOWNLOADABLE FIRMWARE MODULE STORED ON PROGRAM RAM

RADIO STATE

Figure 47. Radio State Diagram

Rev. 0 | Page 28 of 100

ADF7023-J

INITIALIZATION

Initialization After Application of Power

CS

Initialization on Transitioning from PHY_SLEEP (After

Is Brought Low)

When power is applied to the ADF7023-J (through the

VDDBAT1/VDDBAT2 pins), it registers a power-on reset

(POR) event and transitions to the PHY_OFF state. The

BBRAM memory is unknown, the packet RAM memory is

cleared to 0x00, and the MCR memory is reset to its default

values. The host processor should use the following procedure

to complete the initialization sequence:

CS

The host processor can bring

low at any time to wake the

ADF7023-J from the PHY_SLEEP state. This event is not

registered as a POR event because the BBRAM contents are

valid. The following is the procedure that the host processor is

required to follow:

CS

1. Bring the

line of the SPI low and wait until the MISO

output goes high. The ADF7023-J enters the PHY_OFF state.

2. Issue the CMD_SYNC command.

CS

1. Bring the

pin of the SPI low and wait until the MISO

output goes high.

3. Wait for the CMD_READY bit in the status word to go high.

4. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

2. Issue the CMD_SYNC command.

3. Wait for the CMD_READY bit in the status word to go high.

4. Configure the part by writing to all 64 of the BBRAM

registers.

The ADF7023-J is now configured and ready to transition to

the PHY_ON state.

5. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

Initialization After a WUC Timeout

The ADF7023-J is now configured in the PHY_OFF state.

The ADF7023-J can autonomously wake from the PHY_SLEEP

state using the wake-up controller. If the ADF7023-J wakes after

a WUC timeout in smart wake mode (SWM), it follows the SWM

routine based on the smart wake mode configuration in BBRAM

(see the Low Power Modes section). If the ADF7023-J wakes

after a WUC timeout with SWM disabled and the firmware

timer disabled, it wakes in the PHY_OFF state, and the following

is the procedure that the host processor is required to follow:

Initialization After Issuing the CMD_HW_RESET

Command

The CMD_HW_RESET command performs a full power-down

of all hardware, and the device enters the PHY_SLEEP state. To

complete the hardware reset, the host processor should

complete the following procedure:

1. Wait for 1 ms.

1. Issue the CMD_SYNC command.

CS

2. Bring the

pin of the SPI low and wait until the MISO

2. Wait for the CMD_READY bit in the status word to go high.

3. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

output goes high. The ADF7023-J registers a POR and

enters the PHY_OFF state.

3. Issue the CMD_SYNC command.

4. Wait for the CMD_READY bit in the status word to go high.

5. Configure the part by writing to all 64 of the BBRAM registers.

6. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

The ADF7023-J is now configured in the PHY_OFF state.

Rev. 0 | Page 29 of 100

ADF7023-J

COMMANDS

The commands that are supported by the radio controller are

detailed in this section. They initiate transitions between radio

states or perform tasks as indicated in Figure 47. The execution

times for all radio state transitions are detailed in Table 11 and

Table 12.

If the command is issued in the PHY_RX state, the communications

processor performs the following procedure:

1. Sets the external LNA signal low (if enabled).

2. Unlocks the AFC and AGC.

3. Turns off the receive blocks.

CMD_PHY_OFF (0xB0)

4. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

5. Sets the synthesizer bandwidth.

6. Does a VCO calibration.

This command transitions the ADF7023-J to the PHY_OFF

state. It can be issued in the PHY_ON state. It powers down

the RF and VCO regulators.

7. Delays for synthesizer settling.

CMD_PHY_ON (0xB1)

8. Enables the digital receiver blocks.

9. Sets the external LNA enable signal high (if enabled).

10. Sets FW_STATE = PHY_RX.

This command transitions the ADF7023-J to the PHY_ON state.

If the command is issued in the PHY_OFF state, it powers up

the RF and VCO regulators and performs an IF filter calibration

if the BB_CAL bit is set in the MODE_CONTROL register

(Address 0x11A).

If the command is issued in the PHY_TX state, the communications

processor performs the following procedure:

1. Ramps down the PA.

If the command is issued from the PHY_TX state, the host

processor performs the following procedure:

2. Sets the external PA signal low (if enabled).

3. Turns off the digital transmit blocks.

4. Powers up the receiver circuitry (ADC, RSSI, IF filter,

mixer, and LNA).

5. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

6. Sets the synthesizer bandwidth.

7. Does a VCO calibration.

8. Delays for synthesizer settling.

1. Ramps down the PA.

2. Sets the external PA signal low (if enabled).

3. Turns off the digital transmit clocks.

4. Powers down the synthesizer.

5. Sets FW_STATE = PHY_ON.

If the command is issued from the PHY_RX state, the

communications processor performs the following procedure:

9. Enables the digital receiver blocks.

10. Sets the external LNA enable signal high (if enabled).

11. Sets FW_STATE = PHY_RX.

1. Copies the measured RSSI to the RSSI_READBACK register.

2. Sets the external LNA signal low (if enabled).

3. Turns off the digital receiver clocks.

CMD_PHY_TX (0xB5)

4. Powers down the synthesizer and the receiver circuitry

(ADC, RSSI, IF filter, mixer, and LNA).

5. Sets FW_STATE = PHY_ON.

This command can be issued in the PHY_ON, PHY_TX, or

PHY_RX state. If the command is issued in the PHY_ON state,

the communications processor performs the following procedure:

CMD_PHY_SLEEP (0xBA)

This command transitions the ADF7023-J to the very low

power PHY_SLEEP state in which the WUC is operational (if

enabled), and the BBRAM contents are retained. It can be issued

from the PHY_OFF or PHY_ON state.

1. Powers up the synthesizer.

2. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

3. Sets the synthesizer bandwidth.

4. Does a VCO calibration.

CMD_PHY_RX (0xB2)

5. Delays for synthesizer settling.

6. Enables the digital transmit blocks.

7. Sets the external PA enable signal high (if enabled).

8. Ramps up the PA.

9. Sets FW_STATE = PHY_TX.

10. Transmits data.

This command can be issued in the PHY_ON, PHY_RX, or

PHY_TX state. If the command is issued in the PHY_ON state,

the communications processor performs the following procedure:

1. Powers up the synthesizer.

2. Powers up the receiver circuitry (ADC, RSSI, IF filter,

mixer, and LNA).

3. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

4. Sets the synthesizer bandwidth.

5. Does a VCO calibration.

6. Delays for synthesizer settling.

7. Enables the digital receiver blocks.

8. Sets the external LNA enable signal high (if enabled).

9. Sets FW_STATE = PHY_RX.

Rev. 0 | Page 30 of 100

ADF7023-J

If the command is issued in the PHY_TX state, the communications

processor performs the following procedure:

CMD_BB_CAL (0xBE)

This command performs an IF filter calibration. It can be issued

only in the PHY_ON state. In many cases, it may not be

necessary to use this command because an IF filter calibration

is automatically performed on the PHY_OFF to PHY_ON

transition if BB_CAL = 1 in the MODE_CONTROL register

(Address 0x11A).

1. Ramps down the PA.

2. Sets the external PA enable signal low (if enabled).

3. Turns off the digital transmit blocks.

4. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

5. Sets the synthesizer bandwidth.

6. Does a VCO calibration.

7. Delays for synthesizer settling.

8. Enables the digital transmit blocks.

9. Sets the external PA enable signal high (if enabled).

10. Ramps up the PA.

CMD_SYNC (0xA2)

This command is used to allow the host processor and

communications processor to establish communications. It is

required to issue a CMD_SYNC command during each of the

following scenarios:

•

After application of power

On a WUC wake-up

After a CMD_HW_RESET

After a CMD_RAM_LOAD_DONE command has

been issued

11. Sets FW_STATE = PHY_TX.

12. Transmits data.

If the command is issued in the PHY_RX state, the communications

processor performs the following procedure:

1. Sets the external LNA signal low (if enabled).

2. Unlocks the AFC and AGC.

3. Turns off the receive blocks.

4. Powers down the receiver circuitry (ADC, RSSI, IF filter,

mixer, and LNA).

5. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

After issuing a CMD_SYNC command, the host processor

should wait until the CMD_READY status bit is high (see

the Initialization section). This process ensures that the next

command issued by the host processor is processed by the

communications processor. See the Initialization section for

further details on using a CMD_SYNC command.

6. Sets the synthesizer bandwidth.

7. Delays for synthesizer settling.

8. Enables the digital transmit blocks.

9. Sets the external PA enable signal high (if enabled).

10. Ramps up the PA.

CMD_HW_RESET (0xC8)

The command performs a full power-down of all hardware,

and the device enters the PHY_SLEEP state. This command

can be issued in any state and is independent of the state of the

communications processor. The procedure for initialization of

the device after a CMD_HW_RESET command is described in

detail in the Initialization section.

11. Sets FW_STATE = PHY_TX.

12. Transmits data.

CMD_CONFIG_DEV (0xBB)

CMD_RAM_LOAD_INIT (0xBF)

This command interprets the BBRAM contents and configures

each of the radio parameters based on these contents. It can be

issued from the PHY_OFF or PHY_ON state. The only radio

parameter that is not configured on this command is the

CHANNEL_FREQ[23:0] setting, which instead is configured as

part of a CMD_PHY_TX or CMD_PHY_RX command.

This command prepares the communications processor for a

subsequent download of a software module to program RAM.

This command should be issued only prior to the program

RAM being written to by the host processor.

CMD_RAM_LOAD_DONE (0xC7)

This command is required only after download of a software

module to program RAM. It indicates to the communications

processor that a software module is loaded to program RAM.

The CMD_RAM_LOAD_DONE command can be issued only

in the PHY_OFF state. The command resets the communications

processor and the packet RAM. This command should be

followed by a CMD_SYNC command.

The user should write to the entire 64 bytes of the BBRAM and

then issue the CMD_CONFIG_DEV command, which can be

issued in the PHY_OFF or PHY_ON state.

CMD_GET_RSSI (0xBC)

This command turns on the receiver, performs an RSSI measure-

ment on the current channel, and returns the ADF7023-J to the

PHY_ON state. The command can be issued from the PHY_ON

state. The RSSI result is saved to the RSSI_READBACK register

(Address 0x312). This command can be issued from the

PHY_ON state only.

CMD_IR_CAL (0xBD)

This command performs a fully automatic image rejection

calibration on the ADF7023-J receiver.

This command requires that the IR calibration firmware module

has been loaded to the ADF7023-J program RAM. The firmware

module is available from Analog Devices, Inc.. For more information,

see the Downloadable Firmware Modules section.

Rev. 0 | Page 31 of 100

ADF7023-J

CMD_AES_ENCRYPT (0xD0), CMD_AES_DECRYPT

(0xD2), and CMD_AES_DECRYPT_INIT (0xD1)

RX_TO_TX_AUTO_TURNAROUND

If the RX_TO_TX_AUTO_TURNAROUND bit in the MODE_

CONTROL register (Address 0x11A) is enabled, the device

automatically transitions to the PHY_TX state at the end of a

valid packet reception, on the same RF channel frequency. On

the transition, the communications processor performs the

following actions:

These commands allow AES, 128-bit block encryption and

decryption of transmit and receive data using key sizes of

128 bits, 192 bits, or 256 bits.

The AES commands require that the AES firmware module

has been loaded to the ADF7023-J program RAM. The AES

firmware module is available from Analog Devices. See the

Downloadable Firmware Modules section for details on the

AES encryption and decryption module.

1. Sets the external LNA signal low.

2. Unlocks the AGC and AFC (if enabled).

3. Disables the digital receiver blocks.

4. Powers down the receiver circuitry (ADC, RSSI, IF filter,

mixer, and LNA).

5. Sets RF channel frequency (same as the previous receive

channel frequency).

6. Sets the synthesizer bandwidth.

CMD_RS_ENCODE_INIT (0xD1), CMD_RS_ENCODE

(0xD0), and CMD_RS_DECODE (0xD2)

These commands perform Reed-Solomon encoding and

decoding of transmit and receive data, thereby allowing

detection and correction of errors in the received packet.

7. Does VCO calibration.

These commands require that the Reed-Solomon firmware

module has been loaded to the ADF7023-J program RAM.

The Reed-Solomon firmware module is available from Analog

Devices. See the Downloadable Firmware Modules section for

details on this module.

8. Delays for synthesizer settling.

9. Enables the digital transmitter blocks.

10. Sets the external PA signal high (if enabled).

11. Ramps up the PA.

12. Sets FW_STATE = PHY_TX.

13. Transmits data.

AUTOMATIC STATE TRANSITIONS

On certain events, the communications processor can automatically

transition the ADF7023-J between states. These automatic

transitions are illustrated as dashed lines in Figure 47 and are

explained in this section.

In sport mode, the RX_TO_TX_AUTO_TURNAROUND

transition is disabled.

TX_TO_RX_AUTO_TURNAROUND

If the TX_TO_RX_AUTO_TURNAROUND bit in the MODE_

CONTROL register (Address 0x11A) is enabled, the device

automatically transitions to the PHY_RX state at the end of a

packet transmission, on the same RF channel frequency. On

the transition, the communications processor performs the

following actions:

TX_EOF

The communications processor automatically transitions the

device from the PHY_TX state to the PHY_ON state at the end

of a packet transmission. On the transition, the communications

processor performs the following actions:

1. Ramps down the PA.

2. Sets the external PA signal low.

3. Disables the digital transmitter blocks.

4. Powers up the receiver circuitry (ADC, RSSI, IF filter, mixer,

and LNA).

2. Sets the external PA signal low.

3. Disables the digital transmitter blocks.

4. Powers down the synthesizer.

5. Sets FW_STATE = PHY_ON.

5. Sets the RF channel (same as the previous transmit channel

frequency).

6. Sets the synthesizer bandwidth.

7. Does VCO calibration.

8. Delays for synthesizer settling.

9. Turns on AGC and AFC (if enabled).

10. Enables the digital receiver blocks.

11. Sets the external LNA signal high (if enabled).

12. Sets FW_STATE = PHY_RX.

RX_EOF

The communications processor automatically transitions the

device from the PHY_RX state to the PHY_ON state at the end

of a packet reception. On the transition, the communications

processor performs the following actions:

1. Copies the measured RSSI to the RSSI_READBACK

register (Address 0x312).

2. Sets the external LNA signal low.

3. Disables the digital receiver blocks.

4. Powers down the synthesizer and the receiver circuitry

(ADC, RSSI, IF filter, mixer, and LNA).

5. Sets FW_STATE = PHY_ON.

In sport mode, the TX_TO_RX_AUTO_TURNAROUND

transition is disabled.

WUC Timeout

The ADF7023-J can use the WUC to wake from sleep on a

timeout of the hardware timer. The device wakes into the

PHY_OFF state. See the WUC Mode section for further details.

Rev. 0 | Page 32 of 100

ADF7023-J

STATE TRANSITION AND COMMAND TIMING

The execution times for all radio state transitions are detailed in Table 11 and Table 12. Note that these times are typical and can vary,

depending on the BBRAM configuration.

Table 11. ADF7023-J Command Execution Times and State Transition Times That Are Not Related to PHY_TX or PHY_RX

Transition

Time (μs),

Command

Command/Bit

Initiated By

Present State

Any

Next State

PHY_SLEEP

PHY_OFF

PHY_ON

Typical

Condition

CMD_HW_RESET

CMD_PHY_SLEEP

CMD_PHY_OFF

CMD_PHY_ON

Host

1

Host

PHY_OFF

PHY_ON

PHY_OFF

PHY_ON

PHY_OFF

PHY_ON

PHY_SLEEP

22.3

24.1

19

Host

248

Including IF filter calibration

CMD_GET_RSSI

CMD_CONFIG_DEV

CMD_BB_CAL

Host

PHY_ON

612.5

66.8

211

Host

PHY_OFF

PHY_ON

Host

PHY_ON

Wake-Up from PHY_SLEEP,

(WUC Timeout)

Automatic

PHY_OFF

310 + 252.8

The 310 μs is for startup of the 26 MHz

crystal (7 pF load capacitance, T_A= 25°C)

Wake-Up from PHY_SLEEP,

(CS Low)

Host

PHY_SLEEP

PHY_OFF

310 + 252.8

The 310 μs is for startup of the 26 MHz

crystal (7 pF load capacitance, T_A= 25°C)

Cold Start

Application

of power

Not applicable

The 310 μs is for startup of the 26 MHz

crystal (7 pF load capacitance, T_A= 25°C)

Table 12. ADF7023-J State Transition Times Related to PHY_TX and PHY_RX

Command/Bit/

Automatic

Transition

Present

State

Transition Time (ꢀs)^{1, 2}

Typical

,

Mode

Packet

Condition

CMD_PHY_ON

PHY_TX

PHY_RX

PHY_ON

T_EOP+ 10.8 + T_{PARAMP_DOWN}+ 36

5 + T_BYTE+ 38.2

CMD_PHY_ON issued during search for

preamble

41.7

41.2

CMD_PHY_ON issued during preamble

qualification

CMD_PHY_ON issued during sync word

qualification

T

_EOP+ 31.7

CMD_PHY_ON issued during Rx data (after a

sync word)

Packet

CMD_PHY_TX

PHY_ON

PHY_RX

PHY_TX

293 + T_{PARAMP_UP}+ 3

5 + T_BYTE+ 305.3 + T_{PARAMP_UP}+ 3 CMD_PHY_TX issued during search for

preamble

308.5 + T_{PARAMP_UP}+ 3

CMD_PHY_TX issued during preamble

qualification

308 + T_{PARAMP_UP}+ 3

CMD_PHY_TX issued during sync word

qualification

298.5 + T_EOP+ T_{PARAMP_UP}+ 3

CMD_PHY_TX issued during Rx data (after a

sync word)

Packet

CMD_PHY_TX

PHY_TX

T_EOP+ 10.8 + T_{PARAMP_DOWN}

297 + T_{PARAMP_UP}+ 3

+

CMD_PHY_TX issued during packet trans-

mission

RX_TO_TX_AUTO PHY_RX

_TURNAROUND

287.3 + T_{PARAMP_UP}+ 3

Packet

CMD_PHY_RX

PHY_ON

PHY_TX

PHY_RX

300

T_EOP+ 10.8 + T_{PARAMP_DOWN}+ 317 CMD_PHY_RX issued during packet trans-

mission

Rev. 0 | Page 33 of 100

ADF7023-J

Command/Bit/

Automatic

Transition

Present

State

Transition Time (ꢀs)^{1, 2}

Typical

,

Mode

Condition

Packet

CMD_PHY_RX

PHY_RX

5 + T_BYTE+ 305.2

CMD_PHY_RX issued during search for

preamble

308.4

CMD_PHY_RX issued during preamble

qualification

307.9

CMD_PHY_RX issued during sync word

qualification

T_EOP+ 298.4

CMD_PHY_RX issued during Rx data (after a

sync word)

Packet

TX_TO_RX_AUTO_ PHY_TX

TURNAROUND

PHY_RX

10.8 + T_{PARAMP_DOWN}+ 306

Packet

Sport

TX_EOF

PHY_TX

PHY_RX

PHY_TX

PHY_RX

PHY_ON

10.8 + T_{PARAMP_DOWN}+ 36

17.2

RX_EOF

CMD_PHY_ON

10.8 + T_{PARAMP_DOWN}+ 36

5 + T_BYTE+ 38.2

CMD_PHY_ON issued during search for a

preamble

41.7

CMD_PHY_ON issued during preamble

qualification

41.2

CMD_PHY_ON issued during sync word

qualification

31.7

CMD_PHY_ON issued during Rx data (after a

sync word)

Sport

CMD_PHY_TX

PHY_ON

PHY_RX

PHY_TX

293 + T_{PARAMP_UP}+ 3

5 + T_BYTE+ 305.3 + T_{PARAMP_UP}+ 3 CMD_PHY_TX issued during search for a

preamble

308.5 + T_{PARAMP_UP}+ 3

CMD_PHY_TX issued during preamble

qualification

308 + T_{PARAMP_UP}+ 3

CMD_PHY_TX issued during sync word

qualification

298.5 + T_{PARAMP_UP}+ 3

10.8 + T_{PARAMP_DOWN}+ 297 +

CMD_PHY_TX issued during Rx data (after a

sync word)

Sport

CMD_PHY_TX

PHY_TX

T

_{PARAMP_UP}+ 3

RX_TO_TX_AUTO PHY_RX

_TURNAROUND

287.3 + T_{PARAMP_UP}+ 3

Sport

CMD_PHY_RX

PHY_ON

PHY_TX

PHY_RX

300

10.8 + T_{PARAMP_DOWN}+ 317

5 + T_BYTE+ 305.2

CMD_PHY_RX issued during search for a

preamble

308.4

CMD_PHY_RX issued during preamble

qualification

307.9

CMD_PHY_RX issued during sync word

qualification

298.4

CMD_PHY_RX issued during Rx data (after a

sync word)

Sport

TX_TO_RX_AUTO_ PHY_TX

TURNAROUND

PHY_RX

10.8 + T_{PARAMP_DOWN}+ 306

PA_LEVEL_MCR

¹T_{PARAMP_UP}= T_{PARAMP_DOWN}

=

, where PA_LEVEL_MCR sets the maximum PA output power (PA_LEVEL_MCR register, Address 0x307),

(9

− PA_RAMP)

2

× DATA_RATE × 100

PA_RAMP sets the PA ramp rate (RADIO_CFG_8 register, Address 0x114), and DATA_RATE sets the transmit data rate (RADIO_CFG_0 register, Address 0x10C and

RADIO_CFG_1 register, Address 0x10D).

²T_BYTE= one byte period (μs), T_EOP= time to end of packet (μs).

Rev. 0 | Page 34 of 100

ADF7023-J

SPORT MODE

It is possible to bypass all of the packet management features of

the ADF7023-J and use the sport interface for transmit and receive

data. The sport interface is a high speed synchronous serial

interface allowing direct interfacing to processors and DSPs.

Sport mode is enabled using the DATA_MODE setting in the

PACKET_LENGTH_CONTROL register (Address 0x126), as

described in Table 13. The sport mode interface is on the GPIO

pins (GP0, GP1, GP2, GP4, and XOSC32KP_GP5_ATB1). These

GPIO pins can be configured using the GPIO_CONFIGURE

setting (Address 0x3FA), as described in Table 14.

the Status Word section) or the CMD_FINISHED interrupt (see

the Interrupts in Sport Mode section) can be used to indicate

when the ADF7023-J has reached the PHY_TX state and,

therefore, is ready to begin transmitting data. The ADF7023-J

keeps transmitting the serial data presented at the GP1 input

until the host processor issues a command to exit the PHY_TX state.

SPORT MODE IN RECEIVE

The sport interface supports the receive operation with a number

of modes to suit particular signaling requirements. The receive

data appears on the GP0 pin, whereas the receive synchronized

clock appears on the GP2 pin. The GP4 pin provides a dedicated

SPORT mode interrupt or strobe signal on either preamble or

sync word detection, as described in Table 13 and Table 14.

Once enabled, the interrupt signal and strobe signals remain

operational while in the PHY_RX state. The strobe signal gives

a single high pulse of 1-bit duration every eight bits. The strobe

signal is most useful when used with sync word detection because

it is synchronized to the sync word and strobes the first bit in

every byte.

Sport mode provides a receive interrupt source on GP4. This

interrupt source can be configured to provide an interrupt, or

strobe signal, on either preamble detection or sync word detection.

The type of interrupt is configured using the GPIO_CONFIGURE

setting.

PACKET STRUCTURE IN SPORT MODE

In sport mode, the host processor has full control over the packet

structure. However, the preamble frame is still required to allow

sufficient bits for receiver settling (AGC, AFC, and CDR). In

sport mode, sync word detection is not mandatory in the ADF7023-J

but can be enabled to provide byte level synchronization for the host

processor via the sync word detect interrupt or strobe on GP4. The

general format of a sport mode packet is shown in Figure 48.

In SPORT mode, IRQ_GP3 retains its normal interrupt

functionality for INTERRUPT_SOURCE_1; however, only

INTERRUPT_PREAMBLE_DETECT and INTERRUPT_

SYNC_DETECT are available from INTERRUPT_SOURCE_0.

Refer to the Interrupt Generation section for more details.

SYNC

WORD

PREAMBLE

PAYLOAD

TRANSMIT BIT LATENCIES IN SPORT MODE

The transmit bit latency is the time from the sampling of a bit

by the transmit data clock on GP2 to when that bit appears at

the RF output. There is no transmit bit latency when using

2FSK/MSK modulation. The latency when using GFSK/GMSK

modulation is two bits. It is important that the host processor

keep the ADF7023-J in the PHY_TX state for two bit periods

after the last data bit is sampled by the data clock to account for

this latency when using GMSK/GFSK modulation.

Figure 48. General Sport Mode Packet

SPORT MODE IN TRANSMIT

Figure 49 illustrates the operation of the sport interface in

transmit. Once in the PHY_TX state with sport mode enabled,

the data input of the transmitter is fully controlled by the sport

interface (Pin GP1). The transmit clock appears on the GP2 pin.

The transmit data from the host processor should be synchronized

with this clock. The FW_STATE variable in the status word (see

Table 13. SPORT Mode Setup

DATA_MODE Bits in

PACKET_LENGTH_

CONTROL Register

Description

GPIO Configuration

DATA_MODE = 0

Packet mode enabled. Packet management is

controlled by the communications processor.

DATA_MODE = 1

DATA_MODE = 2

Sport mode enabled. The Rx data and Rx clock are

enabled in the PHY_RX state (GPIO_CONFIGURE =

0xA0, 0xA3, 0xA6). The Rx clock is enabled in the

PHY_RX state, and Rx data is enabled on the preamble

detect (GPIO_CONFIGURE = 0xA1, 0xA2, 0xA4, 0xA5,

0xA7, 0xA8).

GP0: Rx data

GP1: Tx data

GP2: Tx/Rx clock

GP4: interrupt or strobe enabled on preamble detect

(depends on GPIO_CONFIGURE)

XOSC32KP_GP5_ATB1: depends on GPIO_CONFIGURE

Sport mode enabled. The Rx data and Rx clock are

enabled in the PHY_RX state if GPIO_CONFIGURE =

0xA0, 0xA3, 0xA6. The Rx clock is enabled in the

PHY_RX state, and Rx data is enabled on the preamble

detect if GPIO_CONFIGURE = 0xA1, 0xA2, 0xA4, 0xA5,

0xA7, 0xA8.

GP0: Rx data

GP1: Tx data

GP2: Tx/Rx clock

GP4: interrupt or strobe enabled on sync word detect

(depends on GPIO_CONFIGURE)

XOSC32KP_GP5_ATB1: depends on GPIO_CONFIGURE

Rev. 0 | Page 35 of 100

ADF7023-J

Table 14. GPIO Functionality in Sport Mode

GPIO_CONFIGURE

GP0

GP1

GP2

IRQ_GP3

GP4

XOSC32KP_GP5_ATB1

Not used

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

Rx data

Tx data

Tx/Rx clock

Normal interrupt

generation from

Not used

Interrupt

Strobe

Not used

INTERRUPT_SOURCE_1.

Reduced set from

INTERRUPT_SOURCE_0.

Refer to interrupts in

sport mode.

Not used

Interrupt

Strobe

32.768 kHz XTAL input

EXT_UC_CLK output

Not used

Interrupt

Strobe

PHY_TX

PHY_ON

CMD_PHY_ON

CMD_PHY_TX

PACKET

PA

RAMP

PA

RAMP

300µs

55.4µs

SYNC

WORD

PREAMBLE

PAYLOAD

GP2 (TX CLK)

GP1 (TX DATA)

IRQ_GP3

(CMD_FINISHED INTERRUPT)

GP2 (TX CLK)

GP1 (TX DATA)

Figure 49. Sport Mode Transmit

PHY_RX

PHY_ON

CMD_PHY_RX

CMD_PHY_ON

309µs

55.4µs

SYNC

WORD

PACKET

PREAMBLE

PAYLOAD

GP2 (RX CLK)

GP0 (RX DATA)

GP4

GP2 (RX CLK)

GP0 (RX DATA)

Figure 50. Sport Mode Receive, DATA_MODE = 1, 2 and GPIO_CONFIGURE = 0xA0, 0xA3, or 0xA6

Rev. 0 | Page 36 of 100

ADF7023-J

PHY_RX

PHY_ON

CMD_PHY_RX

CMD_PHY_ON

309µs

55.4µs

SYNC

WORD

PACKET

PREAMBLE

PAYLOAD

GP2 (RX CLK)

GP0 (RX DATA)

GP4 (GPIO_CONFIGURE = 0xA1)

GP4 (GPIO_CONFIGURE = 0xA2)

8/(DATA RATE)

PREAMBLE

DETECTED

GP2 (RX CLK)

GP0 (RX DATA)

GP4 (GPIO_CONFIGURE = 0xA1)

GP4 (GPIO_CONFIGURE = 0xA2)

Figure 51. Sport Mode Receive, DATA_MODE = 1, GPIO_CONFIGURE = 0xA1, 0xA2, 0xA4, 0xA5, 0xA7, 0xA8

PHY_RX

PHY_ON

CMD_PHY_RX

CMD_PHY_ON

309µs

55.4µs

SYNC

WORD

PACKET

PREAMBLE

PAYLOAD

GP2 (RX CLK)

GP0 (RX DATA)

GP4 (GPIO_CONFIGURE = 0xA1)

GP4 (GPIO_CONFIGURE = 0xA2)

GP2 (RX CLK)

GP0 (RX DATA)

GP4 (GPIO_CONFIGURE = 0xA1)

GP4 (GPIO_CONFIGURE = 0xA2)

Figure 52. Sport Mode Receive, DATA_MODE = 2, GPIO_CONFIGURE = 0xA1, 0xA2, 0xA4, 0xA5, 0xA7, 0xA8

Rev. 0 | Page 37 of 100

ADF7023-J

PACKET MODE

The on-chip communications processor can be configured for

use with a wide variety of packet-based radio protocols using

2FSK/GFSK/MSK/GMSK modulation. The general packet

format, when using the packet management features of the

communications processor, is illustrated in Table 16. To use the

packet management features, the DATA_MODE setting in the

PACKET_LENGTH_CONTROL register (Address 0x126)

should be set to packet mode; 240 bytes of dedicated packet

RAM are available to store, transmit, and receive packets. In

transmit mode, preamble, sync word, and CRC can be added by

the communications processor to the data stored in the packet

RAM for transmission. In addition, all packet data after the

sync word can be optionally whitened, Manchester encoded, or

8b/10b encoded on transmission and decoded on reception.

(Address 0x11D). It is necessary to have preamble at the

beginning of the packet to allow time for the receiver AGC,

AFC, and clock and data recovery circuitry to settle before the

start of the sync word. The required preamble length depends

on the radio configuration. See the Radio Blocks section for

more details.

In receive mode, the ADF7023-J can use a preamble qualification

circuit to detect preamble and interrupt the host processor. The

preamble qualification circuit tracks the received frame as a

sliding window. The window is three bytes in length, and the

preamble pattern is fixed at 0x55. The preamble bits are examined

in 01pairs. If either bit or both bits are in error, the pair is deemed

erroneous. The possible erroneous pairs are 00, 11, and 10. The

number of erroneous pairs tolerated in the preamble can be set

using the PREAMBLE_MATCH register value (Address 0x11B)

according to Table 15.

In receive mode, the communications processor can be used to

qualify received packets based on the preamble detection, sync

word detection, CRC detection, or address match and generate

an interrupt on the IRQ_GP3 pin. On reception of a valid packet,

the received payload data is loaded to packet RAM memory.

More information on interrupts is contained in the Interrupt

Generation section.

Table 15. Preamble Detection Tolerance (PREAMBLE_MATCH,

Address 0x11B)

Value

0x0C

0x0B

0x0A

0x09

0x08

0x00

Description

No errors allowed.

One erroneous bit-pair allowed in 12 bit-pairs.

Two erroneous bit-pairs allowed in 12 bit-pairs.

Three erroneous bit-pairs allowed in 12 bit-pairs.

Four erroneous bit-pairs allowed in 12 bit-pairs.

Preamble detection disabled.

PREAMBLE

The preamble is a mandatory part of the packet that is automatically

added by the communications processor when transmitting a

packet and removed after receiving a packet. The preamble is a

0x55 sequence, with a programmable length between 1 byte

and 256 bytes, that is set in the PREAMBLE_LEN register

Table 16. ADF7023-J Packet Structure Description

Packet Structure¹

Payload

Length Address Payload Data CRC

1 bit to 24 bits 1 byte 2 bytes 2 bytes

1 byte to 0 bytes to

Packet Format Options

Preamble Sync

Postamble

Field Length

1 byte to

256 bytes

9 bytes

Yes

X

240 bytes

Optional Field in Packet Structure

X

Yes

X

Yes

X

Yes

X

Comms Processor Adds in Tx, Removes in Rx Yes

Yes

X

Yes

X

Host Writes These Fields to Packet RAM

Whitening/Dewhitening (Optional)

Manchester Encoding/Decoding (Optional)

8b/10b Encoding/Decoding (Optional)

Configurable Parameter

X

Yes

X

Yes

X

Yes

X

Yes

X

Yes

X

Yes

X

Receive Interrupt on Valid Field Detection

Programmable Field Error Tolerance

Programmable Field Offset (See Figure 55)

X

Yes

X

¹Yes indicates that the packet format option is supported, and X indicates that the packet format option is not supported.

Rev. 0 | Page 38 of 100

ADF7023-J

If PREAMBLE_MATCH is set to 0x0C, the ADF7023-J must

receive 12 consecutive 01 pairs (three bytes) to confirm that valid

preamble has been detected. The user can select the option to

automatically lock the AFC and/or AGC once the qualified

preamble is detected. The AFC lock on preamble detection

can be enabled by setting AFC_LOCK_MODE = 3 in the

RADIO_CFG_10 register (Address 0x116). The AGC lock on

preamble detection can be enabled by setting AGC_LOCK_

MODE = 3 in the RADIO_CFG_7 register (Address 0x113).

The value of the sync word is set in the SYNC_BYTE_0,

SYNC_BYTE_1, and SYNC_BYTE_2 registers (Address 0x121,

Address 0x122, and Address 0x123, respectively). The sync word is

transmitted most significant bit first starting with SYNC_BYTE_0.

The sync word matching length at the receiver is set using

SYNC_WORD_LENGTH in the SYNC_CONTROL register

(Address 0x120) and can be one bit to 24 bits long; the transmitted

sync word is a multiple of eight bits. Therefore, for nonbyte

length sync words, the transmitted sync pattern should be

appended with the preamble pattern as described in Figure 53

and Table 18.

After the preamble is detected and the end of preamble has been

reached, the communications processor searches for the sync

word. The search for the sync word lasts for a duration equal to

the sum of the number of programmed sync word bits, plus the

preamble matching tolerance (in bits) plus 16 bits. If the sync

word routine is detected during this duration, the communications

processor loads the received payload to packet RAM and computes

the CRC (if enabled). If the sync word routine is not detected

during this duration, the communications processor continues

searching for the preamble.

In receive mode, the ADF7023-J can provide an interrupt on

reception of the sync word sequence programmed in the

SYNC_BYTE_0, SYNC_BYTE_1, and SYNC_BYTE_2 registers.

This feature can be used to alert the host processor that a qualified

sync word has been received. An error tolerance parameter can

also be programmed that accepts a valid match when up to three

bits of the sync word sequence are incorrect. The error tolerance

value is set using the SYNC_ERROR_TOL setting in the

SYNC_CONTROL register (Address 0x120), as described

in Table 17.

Preamble detection can be disabled by setting the PREAMBLE_

MATCH register to 0x00. To enable an interrupt upon preamble

detection, the user must set INTERRUPT_PREAMBLE_DETECT =

1 in the INTERRUPT_MASK_0 register (Address 0x100).

Table 17. Sync Word Detection Tolerance (SYNC_ERROR_TOL,

Bits[7:6] of Address 0x120)

Value

Description

SYNC WORD

00

01

10

11

No bit errors allowed.

One bit error allowed.

Two bit errors allowed.

Three bit errors allowed.

Sync word is the synchronization word used by the receiver for

byte level synchronization while also providing an optional

interrupt on detection. It is automatically added to the packet

by the communications processor in transmit mode and removed

during reception of a packet.

FIRST BIT SENT

MSB

LSB

24 BITS ≥ SYNC_WORD_LENGTH > 16 BITS

SYNC_BYTE_0

SYNC_BYTE_1

SYNC_BYTE_2

APPEND UNUSED BITS

WITH PREAMBLE (0101..)

MSB

LSB

16 BITS ≥ SYNC_WORD_LENGTH > 8 BITS

SYNC_BYTE_1

SYNC_BYTE_2

APPEND UNUSED BITS

WITH PREAMBLE (0101..)

MSB

SYNC_WORD_LENGTH ≤ 8 BITS

SYNC_BYTE_2

APPEND UNUSED BITS

WITH PREAMBLE (0101..)

Figure 53. Transmit Sync Word Configuration

Rev. 0 | Page 39 of 100

ADF7023-J

Table 18. Sync Word Programming Examples

SYNC_WORD_

LENGTH Bits in

Receiver Sync

Word Match

Length (Bits)

Required Sync Word (Binary,

First Bit Being First in Time)

SYNC_CONTROL SYNC_

SYNC_

SYNC_ Transmitted Sync Word (Binary,

Register (0x120) BYTE_0¹BYTE_1¹BYTE_2 First Bit Being First in Time)

000100100011010001010110 24

0x12

0x5D

0xXX

0x34

0x39

0x12

0x57

0xXX

0x56

0x44

0x34

0x0E

0x12

0x5C

0001_0010_0011_0100_0101_0110 24

0101_1101_0011_1001_0100_0100 21

111010011100101000100

0001001000110100

011100001110

00010010

21

16

12

8

0001_0010_0011_0100

0101_0111_0000_1110

0001_0010

16

12

8

011100

6

0101_1100

6

¹X = don’t care.

The communications processor calculates the actual received

payload length as

Choice of Sync Word

The sync word should be chosen to have low correlation with the

preamble and have good autocorrelation properties. When the AFC

is set to lock on detection of sync word (AFC_LOCK_MODE = 3

and PREAMBLE_MATCH = 0), the sync word should be chosen

to be dc free, and it should have a run length limit not greater

than four bits.

RxPayload Length = Length + LENGTH_OFFSET − 4

where:

Length is the length field (the first byte in the received payload).

LENGTH_OFFSET is a programmable offset (set in the

PACKET_LENGTH_CONTROL register (Address 0x126).

PAYLOAD

The LENGTH_OFFSET value allows compatibility with

systems where the length field in the proprietary packet may

also include the length of the CRC and/or the sync word. The

ADF7023-J defines the payload length as the number of bytes

from the end of the sync word to the start of the CRC. In

variable packet length mode, the PACKET_LENGTH_MAX

value defines the maximum packet length that can be received,

as described in Figure 54.

The host processor writes the transmit data payload to the packet

RAM. The location of the transmit data in the packet RAM is

defined by the TX_BASE_ADR value register (Address 0x124).

The TX_BASE_ADR value is the location of the first byte of the

transmit payload data in the packet RAM. On reception of a

valid sync word, the communications processor automatically

loads the receive payload to the packet RAM. The RX_BASE_ADR

register value (Address 0x125) sets the location in the packet

RAM of the first byte of the received payload. For more details on

packet RAM memory, see the ADF7023-J Memory Map section.

TX PAYLOAD LENGTH = PACKET_LENGTH_MAX

RX PAYLOAD LENGTH = PACKET_LENGTH_MAX

SYNC

WORD

PAYLOAD

PREAMBLE

CRC

FIXED

Byte Orientation

TX PAYLOAD LENGTH = LENGTH

RX PAYLOAD LENGTH = LENGTH + LENGTH_OFFSET – 4

The over-the-air arrangement of each transmitted packet RAM

byte can be set to MSB first or LSB first using the DATA_BYTE

setting in the PACKET_LENGTH_CONTROL register

(Address 0x126). The same orientation setting should be

used on the transmit and receive sides of the RF link.

SYNC

WORD

VARIABLE PREAMBLE

LENGTH

PAYLOAD

CRC

Figure 54. Payload Length in Fixed and Variable Length Packet Modes

Addressing

Packet Length Modes

The ADF7023-J provides a very flexible address matching scheme,

allowing matching of a single address, multiple addresses, and

broadcast addresses. The address information can be included

at any section of the transmit payload. The location of the

starting byte of the address data in the received payload is set in

the ADDRESS_MATCH_OFFSET register (Address 0x129), as

illustrated in Figure 55. The number of bytes in the first address

field is set in the ADDRESS_LENGTH register (Address 0x12A).

These settings allow the communications processor to extract the

address information from the received packet.

The ADF7023-J can be used in both fixed and variable length

packet systems. Fixed or variable length packet mode is set

using the PACKET_LEN variable setting in the PACKET_

LENGTH_CONTROL register (Address 0x126).

For a fixed packet length system, the length of the transmit and

received payload is set by the PACKET_LENGTH_MAX register

(Address 0x127). The payload length is defined as the number

of bytes from the end of the sync word to the start of the CRC.

In variable packet length mode, the communications processor

extracts the length field from the received payload data. In

transmit mode, the length field must be the first byte in the

transmit payload.

Rev. 0 | Page 40 of 100

ADF7023-J

The address data is then compared against a list of known addresses

that are stored in BBRAM (Address 0x12B to Address 0x13D).

Each stored address byte has an associated mask byte, thereby

allowing matching of partial sections of the address bytes,

which is useful for checking broadcast addresses or a family of

addresses that have a unique identifier in the address sequence.

The format and placement of the address information in the

payload data should match the address check settings at the

receiver to ensure exact address detection and qualification.

Table 19 shows the register locations in the BBRAM that are

used for setup of the address checking. When Register 0x12A

(number of bytes in the first address field) is set to 0x00,

address checking is disabled.

Table 20. Example Address Check Configuration

BBRAM

Address

0x129

Value

0x09

0x04

Description

Location in payload of the first address byte

Number of bytes in the first address field,

N_{ADR_1}= 4

0x12A

0x12B

0x12C

0x12D

0x12E

0x12F

0x130

0x131

0x132

0x133

0xAB

0xFF

0xCD

0xFF

0xEF

0xFF

0x01

0xFF

0x04

Address 1 Match Byte 0

Address 1 Mask Byte 0

Address 1 Match Byte 1

Address 1 Mask Byte 1

Address 1 Match Byte 2

Address 1 Mask Byte 2

Address 1 Match Byte 3

Address 1 Mask Byte 3

ADDRESS_MATCH_OFFSET

Number of bytes in the second address

field, N_{ADR_2}= 4

SYNC

WORD

ADDRESS

DATA

PREAMBLE

CRC

0x134

0x135

0x136

0x137

0x138

0x139

0x13A

0x13B

0x13C

0x13D

0xAA

0xFF

0x00

0xXX

Address 2 Match Byte 0

Address 2 Mask Byte 0

Address 2 Match Byte 1

Address 2 Mask Byte 1

Address 2 Match Byte 2

Address 2 Mask Byte 2

Address 2 Match Byte 3

Address 2 Mask Byte 3

End of addresses (indicated by 0x00)

Don’t care

PAYLOAD

Figure 55. Address Match Offset

Table 19. Address Check Register Setup

Address (BBRAM)

Description¹

0x129, ADDRESS_MATCH_

OFFSET

Position of first address byte in the

received packet (first byte after

sync word = 0)

0x12A, ADDRESS_LENGTH

Number of bytes in the first

address field (N_{ADR_1}

)

0x12B

0x12C

0x12D

0x12E

…

Address 1 Match Byte 0

Address 1 Mask Byte 0

Address 1 Match Byte 1

Address 1 Mask Byte 1

…

Address 1 Match Byte N_{ADR_1}− 1

Address 1 Mask Byte N_{ADR_1}− 1

0x00 to end or N_{ADR_2}for another

address check sequence

CRC

An optional CRC-16 can be appended to the packet by setting

CRC_EN =1 in the PACKET_LENGTH_CONTROL register

(Address 0x126). In receive mode, this bit enables CRC detection

on the received packet. A default polynomial is used if

PROG_CRC_EN = 0 in the SYMBOL_MODE register

(Address 0x11C). The default CRC polynomial is

g(x) = x¹⁶+ x¹²+ x⁵+ 1

Any other 16-bit polynomial can be used if PROG_CRC_EN =

1, and the polynomial is set in CRC_POLY_0 and CRC_POLY_1

(Address 0x11E and Address 0x11F, respectively). The setup of

the CRC is described in Table 21.

¹N_{ADR_1}= the number of bytes in the first address field; N_{ADR_2}= the number of

bytes in the second address field.

The host processor should set the INTERRUPT_ADDRESS_

MATCH bit in the INTERRUPT_SOURCE_0 register

(Address 0x336) if an interrupt is required on the IRG_GP3

pin. Additional information on interrupts is contained in the

Interrupt Generation section.

Table 21.CRC Setup

CRC_EN

Bit in the

PACKET_

LENGTH

PROG_

CRC_EN

Bit in the

SYMBOL_

Example Address Check

CONTROL MODE

Consider a system with 32-bit address lengths, in which the first

byte is located in the 10^thbyte of the received payload data. The

system also uses broadcast addresses in which the first byte is

always 0xAA. To match the exact address, 0xABCDEF01 or any

broadcast address in the form 0xAAXXXXXX, the ADF7023-J

must be configured as shown in Table 20.

Description

Register

0

Register

X¹

CRC is disabled in transmit, and CRC

detection is disabled in receive.

1

0

1

CRC is enabled in transmit, and CRC

detection is enabled in receive, with

the default CRC polynomial.

CRC is enabled in transmit, and CRC

detection is enabled in receive, with

the CRC polynomial defined by

CRC_POLY_0 and CRC_POLY_1.

¹X = don’t care.

Rev. 0 | Page 41 of 100

ADF7023-J

To convert a user-defined polynomial to the 2-byte value, the

polynomial should be written in binary format. The x¹⁶coefficient

is assumed equal to 1 and is, therefore, discarded. The remaining

16 bits then make up CRC_POLY_0 (most significant byte) and

CRC_POLY_1 (least significant byte). Two examples of setting

common 16-bit CRCs are shown in Table 22.

POSTAMBLE

The communications processor automatically appends two

bytes of postamble to the end of the transmitted packet. Each

byte of the postamble is 0x55. The first byte is transmitted

immediately after the CRC. The PA ramp-down begins

immediately after the first postamble byte. The second byte

is transmitted while the PA is ramping down.

Table 22. Example Programming of CRC_POLY_0 and

CRC_POLY_1

On the receiver, if the received packet is valid, the RSSI is

automatically measured during the first postamble byte, and the

result is stored in the RSSI_READBACK register (Address 0x312).

The RSSI is measured by the communications processor 17 μs

after the last CRC bit.

Polynomial

Binary Format CRC_POLY_0 CRC_POLY_1

x¹⁶+ x¹⁵+ x²+ 1 1_1000_0000_ 0x80

0x05

(CRC-16-IBM)

0000_0101

x¹⁶+ x¹³+ x¹²

+

1_0011_1101_ 0x3D

0110_0101

0x65

x¹¹x¹⁰+ x⁸+

x⁶+ x⁵+ x²+ 1

(CRC-16-DNP)

TRANSMIT PACKET TIMING

The PA ramp timing in relation to the transmit packet data is

described in Figure 56. After the CMD_PHY_TX command is

issued, a VCO calibration is carried out, followed by a delay for

synthesizer settling. The PA ramp follows the synthesizer settling.

After the PA is ramped up to the programmed rate, there is 1-byte

delay before the start of modulation (preamble). At the beginning

of the second byte of postamble, the PA ramps down. The

communications processor then transitions to the PHY_ON state

or the PHY_RX state (if the TX_TO_RX_AUTO_TURNAROUND

is enabled or the CMD_PHY_RX command is issued).

To enable CRC detection on the receiver, with the default CRC or

user-defined 16-bit CRC, CRC_EN in the PACKET_LENGTH_

CONTROL register (Address 0x126) should be set to 1. An

interrupt can be generated on reception of a CRC verified

packet (see the Interrupt Generation section).

RAMP TIME

1 BYTE

RAMP TIME

~19µs

CMD_PHY_TX

PA OUTPUT

TX DATA

SYNC

WORD

PREAMBLE

PAYLOAD

CRC POSTAMBLE

300µs

142µs

55µs

COMMUNICATIONS

PROCESSOR

PA

RAMP

PA

RAMP

VCO CAL

SYNTH

PHY_TX

= 0x00 (BUSY)

= 0x14 (PHY_TX)

FW_STATE

Figure 56. Transmit Packet Timing

Rev. 0 | Page 42 of 100

ADF7023-J

DATA WHITENING

MANCHESTER ENCODING

Data whitening can be employed to avoid long runs of 1s or

0s in the transmitted data stream. This ensures sufficient bit

transitions in the packet, which aids in receiver clock and data

recovery because the encoding breaks up long runs of 1s or 0s

in the transmit packet. The data, excluding the preamble and

sync word, is automatically whitened before transmission by

XOR’ing the data with an 8-bit pseudorandom sequence. At

the receiver, the data is XOR’ed with the same pseudorandom

sequence, thereby reversing the whitening. The linear feedback

shift register polynomial used is x⁷+ x¹+ 1. Data whitening and

dewhitening are enabled by setting DATA_WHITENING = 1 in

the SYMBOL_MODE register (Address 0x11C).

Manchester encoding can be used to ensure a dc-free (zero mean)

transmission. The encoded over-the-air bit rate (chip rate) is

double the rate set by the DATA_RATE variable (Address 0x10C

and Address 0x10D). A Binary 0 is mapped to 10, and a Binary 1 is

mapped to 01. Manchester encoding and decoding are applied

to the payload data and the CRC. Manchester encoding and

decoding are enabled by setting MANCHESTER_ENC = 1 in

the SYMBOL_MODE register (Address 0x11C).

8b/10b ENCODING

8b/10b encoding is a byte-orientated encoding scheme that

maps an 8-bit byte to a 10-bit data block. It ensures that the

maximum number of consecutive 1s or 0s (that is, run length)

in any 10-bit transmitted symbol is five. The advantage of this

encoding scheme is that dc balancing is employed without the

efficiency loss of Manchester encoding. The rate loss for 8b/10b

encoding is 0.8, whereas for Manchester encoding, it is 0.5.

Encoding and decoding are applied to the payload data and

the CRC. The 8b/10b encoding and decoding are enabled by

setting EIGHT_TEN_ENC =1 in the SYMBOL_MODE register

(Address 0x11C).

Rev. 0 | Page 43 of 100

ADF7023-J

INTERRUPT GENERATION

The ADF7023-J uses a highly flexible, powerful interrupt

system with support for MAC level interrupts and PHY level

interrupts. To enable an interrupt source, the corresponding

mask bit must be set. When an enabled interrupt occurs, the

IRQ_GP3 pin goes high, and the interrupt bit of the status word

is set to Logic 1. The host processor can use either the IRQ_GP3

pin or the status word to check for an interrupt. After an

interrupt is asserted, the ADF7023-J continues operations

unaffected, unless it is directed to do otherwise by the host

processor. An outline of the interrupt source and mask system

is shown in Table 23.

Following an interrupt condition, the host processor should

clear the relevant interrupt flag so that further interrupts assert

the IRQ_GP3 pin. This is performed by writing a Logic 1 to the

bit that is high in either the INTERRUPT_SOURCE_0 or the

INTERRUPT_SOURCE_1 register. If multiple bits in the interrupt

source registers are high, they can be cleared individually or

altogether by writing Logic 1 to them. The IRQ_GP3 pin goes

low when all the interrupt source bits are cleared.

As an example, take the case where a battery alarm (in the

INTERRUPT_SOURCE_1 register) interrupt occurs. The host

processor should do the following:

MAC interrupts can be enabled by writing a Logic 1 to the relevant

bits of the INTERRUPT_MASK_0 register (Address 0x100) and

PHY level interrupts by writing a Logic 1 to the relevant bits of

the INTERRUPT_MASK_1 register (Address 0x101). The

structure of these memory locations is described in Table 23.

1. Read the interrupt source registers. In this example, if none

of the interrupt flags in INTERRUPT_SOURCE_0 are

enabled, only INTERRUPT_SOURCE_1 must be read.

2. Clear the interrupt by writing 0x80 (or 0xFF) to

INTERRUPT_SOURCE_1.

In the case of an interrupt condition, the interrupt source can

be determined by reading the INTERRUPT_SOURCE_0

register (Address 0x336) and the INTERRUPT_SOURCE_1

register (Address 0x337). The bit that corresponds to the

relevant interrupt condition is high. The structure of these two

registers is shown in Table 24.

3. Respond to the interrupt condition.

Table 23. Structure of the Interrupt Mask Registers

Register

Bit

Name

Description

INTERRUPT_MASK_0,

Address 0x100

7

INTERRUPT_NUM_WAKEUPS

Interrupt when the number of WUC wake-ups

(NUMBER_OF_WAKEUPS[15:0]) has reached the threshold

(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])

1: interrupt enabled; 0: interrupt disabled

6

5

INTERRUPT_SWM_RSSI_DET

INTERRUPT_AES_DONE

Interrupt when the measured RSSI during smart wake mode has

exceeded the RSSI threshold value (SWM_RSSI_THRESH,

Address 0x108)

1: interrupt enabled; 0: interrupt disabled

Interrupt when an AES encryption or decryption command is

complete; available only when the AES firmware module has been

loaded to the ADF7023-J program RAM

1: interrupt enabled; 0: interrupt disabled

4

3

2

1

INTERRUPT_TX_EOF

Interrupt when a packet has finished transmitting

1: interrupt enabled; 0: interrupt disabled

INTERRUPT_ADDRESS_MATCH

INTERRUPT_CRC_CORRECT

INTERRUPT_SYNC_DETECT

Interrupt when a received packet has a valid address match

1: interrupt enabled; 0: interrupt disabled

Interrupt when a received packet has the correct CRC

1: interrupt enabled; 0: interrupt disabled

Interrupt when a qualified sync word has been detected in the

received packet

1: interrupt enabled; 0: interrupt disabled

0

INTERRUPT_PREAMBLE_DETECT

Interrupt when a qualified preamble has been detected in the

received packet

1: interrupt enabled; 0: interrupt disabled

Rev. 0 | Page 44 of 100

ADF7023-J

Register

Bit

Name

Description

INTERRUPT_MASK_1,

Address 0x101

7

BATTERY_ALARM

Interrupt when the battery voltage has dropped below the threshold

value (BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D)

1: interrupt enabled; 0: interrupt disabled

6

CMD_READY

Interrupt when the communications processor is ready to load a new

command; mirrors the CMD_READY bit of the status word

1: interrupt enabled; 0: interrupt disabled

5

4

Reserved

WUC_TIMEOUT

Interrupt when the WUC has timed out

1: interrupt enabled; 0: interrupt disabled

3

2

1

Reserved

SPI_READY

Interrupt when the SPI is ready for access

1: interrupt enabled; 0: interrupt disabled

0

CMD_FINISHED

Interrupt when the communications processor has finished

performing a command

1: interrupt enabled; 0: interrupt disabled

Table 24. Structure of the Interrupt Source Registers

Register

Bit

Name

Interrupt Description

INTERRUPT_SOURCE_0,

Address: 0x336

7

INTERRUPT_NUM_WAKEUPS

Asserted when the number of WUC wake-ups

(NUMBER_OF_WAKEUPS[15:0]) has reached the threshold

(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])

6

5

INTERRUPT_SWM_RSSI_DET

INTERRUPT_AES_DONE

Asserted when the measured RSSI during smart wake mode has

exceeded the RSSI threshold value (SWM_RSSI_THRESH,

Address 0x108)

Asserted when an AES encryption or decryption command is

complete; available only when the AES firmware module has been

loaded to the ADF7023-J program RAM

4

3

INTERRUPT_TX_EOF

Asserted when a packet has finished transmitting (packet mode only)

INTERRUPT_ADDRESS_MATCH

Asserted when a received packet has a valid address match (packet

mode only)

2

1

INTERRUPT_CRC_CORRECT

INTERRUPT_SYNC_DETECT

Asserted when a received packet has the correct CRC (packet mode only)

Asserted when a qualified sync word has been detected in the

received packet

0

7

6

INTERRUPT_PREAMBLE_DETECT

BATTERY_ALARM

Asserted when a qualified preamble has been detected in the

received packet

INTERRUPT_SOURCE_1,

Address: 0x337

Asserted when the battery voltage has dropped below the threshold

value (BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D)

CMD_READY

Asserted when the communications processor is ready to load a new

command; mirrors the CMD_READY bit of the status word

5

4

3

2

1

0

Reserved

WUC_TIMEOUT

Reserved

Asserted when the WUC has timed out

Reserved

SPI_READY

CMD_FINISHED

Asserted when the SPI is ready for access

Asserted when the communications processor has finished

performing a command

Rev. 0 | Page 45 of 100

ADF7023-J

on GP4, which gives a dedicated sport mode interrupt on either

preamble or sync word detection. For more details, see the

Sport Mode section.

INTERRUPTS IN SPORT MODE

In sport mode, the interrupts from INTERRUPT_SOURCE_1 are

all available. However, only INTERRUPT_PREAMBLE_DETECT

and INTERRUPT_SYNC_DETECT are available from

Following receipt of the packet in SPORT mode, re-issue the

PHY_RX command to re-enable the interrupts for the next packet.

INTERRUPT_SOURCE_0. A second interrupt pin is provided

Rev. 0 | Page 46 of 100

ADF7023-J

ADF7023-J MEMORY MAP

11-BIT

ADDRESSES

0x3FF

PROGRAM

RAM

MCR

256 BYTES

ADDRESS

[12:0]

2kB

0x300

CS

MISO

MOSI

SCLK

NOT USED

0x13F

PROGRAM

ROM

SPI

4kB

BBRAM

64 BYTES

0x100

SPI/CP

MEMORY

ARBITRATION

0x0FF

COMMS

INSTRUCTION/DATA

[7:0]

PACKET

RAM

PROCESSOR

COMMS

PROCESSOR

CLOCK

256 BYTES

8-BIT

RISC

ENGINE

ADDRESS/

DATA

MUX

ADDRESS[10:0]

DATA[7:0]

0x010

0x00F

RESERVED

0x000

Figure 57. ADF7023-J Memory Map

This section describes the various memory locations used by

the ADF7023-J. The radio control, packet management, and

smart wake mode capabilities of the part are realized using an

integrated RISC processor, which executes instructions stored

in the embedded program ROM. There is also a local RAM,

subdivided into three sections, that is used as a data packet

buffer, both for transmitted and received data (packet RAM),

and for storing the radio and packet management configuration

(BBRAM and MCR). The RAM addresses of these memory

banks are 11 bits long.

MODEM CONFIGURATION RAM (MCR)

The 256-byte modem configuration RAM (MCR) contains the

various registers used for direct control or observation of the

physical layer radio blocks of the ADF7023-J. The contents of

the MCR are not retained in the PHY_SLEEP state.

PROGRAM ROM

The program ROM consists of 4 kB of nonvolatile memory. It

contains the firmware code for radio control, packet management,

and smart wake mode.

BBRAM

PROGRAM RAM

The battery backup RAM contains the main radio and packet

management registers used to configure the radio. On application

of battery power to the ADF7023-J for the first time, the entire

BBRAM should be initialized by the host processor with the

appropriate settings. After the BBRAM is written to, the

CMD_CONFIG_DEV command should be issued to update the

radio and communications processor with the current BBRAM

settings. The CMD_CONFIG_DEV command can be issued in

the PHY_OFF state or the PHY_ON state only.

The program RAM consists of 2 kB of volatile memory. This

memory space is used for software modules, such as AES

encryption, IR calibration, and Reed-Solomon coding, which

are available from Analog Devices. The software modules are

downloaded to the program RAM memory space over the SPI

by the host processor. See the Downloadable Firmware Modules

section for details on loading a firmware module to program RAM.

The BBRAM is used to maintain settings needed at wake-up from

sleep mode by the wake-up controller. Upon wake-up from sleep,

in smart wake mode, the BBRAM contents are read by the on-chip

processor to recover the packet management and radio parameters.

Rev. 0 | Page 47 of 100

ADF7023-J

PACKET RAM

The packet RAM consists of 256 bytes of memory space. The

first 16 bytes of this memory space are allocated for use by the

on-chip processor. The remaining 240 bytes of this memory

space are allocated for storage of data from valid received packets

and packet data to be transmitted. The communications processor

stores received payload data at the memory location indicated

by the value of the RX_BASE_ADR register (Address 0x125),

the receive address pointer. The value of the TX_BASE_ADR

register (Address 0x124), the transmit address pointer, determines

the start address of data to be transmitted by the communications

processor. This memory can be arbitrarily assigned to store

single or multiple transmit or receive packets, with and without

overlap. The RX_BASE_ADR value should be chosen to ensure

that there is enough allocated packet RAM space for the

maximum receiver payload length.

TRANSMIT

AND RECEIVE

PACKET

240 BYTE TRANSMIT

MULTIPLE TRANSMIT

AND RECEIVE

PACKETS

OR RECEIVE

PACKET

TX_BASE_ADR

RX_BASE_ADR

TX_BASE_ADR

(PACKET 1)

TX_BASE_ADR

0x010

TRANSMIT

PAYLOAD

TRANSMIT

PAYLOAD

TX_BASE_ADR

(PACKET 2)

TRANSMIT

PAYLOAD 2

RX_BASE_ADR

(PACKET 1)

TRANSMIT OR

RECEIVE

PAYLOAD

RX_BASE_ADR

PAYLOAD

RECEIVE

PAYLOAD

RX_BASE_ADR

(PACKET 2)

RECEIVE

PAYLOAD 2

0x0FF

Figure 58. Example Packet RAM Configurations Using the Tx Packet and Rx Packet Address Pointers

Rev. 0 | Page 48 of 100

ADF7023-J

SPI INTERFACE

GENERAL CHARACTERISTICS

CS

MOSI

MISO

The ADF7023-J is equipped with a 4-wire SPI interface, using

the SCLK, MISO, MOSI, and

acts as a slave to the host processor. Figure 59 shows an example

connection diagram between the processor and the ADF7023-J.

The diagram also shows the direction of the signal flow for each

pin. The SPI interface is active, and the MISO outputs enabled,

CS

CMD

pins. The ADF7023-J always

IGNORE

Figure 60. Command Write (No Parameters)

STATUS WORD

CS

only while the

input is low. The interface uses a word length

The status word of the ADF7023-J is automatically returned

over the MISO each time a byte is transferred over the MOSI.

Shifting in double SPI_NOP commands (see Table 27) causes

the status word to be shifted out as shown in Figure 61. The

meaning of the various bit fields is illustrated in Table 25. The

FW_STATE variable can be used to read the current state of the

communications processor and is described in Table 26. If it is busy

performing an action or state transition, FW_STATE is busy.

The FW_STATE variable also indicates the current state of the radio.

of eight bits, which is compatible with the SPI hardware of most

processors. The data transfer through the SPI interface occurs

with the most significant bit first. The MOSI input is sampled at

the rising edge of SCLK. As commands or data are shifted in

from the MOSI input at the SCLK rising edge, the status word

or data is shifted out at the MISO pin synchronous with the

CS

SCLK clock falling edge. If is brought low, the most significant

bit of the status word appears on the MISO output without the

need for a rising clock edge on the SCLK input.

The SPI_READY variable is used to indicate when the SPI is ready

for access. The CMD_READY variable is used to indicate when

the communications processor is ready to accept a new command.

The status word should be polled and the CMD_READY bit

examined before issuing a command to ensure that the

communications processor is ready to accept a new command.

It is not necessary to check the CMD_READY bit before issuing

a SPI memory access command. It is possible to queue one

command while the communications processor is busy. This

is discussed in the Command Queuing section.

GPIO

SCLK

MOSI

MISO

IRQ

CS

SCLK

MOSI

MISO

HOST

ADF7023-J

PROCESSOR

IRQ_GP3

Figure 59. SPI Interface Connections

COMMAND ACCESS

The ADF7023-J is controlled through commands. Command

words are single octet instructions that control the state transitions

of the communications processor and access to the registers and

packet RAM. The complete list of valid commands is given in

the Command Reference section. Commands that have a CMD

prefix are handled by the communications processor. Memory

access commands have an SPI prefix and are handled by an

independent controller. Thus, SPI commands can be issued

independent of the state of the communications processor.

The ADF7023-J interrupt handler can also be configured

to generate an interrupt signal on IRQ_GP3 when the

communications processor is ready to accept a new command

(CMD_READY in the INTERRUPT_SOURCE_1 register

[Address 0x337]) or when it has finished processing a command

(CMD_FINISHED in the INTERRUPT_SOURCE_1 register

[Address 0x337]).

CS

A command is initiated by bringing

command word over the SPI, as shown in Figure 60. All commands

CS

low and shifting in the

CS

are executed after

goes high again or at the next positive edge

MOSI

MISO

SPI_NOP

IGNORE

SPI_NOP

STATUS

of the SCLK input. The latter condition occurs in the case of a

memory access command, in which case the command is executed

on the positive SCLK clock edge corresponding to the most

Figure 61. Reading the Status Word Using a Double SPI_NOP Command

CS

significant bit of the first parameter word. The

input must

be brought high again after a command has been shifted into

the ADF7023-J to enable the recognition of successive

command words. This is because a single command can be

Table 25. Status Word

Bit

Name

Description

[7]

SPI_READY

0: SPI is not ready for access.

1: SPI is ready for access.

0: no pending interrupt condition.

1: pending interrupt condition (mirrors

the IRQ_GP3 pin).

CS

issued only during a

low period (with the exception of a

[6]

[5]

IRQ_STATUS

double NOP command).

CMD_READY 0: the radio controller is not ready to

receive a radio controller command.

1: the radio controller is ready to receive a

radio controller command.

[4:0] FW_STATE

Indicates the ADF7023-J state (in Table 26).

Rev. 0 | Page 49 of 100

ADF7023-J

Table 26. FW_STATE Description

COMMAND QUEUING

Value

0x0F

0x00

0x11

0x12

0x13

0x14

0x06

0x05

0x07

0x08

0x09

0x0A

State

The CMD_READY status bit is used to indicate that the command

queue used by the communications processor is empty. The queue

is one command deep. The FW_STATE bit is used to indicate

the state of the communications processor. The operation of the

status word and these bits is illustrated in Figure 62 when a

CMD_PHY_ON command is issued in the PHY_OFF state.

Initializing

Busy, performing a state transition

PHY_OFF

PHY_ON

PHY_RX

PHY_TX

PHY_SLEEP

Operation of the status word when a command is being queued

is illustrated in Figure 63 when a CMD_PHY_ON command is

issued in the PHY_OFF state followed quickly by a CMD_PHY_

RX command. The CMD_PHY_RX command is issued while

FW_STATE is busy (that is, transitioning between the PHY_OFF

and PHY_ON states) but the CMD_READY bit is high, indicating

that the command queue is empty. After the CMD_PHY_RX

command is issued, the CMD_READY bit transitions to a logic

low, indicating that the command queue is full. After the PHY_OFF

to PHY_ON transition is finished, the PHY_RX command is

processed immediately by the communications processor, and

the CMD_READY bit goes high, indicating that the command

queue is empty and another command can be issued.

Performing CMD_GET_RSSI

Performing CMD_IR_CAL

Performing CMD_AES_DECRYPT_INIT

Performing CMD_AES_DECRYPT

Performing CMD_AES_ENCRYPT

ISSUE

CMD_PHY_ON

CS

CMD_READY

FW_STATE

= 0x11 (PHY_OFF)

0xB1

= 0x00 (BUSY)

= 0x12 (PHY_ON)

0xB2

0x80

0xA0

STATUS WORD

TRANSITION RADIO FROM

PHY_OFF TO PHY_ON

COMMUNICATIONS

PROCESSOR ACTION

WAITING FOR COMMAND

Figure 62. Operation of the CMD_READY and FW_STATE Bits in Transitioning the ADF7023-J from the PHY_OFF State to the PHY_ON State

ISSUE

CMD_PHY_ON CMD_PHY_RX

CS

CMD_READY

FW_STATE

0x12

0xB2

= 0x11 (PHY_OFF)

= 0x00 (BUSY)

0xA0

= 0x13 (PHY_RX)

0xB3

STATUS WORD

0xB1

0x80

0xA0

0x80

COMMUNICATIONS

PROCESSOR ACTION

TRANSITION RADIO FROM

PHY_OFF TO PHY_ON

TRANSITION RADIO FROM

PHY_ON TO PHY_RX

WAITING FOR COMMAND

IN PHY_ON, READING

NEW COMMAND

Figure 63. Command Queuing and Operation of the CMD_READY and FW_STATE Bits in Transitioning the ADF7023-J

from the PHY_OFF State to the PHY_ON State and Then to the PHY_RX State

Rev. 0 | Page 50 of 100

ADF7023-J

Block Write

MEMORY ACCESS

MCR, BBRAM, and packet RAM memory locations can be

written to in block format using the SPI_MEM_WR command.

The SPI_MEM_WR command code is 00011xxxb, where xxxb

represent Bits[10:8] of the first 11-bit address. If more than one

data byte is written, the write address is automatically incremented

Memory locations are accessed by invoking the relevant SPI

command. An 11-bit address is used to identify registers or

locations in the memory space. The most significant three bits

of the address are incorporated into the SPI command by

appending them as the LSBs of the command word. Figure 64

illustrates command, address, and data partitioning. The various

SPI memory access commands are different, depending on the

memory location being accessed (see Table 27).

CS

for every byte sent until

is set high, which terminates the

memory access command (see Figure 65 for more details). The

maximum block write for the MCR, packet RAM, and BBRAM

memories is 256 bytes, 256 bytes, and 64 bytes, respectively.

These maximum block-write lengths should not be exceeded.

An SPI command should be issued only if the SPI_READY bit

in the INTERRUPT_SOURCE_1 register (Address 0x337) of

the status word bit is high. The ADF7023-J interrupt handler

can also be configured to generate an interrupt signal on

IRQ_GP3 when the SPI_READY bit is high.

Example

Write 0x00 to the ADC_CONFIG_HIGH register

(Address 0x35A).

An SPI command should not be issued while the communications

processor is initializing (FW_STATE = 0x0F). SPI commands

can be issued in any other communications processor state,

including the busy state (FW_STATE = 0x00). This allows the

ADF7023-J memory to be accessed while the radio is transi-

tioning between states.

•

The first five bits of the SPI_MEM_WR command are 00011.

The 11-bit address of ADC_CONFIG_HIGH is

01101011010.

The first byte sent is 00011011 or 0x1B.

The second byte sent is 01011010 or 0x5A.

The third byte sent is 0x00.

•

Thus, 0x1B, 0x5A, 0x00 is written to the part.

CS

SPI MEMORY ACCESS COMMAND

MEMORY ADDRESS

BITS[7:0]

DATA BYTE

MOSI

5 BITS

MEMORY ADDRESS

BITS[10:0]

DATA

n × 8 BITS

Figure 64. SPI Memory Access Command/Address Format

Table 27. Summary of SPI Memory Access Commands

SPI Command

Command Value

Description

SPI_MEM_WR

0x18 (packet RAM),

0x19 (BBRAM),

0x1B (MCR),

Write data to BBRAM, MCR, or packet RAM sequentially. An 11-bit address is used to

identify memory locations. The most significant three bits of the address are

incorporated into the command (xxxb). This command is followed by the remaining

eight bits of the address.

0x1E (program RAM)

SPI_MEM_RD

0x38 (packet RAM),

0x39 (BBRAM),

0x3B (MCR)

Read data from BBRAM, MCR, or packet RAM sequentially. An 11-bit address is used to

identify memory locations. The most significant three bits of the address are

incorporated into the command (xxxb). This command is followed by the remaining

eight bits of the address, which is subsequently followed by the appropriate number

of SPI_NOP commands.

SPI_MEMR_WR

SPI_MEMR_RD

SPI_NOP

0x08 (packet RAM),

0x09 (BBRAM),

0x0B (MCR)

Write data to BBRAM, MCR, or packet RAM nonsequentially.

0x28 (packet RAM),

0x29 (BBRAM),

0x2B (MCR)

Read data from BBRAM, MCR, or packet RAM nonsequentially.

0xFF

No operation. Use for dummy writes when polling the status word. Also used as

dummy data on the MOSI line when performing a memory read.

Rev. 0 | Page 51 of 100

ADF7023-J

Random Address Write

Random Address Read

MCR, BBRAM, and packet RAM memory locations can be

written to in a nonsequential manner using the SPI_MEMR_WR

command. The SPI_MEMR_WR command code is 00001xxxb,

where xxxb represent Bits[10:8] of the 11-bit address. The lower

eight bits of the address should follow this command and then

the data byte to be written to the address. The lower eight bits of

the next address are entered, followed by the data for that address

until all required addresses within that block are written, as

shown in Figure 66.

MCR, BBRAM, and packet RAM memory locations can be

read from memory in a nonsequential manner using the

SPI_MEMR_RD command. The SPI_MEMR_RD command

code is 00101xxxb, where xxxb represent Bits[10:8] of the 11-bit

address. This command is followed by the remaining eight bits

of the address to be written. Each subsequent address byte is

then written. The last address byte to be written should be

followed by two SPI_NOP commands, as shown in Figure 68.

The data bytes from memory, starting at the first address

location, are available after the second status byte.

Program RAM Write

Example

The program RAM can be written to only by using the memory

block write, as illustrated in Figure 65. SPI_MEM_WR should

be set to 0x1E. See the Downloadable Firmware Modules section

for details on loading a firmware module to program RAM.

Read the value stored in the ADC_CONFIG_HIGH register.

•

The first five bits of the SPI_MEM_RD command are

00111.

Block Read

•

The 11-bit address of ADC_CONFIG_HIGH is

01101011010.

MCR, BBRAM, and packet RAM memory locations can be read

from in block format using the SPI_MEM_RD command. The

SPI_MEM_RD command code is 00111xxxb, where xxxb represent

Bits[10:8] of the first 11-bit address. This command is followed

by the remaining eight bits of the address to be read and then

two SPI_NOP commands (dummy byte). The first byte available

after writing the address should be ignored, with the second

byte constituting valid data. If more than one data byte is to be

read, the write address is automatically incremented for subsequent

SPI_NOP commands sent. See Figure 67 for more details.

•

The first byte sent is 00111011 or 0x3B.

The second byte sent is 01011010 or 0x5A.

The third byte sent is 0xFF (SPI_NOP).

The fourth byte sent is 0xFF.

Thus, 0x3B5AFFFF is written to the part.

The value shifted out on the MISO line while the fourth byte is

sent is the value stored in the ADC_CONFIG_HIGH register.

CS

DATA FOR

SPI_MEM_WR

IGNORE

ADDRESS

STATUS

MOSI

MISO

[ADDRESS]

[ADDRESS + 1]

[ADDRESS + 2]

[ADDRESS + N]

STATUS

Figure 65. Memory (MCR, BBRAM, or Packet RAM) Block Write

CS

MOSI

MISO

DATA FOR

SPI_MEMR_WR

IGNORE

ADDRESS 1

STATUS

ADDRESS 2

STATUS

[ADDRESS 1]

[ADDRESS 2]

[ADDRESS N]

STATUS

Figure 66. Memory (MCR, BBRAM, or Packet RAM) Random Address Write

Rev. 0 | Page 52 of 100

ADF7023-J

MAX N = (256-INITIAL ADDRESS)

SPI_NOP

CS

MOSI

MISO

SPI_MEM_RD

IGNORE

ADDRESS

STATUS

SPI_NOP

STATUS

SPI_NOP

DATA FROM

ADDRESS

DATA FROM

ADDRESS + N

ADDRESS + 1

Figure 67. Memory (MCR, BBRAM, or Packet RAM) Block Read

CS

SPI_MEMR_RD

ADDRESS 1

STATUS

ADDRESS 2

STATUS

ADDRESS 3

ADDRESS 4

ADDRESS N

SPI_NOP

MOSI

DATA FROM

ADDRESS N – 2

DATA FROM

ADDRESS 1

DATA FROM

ADDRESS 2

DATA FROM

ADDRESS N – 1

DATA FROM

ADDRESS N

MISO

IGNORE

Figure 68. Memory (MCR, BBRAM, or Packet RAM) Random Address Read

Rev. 0 | Page 53 of 100

ADF7023-J

LOW POWER MODES

The ADF7023-J can be configured to operate in a broad range

of energy sensitive applications where battery lifetime is critical.

This includes support for applications where the ADF7023-J is

required to operate in a fully autonomous mode or applications

where the host processor controls the transceiver during low power

mode operation. These low power modes are implemented using a

hardware wake-up controller (WUC), a firmware timer, and the

smart wake mode functionality of the on-chip communications

processor. The hardware WUC is a low power WUC that comprises

a 16-bit wake-up timer with a programmable prescaler. The

32.768 kHz RCOSC or XOSC provides the clock source for

the timer.

The WUC and the firmware timer, therefore, provide a real-time

clock capability.

Using the low power WUC and the firmware timer, the SWM

firmware allows the ADF7023-J to wake up autonomously from

sleep without intervention from the host processor. During this

wake-up period, the ADF7023-J is controlled by the communi-

cations processor. This functionality allows carrier sense, packet

sniffing, and packet reception while the host processor is in

sleep, thereby dramatically reducing overall system current

consumption. The smart wake mode can then wake the host

processor on an interrupt condition. An overview of the low

power mode configuration is shown in Figure 69, and the

register settings that are used for the various low power modes

are described in Table 28.

The firmware timer is a software timer residing on the ADF7023-J.

The firmware timer is used to count the number of WUC timeouts

and can be used to count the number of ADF7023-J wake-ups.

Table 28. Settings for Low Power Modes

Low Power Memory

Mode

Address

Register Name

Bit

Description

Deep Sleep 0x30D¹

Modes

WUC_CONFIG_LOW

WUC_BBRAM_EN

0: BBRAM contents are not retained during

PHY_SLEEP.

1: BBRAM contents are retained during

PHY_SLEEP.

WUC

0x30C¹

0x30D¹

WUC_CONFIG_HIGH

WUC_CONFIG_LOW

WUC_PRESCALER[2:0]

WUC_RCOSC_EN

WUC_XOSC32K_EN

WUC_CLKSEL

Sets the prescaler value of the WUC.

Enables the 32.768 kHz RC OSC.

Enables the 32.768 kHz external OSC.

Sets the WUC clock source.

1: RC OSC selected.

2: XOSC selected.

WUC

0x30D¹

WUC_CONFIG_LOW

WUC_ARM

Enable to ensure that the device wakes

from the PHY_SLEEP state on aWUC

timeout.

0x30E²,

0x30F²

WUC_VALUE_HIGH

WUC_VALUE_LOW

WUC_TIMER_VALUE[15:0]

The WUC timer value.

WUC Interval(s) = WUC_TIMER_VALUE ×

(WUC_PRESCALER + 1)

2

32,768

WUC

0x101

0x100

INTERRUPT_MASK_1

INTERRUPT_MASK_0

WUC_TIMEOUT

Enables the interrupt on a WUC timeout.

Firmware

Timer

INTERRUPT_NUM_WAKEUPS

Enabling this interrupt enables the

firmware timer. Interrupt is set when the

NUMBER_OF WAKEUPS count exceeds the

threshold.

Firmware

Timer

0x102,

0x103

NUMBER_OF_WAKEUPS_0

NUMBER_OF_WAKEUPS_1

NUMBER_OF_WAKEUPS[15:0]

Number of ADF7023-J wake-ups.

Firmware

Timer

0x104,

0x105

NUMBER_OF_WAKEUPS_IRQ_ NUMBER_OF_WAKEUPS_IRQ_

Threshold for the number of ADF7023-J

wake-ups. When exceeded, the ADF7023-J

exits low power mode.

THRESHOLD_0

THRESHOLD[15:0]

NUMBER_OF_WAKEUPS_IRQ_

THRESHOLD_1

SWM

0x11A

MODE_CONTROL

SWM_EN

Enables smart wake mode.

SWM_RSSI_QUAL

Enables RSSI prequalification in smart

wake mode.

Rev. 0 | Page 54 of 100

ADF7023-J

Low Power Memory

Mode

Address

Register Name

Bit

Description

SWM

0x108

SWM_RSSI_THRESH

SWM_RSSI_THRESH[7:0]

RSSI threshold for RSSI prequalification.

RSSI threshold (dBm) =

SWM_RSSI_THRESH − 107.

SWM

0x107

0x106

PARMTIME_DIVIDER

RX_DWELL_TIME

PARMTIME_DIVIDER[7:0]

RX_DWELL_TIME[7:0]

Tick rate for the Rx dwell timer.

Time that the ADF7023-J remains awake

during SWM.

Receive Dwell Time = RX_DWELL_TIME ×

6.5 MHz

128 × PARMTIME_DIVIDER

SWM

0x100

INTERRUPT_MASK_0

INTERRUPT_SWM_RSSI_DET

INTERRUPT_PREAMBLE_DETECT

INTERRUPT_SYNC_DETECT

INTERRUPT_ADDRESS_MATCH

Various interrupts that can be used in

SWM.

¹It is necessary to write to the 0x30C and 0x30D registers in the following order: WUC_CONFIG_HIGH (Address 0x30C), directly followed by writing to WUC_CONFIG_LOW

(Address 0x30D).

²It is necessary to write to the 0x30E and 0x30F registers in the following order: WUC_VALUE_HIGH (Address 0x30E), directly followed by writing to WUC_VALUE_LOW

(Address 0x30F).

Rev. 0 | Page 55 of 100

ADF7023-J

INTERRUPT

ADF7023-J

PHY_SLEEP

(IF ENABLED)

HOST

NO

WAIT FOR HOST

COMMAND

BBRAM RETAINED?

YES

WAIT FOR HOST

COMMAND

WUC CONFIGURED?

YES

SET WUC_TIMEOUT

INTERRUPT

INCREMENT

NUMBER_OF_WAKEUPS

SET

YES

NUMBER_OF_WAKEUPS

> THRESHOLD?

WAIT FOR HOST

COMMAND

INTERRUPT_NUM_

WAKEUPS

NO

SWM ENABLED?

(SWM_EN = 1)

NO

YES

RSSI QUAL ENABLED?

(SWM_RSSI_QUAL)

MEASURE RSSI

NO

RSSI > THRESHOLD

(SWM_RSSI_THRESH)

YES

RSSI INT ENABLED?

(INTERRUPT_

SWM_RSSI_DET)

YES

SET INTERRUPT_

SWM_RSSI_DET

WAIT FOR HOST

COMMAND

NO

YES

SET INTERRUPT_

NUM_WAKEUPS

PREAMBLE

DETECTED?

NO AND

RX_DWELL_TIME

EXCEEDED

YES

SET INTERRUPT_

SYNC_DETECT

SYNC WORD

DETECTED?

NO

YES

SET INTERRUPT_

CRC_CORRECT

CRC

CORRECT?

YES

NO

ADDRESS

MATCH?

SET INTERRUPT_

ADDRESS_MATCH

YES

ANY INTERRUPT

SET?

WAIT FOR HOST

COMMAND

NO

TIME IN RX >

RX_DWELL_TIME?

YES

Figure 69. Low Power Mode Operation

Rev. 0 | Page 56 of 100

ADF7023-J

WUC Mode with Firmware Timer

EXAMPLE LOW POWER MODES

In this low power mode, the WUC is used to periodically wake

the ADF7023-J from the PHY_SLEEP state, and the firmware

timer is used to count the number of WUC timeouts. The

combination of the WUC and the firmware timer provides a

real-time clock (RTC) capability.

Deep Sleep Mode 2

Deep Sleep Mode 2 is suitable for applications where the host

processor controls the low power mode timing and the lowest

possible ADF7023-J sleep current is required.

In this low power mode, the ADF7023-J is in the PHY_SLEEP

state. The BBRAM contents are not retained. This low power

mode is entered by issuing the CMD_HW_RESET command

from any radio state. To wake the part from the PHY_SLEEP

The host processor should set up the WUC and the firmware

timer before entering the PHY_SLEEP state. The WUC_

BBRAM_EN bit (Address 0x30D) should be set to 1 to ensure

that the BBRAM is retained. The WUC can be configured to

time out at some standard time interval (for example, 1 sec, 60 sec).

On issuing the CMD_PHY_SLEEP command, the device enters

the PHY_SLEEP state for a period until the hardware timer times

out. At this point, the device wakes up, increments the 16-bit

firmware timer (NUMBER_OF_WAKEUPS_x, Address 0x102 and

Address 0x103) and, if the WUC_TIMEOUT bit (Address 0x101)

is enabled, the device asserts the IRQ_GP3 pin. If the 16-bit

firmware count is less than or equal to the user set threshold

(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_x,

CS

state, the

pin should be set low. The initialization routine

after a CMD_HW_RESET command should be followed, as

detailed in the Radio Control section.

Deep Sleep Mode 1

Deep Sleep Mode 1 is suitable for applications where the host

processor controls the low power mode timing and the ADF7023-J

configuration is retained during the PHY_SLEEP state.

In this low power mode, the ADF7023-J is in the PHY_SLEEP

state with the BBRAM contents retained. Before entering the

PHY_SLEEP state, the WUC_BBRAM_EN bit (Address 0x30D)

should be set to 1 to ensure that the BBRAM is retained. This

low power mode is entered by issuing the CMD_PHY_SLEEP

command from either the PHY_OFF or PHY_ON state. To exit

the PHY_SLEEP state, the

initialization routine should then be followed, as detailed in the

Radio Control section.

Address 0x104 and Address 0x105), the device returns to the

PHY_SLEEP state. With this method, the firmware count

(NUMBER_OF_WAKEUPS_x) equates to a real-time interval.

When the firmware count exceeds the user-set threshold

(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_x), the

ADF7023-J asserts the IRQ_GP3 pin, if the INTERRUPT_NUM_

WAKEUPS bit (Address 0x100) is set, and enters the PHY_OFF

state. The operation of this low power mode is illustrated in

Figure 71.

CS

pin can be set low. The

low

WUC Mode

In this low power mode, the hardware WUC is used to wake the

ADF7023-J from the PHY_SLEEP state after a user-defined duration.

At the end of this duration, the ADF7023-J can provide an

interrupt to the host processor. While the ADF7023-J is in the

PHY_SLEEP state, the host processor can optionally be in a

deep sleep state to save power.

Smart Wake Mode (Carrier Sense Only)

In this low power mode, the WUC, firmware timer, and smart

wake mode are used to implement periodic RSSI measurements

on a particular channel (that is, carrier sense). To enable this

mode, the WUC and firmware timer should be configured before

entering the PHY_SLEEP state. The WUC_BBRAM_EN bit

(Address 0x30D) should be set to 1 to ensure that the BBRAM

is retained. The RSSI measurement is enabled by setting the

SWM_RSSI_QUAL bit = 1 and the SWM_EN bit = 1

(Address 0x11A). The INTERRUPT_SWM_RSSI_DET bit

(Address 0x100) should also be enabled. If the measured

RSSI value is below the user-defined threshold set in the

SWM_RSSI_THRESH register (Address 0x108), the device

returns to the PHY_SLEEP state. If the RSSI measurement is

greater than the SWM_RSSI_THRESH value, the device sets the

INTERRUPT_SWM_RSSI_DET interrupt to alert the host

processor and waits in the PHY_ON state for a host command.

The operation of this low power mode is illustrated in Figure 72.

Before issuing the CMD_PHY_SLEEP command, the host

processor should configure the WUC and set the firmware

timer threshold to zero (NUMBER_OF_WAKEUPS_IRQ_

THRESHOLD_x = 0, Address 0x104 and Address 0x105). The

WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to

ensure that the BBRAM is retained. On issuing the CMD_PHY_

SLEEP command, the device goes to sleep for a period until the

hardware timer times out. At this point, the device wakes up,

and, if the WUC_TIMEOUT bit (Address 0x101) or the

INTERRUPT_NUM_WAKEUPS bit (Address 0x100) interrupts

are enabled, the device asserts the IRQ_GP3 pin.

The operation of this low power mode is illustrated in Figure 70.

Rev. 0 | Page 57 of 100

ADF7023-J

This low power mode terminates when a valid packet interrupt

is received. Alternatively, this low power mode can be terminated

via a firmware timer timeout. This can be useful if certain radio

tasks (for example, IR calibration) or processor tasks must be

run periodically while in the low power mode.

Smart Wake Mode

In this low power mode, the WUC, firmware timer, and smart

wake mode are employed to periodically listen for packets. To

enable this mode, the WUC and firmware timer should be

configured and smart wake mode (SWM) enabled (the SWM_EN

bit, Address 0x11A) before entering the PHY_SLEEP state. The

WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to

ensure that the BBRAM is retained. RSSI prequalification can

be optionally enabled (SWM_RSSI_QUAL = 1, Address 0x11A).

When RSSI prequalification is enabled, the ADF7023-J begins

searching for the preamble only if the RSSI measurement is

greater than the user-defined threshold.

The operation of this low power mode is illustrated in Figure 73.

Exiting Low Power Mode

As described in Figure 69, the ADF7023-J waits for a host

command on any of the termination conditions of the low power

mode. It is also possible to perform an asynchronous exit from

low power mode using the following procedure:

CS

1. Bring the

pin of the SPI low and wait until the MISO

The ADF7023-J is in the PHY_RX state for a duration deter-

mined by the RX_DWELL_TIME setting (Address 0x106).

If the ADF7023-J detects the preamble during the receive dwell

time, it searches for the sync word. If the sync word routine is

detected, the ADF7023-J loads the received data to packet RAM

and checks for a CRC and address match, if enabled. If any of

the receive packet interrupts has been set, the ADF7023-J

returns to the PHY_ON state and waits for a host command.

output goes high.

2. Issue a CMD_HW_RESET command.

The host processor should then follow the initialization

procedure after a CMD_HW_RESET command, as described in

the Initialization section.

If the ADF7023-J receives preamble detection during the receive

dwell time but the remainder of the received packet extends

beyond the dwell time, the ADF7023-J extends the dwell time

until all of the packet is received or the packet is recognized as

invalid (for example, there is an incorrect sync word).

Rev. 0 | Page 58 of 100

ADF7023-J

LOW POWER MODE TIMING DIAGRAMS

HOST: CMD_PHY_SLEEP

HOST: START WUC

ADF7023-J

OPERATION

PHY_OFF OR PHY_ON

PHY_SLEEP

PHY_OFF

WUC TIMEOUT PERIOD

INTERRUPT

WUC_TIMEOUT

(IF ENABLED)

INTERRUPT

INTERRUPT_NUM_WAKEUPS

(IF ENABLED AND

NUMBER_OF_WAKEUPS_IRQ_THRESHOLD = 0)

Figure 70. Low Power Mode Timing When Using the WUC

HOST: CMD_PHY_SLEEP

HOST: START WUC

INCREMENT

FIRMWARE TIMER

INCREMENT

FIRMWARE TIMER

> THRESHOLD

PHY_OFF OR

ADF7023-J

PHY_SLEEP

PHY_OFF

PHY_ON

OPERATION

WUC TIMEOUT PERIOD

WUC TIMEOUT PERIOD × NUMBER_OF_WAKEUPS_IRQ_THRESHOLD

REAL TIME INTERNAL

INTERRUPT_

NUM_WAKEUPS

Figure 71. Low Power Mode Timing When Using the WUC and the Firmware Timer

HOST: CMD_PHY_SLEEP

HOST: START WUC

RSSI ≤ THRESHOLD

RSSI > THRESHOLD

PHY_OFF OR

PHY_ON

ADF7023-J

OPERATION

PHY_SLEEP

RSSI

PHY_SLEEP

RSSI

PHY_SLEEP

RSSI

PHY_ON

WUC TIMEOUT PERIOD

INTERRUPT_

SWM_RSSI_DET

Figure 72. Low Power Mode Timing When Using the WUC, Firmware Timer, and SWM with Carrier Sense

HOST: CMD_PHY_SLEEP

HOST: START WUC

NO PACKET

DETECTED

NO PACKET

DETECTED

PACKET

DETECTED

PHY_OFF OR

PHY_ON

ADF7023-J

OPERATION

PHY_SLEEP

RX

PHY_SLEEP

RX

PHY_SLEEP

PHY_ON

WUC TIMEOUT PERIOD

INTERRUPT_

SWM_RSSI_DET

INTERRUPT_

PREAMBLE_DETECT

INTERRUPT_

SYNC_DETECT

INTERRUPT_

CRC_CORRECT

INTERRUPT_

ADDRESS_MATCH

INIT

PHY_RX

RECEIVE DWELL TIME

(RX_DWELL_TIME)

Figure 73. Low Power Mode Timing When Using the WUC, Firmware Timer, and SWM

Rev. 0 | Page 59 of 100

ADF7023-J

The relevant fields of each register are detailed in Table 29. All

four of these registers are write only.

WUC SETUP

Circuit Description

The WUC should be configured as follows:

The ADF7023-J features a low power wake-up controller

comprising a 16-bit wake-up timer with a 3-bit programmable

prescaler, as illustrated in Figure 74. The prescaler clock source

can be configured to use either the 32.76 kHz internal RC oscillator

(RCOSC) or the 32.76 kHz external oscillator (XOSC). This

combination of programmable prescaler and 16-bit down counter

gives a total hardware timer range of 30.52 μs to 36.4 hours.

1. Clear all interrupts.

2. Set required interrupts.

3. Write to WUC_CONFIG_HIGH and WUC_CONFIG_

LOW. Ensure that the WUC_ARM bit = 1. Ensure that the

WUC_BBRAM_EN bit = 1 (retain BBRAM during

PHY_SLEEP). It is necessary to write to both registers

together in the following order: WUC_CONFIG_HIGH

directly followed by writing to WUC_CONFIG_LOW.

4. Write to WUC_VALUE_HIGH and WUC_VALUE_LOW.

This configures the WUC_TIMER_VALUE[15:0] and,

thus, the WUC timeout period. The timer begins counting

from the configured value after these registers have been

written to. It is necessary to write to both registers together

in the following order: WUC_VALUE_HIGH directly

followed by writing to WUC_VALUE_LOW.

Configuration and Operation

The hardware WUC is configured via the following registers:

•

WUC_CONFIG_HIGH (Address 0x30C)

WUC_CONFIG_LOW (Address 0x30D)

WUC_VALUE_HIGH (Address 0x30E)

WUC_VALUE_LOW (Address 0x30F)

WUC

WUC_VALUE_HIGH

WUC_VALUE_LOW

WUC_CONFIG_LOW[4]

16-BIT

WUC_CONFIG_HIGH[2:0]

RELOAD VALUE

1

0

RC OSCILLATOR

32kHz XTAL

TICK RATE

32.768kHz

ADF7023-J

WAKE-UP CIRCUIT

16-BIT DOWN

COUNTER

PRESCALER

WUC_TIMEOUT

INTERRUPT

TO FIRMWARE TIMER

Figure 74. Hardware Wake-Up Controller (WUC)

Table 29. WUC Register Settings

WUC Setting

Name

Description

WUC_VALUE_HIGH [7:0]

WUC_TIMER_VALUE[15:8]

WUC timer value.

(WUC_PRESCALER + 1)

2

WUC Interval(s) = WUC_TIMER_VALUE ×

32,768

WUC_VALUE_LOW[7:0]

WUC_CONFIG_HIGH[7:3]

WUC_CONFIG_HIGH[2:0]

WUC_TIMER_VALUE[7:0]

Reserved

WUC timer value.

Set to 0.

WUC_PRESCALER

32.768 kHz Divider

Tick Period

30.52 μs

122.1 μs

244.1 μs

488.3 μs

3.91 ms

000

001

010

011

100

101

110

111

1

4

8

16

128

1034

8192

65,536

31.25 ms

250 ms

2000 ms

Rev. 0 | Page 60 of 100

ADF7023-J

WUC Setting

Name

Description

WUC_CONFIG_LOW[7]

WUC_CONFIG_LOW[6]

Reserved

Set to 0.

WUC_RCOSC_EN

1: enable.

0: disable RCOSC32K.

1: enable.

WUC_CONFIG_LOW[5]

WUC_CONFIG_LOW[4]

WUC_CONFIG_LOW [3]

WUC_XOSC32K_EN

WUC_CLKSEL

0: disable XOSC32K.

1: RC 32.768 kHz oscillator.

0: external crystal oscillator.

WUC_BBRAM_EN

1: enable power to BBRAM during the PHY_SLEEP state.

0: disable power to BBRAM during the PHY_SLEEP state.

Set to 0.

WUC_CONFIG_LOW[2:1]

WUC_CONFIG_LOW[0]

Reserved

WUC_ARM

1: enable wake-up on WUC timeout event.

0: disable wake-up on WUC timeout event.

interrupts the host processor. At each wake-up, the ADF7023-J

increments the NUMBER_OF_WAKEUPS[15:0] registers

(Address 0x102 and Address 103). If this value exceeds the value

set by the NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0]

registers, the NUMBER_OF_WAKEUPS[15:0] value is cleared

to 0. At this time, if the INTERRUPT_NUM_WAKEUPS bit in

the INTERRUPT_MASK_0 register (Address 0x100) is set, the

device asserts the IRQ_GP3 pin and enters the PHY_OFF state.

FIRMWARE TIMER SETUP

The ADF7023-J wakes up from the PHY_SLEEP state at the rate

set by the WUC. A firmware timer, implemented by the on-chip

processor, can be used to count the number of hardware wake-ups

and generate an interrupt to the host processor. Thus, the

ADF7023-J can be used to handle the wake-up timing of the

host processor, reducing overall system power consumption.

To set up the firmware timer, the host processor must set a value

in the NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0]

registers (Address 0x104 and Address 0x105). This 16-bit value

represents the number of times the device wakes up before it

Rev. 0 | Page 61 of 100

ADF7023-J

DOWNLOADABLE FIRMWARE MODULES

The program RAM memory of the ADF7023-J can be used to

store firmware modules for the communications processor that

provide the ADF7023-J with extra functionality. The binary

code for these firmware modules and details on their functionality

are available from Analog Devices. These firmware modules are

included in the Applications Software, which is available online

at ftp://ftp.analog.com/pub/RFL/ADF7023/. Three modules are

briefly described in this section: image rejection calibration,

AES encryption and decryption, and Reed-Solomon coding.

AES ENCRYPTION AND DECRYPTION MODULE

The downloadable AES firmware module supports 128-bit block

encryption and decryption with key sizes of 128 bits, 192 bits,

and 256 bits. Two modes are supported: ECB mode and CBC

Mode 1. ECB mode simply encrypts/decrypts on a 128-bit block

by block with a single secret key as illustrated in Figure 76. CBC

Mode 1 encrypts after first adding (Modulo 2), a 128-bit user-

supplied initialization vector. The resulting cipher text is then

used as the initialization vector for the next block and so forth,

as illustrated in Figure 77. Decryption provides the inverse

functionality. The firmware also takes advantage of an on-chip

hardware accelerator module to enhance throughput and minimize

the latency of the AES processing.

WRITING A MODULE TO PROGRAM RAM

The sequence to write a firmware module to program RAM is

as follows:

1. Ensure that the ADF7023-J is in PHY_OFF.

2. Issue the CMD_RAM_LOAD_INIT command.

3. Write the module to program RAM using an SPI memory

block write (see the SPI Interface section).

4. Issue the CMD_RAM_LOAD_DONE command.

5. Issue the CMD_SYNC command.

REED-SOLOMON CODING MODULE

This coding module uses Reed-Solomon block coding to detect

and correct errors in the received packet. A transmit message of

k bytes in length is appended with an error checking code (ECC) of

length n − k bytes to give a total message length of n bytes, as

shown in Figure 75.

The firmware module is now stored on program RAM.

n BYTES

IMAGE REJECTION CALIBRATION MODULE

SYNC

PREAMBLE

ECC

PAYLOAD

WORD

The calibration system initially disables the ADF7023-J receiver,

and an internal RF source is applied to the RF input at the

image frequency. The algorithm then maximizes the receiver

image rejection performance by iteratively minimizing the

quadrature gain and phase errors in the polyphase filter.

k BYTES

(n – k) BYTES

Figure 75. Packet Structure with Appended Reed-Solomon ECC

The receiver decodes the ECC to detect and correct up to t bytes

in error, where t = (n − k)/2. The firmware supports correction

of up to five bytes in the n byte field. To correct t bytes in error,

an ECC length of 2t bytes is required, and the byte errors can be

randomly distributed throughout the payload and ECC fields.

The calibration algorithm takes its initial estimates for quadrature

phase correction (Address 0x118) and quadrature gain correction

(Address 0x119) from BBRAM. After calibration, new optimum

values of phase and gain are loaded back into these locations.

These calibration values are maintained in BBRAM during

sleep mode and are automatically reapplied from a wake-up

event, which keeps the number of calibrations required to a

minimum.

Reed-Solomon coding exhibits excellent burst error correction

capability and is commonly used to improve the robustness of a

radio link in the presence of transient interference or due to

rapid signal fading conditions that can corrupt sections of the

message payload.

Depending on the initial values of quadrature gain and phase

correction, the calibration algorithm can take approximately 20 ms

to find the optimum image rejection performance. However, the

calibration time can be significantly less than this when the seed

values used for gain and phase correction are close to optimum.

Reed-Solomon coding is also capable of improving the receiver’s

sensitivity performance by several dB, where random errors

tend to dominate under low SNR conditions and the receiver’s

packet error rate performance is limited by thermal noise.

The number of consecutive bit errors that can be 100ꢀ corrected is

{(t − 1) × 8 + 1}. Longer, random bit-error patterns, up to t bytes,

can also be corrected if the error patterns start and end at byte

boundaries.

The image rejection performance is also dependent on temperature.

To maintain optimum image rejection performance, a calibration

should be activated whenever a temperature change of more than

10°C occurs. The ADF7023-J on-chip temperature sensor can

be used to determine when the temperature exceeds this limit.

The firmware also takes advantage of an on-chip hardware

accelerator module to enhance throughput and minimize the

latency of the Reed-Solomon processing.

To run the IR calibration, issue a CMD_IR_CAL (Register 0xBD).

In order for this to work successfully, ensure that the BB filter

calibration is enabled in the MODE_CONTROL register

(Address 0x11A).

Rev. 0 | Page 62 of 100

ADF7023-J

ECB MODE

128 BITS

PLAIN TEXT

128 BITS

KEY

AES

ENCRYPT

128 BITS

CIPHER TEXT

Figure 76. ECB Mode

CBC MODE 1

128 BITS

PLAIN TEXT

128 BITS

INITIAL VECTOR

+

KEY

AES

ENCRYPT

128 BITS

CIPHER TEXT

Figure 77. CBC Mode 1

Rev. 0 | Page 63 of 100

ADF7023-J

RADIO BLOCKS

Synthesizer Bandwidth

FREQUENCY SYNTHESIZER

The synthesizer loop filter is fully integrated on chip and has a

programmable bandwidth. The communications processor

automatically sets the bandwidth of the synthesizer when the device

enters the PHY_TX or the PHY_RX state. Upon entering the

PHY_TX state, the communications processor chooses the band-

width based on the programmed modulation scheme (2FSK or

GFSK) and the data rate. This ensures optimum modulation quality

for each data rate. Upon entering the PHY_RX state, the

communications processor sets a narrow bandwidth to ensure best

receiver rejection. In all, there are eight bandwidth configurations.

Each synthesizer bandwidth setting is described in Table 30.

A fully integrated RF frequency synthesizer is used to generate

both the transmit signal and the receiver’s local oscillator (LO)

signal. The architecture of the frequency synthesizer is shown in

Figure 78.

The receiver uses a fractional-N frequency synthesizer to generate

the mixer’s LO for down conversion to the intermediate frequency

(IF) of 200 kHz or 300 kHz. In transmit mode, a high resolution

sigma-delta (Σ-Δ) modulator is used to generate the required

frequency deviations at the RF output when FSK data is trans-

mitted. To reduce the occupied FSK bandwidth, the transmitted

bit stream can be filtered using a digital Gaussian filter, which is

enabled via the RADIO_CFG_9 register (Address 0x115). The

Gaussian filter uses a bandwidth time (BT) of 0.5.

Table 30. Automatic Synthesizer Bandwidth Selections

Closed-Loop

Synthesizer

Bandwidth (kHz)

Data Rate

(kbps)

The VCO and the PLL loop filter of the ADF7023-J are fully

integrated. To reduce the effect of pulling of the VCO by the

power-up of the PA and to minimize spurious emissions, the

VCO operates at twice the RF frequency. The VCO signal is

then divided by 2, giving the required frequency for the

transmitter and the required LO frequency for the receiver.

Description

Rx 2FSK/GFSK/MSK/GMSK All

92

Tx 2FSK/GFSK/MSK/GMSK

1 to 49.5

49.6 to 99.1

99.2 to 129.5

129.6 to 179.1 226

179.2 to 239.9 305

130

174

A high speed, fully automatic calibration scheme is used to

ensure that the frequency and amplitude characteristics of the

VCO are maintained over temperature, supply voltage, and

process variations.

240 to 300

382

For performance margin to the T96 specification limits, the PLL

closed-loop bandwidth is optimized depending on the data rate.

The calibration is automatically performed when the

CMD_PHY_RX or the CMD_PHY_TX command is

issued. The calibration duration is 142 μs, and if required,

the CALIBRATION_STATUS register (Address 0x339) can be

polled to indicate the completion of the VCO self calibration.

After the VCO is calibrated, the frequency synthesizer settles

to within 5 ppm of the target frequency in 56 μs.

The following procedure must be used to program the device

for optimized PLL bandwidth settings during transmit operation.

As part of the initial BBRAM configuration, do the following:

•

Issue the SPI_MEM_WR command, writing 0x2 to Bits[5:4]

of Register 0x113 (RADIO_CFG_7).

•

Issue the CMD_CONFIG_DEV command.

VCO

CALIBRATION

The custom transmit LUT must be written to the 0x010 to 0x018

packet RAM locations. This is achieved using a SPI_MEM_WR

command and a block write as described in the Memory Access

section. The LUT values are described in Table 31.

RF

FREQ

26MHz

REF

CHARGE

PUMP

PFD

÷2

VCO

LOOP

FILTER

These values are retained in memory while VDDBAT remains

valid, unless PHY_SLEEP is entered; in which case, the values

must be reprogrammed.

N DIVIDER

÷2

TX

DATA

FRAC-N

Table 31. T96 Custom Transmit Look-Up Table (LUT)

Σ-∆ DIVIDER

GAUSSIAN

FILTER

Data Rate = 50 kbps or

Data Rate = 200 kbps

INTEGER-N

Register 100 kbps (CLBW = 130 kHz) (CLBW = 223 kHz)

F_DEVIATION

0x010

0x011

0x012

0x013

0x014

0x015

0x016

0x017

0x018

0x10

0x0F

0x1F

0x0F

0x1F

0x33

0x22

0x20

0x0F

0x1F

0x05

0x1F

0x33

0x18

Figure 78. RF Frequency Synthesizer Architecture

Rev. 0 | Page 64 of 100

ADF7023-J

Synthesizer Settling

load capacitance of the crystal, usually 10 pF to 20 pF. Track

capacitance values vary from 2 pF to 5 pF, depending on board

layout. The total load capacitance is described by

After the VCO calibration, a 56 μs delay is allowed for synthesizer

settling. This delay is fixed at 56 μs by default and ensures that

the synthesizer has fully settled when using any of the default

synthesizer bandwidths.

C_PIN

2

1

C_LOAD

=

+

+C_PCB

1

+

C1 C2

However, in some cases, it may be necessary to use a custom

synthesizer settling delay. To use a custom delay, set the CUSTOM_

TRX_SYNTH_LOCK_TIME EN bit to 1 in the MODE_CONTROL

register (Address 0x11A). The synthesizer settling delays for the

PHY_RX and the PHY_TX state transitions can be set independently

in the RX_SYNTH_LOCK_TIME register (Address 0x13E) and

the TX_SYNTH_LOCK_TIME register (Address 0x13F). The

settling time can be set in the 2 μs to 512 μs range in steps of 2 μs.

where:

_LOADis the total load capacitance.

C1 and C2 are the external crystal load capacitors.

_PINis the ADF7023-J input capacitance of the XOSC26P and

XOSC26N pins and is equal to 2.1 pF.

_PCBis the PCB track capacitance.

C

When possible, choose capacitors that have a very low

temperature coefficient to ensure stable frequency operation

over all conditions.

Bypassing VCO Calibration

It is possible to bypass the VCO calibration for ultrafast frequency

hopping in transmit or receive. The calibration data for each RF

channel should be stored in the host processor memory. The

calibration data comprises two values: the VCO band select

value and the VCO amplitude level.

The crystal frequency error can be corrected by means of an

integrated digital tuning varactor. For a typical crystal load

capacitance of 10 pF, a tuning range of −15 ppm to +11.25 ppm

is available via programming of a 3-bit DAC, according to Table 32.

The 3-bit value should be written to the XOSC_CAP_DAC bits

in the OSC_CONFIG register (Address 0x3D2).

Read and Store Calibration Data

1. Go to the PHY_TX or the PHY_RX state without bypassing

the VCO calibration.

2. Read the following MCR registers and store the calibrated

data in memory on the host processor:

Alternatively, any error in the RF frequency due to crystal error

can be adjusted for by offsetting the RF channel frequency using

the RF channel frequency setting in BBRAM memory.

a. VCO_BAND_READBACK (Address 0x3DA)

b. VCO_AMPL_READBACK (Address 0x3DB)

Table 32. Crystal Frequency Pulling Programming

XOSC_CAP_DAC

Pulling (ppm)

Bypassing VCO Calibration on CMD_PHY_TX or

CMD_PHY_RX

000

001

010

011

100

101

110

111

+15

+11.25

+7.5

+3.75

0

−3.75

−7.5

1. Ensure that the BBRAM is configured.

2. Set VCO_OVRW_EN (Address 0x3CD) = 0x3.

3. Set VCO_CAL_CFG (Address 0x3D0) = 0x0F.

4. Set VCO_BAND_OVRW_VAL (Address 0x3CB) = stored

VCO_BAND_READBACK (Address 0x3DA) for that

channel.

−11.25

5. Set VCO_AMPL_OVRW_VAL (Address 0x3CC) = stored

VCO_AMPL_READBACK (Address 0x3DB) for that

channel.

MODULATION

The ADF7023-J supports binary frequency shift keying (2FSK),

minimum shift keying (MSK), binary level Gaussian filtered

2FSK (GFSK), and Gaussian filtered MSK (GMSK). The desired

transmit and receive modulation formats are set in the

RADIO_CFG_9 register (Address 0x115).

6. Set SYNTH_CAL_EN = 0 (in the CALIBRATION_

CONTROL register, Address 0x338).

7. Set SYNTH_CAL_EN = 1 (in the CALIBRATION_

CONTROL register, Address 0x338).

8. Issue CMD_PHY_TX or CMD_PHY_RX to go to the

PHY_TX or PHY_RX state without the VCO calibration.

When using 2FSK/GFSK/MSK/GMSK modulation, the frequency

deviation can be set using the FREQ_DEVIATION[11:0] bits

in the RADIO_CFG_1 register (Address 0x10D) and the

RADIO_CFG_2 register (Address 0x10E). The data rate can be

set in the 1 kbps to 300 kbps range using the DATA_RATE[11:0]

parameter in the RADIO_CFG_0 register (Address 0x10C) and

RADIO_CFG_1 register (Address 0x10D). For GFSK/GMSK

modulation, the Gaussian filter uses a fixed BT of 0.5.

CRYSTAL OSCILLATOR

A 26 MHz crystal oscillator operating in parallel mode must be

connected between the XOSC26P and XOSC26N pins. Two

parallel loading capacitors are required for oscillation at the

correct frequency. Their values are dependent upon the crystal

specification. They should be chosen to ensure that the shunt

value of capacitance added to the PCB track capacitance and the

input pin capacitance of the ADF7023-J equals the specified

Rev. 0 | Page 65 of 100

ADF7023-J

RF OUTPUT STAGE

PA/LNA INTERFACE

Power Amplifier (PA)

The ADF7023-J supports both single-ended and differential PA

outputs. Only one PA can be active at a time. The differential

PA and LNA share the same pins, RFIO_1P and RFIO_1N,

which facilitate a simpler antenna interface. The single-ended

PA output is available on the RFO2 pin. A number of PA/LNA

antenna matching options are possible and are described in the

PA/LNA Matching section.

The ADF7023-J PA can be configured for single-ended or

differential output operation using the PA_SINGLE_DIFF_SEL

bit in the RADIO_CFG_8 register (Address 0x114). The PA level

is set by the PA_LEVEL bit in the RADIO_CFG_8 register and

has a range of 0 to 15. For finer control of the output power

level, the PA_LEVEL_MCR register (Address 0x307) can be

used. It offers more resolution with a setting range of 0 to 63.

The relationship between the PA_LEVEL and PA_LEVEL_MCR

settings is given by

RECEIVE CHANNEL FILTER

The channel filter of the receiver is a fourth-order, active polyphase

Butterworth filter with programmable bandwidths of 100 kHz,

150 kHz, 200 kHz, and 300 kHz. The fourth-order filter gives very

good interference suppression of adjacent and neighboring channels

and also suppresses the image channel by approximately 36 dB at a

100 kHz IF bandwidth and an RF frequency of 915 MHz.

PA_LEVEL_MCR = 4 × PA_LEVEL + 3

The single-ended configuration can deliver 13.5 dBm output

power. The differential PA can deliver 10 dBm output power

and allows a straightforward interface to dipole antennae. The

two PA configurations offer a Tx antenna diversity capability.

Note that the two PAs cannot be enabled at the same time.

For channel bandwidths of 100 kHz to 200 kHz, an IF frequency

of 200 kHz is used, which results in an image frequency located

400 kHz below the wanted RF frequency. When the 300 kHz

bandwidth is selected, an IF frequency of 300 kHz is used, and

the image frequency is located at 600 kHz below the wanted

frequency.

Automatic PA Ramp

The ADF7023-J has built-in up and down PA ramping for both

single-ended and differential PAs. There are eight ramp rate

settings, with the ramp rate defined as a certain number of PA

power level settings per data bit period. The PA_RAMP

variable in the RADIO_CFG_8 register (Address 0x114)

sets this PA ramp rate, as illustrated in Figure 79.

The bandwidth and center frequency of the IF filter are calibrated

automatically after entering the PHY_ON state if the BB_CAL

bit is set in the MODE_CONTROL register (Address 0x11A).

The filter calibration time takes 100 μs.

1

2

3

4

...

8

... 16

DATA BITS

The IF bandwidth is programmed by setting the IFBW field in

the RADIO_CFG_9 register (Address 0x115). The filter’s pass

band is centered at an IF frequency of 200 kHz when bandwidths

of 100 kHz to 200 kHz are used and centered at 300 kHz when

an IF bandwidth of 300 kHz is used.

PA RAMP 1

(256 CODES PER BIT)

PA RAMP 2

(128 CODES PER BIT)

PA RAMP 3

(64 CODES PER BIT)

IMAGE CHANNEL REJECTION

PA RAMP 4

(32 CODES PER BIT)

The ADF7023-J is capable of providing improved receiver image

rejection performance by the use of a fully integrated image

rejection calibration system under the control of the on-chip

communications processor. To operate the calibration system, a

firmware module is downloaded to the on-chip program RAM.

The firmware download is supplied by Analog Devices and

described in the Downloadable Firmware Modules section.

PA RAMP 5

(16 CODES PER BIT)

PA RAMP 6

(8 CODES PER BIT)

PA RAMP 7

(4 CODES PER BIT)

Figure 79. PA Ramp for Different PA_RAMP Settings

The PA ramps to the level set by the PA_LEVEL or PA_LEVEL_

MCR settings. Enabling the PA ramp reduces spectral splatter

and helps meet radio regulations, which limit PA transient

spurious emissions. To ensure optimum performance, an

adequately long PA ramp rate is required based on the data rate

and the PA output power setting. The PA_RAMP setting should,

therefore, be set such that

AUTOMATIC GAIN CONTROL (AGC)

AGC is enabled by default and keeps the receiver gain at the

correct level by selecting the LNA, mixer, and filter gain settings

based on the measured RSSI level. The LNA has three gain levels,

the mixer has two gain levels, and the filter has three gain levels.

In all, there are six AGC stages, which are defined in Table 33.

Table 33. AGC Gain Modes

PA_LEVEL_MCR[5 : 0]

DATA_RATE[11: 0]

Ramp Rate (Codes/Bit) < 2500 ×

Gain Mode

LNA Gain

Mixer Gain

Filter Gain

1

2

3

4

5

6

High

Medium

Low

High

Low

High

Medium

Low

where PA_LEVEL_MCR is related to the PA_LEVEL setting by

PA_LEVEL_MCR = 4 × PA_LEVEL + 3.

Low

Rev. 0 | Page 66 of 100

ADF7023-J

The AGC remains at each gain stage for a time defined by the

AGC_CLK_DIVIDE register (Address 0x32F). The default

value of AGC_CLK_DIVIDE = 0x28 gives an AGC delay of

25 ꢁs. When the RSSI is above AGC_HIGH_THRESHOLD

(Address 0x35F), the gain is reduced. When the RSSI is below

AGC_LOW_THRESHOLD (Address 0x35E), the gain is increased.

RSSI Method 2

The CMD_GET_RSSI command can be used from the PHY_ON

state to read the RSSI. This RSSI measurement method uses

additional low-pass filtering, resulting in a more accurate RSSI

reading. The RSSI result is loaded to the RSSI_READBACK

register (Address 0x312) by the communications processor.

The RSSI_READBACK register contains a twos complement

value and can be converted to input power in dBm using the

following formula:

The AGC can be configured to remain active while in the PHY_RX

state or can be locked on preamble detection. The AGC can also

be set to manual mode, in which case, the host processor must

set the LNA, filter, and mixer gains by writing to the AGC_MODE

register (Address 0x35D). The AGC operation is set by the

AGC_LOCK_MODE setting in the RADIO_CFG_7 register

(Address 0x113) and is described in Table 34.

RSSI(dBm) = RSSI_READBACK – 107

The CMD_GET_RSSI execution time is specified in Table 11.

RSSI Method 3

This method supports the measurement of RSSI by the host

processor at any time while in the PHY_RX state. The receiver

input power can be calculated using the following procedure:

The LNA, filter, and mixer gains can be read back through the

AGC_GAIN_STATUS register (Address 0x360).

Table 34. AGC Operation

AGC_LOCK_MODE Bits

in RADIO_ CFG_7 Register Description

1. Set AGC to hold by setting the AGC_MODE register

(Address 0x35D) = 0x40 (only necessary if AGC has not

been locked on the preamble or sync word).

2. Read back the AGC gain settings (AGC_GAIN_STATUS

register, Address 0x360).

0

1

AGC is free running.

AGC is disabled. Gains must be set

manually.

3. Read the ADC_READBACK[7:0] bit values (Address

0x327 and Address 0x328; see the Analog-to-Digital

Converter section).

4. Re-enable the AGC by setting the AGC_MODE register

(Address 0x35D) = 0x00 (only necessary if AGC has not

already been locked on the preamble or sync word).

5. Calculate the RSSI in dBm as follows:

2

3

AGC is held at the current gain level.

AGC is locked on preamble detection.

RSSI

The RSSI is based on a successive compression, log amplifier

architecture following the analog channel filter. The analog

RSSI level is digitized by an 8-bit SAR ADC for user readback

and for use by the digital AGC controller.

RSSI(dBm) =

The ADF7023-J has three RSSI measurement functions that

support a wide range of applications. These functions can be

used to implement carrier sense (CS) or clear channel assessment

(CCA). In packet mode, the RSSI is automatically recorded in MCR

memory and is available for user readback after receipt of a packet.

1

7

⎛

⎜

⎝

⎞

⎠

ADC_READBACK[7:0] × + Gain_Correction −109

⎟

where Gain_Correction is determined by the value of the

AGC_GAIN_STATUS register (Address 0x360) as shown

in Table 35.

Table 36 details the three RSSI measurement methods.

Table 35. Gain Mode Correction for 2FSK/GFSK/MSK/GMSK

RSSI Method 1

RSSI

When a valid packet is received in packet mode, the RSSI level

during postamble is automatically loaded to the RSSI_READBACK

register (Address 0x312) by the communications processor. The

RSSI_READBACK register contains a twos complement value and

can be converted to input power in dBm using the following

formula:

AGC_GAIN_STATUS

(Address 0x360)

GAIN_CORRECTION

0x00

0x01

0x02

0x0A

0x12

0x16

44

35

26

17

10

0

RSSI(dBm) = RSSI_READBACK − 107

To extend the linear range of RSSI measurement down to an

input power of −110 dBm (see Figure 42), a cosine adjustment

can be applied using the following formula:

To simplify the RSSI calculation, the following approximation

can be used by the host processor:

RSSI(dBm) =

1

7

1

8

1

8

1

⎛

⎜

⎞

⎟

≈

1 +

+

64

8

⎛

⎞

⎟

⎝

⎠

COS

× RSSI_READBACK − 106

⎜

RSSI _ READBACK

⎝

⎠

where COS(X) is the cosine of angle X (radians).

Rev. 0 | Page 67 of 100

ADF7023-J

Table 36. Summary of RSSI Measurement Methods

RSSI

Available in

Method RSSI Type

Modulation Packet Mode Sport Mode Description

1

2

3

Automatic end of 2FSK/GFSK/

Yes

No

Yes

Automatic RSSI measurement during reception of

the postamble in packet mode. The RSSI result is available

in the RSSI_READBACK register (Address 0x312).

Automatic RSSI measurement from PHY_ON using

CMD_GET_RSSI. The RSSI result is available in the

RSSI_READBACK register (Address 0x312).

packet RSSI

MSK/GMSK

CMD_GET_RSSI

command from

PHY_ON

2FSK/GFSK/

MSK/GMSK

RSSI via ADC and

2FSK/GFSK/

RSSI measurement based on the ADC and AGC gain

read backs. The host processor calculates RSSI in dBm.

AGC readback, FSK MSK/GMSK

Rev. 0 | Page 68 of 100

ADF7023-J

SPORT MODE

GPIOS

COMMUNICATIONS PROCESSOR

FREQUENCY

CORRELATOR

POST-DEMOD

FILTER

IF FILTER

LIMITERS

I

MIXER

LNA

RxDATA/

RxCLK

CLOCK AND

DATA

RECOVERY

RFIO_1P

RFIO_1N

PREAMBLE

DETECT

Q

IF

SYNC WORD

DETECT

POST_DEMOD_BW[7:0]

DATA_RATE[11:0]

DISCRIM_PHASE[1:0]

IFBW[1:0]

(ADDRESS RADIO_CFG_9[7:6])

DISCRIM_BW[7:0]

PREAMBLE_MATCH = 0

AFC SYSTEM

T

2

AVERAGING

FILTER

RF

PI

RANGE

SYNTHESIZER

(LO)

CONTROL

AFC LOCK

MAX_AFC_RANGE[7:0]

AFC_LOCK_MODE[1:0]

AFC_KI[3:0] (ADDRESS RADIO_CFG_11[7:4])

AFC_KP[3:0]

Figure 80. 2FSK/GFSK/MSK/GMSK Demodulation and AFC Architecture

2FSK/GFSK/MSK/GMSK DEMODULATION

The value of K is then determined by

A correlator demodulator is used for 2FSK, GFSK, MSK, and GMSK

demodulation. The quadrature outputs of the IF filter are first

limited and then fed to a digital frequency correlator that performs

filtering and frequency discrimination of the 2FSK/GFSK/MSK/

GMSK spectrum. Data is recovered by comparing the output

levels from two correlators. The performance of this frequency

discriminator approximates that of a matched filter detector, which

is known to provide optimum detection in the presence of additive

white Gaussian noise (AWGN). This method of 2FSK/GFSK/MSK/

GMSK demodulation provides approximately 3 dB to 4 dB better

sensitivity than a linear frequency discriminator. The 2FSK/GFSK/

MSK/GMSK demodulator architecture is shown in Figure 80.

The ADF7023-J is configured for 2FSK/GFSK/MSK/GMSK

demodulation by setting DEMOD_SCHEME = 0 in the

IF _ Freq

FSK _ Dev

⎡

⎤

MI ≥ 1, AFC off: K = Floor

⎢

⎥

⎣

⎦

⎡

⎤

⎢

⎣

⎥

⎦

IF _ Freq

Data Rate

MI < 1, AFC off: K = Floor

2

⎡

⎤

⎥

IF _ Freq

MI ≥ 1, AFC on: K = Floor

⎢

FSK _ Dev + Freq _ Error _ Max

⎢

⎥

⎣

⎦

⎡

⎤

⎢

⎣

⎥

⎦

IF _ Freq

MI < 1, AFC on: K = Floor

Data Rate

+ Freq_ Error _ Max

2

where:

RADIO_CFG_9 register (Address 0x115).

MI is the modulation index.

To optimize receiver sensitivity, the correlator bandwidth and

phase must be optimized for the specific deviation frequency,

data rate, and maximum expected frequency error between the

transmitter and receiver. The bandwidth and phase of the

discriminator must be set using the DISCRIM_BW bits in the

RADIO_CFG_3 register (Address 0x10F) and the DISCRIM_

PHASE[1:0] bits in the RADIO_CFG_6 register (Address 0x112).

The discriminator setup is performed in three steps.

K is the discriminator coefficient.

Floor[x] is a function to round down to the nearest integer.

IF_Freq is the IF frequency in hertz (200 kHz or 300 kHz).

FSK_Dev is the 2FSK/GFSK/MSK/GMSK frequency deviation

in hertz.

Freq_Error_Max is the maximum expected frequency error, in

hertz, between Tx and Rx.

Step 2: Calculate the DISCRIM_BW Setting

The bandwidth setting of the discriminator is calculated based

on the Discriminator Coefficient K and the IF frequency. The

bandwidth is set using the DISCRIM_BW[7:0] setting

(Address 0x10F), which is calculated according to

Step 1: Calculate the Discriminator Bandwidth

Coefficient K

The Discriminator Bandwidth Coefficient K depends on the

modulation index (MI), which is determined by

2 × FSK _ Dev

MI =

⎡K × 3.25 MHz ⎤

DISCRIM_BW[7:0] = Round

⎢

⎣

⎥

⎦

Data Rate

IF _ Freq

where

FSK_Dev is the 2FSK/GFSK/MSK/GMSK frequency deviation

in hertz (Hz), measured from the carrier to the +1 symbol

frequency (positive frequency deviation) or to the −1 symbol

frequency (negative frequency deviation).

Data Rate is the data rate in bits per second (bps).

Rev. 0 | Page 69 of 100

ADF7023-J

The bandwidth of the AFC loop can be controlled by the

AFC_KI and AFC_KP bits in the RADIO_CFG_11 register

(Address 0x117).

Step 3: Calculate the DISCRIM_PHASE Setting

The phase setting of the discriminator is calculated based on the

Discriminator Coefficient K, as described in Table 37. The phase is

set using the DISCRIM_PHASE[1:0] value in the RADIO_CFG_6

register (Address 0x112).

The maximum AFC pull-in range is automatically set based

on the programmed IF filter bandwidth (the IFBW bits in the

RADIO_CFG_9 register (Address 0x115).

Table 37. Setting the DISCRIM_PHASE[1:0] Values Based on K

K

K/2

(K + 1)/2

DISCRIM_PHASE[1:0]

Table 39. Maximum AFC Pull-In Range

Even

Odd

Even

Odd

0

1

2

3

IF Bandwidth (kHz)

Max AFC Pull-In Range (kHz)

Even

100

150

200

300

50

75

100

150

Even

Odd

AFC

The ADF7023-J features an internal real-time automatic frequency

control loop. In receive mode, the control loop automatically

monitors the frequency error during the packet preamble

sequence and adjusts the receiver synthesizer local oscillator using

proportional integral (PI) control. The AFC frequency error

measurement bandwidth is targeted specifically at the packet

preamble sequence (dc free). AFC is supported during

2FSK/GFSK/MSK/GMSK demodulation.

AFC and Preamble Length

The AFC requires a certain number of the received preamble

bits to correct the frequency error between the transmitter and

the receiver. The number of preamble bits required depends on

the data rate and whether the AFC is locked on detection of the

qualified preamble or locked on detection of the qualified sync

word. This is discussed in more detail in the Recommended

Receiver Settings for 2FSK/GFSK/MSK/GMSK section.

AFC can be configured to lock on detection of the qualified

preamble or on detection of the qualified sync word. To lock

AFC on detection of the qualified preamble, set AFC_LOCK_

MODE = 3 (Address 0x116) and ensure that preamble detection is

enabled in the PREAMBLE_MATCH register (Address 0x11B).

AFC lock is released if the sync word is not detected immediately

after the end of the preamble. In packet mode, if the qualified

preamble is followed by a qualified sync word, the AFC lock is

maintained for the duration of the packet. In sport mode, the

AFC lock is released on transitioning back to the PHY_ON state or

when a CMD_PHY_RX is issued while in the PHY_RX state.

AFC Readback

The frequency error between the received carrier and the receiver

local oscillator can be measured when AFC is enabled. The error

value can be read from the FREQUENCY_ERROR_READBACK

register (Address 0x372), where each LSB equates to 1 kHz. The

value is a twos complement number. The FREQUENCY_ERROR_

READBACK value is valid in the PHY_RX state after the AFC

has been locked. The value is retained in the FREQUENCY_

ERROR_READBACK register after recovering a packet and

transitioning back to the PHY_ON state.

Post-Demodulator Filter

To lock AFC on detection of the qualified sync word, set

AFC_LOCK_MODE = 3 and ensure that preamble detection is

disabled in the PREAMBLE_MATCH register (Address 0x11B). If

this mode is selected, consideration must be given to the selection of

the sync word. The sync word should be dc free and have short run

lengths yet low correlation with the preamble sequence. See the

sync word description in the Packet Mode section for further

details. After lock on detection of the qualified sync word, the AFC

lock is maintained for the duration of the packet. In sport mode,

the AFC lock is released on transitioning back to the PHY_ON state

or when CMD_ PHY_RX is issued while in the PHY_RX state.

A second-order, digital low-pass filter removes excess noise from

the demodulated bit stream at the output of the discriminator. The

bandwidth of this post-demodulator filter is programmable and

must be optimized for the user’s data rate and received modulation

type. If the bandwidth is set too narrow, performance degrades

due to inter-symbol interference (ISI). If the bandwidth is set

too wide, excess noise degrades the performance of the receiver.

For optimum performance, the post-demodulator filter bandwidth

should be set close to 0.75 times the data rate (when using

FSK/GFSK/MSK/GMSK modulation). The actual bandwidth of

the post-demodulator filter is given by

AFC is enabled by setting the AFC_LOCK_MODE bits in the

RADIO_CFG_10 register (Address 0x116), as described in Table 38.

Post-Demodulator Filter Bandwidth (kHz) =

POST_DEMOD_BW × 2

Table 38. AFC Mode

where POST_DEMOD_BW is set in the RADIO_CFG_4

register (Address 0x110).

AFC_LOCK_MODE [1:0]

Mode

0

1

2

3

Free running: AFC is free running.

Disabled: AFC is disabled.

Hold: AFC is paused.

Lock: AFC locks after the preamble

or sync word.

Rev. 0 | Page 70 of 100

ADF7023-J

MCR memory is not retained in PHY_SLEEP; therefore, to

CLOCK RECOVERY

allow the use of these optimized AGC settings in low power

mode applications, a static register fix can be used. An example

static register fix to write to the AGC settings in MCR memory

is shown in Table 40.

An oversampled digital clock and data recovery (CDR) PLL is

used to resynchronize the received bit stream to a local clock in

all modulation modes. The maximum symbol rate tolerance of

the CDR PLL is determined by the number of bit transitions in

the transmitted bit stream. For example, during reception of a

010101 preamble, the CDR achieves a maximum data rate

tolerance of 3.0ꢀ. However, this tolerance is reduced during

recovery of the remainder of the packet where symbol transitions

may not be guaranteed to occur at regular intervals during the

payload data. To maximize data rate tolerance of the receiver’s

CDR, 8b/10b encoding or Manchester encoding should be

enabled, which guarantees a maximum number of contiguous

bits in the transmitted bit stream. Data whitening can also be

enabled on the ADF7023-J to break up long sequences of

contiguous data bit patterns.

Note that the accuracy of the RSSI readback is degraded with

these modified settings.

Table 40. Example Static Register Fix for AGC Settings

BBRAM Register

Data

Description

0x128

0x2B

Pointer to BBRAM Address 0x12B

(STATIC_REG_FIX)

0x12B

0x12C

0x5E

0x46

MCR Address 0x35E

Data to write to MCR Address

0x35E (sets AGC low threshold)

0x12D

0x12E

0x5F

0x78

MCR Address 0x35F

Data to write to MCR Address

0x35F (sets AGC high threshold)

Using 2FSK/GFSK/MSK/GMSK modulation, it is also possible

to tolerate uncoded payload data fields and payload data fields

with long run length coding constraints if the data rate tolerance

and packet length are both constrained. More details of CDR

operation using uncoded packet formats are discussed in the

AN-915 Application Note.

0x12F

0x130

0x2F

0x0F

MCR Address 0x32F

Data to write to MCR Address

0x32F (sets AGC clock divide)

0x131

0x00

Ends static MCR register fixes

Recommended AFC Settings

The CDR PLL of the ADF7023-J is optimized for fast acquisition of

the recovered symbols during preamble and typically achieves

bit synchronization within five symbol transitions of preamble.

The bandwidth of the AFC loop is controlled by the AFC_KI and

AFC_KP bits in the RADIO_CFG_11 register (Address 0x117).

To ensure optimum AFC accuracy while minimizing the AFC

settling time (and thus the required preamble length), the

AFC_KI and AFC_KP bits should be set as outlined in Table 41.

RECOMMENDED RECEIVER SETTINGS FOR

2FSK/GFSK/MSK/GMSK

Recommended Preamble Length

To optimize the ADF7023-J receiver performance and to ensure

the lowest possible packet error rate, it is recommended to use

the following configurations:

When AFC is locked on preamble detection, the minimum

preamble length is between 40 bits and 60 bits depending on

the data rate. When AFC is set to lock on sync word detection,

the minimum preamble length is between 14 bits and 32 bits,

depending on the data rate. When AFC and preamble detection

are disabled, the minimum preamble length is dependent on the

AGC settling time and the CDR acquisition time and is between

8 bits and 24 bits, depending on the data rate. The required

preamble length for various data rates and receiver configurations

is summarized in Table 41.

•

Set the recommended AGC low and high thresholds and

the AGC clock divide.

•

Set the recommended AFC Ki and Kp parameters.

Use a preamble length ≥ the minimum recommended

preamble length.

•

When the AGC is configured to lock on the sync word at

data rates greater than 200 kbps, it is recommended to set

the sync word error tolerance to one bit.

Recommended Sync Word Tolerance

The recommended settings for AGC, AFC, preamble length,

and sync word are summarized in Table 41.

At data rates greater than 200 kbps and when the AGC is configured

to lock on the sync word, it is recommended to set the sync word

error tolerance to one bit (SYNC_ERROR_TOL = 1). This prevents

an AGC gain change during sync word reception causing a packet

loss by allowing one bit error in the received sync word.

Recommended AGC Settings

To optimize the receiver for robust packet error rate performance,

when using minimum preamble length over the full input power

range, it is recommended to overwrite the default AGC settings

in the MCR memory. The recommended settings are as follows:

•

AGC_HIGH_THRESHOLD (Address 0x35F) = 0x78

AGC_LOW_THRESHOLD (Address 0x35E) = 0x46

AGC_CLK_DIVIDE (Address 0x32F) = 0x0F or 0x19

(depends on the data rate; see Table 41)

Rev. 0 | Page 71 of 100

ADF7023-J

Table 41. Summary of Recommended AGC, AFC, Preamble Length, and Sync Word Error Tolerance for 2FSK/GFSK/MSK/GMSK

AGC²

AFC³

Sync

Word

Error

AFC

Pull-In

Range

Minimum

Preamble

Length

Data

Rate

(kbps) (kHz)

Frequency IF

Deviation BW

High

Low

Clock

Tolerance

(Bits)⁵

(kHz) (kHz)

Setup¹

(Bits)⁴

Threshold Threshold Divide

On/Off Ki

Kp

3

300

75

300

150

1

2

3

1

2

3

1

0x78

0x46

0x0F

0x19

On

Off

On

Off

On

Off

On

7

8

64

32

24

58

54

52

50

44

14

8

0

1

0

3

200

150

100

50

200

150

100

75

50

7

3

37.5

25

12.5

20

38.4

9.6

1

10

100

50

8

7

3

46

8

40

¹Setup 1: AFC and AGC are configured to lock on preamble detection by setting AFC_LOCK_MODE = 3 and AGC_LOCK_MODE = 3.

Setup 2: AFC and AGC are configured to lock on sync word detection by setting AFC_LOCK_MODE = 3, AGC_LOCK_MODE = 3, and PREAMBLE_MATCH = 0.

Setup 3: AFC is disabled and AGC is configured to lock on sync word detection by setting AFC_LOCK_MODE = 1, AGC_LOCK_MODE = 3, and PREAMBLE_MATCH = 0.

For Setup 2 and Setup 3, sync word length is 24 bits. Sync word detect length has an impact on minimum preamble length.

²The AGC high threshold is configured by writing to the AGC_HIGH_THRESHOLD register (Address 0x35F). The AGC low threshold is configured by writing to the

AGC_LOW_THRESHOLD register (Address 0x35E). The AGC clock divide is configured by writing to the AGC_CLK_DIVIDE register (Address 0x32F). Note that the

accuracy of the RSSI readback is degraded with these modified AGC threshold settings.

³The AFC is enabled or disabled by writing to the AFC_LOCK_MODE setting in register RADIO_CFG_10 (Address 0x116). The AFC Ki and Kp parameters are configured

by writing to the AFC_KP and AFC_KI settings in the RADIO_CFG_11 register (Address 0x117).

⁴The transmit preamble length (in bytes) is set by writing to the PREAMBLE_LEN register (Address 0x11D).

⁵The sync word error tolerance (in bits) is set by writing to the SYNC_ERROR_TOL setting in the SYNC_CONTROL register (Address 0x120).

Rev. 0 | Page 72 of 100

ADF7023-J

PERIPHERAL FEATURES

converts it to a high frequency, single-bit output using a second-

order Σ-Δ converter. The output can be viewed on the GP0 pin.

This signal, when filtered appropriately, can be used to

ANALOG-TO-DIGITAL CONVERTER

The ADF7023-J supports an integrated SAR ADC for digitization

of analog signals that include the analog temperature sensor, the

analog RSSI level, and an external analog input signal (Pin 30).

The conversion time is typically 1 μs. The result of the conversion

can be read from the ADC_READBACK_HIGH register

(Address 0x327), and the ADC_READBACK_LOW register

(Address 0x328). The ADC readback is an 8-bit value.

•

Monitor the signal at the post-demodulator filter output

Measure the demodulator output SNR

Construct an eye diagram of the received bit stream to

measure the received signal quality

•

Implement analog FM demodulation

The signal source for the ADC input is selected via the

ADC_CONFIG_LOW register (Address 0x359). In the

PHY_RX state, the source is automatically set to the analog

RSSI. The ADC is automatically enabled in PHY_RX. In other

radio states, the host processor must enable the ADC by setting

POWERDOWN_RX (Address 0x324) = 0x10.

To enable the test DAC, the GPIO_CONFIGURE setting

(Address 0x3FA) should be set to 0xC9. The TEST_DAC_GAIN

setting (Address 0x3FD) should be set to 0x00. The test DAC

signal at the GP0 pin can be filtered with a 3-stage, low-pass RC

filter to reconstruct the demodulated signal. For more information,

see the AN-852 Application Note.

To perform an ADC readback, the following procedure should

be completed:

TRANSMIT TEST MODES

There are two transmit test modes that are enabled by setting

the VAR_TX_MODE parameter (Address 0x00D in packet

RAM memory), as described in Table 42. VAR_TX_MODE

should be set before entering the PHY_TX state.

1. Read ADC_READBACK_HIGH. This initializes an ADC

readback.

2. Read ADC_READBACK_LOW. This returns

ADC_READBACK[1:0] of the ADC sample.

3. Read ADC_READBACK_HIGH. This returns

ADC_READBACK[7:2] of the ADC sample.

Table 42. Transmit Test Modes

VAR_TX_MODE

Mode

0

1

Default; no transmit test mode

Reserved

TEMPERATURE SENSOR

The integrated temperature sensor has an operating range between

−40°C and +85°C. To enable readback of the temperature

sensor in PHY_OFF, PHY_ON, or PHY_TX, the following

registers must be set:

2

3

Transmit the preamble continuously

Transmit the carrier continuously

Reserved

4 to 255

SILICON REVISION READBACK

1. Set POWERDOWN_RX (Address 0x324) = 0x10 = 0x10.

This enables the ADC.

2. Set POWERDOWN_AUX (Address 0x325) = 0x02. This

enables the temperature sensor.

3. Set ADC_CONFIG_LOW (Address 0x359) = 0x08. This

sets the ADC input to the temperature sensor.

The product code and silicon revision code can be read from

the packet RAM memory as described in Table 43. The values

of the product code and silicon revision code are valid only on

power-up or wake-up from the PHY_SLEEP state because the

communications processor overwrites these values on transitioning

from the PHY_ON state.

The temperature is determined from the ADC readback value

using the following formula:

Table 43. Product Code and Silicon Revision Code

Packet RAM

Location

Temperature (°C) = (ADC_READBACK[7:0] –

42.197)/1.023 + Correction Value

Description

0x001

0x002

0x003

0x004

Product code, most significant byte = 0x70

Product code, least significant byte = 0x23

Silicon revision code, most significant byte

Silicon revision code least significant byte

The correction value can be determined by performing a

readback at a single known temperature.

TEST DAC

The test DAC allows the output of the post-demodulator filter

to be viewed externally. It takes the 16-bit filter output and

Rev. 0 | Page 73 of 100

ADF7023-J

APPLICATIONS INFORMATION

25

GP4

APPLICATION CIRCUIT

V

DD

A typical application circuit for the ADF7023-J is shown in

Figure 83. All external components required for operation of

the device, excluding supply decoupling capacitors, are shown.

This example circuit uses a combined single-ended PA and LNA

match. Further details on matching topologies and different

host processor interfaces are given in the Host Processor

Interface section and the PA/LNA Matching section.

ADF7023-J

24

23

22

CS

MOSI

SCLK

MISO

GPIO

MOSI

SCLK

MISO

21

20

IRQ_GP3

GP2

IRQ

19

18

GP1

HOST PROCESSOR INTERFACE

17

GP0

The interface, when using packet mode, between the ADF7023-J

and the host processor is shown in Figure 81. In packet mode,

all communication between the host processor and the ADF7023-J

occurs on the SPI interface and the IRQ_GP3 pin. The interface

between the ADF7023-J and the host processor in sport mode is

shown in Figure 82. In sport mode, the transmit and receive data

interface consists of the GP0, GP1, and GP2 pins and a separate

interrupt is available on GP4, while the SPI interface is used for

memory access and issuing of commands.

Figure 81. Processor Interface in Packet Mode

25

V

DD

GP4

IRQ

24

ADF7023-J

CS

MOSI

SCLK

MISO

IRQ_GP3

GP2

GPIO

MOSI

SCLK

MISO

23

22

21

20

IRQ

19

18

GP1

TxRxCLK

TxDATA

RxDATA

17

GP0

Figure 82. Processor Interface in Sport Mode

32kHz XTAL (OPTIONAL)

V

DD

PA/LNA

MATCH

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CS

MOSI

SCLK

MISO

IRQ_GP3

GP2

CREGRF1

RBIAS

GPIO

MOSI

SCLK

MISO

CREGRF2

RFIO_1P

RFIO_1N

RFO2

HARMONIC

FILTER

ANTENNA

CONNECTION

IRQ

ADF7023-J

GND PAD

GP1

VDD

VDDBAT2

NC

GP0

26MHz XTAL

Figure 83. Typical ADF7023-J Application Circuit Diagram

Rev. 0 | Page 74 of 100

ADF7023-J

Separate Single-Ended PA/LNA Match

PA/LNA MATCHING

The separate single-ended PA and LNA matching configuration

is illustrated in Figure 84. The network is the same as the combined

matching network shown in Figure 85 except that the transmit and

receive paths are separate. An external transmit/receive antenna

switch can be used to combine the transmit and receive paths

to allow connection to an antenna. In designing this matching

network, it is not necessary to consider the off impedances of

the PA and LNA, and, thus, achieving an optimum match is less

complex than with the combined single-ended PA and LNA match.

The ADF7023-J has a differential LNA and both a single-ended

PA and differential PA. This flexibility allows numerous

possibilities in interfacing the ADF7023-J to the antenna.

Combined Single-Ended PA and LNA Match

The combined single-ended PA and LNA match allows the

transmit and receive paths to be combined without the use of

an external transmit/receive switch. The matching network

design is shown in Figure 85. The differential LNA match is a

five-element discrete balun giving a single-ended input. The

single-ended PA output is a three-element match consisting of

the choke inductor to the CREGRF2 regulated supply and an

inductor and capacitor series.

LNA MATCH

ADF7023-J

3

CREGRF2

4

RX

RFIO_1P

The LNA and PA paths are combined, and a seventh-order

harmonic filter provides attenuation of the transmit harmonics.

In a combined match, the off impedances of the PA and LNA

must be considered. This can lead to a small loss in transmit

power and degradation in receiver sensitivity in comparison

with a separate single-ended PA and LNA match. However, with

optimum matching, the typical loss in transmit power is <1 dB,

and the degradation in sensitivity is <1 dB when compared with

a separate PA and LNA matching topology.

5

RFIO_1N

HARMONIC FILTER

TX

6

RFO2

PA MATCH

Figure 84. Separate Single-Ended PA and LNA Match

Combined Differential PA/LNA Match

In this matching topology, the single-ended PA is not used. The

differential PA and LNA match comprises a five-element discrete

balun giving a single-ended input/output, as illustrated in

Figure 86. The harmonic filter is used to minimize the RF

harmonics from the differential PA.

ADF7023-J

MATCH

3

4

5

6

CREGRF2

RFIO_1P

RFIO_1N

RFO2

HARMONIC

FILTER

ANTENNA

CONNECTION

Figure 85. Combined Single-Ended PA and LNA Match

ADF7023-J

3

4

5

CREGRF2

RFIO_1P

RFIO_1N

HARMONIC

FILTER

ANTENNA

CONNECTION

6

RFO2

Figure 86. Combined Differential PA and LNA Match

Rev. 0 | Page 75 of 100

ADF7023-J

DIFFERENTIAL PA AND

LNA MATCH

ADF7023-J

3

4

5

TX

CREGRF2

RFIO_1P

RFIO_1N

(DIFFERENTIAL

PA) AND RX

HARMONIC

FILTER

TX

(SINGLE-

ENDED PA)

HARMONIC

FILTER

6

RFO2

SINGLE-ENDED

PA MATCH

Figure 87. Matching Topology for Transmit Antenna Diversity

Transmit Antenna Diversity

The external PA and LNA control signals can be configured

using the EXT_PA_LNA_CONFIG setting (Address 0x11B)

as described in Table 44.

Transmit antenna diversity is possible using the differential PA

and single-ended PA. The required matching network is shown

in Figure 87.

Table 44. Configuration of the External PA and LNA Control

Signals

Support for External PA and LNA Control

The ADF7023-J provides independent control signals for an

external PA or LNA. If the EXT_PA_EN bit is set to 1 in the

MODE_CONTROL register (Address 0x11A), the external PA

control signal is logic high while the ADF7023-J is in the

PHY_TX state and logic low while in any other state. If the

EXT_LNA_EN bit is set to 1 in the MODE_CONTROL register

(Address 0x11A), the external LNA control signal is logic high

while the ADF7023-J is in the PHY_RX state and logic low

while in any other state.

EXT_PA_LNA_CONFIG

Configuration

0

External PA signal on ADCIN_ATB3

and external LNA signal on ATB4

(1.8 V logic outputs)

External PA signal on

XOSC32KP_GP5_ATB1 and

external LNA signal on

1

XOSC32KN_ATB2 (V_DDlogic outputs)

Rev. 0 | Page 76 of 100

ADF7023-J

COMMAND REFERENCE

Table 45. Radio Controller Commands

Command

Code Description

CMD_SYNC

CMD_PHY_OFF

CMD_PHY_ON

CMD_PHY_RX

CMD_PHY_TX

CMD_PHY_SLEEP

CMD_CONFIG_DEV

CMD_GET_RSSI

CMD_BB_CAL

CMD_HW_RESET

CMD_RAM_LOAD_INIT

CMD_RAM_LOAD_DONE

0xA2

0xB0

0xB1

0xB2

0xB5

0xBA

0xBB

0xBC

0xBE

0xC8

0xBF

0xC7

Synchronizes the communications processor to the host processor after reset.

Performs a transition of the device into the PHY_OFF state.

Performs a transition of the device into the PHY_ON state.

Performs a transition of the device into the PHY_RX state.

Performs a transition of the device into the PHY_TX state.

Performs a transition of the device into the PHY_SLEEP state.

Configures the radio parameters based on the BBRAM values.

Performs an RSSI measurement.

Performs a calibration of the IF filter.

Performs a full hardware reset. The device enters the PHY_SLEEP state.

Prepares the program RAM for a firmware module download.

Performs a reset of the communications processor after download of a firmware module to

program RAM.

Initiates an image rejection calibration routine.

Performs an AES encryption on the transmit payload data stored in packet RAM.

Performs an AES decryption on the received payload data stored in packet RAM.

Initializes the internal variables required for AES decryption.

Initializes the internal variables required for the Reed Solomon encoding.

Calculates and appends the Reed-Solomon check bytes to the transmit payload data stored in

packet RAM.

CMD_IR_CAL¹

0xBD

0xD0

0xD2

0xD1

0xD0

CMD_AES_ENCRYPT²

CMD_AES_DECRYPT²

CMD_AES_DECRYPT_INIT²

CMD_RS_ENCODE_INIT³

CMD_RS_ENCODE³

CMD_RS_DECODE³

0xD2

Performs a Reed-Solomon error correction on the received payload data stored in packet RAM.

¹The image rejection calibration firmware module must be loaded to program RAM for this command to be functional.

²The AES firmware module must be loaded to program RAM for this command to be functional.

³The Reed-Solomon Coding firmware module must be loaded to program RAM for this command to be functional.

Table 46. SPI Commands

Command

Code

Description

SPI_MEM_WR

00011xxxb =

Writes data to BBRAM, MCR, or packet RAM memory sequentially. An 11-bit address

is used to identify memory locations. The most significant three bits of the address

are incorporated into the command (xxxb). This command is followed by the

remaining eight bits of the address, which are subsequently followed by the data

bytes to be written.

0x18 (packet RAM),

0x19 (BBRAM),

0x1B (MCR),

0x1E (program RAM)

SPI_MEM_RD

00111xxxb =

Reads data from BBRAM, MCR, or packet RAM memory sequentially. An 11-bit

address is used to identify memory locations. The most significant three bits of the

address are incorporated into the command (xxxb). This command is followed by

the remaining eight bits of the address, which are subsequently followed by the

appropriate number of SPI_NOP commands.

0x38 (packet RAM),

0x39 (BBRAM),

0x3B (MCR)

SPI_MEMR_WR

SPI_MEMR_RD

SPI_NOP

00001xxxb =

Writes data to BBRAM, MCR, or packet RAM memory nonsequentially.

0x08 (packet RAM),

0x09 (BBRAM),

0x0B (MCR)

00101xxxb =

Reads data from BBRAM, MCR, or packet RAM memory nonsequentially.

0x28 (packet RAM),

0x29 (BBRAM),

0x2B (MCR)

0xFF

No operation. Use for dummy writes when polling the status word; used also as

dummy data when performing a memory read.

Rev. 0 | Page 77 of 100

ADF7023-J

REGISTER MAPS

Table 47. Battery Backup Memory (BBRAM)

Address (Hex)

0x100

0x101

0x102

0x103

0x104

0x105

0x106

0x107

0x108

0x109

0x10A

0x10B

0x10C

0x10D

0x10E

0x10F

0x110

0x111

0x112

0x113

0x114

0x115

0x116

0x117

0x118

0x119

0x11A

0x11B

0x11C

0x11D

0x11E

0x11F

0x120

0x121

0x122

0x123

0x124

0x125

0x126

0x127

0x128

0x129

0x12A

0x12B to 0x13D

0x13E

0x13F

Register

Retained in PHY_SLEEP

R/W

Group

MAC

PHY

INTERRUPT_MASK_0

INTERRUPT_MASK_1

NUMBER_OF_WAKEUPS_0

NUMBER_OF_WAKEUPS_1

NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0 Yes

NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1 Yes

RX_DWELL_TIME

PARMTIME_DIVIDER

SWM_RSSI_THRESH

CHANNEL_FREQ_0

CHANNEL_FREQ_1

CHANNEL_FREQ_2

RADIO_CFG_0

RADIO_CFG_1

RADIO_CFG_2

RADIO_CFG_3

RADIO_CFG_4

RADIO_CFG_5

RADIO_CFG_6

RADIO_CFG_7

RADIO_CFG_8

RADIO_CFG_9

RADIO_CFG_10

RADIO_CFG_11

IMAGE_REJECT_CAL_PHASE

IMAGE_REJECT_CAL_AMPLITUDE

MODE_CONTROL

PREAMBLE_MATCH

SYMBOL_MODE

PREAMBLE_LEN

CRC_POLY_0

CRC_POLY_1

SYNC_CONTROL

SYNC_BYTE_0

SYNC_BYTE_1

SYNC_BYTE_2

TX_BASE_ADR

RX_BASE_ADR

Yes

PHY

Packet

PHY

PACKET_LENGTH_CONTROL

PACKET_LENGTH_MAX

STATIC_REG_FIX

ADDRESS_MATCH_OFFSET

ADDRESS_LENGTH

Address matching

RX_SYNTH_LOCK_TIME

TX_SYNTH_LOCK_TIME

Packet

PHY

Rev. 0 | Page 78 of 100

ADF7023-J

Table 48. Modem Configuration Memory (MCR)

Address (Hex)

0x307

0x30C

0x30D

0x30E

0x30F

0x310

0x311

0x312

0x315

0x319

0x322

0x324

0x325

0x327

0x328

0x32D

0x32E

0x32F

0x336

0x337

0x338

0x339

0x345

0x346

0x359

0x35A

0x35B

0x35C

0x35D

0x35E

0x35F

0x360

0x372

0x3CB

0x3CC

0x3CD

0x3D0

0x3D2

0x3DA

0x3DB

0x3F8

0x3F9

0x3FA

0x3FD

Register

Retained in PHY_SLEEP

R/W

W

R/W

R

PA_LEVEL_MCR

No

WUC_CONFIG_HIGH

WUC_CONFIG_LOW

WUC_VALUE_HIGH

WUC_VALUE_LOW

WUC_FLAG_RESET

WUC_STATUS

RSSI_READBACK

MAX_AFC_RANGE

IMAGE_REJECT_CAL_CONFIG

CHIP_SHUTDOWN

POWERDOWN_RX

POWERDOWN_AUX

ADC_READBACK_HIGH

ADC_READBACK_LOW

BATTERY_MONITOR_THRESHOLD_VOLTAGE

EXT_UC_CLK_DIVIDE

AGC_CLK_DIVIDE

INTERRUPT_SOURCE_0

INTERRUPT_SOURCE_1

CALIBRATION_CONTROL

CALIBRATION_STATUS

RXBB_CAL_CALWRD_READBACK

RXBB_CAL_CALWRD_OVERWRITE

ADC_CONFIG_LOW

ADC_CONFIG_HIGH

Reserved

R

R/W

R

R/W

R

RW

R/W

R

AGC_CONFIG

AGC_MODE

AGC_LOW_THRESHOLD

AGC_HIGH_THRESHOLD

AGC_GAIN_STATUS

FREQUENCY_ERROR_READBACK

VCO_BAND_OVRW_VAL

VCO_AMPL_OVRW_VAL

VCO_OVRW_EN

VCO_CAL_CFG

OSC_CONFIG

VCO_BAND_READBACK

VCO_AMPL_READBACK

ANALOG_TEST_BUS

RSSI_TSTMUX_SEL

R

R/W

R

R/W

GPIO_CONFIGURE

TEST_DAC_GAIN

Rev. 0 | Page 79 of 100

ADF7023-J

Table 49. Packet RAM Memory

Address

Register

R/W

R

R/W

R

R/W

0x000

VAR_COMMAND

0x001¹

Product code, most significant byte = 0x70

Product code, least significant byte = 0x23

Silicon revision code, most significant byte

Silicon revision code, least significant byte

Reserved

VAR_TX_MODE

Reserved

Custom PLL loop filter look-up table

0x002¹

0x003¹

0x004¹

0x005 to 0x00B

0x00D

0x00E to 0x00F

0x010 to 0x018

¹Only valid on power-up or wake-up from the PHY_SLEEP state because the communications processor overwrites these values on exit from the PHY_ON state.

BBRAM REGISTER DESCRIPTION

Table 50. 0x100: INTERRUPT_MASK_0

Bit

Name

R/W

Description

[7]

INTERRUPT_NUM_WAKEUPS

R/W

Interrupt when the number of WUC wake-ups (NUMBER_OF_WAKEUPS[15:0]) has

reached the threshold (NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])

1: interrupt enabled; 0: interrupt disabled

[6]

[5]

INTERRUPT_SWM_RSSI_DET

INTERRUPT_AES_DONE

R/W

Interrupt when the measured RSSI during smart wake mode has exceeded the

RSSI threshold value (SWM_RSSI_THRESH, Address 0x108)

1: interrupt enabled; 0: interrupt disabled

Interrupt when an AES encryption or decryption command is complete; available

only when the AES firmware module has been loaded to the ADF7023-J program RAM

1: interrupt enabled; 0: interrupt disabled

[4]

[3]

[2]

[1]

[0]

INTERRUPT_TX_EOF

R/W

Interrupt when a packet has finished transmitting

1: interrupt enabled; 0: interrupt disabled

INTERRUPT_ADDRESS_MATCH

INTERRUPT_CRC_CORRECT

INTERRUPT_SYNC_DETECT

INTERRUPT_PREMABLE_DETECT

Interrupt when a received packet has a valid address match

1: interrupt enabled; 0: interrupt disabled

Interrupt when a received packet has the correct CRC

1: interrupt enabled; 0: interrupt disabled

Interrupt when a qualified sync word has been detected in the received packet

1: interrupt enabled; 0: interrupt disabled

Interrupt when a qualified preamble has been detected in the received packet

1: interrupt enabled; 0: interrupt disabled

Table 51. 0x101: INTERRUPT_MASK_1

Bit

Name

R/W

Description

[7]

BATTERY_ALARM

R/W

Interrupt when the battery voltage has dropped below the threshold value

(BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D)

1: interrupt enabled; 0: interrupt disabled

[6]

CMD_READY

R/W

Interrupt when the communications processor is ready to load a new command;

mirrors the CMD_READY bit of the status word

1: interrupt enabled; 0: interrupt disabled

[5]

[4]

Reserved

R/W

WUC_TIMEOUT

Interrupt when the WUC has timed out

1: interrupt enabled; 0: interrupt disabled

[3]

[2]

[1]

Reserved

SPI_READY

R/W

Interrupt when the SPI is ready for access

1: interrupt enabled; 0: interrupt disabled

[0]

CMD_FINISHED

R/W

Interrupt when the communications processor has finished performing a

command

1: interrupt enabled; 0: interrupt disabled

Rev. 0 | Page 80 of 100

ADF7023-J

Table 52. 0x102: NUMBER_OF_WAKEUPS_0

Bit

Name

R/W Description

[7:0]

NUMBER_OF_WAKEUPS[7:0]

R/W Bits[7:0] of [15:0] of an internal 16-bit count of the number of wake-ups

(WUC timeouts) the device has gone through. It can be initialized to 0x0000.

See Table 53.

Table 53. 0x103: NUMBER_OF_WAKEUPS_1

Bit

Name

R/W Description

[7:0]

NUMBER_OF_WAKEUPS[15:8]

R/W Bits[15:8] of [15:0] of an internal 16-bit count of the number of WUC wake-ups

the device has gone through. It can be initialized to 0x0000. See Table 52.

Table 54. 0x104: NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0

Bit

Name

R/W Description

[7:0] NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[7:0]

R/W Bits[7:0] of [15:0] (see Table 55). The threshold for the number of wake-ups

(WUC timeouts). It is a 16-bit count threshold that is compared against the

NUMBER_OF_WAKEUPS bits. When this threshold is exceeded, the device

wakes up in the PHY_OFF state and optionally generates

INTERRUPT_NUM_WAKEUPS.

Table 55. 0x105: NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1

Bit Name R/W Description

[7:0] NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:8] R/W Bits[15:8] of [15:0] (see Table 54).

Table 56. 0x106: RX_DWELL_TIME

Bit

Name

R/W Description

[7:0] RX_DWELL_TIME

R/W When the WUC is used and SWM is enabled, the radio powers up and

enables the receiver on the channel defined in the BBRAM and listens for

this period of time. If no preamble pattern is detected in this period, the

device goes back to sleep.

Receive Dwell Time (s) = RX_DWELL_TIME ×

6.5 MHz

128 × PARMTIME_DIVIDER

Table 57. 0x107: PARMTIME_DIVIDER

Bit

Name

R/W Description

[7:0] PARMTIME_DIVIDER

R/W Units of time used to define the RX_DWELL_TIME time period.

128 × PARMTIME_DIVIDER

Timer Tick Rate =

6.5 MHz

A value of 0x33 gives a clock of 995.7 Hz or a period of 1.004 ms.

Table 58. 0x108: SWM_RSSI_THRESH

Bit

Name

R/W Description

[7:0] SWM_RSSI_THRESH

R/W This sets the RSSI threshold when in smart wake mode with RSSI detection

enabled.

Threshold (dBm) = SWM_RSSI_THRESH − 107

Table 59. 0x109: CHANNEL_FREQ_0

Bit

Name

R/W Description

[7:0] CHANNEL_FREQ[7:0]

R/W The RF channel frequency in hertz is set according to

(CHANNEL_FREQ[23 : 0])

Frequency (Hz) = f

×

2¹⁶

PFD

where f_PFDis the PFD frequency and is equal to 26 MHz.

Rev. 0 | Page 81 of 100

ADF7023-J

Table 60. 0x10A: CHANNEL_FREQ_1

Bit

Name

R/W

Description

[7:0]

CHANNEL_FREQ[15:8]

R/W

See the CHANNEL_FREQ_0 description in Table 59.

Table 61. 0x10B: CHANNEL_FREQ_2

Bit

Name

R/W

Description

[7:0]

CHANNEL_FREQ[23:16]

R/W

See the CHANNEL_FREQ_0 description in Table 59.

Table 62. 0x10C: RADIO_CFG_0

Bit

Name

R/W

Description

The data rate in bps is set according to Data Rate (bps) = DATA_RATE[11:0] × 100.

[7:0]

DATA_RATE[7:0]

R/W

Table 63. 0x10D: RADIO_CFG_1

Bit

Name

R/W

Description

[7:4]

[3:0]

FREQ_DEVIATION[11:8]

DATA_RATE[11:8]

See the FREQ_DEVIATION description in RADIO_CFG_2 (see Table 64).

See the DATA_RATE description in RADIO_CFG_0 (see Table 62).

Table 64. 0x10E: RADIO_CFG_2

Bit

Name

R/W

Description

[7:0]

FREQ_DEVIATION[7:0]

R/W

The binary level 2FSK/GFSK/MSK/GMSK frequency deviation in hertz (defined

as the frequency difference between carrier frequency and 1/0 tones) is set

according to Frequency Deviation (Hz) = FREQ_DEVIATION[11:0] × 100.

Table 65. 0x10F: RADIO_CFG_3

Bit

Name

R/W

Description

[7:0]

DISCRIM_BW[7:0]

R/W

The DISCRIM_BW value sets the bandwidth of the correlator demodulator. See

the 2FSK/GFSK/MSK/GMSK Demodulation section for the steps required to set

the DISCRIM_BW value.

Table 66. 0x110: RADIO_CFG_4

Bit

Name

R/W

Description

[7:0]

POST_DEMOD_BW[7:0]

R/W

For optimum performance, the post-demodulator filter bandwidth should be

set close to 0.75 times the data rate. The actual bandwidth of the post-

demodulator filter is given by Post-Demodulator Filter Bandwidth (kHz) =

POST_DEMOD_BW × 2. The range of POST_DEMOD_BW is 1 to 255.

Table 67. 0x111: RADIO_CFG_5

Bit

Name

R/W

Description

[7:0]

Reserved

R/W

Set to zero.

Table 68. 0x112: RADIO_CFG_6

Bit

Name

R/W

Description

[7:2]

SYNTH_LUT_CONFIG_0

R/W

If SYNTH_LUT_CONTROL (Address 0x113, Table 69) = 0 or 2, set

SYNTH_LUT_CONFIG_0 = 0. If SYNTH_LUT_CONTROL = 1 or 3, this setting

allows the receiver PLL loop bandwidth to be changed to optimize the receiver

local oscillator phase noise.

[1:0]

DISCRIM_PHASE[1:0]

R/W

The DISCRIM_PHASE value sets the phase of the correlator demodulator. See

the 2FSK/GFSK/MSK/GMSK Demodulation section for the steps required to set

the DISCRIM_PHASE value.

Rev. 0 | Page 82 of 100

ADF7023-J

Table 69. 0x113: RADIO_CFG_7

Bit

Name

R/W

Description

Set to:

[7:6]

AGC_LOCK_MODE

R/W

0: free running

1: manual

2: hold

3: lock after preamble/sync word (only locks on a sync word if PREAMBLE_

MATCH = 0)

[5:4]

SYNTH_LUT_CONTROL

R/W

By default, the synthesizer loop bandwidth is automatically selected from

lookup tables (LUT) in ROM memory. A narrow bandwidth is selected in

receive to ensure optimum interference rejection, whereas in transmit, the

bandwidth is selected based on the data rate and modulation settings. For

the majority of applications, these automatically selected PLL loop

bandwidths are optimum. However, in some applications, it may be

necessary to use custom transmit or receive bandwidths, in which case,

various options exist, as follows.

SYNTH_LUT_CONTROL

Description

0

Use predefined transmit and receive LUTs. The

LUTs are automatically selected from ROM

memory on transitioning into the PHY_TX or

PHY_RX state.

1

2

Use custom receive LUT based on SYNTH_

LUT_CONFIG_0 and SYNTH_LUT_CONFIG_1. In

transmit, the predefined LUT in ROM is used.

Use a custom transmit LUT. The custom

transmit LUT must be written to the 0x10 to

0x18 packet RAM locations. In receive, the

predefined LUT in ROM is used.

3

Use a custom receive LUT based on SYNTH_

LUT_CONFIG_0 and SYNTH_LUT_CONFIG_1,

and use a custom transmit LUT. The custom

transmit LUT must be written to the 0x10 to

0x18 packet RAM locations.

Because packet RAM memory is lost in the PHY_SLEEP state, the custom

LUT for transmit must be reloaded to packet RAM after waking from the

PHY_SLEEP state.

[3:0]

SYNTH_LUT_CONFIG_1

R/W

If SYNTH_LUT_CONTROL = 0 or 2, set SYNTH_LUT_CONFIG_0 to 0. If

SYNTH_LUT_CONTROL = 1 or 3, this setting allows the receiver PLL loop

bandwidth to be changed to optimize the receiver local oscillator phase noise.

Table 70. 0x114: RADIO_CFG_8

Bit

Name

R/W Description

[7]

PA_SINGLE_DIFF_SEL R/W

PA_SINGLE_DIFF_SEL

PA

0

1

Single-ended PA enabled

Differential PA enabled

[6:3] PA_LEVEL

R/W Sets the PA output power. A value of zero sets the minimum RF output power, and a value of 15

sets the maximum PA output power. The PA level can also be set with finer resolution using the

PA_LEVEL_MCR setting (Address 0x307). The PA_LEVEL setting is related to the PA_LEVEL_MCR

setting by PA_LEVEL_MCR = 4 × PA_LEVEL + 3.

PA_LEVEL

PA Level (PA_LEVEL_MCR)

Setting 3

0

1

Setting 7

2

Setting 11

15

Setting 63

Rev. 0 | Page 83 of 100

ADF7023-J

Bit

Name

R/W Description

[2:0] PA_RAMP

R/W Sets the PA ramp rate. The PA ramps at the programmed rate until it reaches the level indicated by the

PA_LEVEL_MCR (Address 0x307) setting. The ramp rate is dependent on the programmed data rate.

PA_RAMP

Ramp Rate

0

1

2

3

4

5

6

Reserved

256 codes per data bit

128 codes per data bit

64 codes per data bit

32 codes per data bit

16 codes per data bit

Eight codes per data bit

To ensure the correct PA ramp-up and ramp-down timing, the PA ramp rate has a minimum value based

on the data rate and the PA_LEVEL or PA_LEVEL_MCR settings. This minimum value is described by

_{Ramp Rate(Codes/Bit) < 2500 ×}PA_LEVEL_MCR[5 : 0]

DATA_RATE[11 : 0]

where PA_LEVEL_MCR is related to the PA_LEVEL setting by PA_LEVEL_MCR = 4 × PA_LEVEL + 3.

Table 71. 0x115: RADIO_CFG_9

Bit

Name

R/W Description

[7:6] IFBW

R/W Sets the receiver IF filter bandwidth. Note that setting an IF filter bandwidth of 300 kHz automatically

changes the receiver IF frequency from 200 kHz to 300 kHz.

IFBW

IF Bandwidth (kHz)

0

1

2

3

100

150

200

300

[5:3] MOD_SCHEME

R/W Sets the transmitter modulation scheme.

MOD_SCHEME

Modulation Scheme

Two-level 2FSK/MSK

Two-level GFSK/GSMK

Reserved

0

1

2

3

Carrier only

4 to 7

Reserved

[2:0] DEMOD_SCHEME

R/W Sets the receiver demodulation scheme.

DEMOD_SCHEME

Demodulation Scheme

2FSK/GFSK/MSK/GMSK

Reserved

0

1

2

Reserved

3 to 7

Reserved

Table 72. 0x116: RADIO_CFG_10

Bit

Name

R/W Description

[7:5] Reserved

R/W Set to 0.

[4]

AFC_POLARITY

R/W Set to 0.

[3:2] AFC_SCHEME

[1:0] AFC_LOCK_MODE

R/W Set to 2.

R/W Sets the AFC mode.

AFC_LOCK_MODE

Mode

0

1

2

3

Free running: AFC is free running.

Disabled: AFC is disabled.

Hold AFC: AFC is paused.

Lock: AFC locks after the preamble or sync word (only

locks on a sync word if PREAMBLE_MATCH = 0).

Rev. 0 | Page 84 of 100

ADF7023-J

Table 73. 0x117: RADIO_CFG_11

Bit

Name

R/W

Description

[7:4]

AFC_KP

R/W

Sets the AFC PI controller proportional gain in 2FSK/GFSK/MSK/GMSK; the

recommended value is 0x3.

AFC_KP

Proportional Gain

0

1

2

2⁰

2¹

2²

…

15

…

2¹⁵

[3:0]

AFC_KI

R/W

Sets the AFC PI controller integral gain in 2FSK/GFSK/MSK/GMSK; the

recommended value is 0x7.

AFC_KI

Integral Gain

0

1

2

2⁰

2¹

2²

…

15

…

2¹⁵

Table 74. 0x118: IMAGE_REJECT_CAL_PHASE

Bit

Name

R/W

Description

[7]

Reserved

Set to 0

[6:0]

IMAGE_REJECT_CAL_PHASE

Sets the I/Q phase adjustment

Table 75. 0x119: IMAGE_REJECT_CAL_AMPLITUDE

Bit

Name

R/W

Description

[7]

Reserved

Set to 0

[6:0]

IMAGE_REJECT_CAL_AMPLITUDE

Sets the I/Q amplitude adjustment

Table 76. 0x11A: MODE_CONTROL

Bit Name

R/W

Description

[7] SWM_EN

R/W

1: smart wake mode enabled.

0: smart wake mode disabled.

1: IF filter calibration enabled.

0: IF filter calibration disabled.

[6] BB_CAL

R/W

IF filter calibration is automatically performed on the transition from the PHY_OFF

state to the PHY_ON state if this bit is set.

[5] SWM_RSSI_QUAL

R/W

1: RSSI qualify in low power mode enabled.

0: RSSI qualify in low power mode disabled.

[4] TX_TO_RX_AUTO_TURNAROUND

If TX_TO_RX_AUTO_TURNAROUND = 1, the device automatically transitions to the

PHY_RX state at the end of a packet transmission, on the same RF channel

frequency. If TX_TO_RX_AUTO_TURNAROUND = 0, this operation is disabled.

TX_TO_RX_AUTO_TURNAROUND is only available in packet mode.

[3] RX_TO_TX_AUTO_TURNAROUND

R/W

If RX_TO_TX_AUTO_TURNAROUND = 1, the device automatically transitions to the

PHY_TX state at the end of a valid packet reception, on the same RF channel

frequency. If RX_TO_TX_AUTO_TURNAROUND = 0, this operation is disabled.

RX_TO_TX_AUTO_TURNAROUND is only available in packet mode.

[2] CUSTOM_TRX_SYNTH_LOCK_TIME_EN R/W

1: use the custom synthesizer lock time defined in Register 0x13E and Register 0x13F.

0: default synthesizer lock time.

[1] EXT_LNA_EN

[0] EXT_PA_EN

R/W

1: external LNA enable signal on ATB4 is enabled. The signal is logic high while the

ADF7023-J is in the PHY_RX state and logic low while in any other nonsleep state.

0: external LNA enable signal on ATB4 is disabled.

1: external PA enable signal on ATB3 is enabled. The signal is logic high while the

ADF7023-J is in the PHY_TX state and logic low while in any other nonsleep state.

0: external PA enable signal on ADCIN_ATB3 is disabled.

Rev. 0 | Page 85 of 100

ADF7023-J

Table 77. 0x11B: PREAMBLE_MATCH

Bit

Name

R/W

Description

[7]

EXT_PA_LNA_CONFIG

R/W

EXT_PA_LNA_CONFIG

Description

0

External PA signal on ADCIN_ATB3 and external LNA

signal on ATB4 (1.8 V logic outputs)

1

External PA signal on XOSC32KP_GP5_ATB1 and

external LNA signal on XOSC32KN_ATB2 (V_DDlogic

outputs)

[6:4]

[3:0]

Reserved

R/W

Set to 0

PREAMBLE_MATCH

Description

15 to 13

Reserved

12

11

10

9

0 errors allowed

One erroneous bit pair allowed in 12 bit-pairs

Two erroneous bit pairs allowed in 12 bit-pairs

Three erroneous bit pairs allowed in 12 bit-pairs

Four erroneous bit pairs allowed in 12 bit-pairs

Not recommended

8

7 to 1

0

Preamble detection disabled

Table 78. 0x11C: SYMBOL_MODE

Bit

[7]

[6]

Name

R/W

Description

Reserved

R/W

Set to 0

MANCHESTER_ENC

1: Manchester encoding and decoding enabled

0: Manchester encoding and decoding disabled

1: programmable CRC enabled

[5]

[4]

[3]

PROG_CRC_EN

R/W

0: programmable CRC disabled

EIGHT_TEN_ENC

DATA_WHITENING

1: 8b/10b encoding and decoding enabled

0: 8b/10b encoding and decoding disabled

1: data whitening and dewhitening enabled

0: data whitening and dewhitening disabled

SYMBOL_LENGTH Description

[2:0] SYMBOL_LENGTH

0

8-bit (recommended except when 8b/10b is being used)

1

10-bit (for 8b/10b encoding)

Reserved

2 to 7

Table 79. 0x11D: PREAMBLE_LEN

Bit

Name

R/W

Description

[7:0]

PREAMBLE_LEN

R/W

Length of preamble in bytes. Example: a value of decimal 3 results in a

preamble of 24 bits.

Table 80. 0x11E: CRC_POLY_0

Bit

Name

R/W

Description

[7:0]

CRC_POLY[7:0]

R/W

Lower byte of CRC_POLY[15:0], which sets the CRC polynomial. See Table 81.

Table 81. 0x11F: CRC_POLY_1

Bit

Name

R/W

Description

[7:0]

CRC_POLY[15:8]

R/W

Upper byte of CRC_POLY[15:0], which sets the CRC polynomial. See the

Packet Mode section for more details on how to configure a CRC polynomial.

Rev. 0 | Page 86 of 100

ADF7023-J

Table 82. 0x120: SYNC_CONTROL

Bit

Name

R/W

Description

[7:6]

SYNC_ERROR_TOL

R/W

Sets the sync word error tolerance in bits.

SYNC_ERROR_TOL

Bit Error Tolerance

0 bit errors allowed.

0

1

2

3

One bit error allowed.

Two bit errors allowed.

Three bit errors allowed.

[5]

Reserved

R/W

Set to 0.

[4:0]

SYNC_WORD_LENGTH

Sets the sync word length in bits; 24 bits is the maximum. Note that the

sync word matching length can be any value up to 24 bits, but the transmitted

sync word pattern is a multiple of eight bits. Therefore, for nonbyte-length

sync words, the transmitted sync pattern should be filled out with the

preamble pattern.

SYNC_WORD_LENGTH

Length in Bits

0

1

…

24

…

24

Table 83. 0x121: SYNC_BYTE_0

Bit

Name

R/W

Description

[7:0]

SYNC_BYTE[7:0]

R/W

Lower byte of the sync word pattern. The sync word pattern is transmitted

most significant bit first starting with SYNC_BYTE_0. For nonbyte-length

sync words, the remainder of the least significant byte should be stuffed

with the preamble. If SYNC_WORD_LENGTH length is >16 bits, SYNC_BYTE_0,

SYNC_BYTE_1, and SYNC_BYTE_2 are all transmitted for a total of 24 bits. If

SYNC_WORD_LENGTH is between 8 and 15, SYNC_BYTE_1 and SYNC_BYTE_2

are transmitted. If SYNC_WORD_LENGTH is between 1 and 7, SYNC_BYTE_2

is transmitted for a total of eight bits. If the SYNC_WORD_LENGTH is 0, no

sync bytes are transmitted.

Table 84. 0x122: SYNC_BYTE_1

Bit

Name

R/W

Description

[7:0]

SYNC_BYTE[15:8]

R/W

Middle byte of the sync word pattern

Table 85. 0x123: SYNC_BYTE_2

Bit

Name

R/W

Description

[7:0]

SYNC_BYTE[23:16]

R/W

Upper byte of the sync word pattern

Table 86. 0x124: TX_BASE_ADR

Bit

Name

R/W

Description

[7:0]

TX_BASE_ADR

R/W

Address in packet RAM of the transmit packet. This address indicates to the

communications processor the location of the first byte of the transmit packet.

Table 87. 0x125: RX_BASE_ADR

Bit

Name

R/W

Description

[7:0]

RX_BASE_ADR

R/W

Address in packet RAM of the receive packet. The communications processor

writes any qualified received packet to packet RAM, starting at this memory

location.

Rev. 0 | Page 87 of 100

ADF7023-J

Table 88. 0x126: PACKET_LENGTH_CONTROL

Bit

Name

R/W

Description

[7]

DATA_BYTE

R/W

Over-the-air arrangement of each transmitted packet RAM byte. A byte is

transmitted either MSB or LSB first. The same setting should be used on the

Tx and Rx sides of the link.

1: data byte MSB first.

0: data byte LSB first.

[6]

PACKET_LEN

R/W

1: fixed packet length mode. Fixed packet length in Tx and Rx modes, given

by PACKET_LENGTH_MAX.

0: variable packet length mode. In Rx mode, packet length is given by the

first byte in packet RAM. In Tx mode, the packet length is given by

PACKET_LENGTH_MAX.

[5]

CRC_EN

R/W

1: append CRC in transmit mode. Check CRC in receive mode.

0: no CRC addition in transmit mode. No CRC check in receive mode.

Sets the ADF7023-J to packet mode or sport mode for transmit and receive data.

[4:3]

DATA_MODE

Description

0

1

Packet mode enabled.

Sport mode enabled. GP4 interrupt enabled on preamble

detection. Rx data enabled on preamble detection.

2

3

Sport mode enabled. GP4 interrupt enabled on sync word

detection. Rx data enabled on preamble detection.

Unused.

[2:0]

LENGTH_OFFSET

R/W

Offset value in bytes that is added to the received packet length field value

(in variable length packet mode) so that the communications processor

knows the correct number of bytes to read. The communications processor

calculates the actual received payload length as Rx Payload Length = Length

+ LENGTH_OFFSET – 4, where Length is the length field (the first byte in the

received payload).

Table 89. 0x127: PACKET_LENGTH_MAX

Bit

Name

R/W

Description

[7:0]

PACKET_LENGTH_MAX

R/W

If variable packet length mode is used (PACKET_LENGTH_CONTROL = 0),

PACKET_LENGTH_MAX sets the maximum receive packet length in bytes.

If fixed packet length mode is used (PACKET_LENGTH_CONTROL = 1),

PACKET_LENGTH_MAX sets the length of the fixed transmit and receive

packet in bytes. Note that the packet length is defined as the number of

bytes from the end of the sync word to the start of the CRC. It also does not

include the LENGTH_OFFSET value.

Rev. 0 | Page 88 of 100

ADF7023-J

Table 90. 0x128: STATIC_REG_FIX

Bit

Name

R/W

Description

[7:0]

STATIC_REG_FIX

R/W

The ADF7023-J has the ability to implement automatic static register fixes

from BBRAM memory to MCR memory. This feature allows a maximum of

nine MCR registers to be programmed via BBRAM memory. This feature is

useful if MCR registers must be configured for optimum receiver performance in

low power mode. The STATIC_REG_FIX value is an address pointer to any

BBRAM memory address between 0x12A and 0x13D. For example, to point

to BBRAM Address 0x12B, set STATIC_REG_FIX = 0x2B.

•

If STATIC_REG_FIX = 0x00, then static register fixes are disabled.

If STATIC_REG_FIX is nonzero, the communications processor looks for

the MCR address and corresponding data at the BBRAM address

beginning at STATIC_REG_FIX.

Example: write 0x46 to MCR Register 0x35E and write 0x78 to

MCR Register 0x35F. Set STATIC_REG_FIX = 0x2B.

BBRAM Register

Data

Description

0x128 (STATIC_REG_FIX) 0x2B

Pointer to BBRAM Address 0x12B

MCR Address 1

Data to write to MCR Address 1

MCR Address 2

Data to write to MCR Address 2

Ends static MCR register fixes

0x12B

0x12C

0x12D

0x12E

0x12F

0x5E

0x46

0x5F

0x78

0x00

Table 91. 0x129: ADDRESS_MATCH_OFFSET

Bit

Name

R/W

Description

[7:0]

ADDRESS_MATCH_OFFSET

R/W

Location of first byte of address information in packet RAM

Table 92. 0x12A: ADDRESS_LENGTH

Bit

Name

R/W

Description

[7:0]

ADDRESS_LENGTH

R/W

Number of bytes in the first address field (N_{ADR_1}). Set to zero if address

matching is not being used.

Table 93. 0x12B to 0x13D: Address Matching

Address

0x12B

0x12C

0x12D

0x12E

…

Bit

R/W

Description

[7:0]

Address 1 Match Byte 0.

Address 1 Mask Byte 0.

Address 1 Match Byte 1.

Address 1 Mask Byte 1.

…

[7:0]

R/W

Address 1 Match Byte N_{ADR_1}

.

Address 1 Mask Byte N_{ADR_1}

.

0x00 to end or number of bytes in the second address field (N_{ADR_2}).

Table 94. 0x13E: RX_SYNTH_LOCK_TIME

Bit Name

R/W

Description

[7:0] RX_SYNTH_LOCK_TIME

R/W

Allows the use of a custom synthesizer lock time counter in receive mode in

conjunction with the CUSTOM_TRX_SYNTH_LOCK_TIME_EN setting in the

MODE_CONTROL register. Applies after VCO calibration is complete. Each

bit equates to a 2 ꢀs increment.

Table 95. 0x13F: TX_SYNTH_LOCK_TIME

Bit

Name

R/W

Description

[7:0] TX_SYNTH_LOCK_TIME

R/W

Allows the use of a custom synthesizer lock time counter in transmit mode in

conjunction with the CUSTOM_TRX_SYNTH_LOCK_TIME_EN setting in the

MODE_CONTROL register. Applies after VCO calibration is complete. Each bit

equates to a 2 μs increment.

Rev. 0 | Page 89 of 100

ADF7023-J

MCR REGISTER DESCRIPTION

The MCR register settings are not retained when the device enters the PHY_SLEEP state.

Table 96. 0x307: PA_LEVEL_MCR

Bit

Name

R/W

Reset Description

[5:0] PA_LEVEL_MCR

R/W

0

Power amplifier level. If PA ramp is enabled, the PA ramps to this target

level. The PA level can be set in the 0 to 63 range. The PA level (with less

resolution) can also be set via the BBRAM; therefore, the MCR setting

should be used only if more resolution is required.

Table 97. 0x30C: WUC_CONFIG_HIGH

Bit

[7]

[6]

[5]

[4]

[3]

Name

R/W

W

Reset

Description

Set to 0

Reserved

0

WUC_BGAP

W

Set to 0

WUC_LDO_SYNTH

WUC_LDO_DIG

WUC_XTO26M_EN

W

Set to 0

W

Set to 0

W

Set to 0

[2:0] WUC_PRESCALER

W

WUC_PRESCALER

32.768 kHz Divider

Tick Period

30.52 μs

122.1 μs

244.1 μs

488.3 μs

3.91 ms

31.25 ms

250 ms

2000 ms

0

1

2

3

4

5

6

7

1

4

8

16

128

1034

81 2

65,536

Register WUC_CONFIG_LOW should never be written to without updating Register WUC_CONFIG_HIGH first.

Table 98. 0x30D: WUC_CONFIG_LOW

Bit

[7]

[6]

Name

R/W

W

Reset

Description

Reserved

0

Set to 0

WUC_RCOSC_EN

W

1: enable RCOSC32K

0: disable RCOSC32K

[5]

[4]

WUC_XOSC32K_EN

WUC_CLKSEL

W

0

1: enable XOSC32K

0: disable XOSC32K

Select the WUC timer clock source

1: RC 32.768 kHz oscillator

0: external crystal oscillator

1: enable power to the BBRAM during the PHY_SLEEP state

0: disable power to the BBRAM during the PHY_SLEEP state

Set to 0

[3]

WUC_BBRAM_EN

W

0

[2:1] Reserved

[0] WUC_ARM

W

0

1: enable wake-up on a WUC timeout event

0: disable wake-up on a WUC timeout event

Updates to Register WUC_VALUE_HIGH become effective only after Register WUC_VALUE_LOW is written to.

Table 99. 0x30E: WUC_VALUE_HIGH

Bit

Name

R/W

Reset

Description

[7:0] WUC_TIMER_VALUE[15:8]

W

0

WUC timer reload value, Bits[15:8] of [15:0]. A wake-up event is triggered

when the WUC unit is enabled and the timer has counted down to 0. The

timer is clocked with the prescaler output rate. An update to this register

becomes effective only after WUC_VALUE_LOW is written. See Table 100.

Rev. 0 | Page 90 of 100

ADF7023-J

Register WUC_VALUE_LOW should never be written to without updating register WUC_VALUE_HIGH first.

Table 100. 0x30F: WUC_VALUE_LOW

Bit

Name

R/W

Reset

Description

[7:0] WUC_TIMER_VALUE[7:0]

W

0

WUC timer reload value, Bits[7:0] of [15:0]. A wake-up event is triggered

when the WUC unit is enabled and the timer has counted down to 0. The

timer is clocked with the prescaler output rate. See Table 101.

Table 101. 0x310: WUC_FLAG_RESET

Bit

Name

R/W

Reset

Description

[1]

WUC_RCOSC_CAL_EN

R/W

0

1: enable

0: disable RCOSC32K calibration

[0]

WUC_FLAG_RESET

R/W

1: reset the WUC_TMR_PRIM_TOFLAG and WUC_PORFLAG bits (Address

0x311, see Table 102)

0: normal operation

Table 102. 0x311: WUC_STATUS

Bit

[7]

[6]

Name

R/W

R

Reset

Description

Reserved

0

Reserved

WUC_RCOSC_CAL_ERROR

R

1: RCOSC32K calibration exited with error

0: without error (only valid if WUC_RCOSC_CAL_EN = 1)

1: RCOSC32K calibration finished

0: in progress (only valid if WUC_RCOSC_CAL_EN = 1)

1: XOSC32K oscillator has settled

[5]

[4]

WUC_RCOSC_CAL_READY

XOSC32K_RDY

R

0

0: not settled (only valid if WUC_XOSC32K_EN = 1)

Output signal of the XOSC32K oscillator (instantaneous)

1: chip cold start event has been registered

0: not registered

[3]

[2]

XOSC32K_OUT

WUC_PORFLAG

R

0

[1]

[0]

WUC_TMR_PRIM_TOFLAG

WUC_TMR_PRIM_TOEVENT

R

0

1: WUC timeout event has been registered

0: not registered (the output of a latch triggered by a timeout event)

1: WUC timeout event is present

0: not present (this bit is set when the counter reaches 0; it is not latched)

Table 103. 0x312: RSSI_READBACK

Bit Name

R/W

Reset

Description

[7:0] RSSI_READBACK

R

0

Receive input power. After reception of a packet, the RSSI_READBACK value

is valid. RSSI (dBm) = RSSI_READBACK – 107.

Table 104. 0x315: MAX_AFC_RANGE

Bit

Name

R/W

Reset

Description

[7:0] MAX_AFC_RANGE

R/W

50

Limits the AFC pull-in range. Automatically set by the communications

processor on transitioning into the PHY_RX state. The range is set equal to

half the IF bandwidth. Example: IF bandwidth = 200 kHz, AFC pull-in range =

100 kHz (MAX_AFC_RANGE = 100).

Rev. 0 | Page 91 of 100

ADF7023-J

Table 105. 0x319: IMAGE_REJECT_CAL_CONFIG

Bit

Name

R/W

Reset

Description

[7:6]

[5]

Reserved

R/W

0

IMAGE_REJECT_CAL_OVWRT_EN R/W

Overwrite control for image reject calibration results.

[4:3]

IMAGE_REJECT_FREQUENCY

R/W

Set the fundamental frequency of the IR calibration signal source. A harmonic

of this frequency can be used as an internal RF signal source for the image

rejection calibration.

0: IR calibration source disabled in XTAL divider

1: IR calibration source fundamental frequency = XTAL/4

2: IR calibration source fundamental frequency = XTAL/8

3: IR calibration source fundamental frequency = XTAL/16

Set power level of IR calibration source.

0: IR calibration source disabled at mixer input

1: power level = min

[2:0]

IMAGE_REJECT_POWER

R/W

0

2: power level = min

3: power level = min × 2

4: power level = min × 2

5: power level = min × 3

6: power level = min × 3

7: power level = min × 4

Table 106. 0x322: CHIP_SHUTDOWN

Bit

Name

R/W

Reset

Description

[7:1]

[0]

Reserved

0

CHIP_SHTDN_REQ

WUC chip-state control flag

0: remain in active state

1: invoke chip shutdown. CS must also be high to initiate a shutdown

Table 107. 0x324: POWERDOWN_RX

Bit

Name

R/W Reset

Description

[7:5]

[4]

Reserved

ADC_PD_N

R/W

0

1: LNA enabled

0: LNA disabled

1: RSSI enabled

0: RSSI disabled

1: IF filter enabled

0: IF filter disabled

1: mixer enabled

0: mixer disabled

1: LNA enabled

0: LNA disabled

[3]

[2]

[1]

[0]

RSSI_PD_N

R/W

0

RXBBFILT_PD_N

RXMIXER_PD_N

LNA_PD_N

Table 108. 0x325: POWERDOWN_AUX

Bit

Name

R/W Reset

Description

[7:2]

[1]

Reserved

R/W

0

TEMPMON_PD_EN

1: enable

0: disable temperature monitor

1: enable

[0]

BATTMON_PD_EN

R/W

0

0: disable battery monitor

Table 109. 0x327: ADC_READBACK_HIGH

Bit

Name

R/W

Reset

Description

[7:6]

[5:0]

Reserved

R

0

ADC_READBACK[7:2]

R

ADC readback of MSBs

Rev. 0 | Page 92 of 100

ADF7023-J

Table 110. 0x328: ADC_READBACK_LOW

Bit

Name

R/W

R

Reset

Description

[7:6]

[5:0]

ADC_READBACK[1:0]

Reserved

0

ADC readback of LSBs

R

Table 111. 0x32D: BATTERY_MONITOR_THRESHOLD_VOLTAGE

Bit

Name

R/W

Reset

Description

[7:5]

[4:0]

Reserved

0

BATTMON_VOLTAGE

The battery monitor threshold voltage sets the alarm level for the battery

monitor. The alarm is raised by the interrupt. Battery monitor trip voltage,

V_TRIP= 1.7 V + 62 mV × BATTMON_VOLTAGE.

Table 112. 0x32E: EXT_UC_CLK_DIVIDE

Bit

Name

R/W

Reset

Description

[7:4]

[3:0]

Reserved

0

4

EXT_UC_CLK_DIVIDE

Optional output clock frequency on XOSC32KP_GP5_ATB1.

Output frequency = XTAL/EXT_UC_CLK_DIVIDE. To disable,

set EXT_UC_CLK_DIVIDE = 0.

Table 113. 0x32F: AGC_CLK_DIVIDE

Bit

Name

R/W

Reset

Description

[7:0]

AGC_CLOCK_DIVIDE

R/W

40

AGC clock divider for 2FSK/GFSK/MSK/GMSK mode. The AGC rate is

(26 MHz/(16 × AGC_CLK_DIVIDE)).

Table 114. 0x336: INTERRUPT_SOURCE_0

Bit

Name

R/W

Reset

Description

[7]

INTERRUPT_NUM_WAKEUPS

R/W

0

Asserted when the number of WUC wake-ups

(NUMBER_OF_WAKEUPS[15:0]) has reached the threshold

(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])

[6]

[5]

INTERRUPT_SWM_RSSI_DET

INTERRUPT_AES_DONE

R/W

0

Asserted when the measured RSSI during smart wake mode has

exceeded the RSSI threshold value (SWM_RSSI_THRESH, Address 0x108)

Asserted when an AES encryption or decryption command is complete;

available only when the AES firmware module has been loaded to the

ADF7023-J program RAM

[4]

[3]

INTERRUPT_TX_EOF

R/W

0

Asserted when a packet has finished transmitting (packet mode only)

INTERRUPT_ADDRESS_MATCH

Asserted when a received packet has a valid address match (packet

mode only)

[2]

[1]

INTERRUPT_CRC_CORRECT

INTERRUPT_SYNC_DETECT

R/W

0

Asserted when a received packet has the correct CRC (packet mode only)

Asserted when a qualified sync word has been detected in the received

packet

[0]

INTERRUPT_PREAMBLE_DETECT

R/W

0

Asserted when a qualified preamble has been detected in the received

packet

Table 115. 0x337: INTERRUPT_SOURCE_1

Bit

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Name

R/W

Reset Description

BATTERY_ALARM

CMD_READY

Unused

R/W

0

Battery voltage dropped below the user-set threshold value

Communications processor ready to accept a new command

Wake-up timer has timed out

WUC_TIMEOUT

Unused

SPI_READY

CMD_FINISHED

SPI ready for access

Command has finished

Rev. 0 | Page 93 of 100

ADF7023-J

Table 116. 0x338: CALIBRATION_CONTROL

Bit

Name

R/W

Reset Description

[7:2] Reserved

0

[1]

[0]

SYNTH_CAL_EN

RXBB_CAL_EN

0

1: enable the synthesizer calibration state machine

0: disable the synthesizer calibration state machine

1: enable receiver baseband filter (RXBB) calibration

0: disable receiver baseband filter (RXBB) calibration

R/W

0

Table 117. 0x339: CALIBRATION_STATUS

Bit

Name

R/W

Reset Description

[7:3] Reserved

R

0

[2]

[1]

PA_RAMP_FINISHED

R

SYNTH_CAL_READY

R

0

1: synthesizer calibration finished successfully

0: synthesizer calibration in progress

Receive IF filter calibration

[0]

RXBB_CAL_READY

R

0

1: complete

0: in progress (valid while RXBB_CAL_EN = 1)

Table 118. 0x345: RXBB_CAL_CALWRD_READBACK

Bit Name R/W Reset Description

[5:0] RXBB_CAL_CALWRD

R

0

RXBB reference oscillator calibration word; valid after RXBB calibration cycle

has been completed.

Table 119. 0x346: RXBB_CAL_CALWRD_OVERWRITE

Bit

[6:1] RXBB_CAL_DCALWRD_OVWRT_IN

[0]

Name

R/W

Reset Description

RW

0

RXBB reference oscillator calibration overwrite word

RXBB_CAL_DCALWRD_OVWRT_EN RW

1: enable RXBB reference oscillator calibration word overwrite mode

0: disable RXBB reference oscillator calibration word overwrite mode

Table 120. 0x359: ADC_CONFIG_LOW

Bit

Name

R/W

Reset Description

[7:4]

[3:2]

Reserved

0

Set to 0

ADC_REF_CHSEL

0: RSSI (default)

1: external AIN

2: temperature sensor

3: unused

[1:0]

ADC_REFERENCE_CONTROL

R/W

0

The following reference values are valid for a 3 V supply:

0: 1.85 V (default)

1: 1.95 V

2: 1.75 V

3: 1.65 V

Table 121. 0x35A: ADC_CONFIG_HIGH

Bit

Name

R/W

Reset

Description

[7]

Reserved

0

[6:5]

FILTERED_ADC_MODE

Filtering modes

00: normal operation (no filter)

01: unfiltered AGC loop, filtered readback (updated upon MCR read)

10: unfiltered AGC loop, filtered readback (update at AGC clock rate)

11: filtered AGC loop, filtered readback

Bring low to power down the ADC reference

Set to 1

[4]

ADC_EXT_REF_ENB

Reserved

R/W

1

[3:0]

Rev. 0 | Page 94 of 100

ADF7023-J

Table 122. 0x35C: AGC_CONFIG

Bit

Name

R/W

Reset

Description

[7:6]

[5:4]

[3:2]

[1]

LNA_GAIN_CHANGE_ORDER

MIXER_GAIN_CHANGE_ORDER

FILTER_GAIN_CHANGE_ORDER

ALLOW_EXTRA_LO_LNA_GAIN

DISALLOW_MAX_GAIN

2

1

3

0

LNA gain change order

Mixer gain change order

Filter gain change order

Allow extra low LNA gain setting

Disallow maximum AGC gain setting

[0]

Table 123. 0x35D: AGC_MODE

Bit

Name

R/W

Reset

Description

[7]

Reserved

0

[6:5]

AGC_OPERATION_MCR

0: free-running AGC

1: manual AGC

2: hold AGC

3: lock AGC after preamble

0: low

[4:3]

LNA_GAIN

R/W

0

1: medium

2: high

3: reserved

0: low

1: high

[2]

MIXER_GAIN

FILTER_GAIN

R/W

0

[1:0]

0: low

1: medium

2: high

3: reserved

Table 124. 0x35E: AGC_LOW_THRESHOLD

Bit

Name

R/W

Reset

Description

[7:0]

AGC_LOW_THRESHOLD

R/W

55

AGC low threshold

Table 125. 0x35F: AGC_HIGH_THRESHOLD

Bit

Name

R/W

Reset

Description

[7:0]

AGC_HIGH_THRESHOLD

R/W

105

AGC high threshold

Table 126. 0x360: AGC_GAIN_STATUS

Bit

Name

R/W

R

Reset

Description

[7:5]

[4:3]

Reserved

0

LNA_GAIN_READBACK

R

0: low

1: medium

2: high

3: reserved

0: low

1: high

[2]

MIXER_GAIN_READBACK

FILTER_GAIN_READBACK

R

0

[1:0]

0: low

1: medium

2: high

3: reserved

Table 127. 0x372: FREQUENCY_ERROR_READBACK

Bit

Name

R/W

Reset

Description

[7:0]

FREQUENCY_ERROR_READBACK

R

0

Frequency error between received signal frequency and receive

channel frequency = FREQUENCY_ERROR_READBACK × 1 kHz.

The FREQUENCY_ERROR_READBACK value is in twos

complement format.

Rev. 0 | Page 95 of 100

ADF7023-J

Table 128. 0x3CB: VCO_BAND_OVRW_VAL

Bit

Name

R/W

Reset

Description

[7:0]

VCO_BAND_OVRW_VAL

R/W

0

Overwrite value for the VCO frequency band; active when

VCO_BAND_OVRW_EN = 1.

Table 129. 0x3CC: VCO_AMPL_OVRW_VAL

Bit

Name

R/W

Reset

Description

[7:0]

VCO_AMPL_OVRW_VAL

R/W

0

Overwrite value for the VCO bias current DAC; active when

VCO_AMPL_OVRW_EN= 1.

Table 130. 0x3CD: VCO_OVRW_EN

Bit

Name

R/W

Reset

Description

[7:6]

[5:2]

[1]

Reserved

0

Reserved.

VCO_Q_AMP_REF

VCO_AMPL_OVRW_EN

VCO amplitude level control reference DAC during Q phase

1: enable VCO bias current DAC overwrite

0: disable VCO bias current DAC overwrite

1: enable VCO frequency band overwrite

0: disable VCO frequency band overwrite

[0]

VCO_BAND_OVRW_EN

R/W

0

Table 131. 0x3D0: VCO_CAL_CFG

Bit

Name

R/W

Reset

Description

[7:4]

[3:0]

Reserved

VCO_CAL_CFG

0

1

Reserved.

VCO calibration state machine configuration. Set VCO_CAL_CFG =

0xF to bypass VCO calibration on the PHY_TX and PHY_RX

transitions. Set VCO_CAL_CFG = 0x1 to enable the VCO

calibrations on the transitions.

Table 132. 0x3D2: OSC_CONFIG

Bit

Name

R/W

Reset

Description

[7:6]

[5:3]

[2:0]

Reserved

0

Write 0

XOSC_CAP_DAC

Reserved

26 MHz crystal oscillator (XOSC26N) tuning capacitor control word

Write 0

Table 133. 0x3DA: VCO_BAND_READBACK

Bit

Name

R/W

Reset

Description

[7:0]

VCO_BAND_READBACK

R

0

Readback of the VCO bias current DAC after calibration

Table 134. 0x3DB: VCO_AMPL_READBACK

Bit

Name

R/W

Reset

Description

[7:0]

VCO_AMPL_READBACK

R

0

Readback of the VCO bias current DAC after calibration

Table 135. 0x3F8: ANALOG_TEST_BUS

Bit

Name

R/W

Reset

Description

[7:0]

ANALOG_TEST_BUS

R/W

0

To enable analog RSSI on ATB3, set ANALOG_TEST_BUS = 0x64 in

conjunction with setting RSSI_TSTMUX_SEL = 0x3.

Table 136. 0x3F9: RSSI_TSTMUX_SEL

Bit

Name

R/W

Reset

Description

[7]

Reserved

0

[6:2]

[1:0]

Reserved

RSSI_TSTMUX_SEL

To enable analog RSSI on ATB3, set RSSI_TSTMUX_SEL = 0x3 in conjunction

with setting ANALOG_TEST_BUS = 0x64.

Rev. 0 | Page 96 of 100

ADF7023-J

Table 137. 0x3FA: GPIO_CONFIGURE

Bit

Name

R/W

Reset

Description

[7:0]

GPIO_CONFIGURE

R/W

0

0x00: default

0x21: slicer output on GP5 (that is, bypass CDR)

0x40: limiter outputs on GP0(Q) and GP1(I)

0x41: filtered limiter outputs on GP0(Q) and GP1(I) and unfiltered limiter

outputs on GP2(Q) and IRQ_GP3 (I)

0x50: packet transmit data from communications processor on GP0

0x53: PA ramp finished on GP0

0xA0: Sport Mode 0

0xA1: Sport Mode 1

0xA2: Sport Mode 2

0xA3: Sport Mode 3

0xA4: Sport Mode 4

0xA5: Sport Mode 5

0xA6: Sport Mode 6

0xA7: Sport Mode 7

0xA8: Sport Mode 8

0xC9: Test DAC output on GP0 (also must set TEST_DAC_GAIN)

Table 138. 0x3FD: TEST_DAC_GAIN

Bit

Name

R/W

Reset

Description

[7:4]

[3:0]

Reserved

0

4

Reserved

TEST_DAC_GAIN

Set TEST_DAC_GAIN = 0 when using the test DAC

PACKET RAM REGISTER DESCRIPTION

Table 139. 0x00D: VAR_TX_MODE

VAR_TX_MODE

Mode

0

1

Default; no transmit test mode

Reserved

2

3

Transmit the preamble continuously

Transmit the carrier continuously

Reserved

4 to 255

Rev. 0 | Page 97 of 100

ADF7023-J

OUTLINE DIMENSIONS

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

25

32

24

1

0.50

BSC

3.45

3.30 SQ

3.15

EXPOSED

PAD

17

8

16

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 88. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm ꢀ 5 mm Body, Very Very Thin Quad

(CP-32-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-32-13

ADF7023-JBCPZ

−40°C to +85°C

32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Evaluation Board (USB Motherboard)

Evaluation Board (RF Daughterboard, 950 MHz, Separate Match)

Evaluation Board (RF Daughterboard, 950 MHz, Combined Match)

ADF7023-JBCPZ-RL

EVAL-ADF7XXXMB3Z

EVAL-ADF7023-JDB1Z

EVAL-ADF7023-JDB2Z

¹Z = RoHS Compliant Part.

Rev. 0 | Page 98 of 100

ADF7023-J

NOTES

Rev. 0 | Page 99 of 100

ADF7023-J

NOTES

registered trademarks are the property of their respective owners.

D09555-0-5/11(0)

Rev. 0 | Page 100 of 100


型号：	ADF7023-JBCPZ-RL
厂家：	ADI
描述：	High Performance, Low Power, ISM Band FSK/GFSK/MSK/GMSK Transceiver IC 高性能，低功耗， ISM频段FSK / GFSK / MSK / GMSK收发器IC 电信集成电路电信电路 ISM频段
文件：	总100页 (文件大小：1251K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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