ADF9010BCPZ-RL7 [ADI]
900 MHz ISM Band Analog RF Front End; 900 MHz的ISM频段RF模拟前端
| 型号： | ADF9010BCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 900 MHz ISM Band Analog RF Front End |
| 文件： | 总28页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
900 MHz ISM Band
Analog RF Front End
ADF9010
FEATURES
FUNCTIONAL BLOCK DIAGRAM
CE
V
R
V
AV
DV
DD
P
X
DD
DD
840 MHz to 960 MHz ISM bands
Rx baseband analog low-pass filtering and PGA
Integrated RF Tx upconverter
Integrated integer-N PLL and VCO
Integrated Tx PA preamplifier
Differential fully balanced architectures
3.3 V supply
Low power mode: <1 mA power-down current
Programmable Rx LPF cutoff
V
CM
ADF9010
Rx IP
BB
Rx IN
BB
Rx IP
IN
Rx IN
IN
Rx
CM
DC OFFSET
CORRECTION
V
CM
OVF
Rx QP
BB
Rx QP
IN
Rx QN
BB
Rx QN
IN
24-BIT
INPUT SHIFT
REGISTER
S
CLK
DC OFFSET
CORRECTION
S
DATA
330 kHz, 880 kHz, 1.76 MHz, and bypass
Rx PGA gain settings: 3 dB to 24 dB in 3 dB steps
Low noise BiCMOS technology
S
LE
MUXOUT
PLL
R
R
SET
REF
IN
PHASE
COUNTER
CHARGE
PUMP
CP
FREQUENCY
DETECTOR
N COUNTER
N = BP + A
B
C
C
C
C
C
1
48-lead, 7 mm × 7 mm LFCSP
EXT
COUNTER
2
EXT
PRESCALER
P/P + 1
V
TUNE
APPLICATIONS
3
EXT
A
COUNTER
4
EXT
900 MHz RFID readers
T
÷4
Unlicensed band 900 MHz applications
LO
LO
P
OUT
QUADRATURE
N
PHASE SPLITTER
OUT
Tx IP
BB
Tx IN
BB
Tx
Tx
P
OUT
N
OUT
Tx QP
BB
Tx QN
BB
DGND
AGND
Figure 1.
GENERAL DESCRIPTION
The ADF9010 is a fully integrated RF Tx modulator and Rx
analog baseband front end that operates in the frequency
range from 840 MHz to 960 MHz. The receive path consists
of a fully differential I/Q baseband PGA, low-pass filter, and
general signal conditioning before connecting to an Rx ADC
for baseband conversion. The Rx LPF gain ranges from 3 dB
to 24 dB, programmable in 3 dB steps. The Rx LPF features
four programmable modes with cutoff frequencies of 330 kHz,
880 kHz, and 1.76 MHz, or the filter can be bypassed if necessary.
The transmit path consists of a fully integrated differential Tx
direct I/Q upconverter with a high linearity PA driver amplifier.
It converts a baseband I/Q signal to an RF carrier-based signal
between 840 MHz and 960 MHz. The highly linear transmit
signal path ensures low output distortion.
Complete local oscillator (LO) signal generation is integrated
on chip, including the integer-N synthesizer and VCO, which
generate the required I and Q signals for transmit I/Q upconver-
sion. The LO signal is also available at the output to drive an
external RF demodulator. Control of all the on-chip registers
is via a simple 3-wire serial interface. The device operates with a
power supply ranging from 3.15 V to 3.45 V and can be powered
down when not in use.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADF9010
TABLE OF CONTENTS
Features .............................................................................................. 1
R Counter .................................................................................... 12
A and B Counters....................................................................... 12
Tx Section.................................................................................... 14
Interfacing ................................................................................... 14
Latch Structure ........................................................................... 15
Control Latch.............................................................................. 21
Tx Latch....................................................................................... 21
Rx Calibration Latch.................................................................. 21
LO Latch ...................................................................................... 22
Rx Latch....................................................................................... 22
Initialization................................................................................ 22
Interfacing ................................................................................... 22
Applications Information.............................................................. 23
Demodulator Connection......................................................... 23
LO and Tx Output Matching.................................................... 24
PCB Design Guidelines ............................................................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Transmit Characteristics.............................................................. 3
Receive Baseband Characteristics .............................................. 4
Integer-N PLL and VCO Characteristics .................................. 5
Write Timing Characteristics...................................................... 6
Absolute Maximum Ratings............................................................ 7
Transistor Count........................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Circuit Description......................................................................... 12
Rx Section.................................................................................... 12
LO Section................................................................................... 12
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADF9010
SPECIFICATIONS
TRANSMIT CHARACTERISTICS
AVDD = DVDD = 3.3 V 5ꢀ, AGND = DGND = GND = 0 V, TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in
quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted.
Table 1.
B Version1
Parameter
Min
Typ
Max Unit
Test Conditions/Comments
TRANSMIT MODULATOR CHARACTERISTICS
Operating Frequency Range
840
960
MHz
Range over which uncompensated sideband
suppression < −30 dBc
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Output IP3
3
10
−40
−46
24
dBm
dBm
dBm
dBc
VIQ = 1.4 V p-p differential
dBm
POUT = −4 dBm per tone, 10 MHz and 12 MHz
baseband input frequencies used.
Noise Floor
−158
dBm/Hz
TRANSMIT BASEBAND CHARACTERISTICS
Input Impedance of Each Pin
Input Capacitance of Each Pin
Input Signal Level
Common-Mode Output Level
Tx Baseband 3 dB Bandwidth
POWER SUPPLIES
4
3
1.4
0.6
20
kΩ typ
pF
V p-p
V
Single-ended frequencies up to 2 MHz
At 10 MHz
Measured differentially at I or Q
MHz
Voltage Supply
3.15
3.45
V
IDD
Digital IDD
Rx Baseband
Tx Modulator
LO Synthesizer and VCO
Total IDD
5
70
140
140
360
6
80
mA
mA
mA
mA
mA
Maximum gain settings
Full power, baseband inputs biased at 0.5 V
+ 5 dBm LO power setting selected
410
Power-Down
Rx VDD
AVDD
DVDD
1
20
20
mA
μA
μA
1
1
LOGIC INPUTS (SERIAL INTERFACE)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS (MUXOUT)
Output High Voltage, VOH
Output Low Voltage, VOL
1.4
V
V
μA
pF
1.8 V logic compatible
0.4
1
5
DVDD − 0.4
V
V
IOL = 500 μA
IOH = 500 μA
0.4
1 Operating temperature range for the B version is −40°C to +85°C.
Rev. 0 | Page 3 of 28
ADF9010
RECEIVE BASEBAND CHARACTERISTICS
AVDD = DVDD = 3.3 V 5ꢀ, AGND = DGND = GND = 0 V, TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in
quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted.
Table 2.
B Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RECEIVE BASEBAND PGA
Highest Voltage Gain
Lowest Voltage Gain
24
3
dB
dB
Gain Control Range
Gain Control Step
Noise Spectral Density (Referred to Input)
RECEIVE BASEBAND FILTERS
3 dB Cutoff Frequency (Mode 0)
Gain Flatness
18
3
3.5
dB
dB
nV/√Hz
Programmable using 3-bit interface
At maximum PGA gain
320
500
kHz
dB
μs
After filter calibration
Typical from dc to 90 kHz
DC to 360 kHz
0.5
Differential Group Delay
150
μs
170 kHz to 310 kHz
After filter calibration
Attenuation Template
@ 330 kHz Offset
@ 500 kHz Offset
@ 1 MHz Offset
3 dB Cutoff Frequency (Mode 1)
Gain Flatness
−3
−8
−28
880
dB
dB
dB
kHz
dB
μs
After filter calibration
DC to 90 kHz
DC to 360 kHz
0.5
Differential Group Delay
500
150
μs
170 kHz to 310 kHz
After filter calibration
Attenuation Template
@ 880 kHz Offset
@ 2 MHz Offset
@ 4 MHz Offset
3 dB Cutoff Frequency (Mode 2)
Gain Flatness
−3
dB
dB
dB
MHz
dB
μs
−17
−38
1.76
After filter calibration
DC to 90 kHz
DC to 360 kHz
0.5
Differential Group Delay
500
150
μs
170 kHz to 310 kHz
After filter calibration
Attenuation Template
@ 1.76 MHz Offset
@ 4 MHz Offset
@ 8 MHz Offset
@ 16 MHz Offset
3 dB Cutoff Frequency (Mode 3)
Gain Flatness
Differential Group Delay
@ 2 MHz Offset
−3
dB
dB
dB
dB
MHz
dB
μs
−18
−38
−60
4
After filter calibration
DC to 90 kHz
DC to 360 kHz
0.5
500
−0.5
−2
dB
dB
@ 4 MHz Offset
Input Impedance of Each Pin
@ 24 dB gain
@ 3 dB gain
Input Capacitance of Each Pin
Input Signal Level
Common-Mode Output Level
Maximum Residual DC
250
4
3
Ω
kΩ
pF
V p-p
V
mV
At 10 MHz
2
Measured differentially at I or Q
On Rx baseband outputs
Baseband gain 0 dB − 27 dB
1.65
150
1 Operating temperature range for the B version is −40°C to +85°C.
Rev. 0 | Page 4 of 28
ADF9010
INTEGER-N PLL AND VCO CHARACTERISTICS
Table 3.
B Version1
Typ
Parameter
Min
3360
Max
Unit
Test Conditions/Comments
Measured at LO output (900 MHz)
VCOOPERATING FREQUENCY
LO OUTPUT CHARACTERISTICS
VCO Control Voltage Sensitivity
3840
MHz
8
MHz/V 3.6 GHz VCO frequency (taking into account
divide by 4)
Harmonic Content (Second)
Harmonic Content (Third)
Frequency Pushing (Open Loop)
Frequency Pulling (Open Loop)
Lock Time
−27
−14
1.2
10
1000
−4 to +5
dBc
dBc
MHz/V
Hz
μs
dBm
Into 2.00 VSWR load.
10 kHz loop bandwidth
LO outputs combined in a 1:1 transformer;
programmable in 3 dB steps
Output Power
Output Power Variation
NOISE CHARACTERISTICS
VCO Phase Noise Performance2
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
In-Band Phase Noise3, 4
3
dB
Measured at LO output (900 MHz)
−120
−141
−154
−96
−220
−70
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz @ 1 kHz offset from carrier
dBc/Hz
dBc
Normalized In-Band Phase Noise Floor3, 4
Spurious Frequencies at Output Channel Spacing
900 MHz offset, 1 MHz PFD frequency, 250 kHz
channel spacing; loop bandwidth = 7.5 kHz
PHASE DETECTOR
Phase Detector Frequency5
Maximum Allowable Prescaler Output Frequency6
CHARGE PUMP
8
325
MHz
MHz
ICP Sink/Source
With RSET = 4.7 kΩ
High Value
Low Value
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
5
mA
mA
kΩ
nA
%
0.625
2.7
10
0.2
2
1.5
2
1.25 V ≤ VCP ≤ 2.5 V
1.25 V ≤ VCP ≤ 2.5 V
VCP = 2.0 V
%
%
ICP vs. Temperature
PLL REFERENCE
Reference Clock Frequency
Reference Clock Sensitivity
Reference Input Capacitance
REFIN Input Current
10
0.7
104
MHz
PLL VDD V p-p
pF
100
5
μA
1 Operating temperature range for the B version is −40°C to +85°C.
2 The noise of the VCO is measured in open-loop conditions.
3 The phase noise is measured with the EVAL-ADF9010EBZ1 evaluation board and the Agilent E5052A spectrum analyzer. The spectrum analyzer provides the REFIN for
the synthesizer; offset frequency = 1 kHz.
4 fREFIN = 10 MHz; fPFD = 1000 kHz; N = 3600; loop BW = 25 kHz.
5 Guaranteed by design. Sample tested to ensure compliance.
6 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
Rev. 0 | Page 5 of 28
ADF9010
WRITE TIMING CHARACTERISTICS
AVDD = DVDD = 3.3 V 5ꢀ% AGND = DGND = GND = 0 V% TA = 25°C, guaranteed by design, but not production tested.
Table 4.
Parameter
Limit at tMIN to tMAX (B Version)
Unit
Test Conditions/Comments
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
SLE pulse width
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
t3
t4
S
S
CLCK
DATA
t1
t2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DB2
t6
S
S
LE
LE
t5
Figure 2. Write Timing Diagram
Rev. 0 | Page 6 of 28
ADF9010
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only% functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
1
DVDD, RxVDD , AVDD to GND
RxVDD, AVDD to DVDD
VP to GND1
Digital I/O Voltage to GND1
Analog I/O Voltage to GND1
Charge Pump Voltage to GND1
REFIN, LOEXTP, LO EXTN to GND1
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +5.5 V
−0.3 V to VDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to VP to GND1
−0.3 V to VDD + 0.3 V
320 mV
This device is a high-performance RF integrated circuit with an
ESD rating of <0.5 kV and is ESD sensitive. Proper precautions
should be taken for handling and assembly.
LOEXTP to LOEXT
N
TRANSISTOR COUNT
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
LCSP θJA Thermal Impedance
Reflow Soldering
The ADF9010 transistor count is 40,454 (CMOS) and 994
(bipolar).
−40°C to +85°C
−65°C to +150°C
150°C
ESD CAUTION
26°C/W
Peak Temperature
Time at Peak Temperature
260°C/W
40 sec
1 GND = AGND = DGND = 0 V.
Rev. 0 | Page 7 of 28
ADF9010
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rx IP
IN
1
2
36 Rx IN
BB
PIN 1
INDICATOR
Rx IN
IN
35 Rx IP
BB
34 Rx QP
BB
RxV
DD
3
33 Rx QN
BB
LO
OUT
N
4
LO
OUT
P
5
32 C
31 C
30 R
3
4
EXT
EXT
SET
AGND
DGND
6
ADF9010
TOP VIEW
7
(Not to Scale)
REF
IN
8
29 AV
DD
DV
9
28 Tx IN
DD
BB
27 Tx IP
V
10
P
BB
CP 11
26 Tx QP
BB
25 Tx QN
AGND 12
BB
NC = NO CONNECT
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
RxINIP, RxININ
RxVDD
Description
1, 2
3, 46
Input/Complementary In-Phase Input to the Receive Filter Stage.
Receiver Filter Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. RxVDD must be the same
value as AVDD and DVDD
.
4, 5
LOOUTN, LOOUT
P
Buffered Local Oscillator Output. These outputs are used to provide the LO for the external RF
demodulator. These require an RF choke to AVDD and a dc bypass capacitor before connection to a
demodulator.
6, 12, 18, 24, 44 AGND
Analog Ground. This is the ground return path of analog circuitry.
Digital Ground.
PLL Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent
input resistance of 100 kΩ (see Figure 13). This input can be driven from a TTL or CMOS crystal
oscillator, or it should be ac-coupled.
7
8
DGND
REFIN
9, 37
10
DVDD
VP
Digital Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the digital
ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD
.
This pin supplies the voltage to the charge pump. If the internal VCO is used, it should equal AVDD
and DVDD. If an external VCO is used, the voltage can be AVDD < VP < 5.5 V.
11
CP
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn
drives the external VCO.
13
CT
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to
AGND with a value of 10 nF. The output voltage on this part is proportional to temperature. At
ambient temperature, the voltage is 2.0 V.
14
CEXT
CEXT
1
2
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to
AGND with a value of 10 nF.
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to
AGND with a value of 10 nF.
15
16, 21, 29
AVDD
Analog Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AVDD must be the same value
as DVDD
.
Rev. 0 | Page 8 of 28
ADF9010
Pin No.
Mnemonic
Description
17
VTUNE
Control Input to the VCO. This input determines the VCO frequency and is derived from filtering the
CP output.
19, 20
22, 23
LOEXTP, LO EXT
N
Single-Ended External VCO Input of 50 Ω. This is used if the ADF9010 utilizes an optional external VCO.
These pins are internally dc-biased and must be ac-coupled. AC-couple LOEXTN to ground with 100 pF
and ac-couple the VCO signal with 100 pF through LOEXTP.
Buffered Tx Output. These pins contain the Tx output signal, which can be combined in a balun for
best results.
TxOUTP, Tx OUT
N
25, 26
27, 28
30
TxBBQN, TxBBQP
TxBBIP, TxBBIN
RSET
Baseband Quadrature Phase Input/Complementary Input to the Transmit Modulator.
Baseband In-Phase Input/Complementary to the Transmit Modulator.
Connecting a resistor between this pin and AGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
ICPMAX = 25.5/RSET
where:
RSET is 5.1 kΩ.
ICPMAX is 5 mA.
31
CEXT
CEXT
4
3
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled
to AGND with a value of 10 nF.
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled
to AGND with a value of 10 nF.
32
33, 34
35, 36
38
RxBBQN, RxBBQP
Output/Complementary Filtered Quadrature Signals from the Receive Filter Stage. The filtered
output is passed to the baseband MxFE chip.
Output/Complementary Filtered In-Phase from the Receive Filter Stage. The filtered output is
passed to the baseband MxFE chip.
Chip Enable. A Logic 0 on this pin powers down the device. A Logic 1 on this pin enables the device
depending on the status of the power-down bits.
RxBBIP, RxBBIN
CE
39
SCLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the SCLK rising edge. This is a high impedance CMOS input.
40
SDATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is
a high impedance CMOS input.
41
SLE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into
one of the four latches; the latch uses the control bits.
42
MUXOUT
OVF
This multiplexer output allows either the PLL lock detect, the scaled VCO frequency, or the scaled
PLL reference frequency to be accessed externally.
A rising edge on this pin drops the gain of the Rx path by 6 dB. This is used to rapidly drop the gain
if the ADC detects an overload.
43
45
NC
No Connect.
47, 48
RxINQP, RxINQN
Input/Complementary Quadrature Input to the Receive Filter Stage.
Rev. 0 | Page 9 of 28
ADF9010
TYPICAL PERFORMANCE CHARACTERISTICS
28
27
26
25
24
23
22
21
20
19
18
–40
900MHz LO
10MHz REF
1MHz PFD
INTEGRATED PHASE ERROR: 0.75 rms
IN
–60
–80
–100
–120
–140
–160
–40°C 3.15V OIP3
–40°C 3.3V OIP3
–40°C 3.45V OIP3
+25°C 3.15V OIP3 +85°C 3.15V OIP3
+25°C 3.3V OIP3 +85°C 3.3V OIP3
+25°C 3.45V OIP3 +85°C 3.45V OIP3
840 850 860 870 880 890 900 910 920 930 940 950 960
LO FREQUENCY (MHz)
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 7. Output IP3 (dBm) vs. LO Frequency (Hz), with Supply and
Temperature Variations; Two-Tone Test (10 MHz and 12 MHz Baseband
Input Frequencies)
Figure 4. LO Phase Noise (900 MHz, Including Open-Loop VCO Noise)
10
9
0
–40°C 3.15V SBS
–40°C 3.3V SBS
–40°C 3.45V SBS
+25°C 3.15V SBS +85°C 3.15V SBS
+25°C 3.3V SBS +85°C 3.3V SBS
+25°C 3.45V SBS +85°C 3.45V SBS
–10
–20
–30
–40
–50
–60
–70
–80
8
7
6
–40°C 3.15V P
OUT
5
4
3
2
1
0
–40°C 3.3V P
OUT
–40°C 3.45V P
+25°C 3.15V P
OUT
OUT
+25°C 3.3V P
OUT
+25°C 3.45V P
+85°C 3.15V P
OUT
OUT
+85°C 3.3V P
OUT
+85°C 3.45V P
OUT
840 850 860 870 880 890 900 910 920 930 940 950 960
LO FREQUENCY (MHz)
840 850 860 870 880 890 900 910 920 930 940 950 960
LO FREQUENCY (MHz)
Figure 5. Single Sideband Tx Power Output (dBm) vs. LO frequency (Hz) with
Supply and Temperature Variations; Outputs Combined in 50:100 Balun
Figure 8. Unwanted Sideband Suppression (dBc) vs. LO Frequency (Hz) with
Supply and Temperature Variations
20
15
10
5
20
10
0
–10
–20
–30
–40
–50
–60
–40°C 3.15V P
OUT
–40°C 3.3V P
OUT
0
–5
–40°C 3.45V P
+25°C 3.15V P
OUT
OUT
+25°C 3.3V P
OUT
+25°C 3.45V P
+85°C 3.15V P
OUT
OUT
–70
–80
25°C 3.3V P
(dBm)
OUT
25°C 3.3V SBS (dBc)
25°C 3.3V LOFT (dBc)
25°C 3.3V HD2 (dBm)
25°C 3.3V HD3 (dBm)
+85°C 3.3V P
OUT
–10
–15
+85°C 3.45V P
IDEAL
OUT
–90
–100
–10
–5
0
5
10
15
20
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
3.4
P
(dBm)
DIFFERENTIAL INPUT VOLTAGE (V)
IN
Figure 9. Second- and Third-Order Distortion, Sideband Suppression (dBc),
Carrier Feedthrough (dBm) and SBS POUT vs. Baseband Differential Input
Level; LO Frequency = 900 MHz
Figure 6. Power Output vs. Baseband Input Power with Supply and
Temperature Variations
Rev. 0 | Page 10 of 28
ADF9010
9
8
7
6
5
4
3
2
1
0
20
0
–20
–40
–60
–80
–100
Fc 330KHz
Fc 1MHz
Fc 2MHz
BYPASS
–40°C 3.15V P
+25°C 3.15V P
+85°C 3.15V P
OUT
OUT
OUT
OUT
OUT
OUT
–40°C 3.3V P
+25°C 3.3V P
+85°C 3.3V P
OUT
OUT
OUT
–40°C 3.45V P
+25°C 3.45V P
+85°C 3.45V P
1
10
100
10k
100k
FREQUENCY (Hz)
1M
10M
INPUT FREQUENCY (MHz)
Figure 10. Single Sideband Power vs. Baseband Input Frequency, with
Supply and Temperature Variations; Maximum Gain Setting Selected;
LO Frequency = 900 MHz
Figure 11. Rx Filter Performance, Power vs. Input Frequency
Rev. 0 | Page 11 of 28
ADF9010
CIRCUIT DESCRIPTION
Rx SECTION
R COUNTER
The 14-bit R counter allows the input clock frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 8191 are allowed.
PGA
SETTING
OVF
Rx IP
IN
Rx IP
BB
A AND B COUNTERS
Rx IN
IN
Rx IN
BB
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide range of division ratios in the PLL
feedback counter. The counters are specified to work when
the prescaler output is 300 MHz or less.
DC OFFSET
CORRECTION
Figure 12. Rx Filter
Pulse Swallow Function
The Rx section of the ADF9010 features programmable base-
band low-pass filters. These are used to amplify the desired Rx
signal from the demodulator while removing the unwanted
portion to ensure no antialiasing occurs in the Rx ADC.
The A and B counters, in conjunction with the dual-modulus
prescaler (see Figure 14), make it possible to generate large
divider ratios. The equation for N is as follows:
N = BP + A
These filters have a programmable gain stage, allowing gain to
be selected from 3 dB to 24 dB in steps of 3 dB. The bandwidth
of these filters is also programmable, allowing 3 dB cutoff fre-
quencies of 330 kHz, 880 kHz, and 1.76 MHz, along with a
bypass mode. The filters utilize a fourth-order Bessel transfer
function (see the Specifications section for more information).
If desired, the filter stage can be bypassed.
where:
N is the overall divider ratio of the signal from the external
RF input.
P is the preset modulus of the dual-modulus prescaler.
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A is the preset divide ratio of the binary 5-bit swallow counter
(0 to 31).
Additionally, a rising edge on the OVF pin reduces the gain of
the Rx amplifiers by 6 dB. This is to correct a potential overflow
of the input to the ADC.
N = BP + A
13-BIT B
COUNTER
TO PFD
Updating the Rx calibration latch with the calibration bit
enabled calibrates the filter to remove any dc offset. The
3 dB cutoff frequency (fC) of the filters is calibrated also.
LOAD
LOAD
6-BIT A
COUNTER
PRESCALER
P/P + 1
FROM RF
INPUT STAGE
MODULUS
CONTROL
LO SECTION
LO Reference Input Section
N DIVIDER
The LO input stage is shown in Figure 13. SW1 and SW2
are normally closed switches% SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 14. A and B Counters
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it down
to a manageable frequency for the A and B CMOS counters.
The prescaler is programmable. The prescaler can be set in
software to 8/9, 16/17, or 32/33. For the ADF9010, however,
the 16/17 and 32/33 settings should be used. It is based on a
synchronous 4/5 core. A minimum divide ratio is possible for
fully contiguous output frequencies. This minimum is deter-
mined by P, the prescaler value, and is given by (P2 − P).
POWER-DOWN
CONTROL
100kΩ
SW2
NC
TO R COUNTER
REF
IN
NC
SW1
BUFFER
SW3
NO
Figure 13. Reference Input Stage
Rev. 0 | Page 12 of 28
ADF9010
DV
DD
PFD and Charge Pump
The phase frequency detector (PFD) takes inputs from the
R counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them (see Figure 15).
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
MUX
CONTROL
V
P
CHARGE
PUMP
UP
HI
D1
Q1
U1
DGND
R DIVIDER
Figure 16. MUXOUT Circuit
CLR1
Voltage-Controlled Oscillator (VCO)
The VCO core in the ADF9010 uses 16 overlapping bands, as
shown in Figure 17, to allow a wide frequency range to be covered
with a low VCO sensitivity (KV) and to result in good phase noise
and spurious performance. The VCO operates at 4× the LO
frequency, providing an output range of 840 MHz to 960 MHz.
CP
U3
DELAY
CLR2
U2
DOWN
HI
D2
Q2
The correct band is chosen automatically by the band select
logic at power-up or whenever the LO latch is updated. During
band select, which takes five PFD cycles, the VCO VTUNE is
disconnected from the output of the loop filter and connected
to an internal reference voltage.
N DIVIDER
CPGND
R DIVIDER
N DIVIDER
CP OUTPUT
3.5
3.0
2.5
2.
Figure 15. PFD Simplified Schematic and Timing (In Lock)
MUXOUT
The output multiplexer on the ADF9010 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the control
latch. The full truth table is shown in Figure 22. Figure 16
shows the MUXOUT section in block diagram form.
1.5
1.0
SERIES 1
0.5
0
750
Lock Detect
800
850
900
950
1000
FREQUENCY (Hz)
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. If the LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
Figure 17. VCO Bands
The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is pro-
vided at the R counter input to allow division by 1, 2, 4, or 8 and
is controlled by Bit BSC1 and Bit BSC2 in the Tx latch. Where the
required PFD frequency exceeds 1 MHz, the divide ratio should be
set to allow enough time to select the correct band.
With the LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
After the band is selected, normal PLL action resumes. The
nominal value of KV is 32 MHz/V or 8 MHz/V, taking into
account the divide by 4.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When a lock has been detected, this output is high with narrow
low-going pulses.
The output from the VCO is divided by 4 for the LO inputs to
the mixers, and for the LO output drive to the demodulator.
Rev. 0 | Page 13 of 28
ADF9010
LO Output
Mixers
The LOOUTP and LOOUTN pins are connected to the collectors
of an NPN differential pair driven by buffered outputs from the
VCO, as shown in Figure 18. To allow optimal power dissipation
vs. the output power requirements, the tail current of the diffe-
rential pair is programmable via Bit TP1 and Bit TP2 in the
control latch. The four current levels that can be set are: 6 mA,
8.5 mA, 11.5 mA, and 17.5 mA. These levels give output power
levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively,
if both outputs are combined in a 1 + 1:1 transformer or a 180°
microstrip coupler.
The ADF9010 has two double-balanced mixers, one for the
in-phase channel (I channel) and one for the quadrature
channel (Q channel). Both mixers are based on the Gilbert
cell design of four cross-connected transistors.
Tx Output
The TxOUTP and TxOUTN pins of the ADF9010 are connected
to the collectors of four NPN differential pairs driven by the
baseband signals, as shown in Figure 20. To allow the user
optimal power dissipation vs. the output power requirements,
the tail current of the differential pair is programmable via
Bit TP1 and Bit TP2 in the control latch. Two levels can be set%
these levels give output power levels of −3 dBm and, +3 dBm,
respectively, using a 50 Ω resistor to VDD and ac coupling into a
50 Ω load. Alternatively, both outputs can be combined in a 1 +
1:1 transformer or a 180° microstrip coupler. This buffer can be
powered off if desired.
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD
.
Another feature of the ADF9010 is that the supply current to
the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by
the mute Tx until lock detect (F4) bit in the control latch.
LO
P
LO N
OUT
OUT
Another feature of the ADF9010 is that the supply current to the Tx
output stage is shut down until the part achieves lock as measured
by the digital lock detect circuitry. This is enabled by the mute LO
until lock detect bit (F5) in the control latch.
BUFFER/
DIVIDE BY 4
VCO
Tx
P
OUT
Tx
N
OUT
Figure 18. LO Output Section
LO
LO
LO
LO
IP
QP
IN
QN
IP
IN
QP
QN
Tx SECTION
Figure 20. Tx Section
VCO
INTERFACING
Input Shift Register
LO
LO
P
OUT
÷4
TX IP
BB
N
OUT
TX IN
BB
The digital section of the ADF9010 includes a 24-bit input shift
register. Data is clocked into the 24-bit shift register on each
rising edge of SCLK. The data is clocked in MSB first. Data is
transferred from the shift register to one of four latches on
the rising edge of SLE. The destination latch is determined by
the state of the two control bits (C2, C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 21.
Tx
Tx
P
N
QUAD
PHASE
SPLITTER
OUT
INT/
EXT
LO
EXT
P
OUT
LO
EXT
N
Tx QP
BB
Tx QN
BB
The truth table for Bit C3, Bit C2, and Bit C1 is shown in Table 7.
It displays a summary of how the latches are programmed. Note
that some bits are used for factory testing and should not be
programmed by the user.
Figure 19. Tx Section
Tx Baseband Inputs
Differential in-phase (I) and quadrature baseband (Q) inputs
are high impedance inputs that must be dc-biased to approx-
imately 500 mV dc and e driven from a low impedance source.
Nominal characterized ac signal swing is 700 mV p-p on each
pin. This results in a differential drive of 1.4 V p-p with a 500 mV
dc bias.
Table 7. Truth Table
Control Bits
C3
X
C2
0
C1
0
Data Latch
Control latch
Tx latch
0
0
1
1
0
1
Rx calibration
LO latch
X
1
0
X
1
1
Rx filter
Rev. 0 | Page 14 of 28
ADF9010
LATCH STRUCTURE
Figure 21 shows the three on-chip latches for the ADF9010. The two LSBs determine which latch is programmed.
CONTROL LATCH
MUTE MUTE
LO Tx
UNTIL UNTIL
LD LD
Tx
OUTPUT
POWER
CHARGE
PUMP
CURRENT
LO
OUTPUT
POWER
CONTROL
BITS
MUXOUT
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RES PD4 PD3 PD2 PD1
TP2 TP1 CPI3 CPI2 CPI1
P2
P1
F5
F4
F3
F2
M3
M2
M1
F1
RES RES C2 (0) C1 (0)
Tx LATCH
Tx MOD
LO PHASE
BAND
SELECT
CLOCK
CONTROL
BITS
LO PHASE
13-BIT REFERENCE COUNTER
SELECT
SELECT
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 (0) C2 (0) C1 (1)
P2
R1
P1
T3
T2
T1 BSC2
R13 R12 R11 R10
R9
R8
R7
R6
R5
R4
R3
R2
BSC1
P3
Rx CALIBRATION
Tx MOD
LO PHASE
SELECT
BAND
SELECT
CLOCK
LO PHASE
SELECT
HIGH-PASS FILTER BOOST
TIMEOUT COUNTER
CONTROL
BITS
Rx CALIBRATION DIVIDER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RC1 HP6 HP5 HP4 HP3 HP2 HP1 C3 (1) C2 (0) C1 (1)
P3
P2
P1
T3
T2
T1 BSC2 BSC1 R13 RC6 RC5 RC4 RC3 RC2
LO LATCH
CONTROL
BITS
13-BIT B COUNTER
PRESCALER
5-BIT A COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
G1
B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1 C2 (1) C2 (0)
M1
P2
P1
Rx LATCH
CONTROL
BITS
Rx FILTER
BANDWIDTH
Rx FILTER
GAIN STEPS
TEST MODES
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
T13 T12 T1
DB1 DB0
T16
T15 T14
T10
T7
T6
T5
T4
HP
BW2 BW1
G2
G1
C2 (1) C1 (1)
T8
T3
T11
T9
T2
G3
Figure 21. Latch Summary
Rev. 0 | Page 15 of 28
ADF9010
MUTE MUTE
LO Tx
UNTIL UNTIL
LD LD
Tx
OUTPUT
POWER
CHARGE
PUMP
CURRENT
LO
OUTPUT
POWER
CONTROL
BITS
MUXOUT
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
RES PD4 PD3 PD2 PD1
TP2 TP1 CPI3 CPI2 CPI1
P2
P1
F5
F4
F3
F2
M3
M2
M1
F1
RES RES C2 (0) C1 (0)
THESE BITS ARE
RESERVED
AND SHOULD BE
SET TO 0, 1
THIS BIT
IS RESERVED
FOR FACTORY
TESTING AND
SHOULD BE
SET TO 0
COUNTER
F1
0
OPERATION
NORMAL
1
COUNTERS HELD
IN RESET
M3
M2
M1
0
OUTPUT
0
0
0
0
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
1
POWER DOWN
PD4 Rx
0
0
1
1
1
1
0
0
0
1
0
1
N DIVIDER OUTPUT
0
1
DISABLED
ENABLED
DV
DD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
1
1
1
1
0
1
SERIAL DATA OUTPUT
DGND
POWER DOWN
PD3 PLL
0
1
DISABLED
ENABLED
PHASE DETECTOR
POLARITY
F2
POWER DOWN
PD2 VCO
0
1
NEGATIVE
POSITIVE
0
1
DISABLED
ENABLED
POWER DOWN
PD1 Tx
0
1
DISABLED
ENABLED
CHARGE PUMP
OUTPUT
F3
0
1
NORMAL
THREE-STATE
Tx OUTPUT POWER
TP2
0
0
1
1
TP1
FULLY ON
–6dB
–6dB
0
1
0
1
MUTE Tx UNTIL
LOCK DETECT
F4
MUTE
0
1
DISABLED
ENABLED
MUTE LO UNTIL
LOCK DETECT
I
(mA)
CP
F5
CPI3
CPI2
CPI1
2.7kΩ
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10.0
4.7kΩ
10kΩ
0.31
0.63
0.94
1.25
1.56
1.87
2.19
2.50
0
1
DISABLED
ENABLED
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.63
1.25
1.87
2.50
3.13
3.75
4.38
5.00
P2
P1
LO OUTPUT POWER (COMBINED)
0
0
1
1
0
1
0
1
–4 dBm
–1 dBm
+2 dBm
+5 dBm
Figure 22. Control Latch
Rev. 0 | Page 16 of 28
ADF9010
Tx MOD
LO PHASE
SELECT
BAND
SELECT
CLOCK
LO PHASE
SELECT
CONTROL
BITS
13-BIT REFERENCE COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 (0) C2 (0) C1 (1)
P2
R1
P1
T3
T2
T1 BSC2
R13 R12 R11 R10
R9
R8
R7
R6
R5
R4
R3
R2
BSC1
P3
X = DON’T
CARE
R13
R12
R11
..........
R3
0
0
0
1
.
R2
0
1
1
0
.
R1
DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
8
0
0
1
1
0
1
0
1
THESE BITS ARE RESERVED AND SHOULD BE SET TO 1,1
T3
0
T2
0
T1
0
OUTPUT
NORMAL QUADRATURE
I TO BOTH
0
0
1
0
1
0
Q TO BOTH
0
1
1
EXTERNAL LO, QUADRATURE
ALL OFF
1
X
X
P3
0
P2
P1
0
OUTPUT
I OUT
0
0
1
1
0
0
1
1
0
1
Q OUT
0
0
IB OUT
0
1
QB OUT
EXTERNAL I
EXTERNAL Q
1
0
1
1
1
0
EXTERNAL I TO PLL, OUT OFF
ALL OFF
1
1
Figure 23. Tx Latch
Rev. 0 | Page 17 of 28
ADF9010
BAND
SELECT
CLOCK
Tx MOD
LO PHASE
SELECT
LO PHASE
SELECT
HIGH-PASS FILTER BOOST
TIMEOUT COUNTER
CONTROL
BITS
Rx CALIBRATION DIVIDER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RC1 HP6 HP5 HP4 HP3 HP2 HP1 C3 (1) C2 (0) C1 (1)
P3
P2
P1
T3
T2
T1 BSC2 BSC1 R13 RC6 RC5 RC4 RC3 RC2
X = DON’T
CARE
TIMEOUT
COUNTER
CYCLES
Rx FILTER f
C
CALIBRATION
F5
HP6
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
HP2
HP1
0
1
DISABLED
ENABLED
0
0
0
0
.
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
1
1
1
1
0
0
1
1
0
1
0
1
60
61
62
63
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
8
0
0
1
1
0
1
0
1
THESE BITS ARE RESERVED AND SHOULD BE SET TO 1,1
T3
T2
0
T1
0
OUTPUT
0
0
0
0
1
NORMALQUADRATURE
I TO BOTH
0
1
1
0
Q TO BOTH
1
1
EXTERNAL LO, QUADRATURE
ALL OFF
X
X
CAL COUNTER
DIVIDE RATIO
RC6
..........
RC2
RC1
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
P3
0
P2
0
P1
0
OUTPUT
I OUT
.
.
.
.
.
0
0
1
Q OUT
.
.
.
.
0
1
0
IB OUT
QB OUT
ALL OFF
1
1
1
1
0
0
1
1
0
1
0
1
60
61
62
63
0
1
1
1
X
X
Figure 24. Rx Calibration Latch
Rev. 0 | Page 18 of 28
ADF9010
CONTROL
BITS
13-BIT B COUNTER
PRESCALER
5-BIT A COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2
P1
G1
M1
B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1 C2 (1) C2 (0)
X = DON’T CARE
A COUNTER
A5
..........
A2
A1
DIVIDE RATIO
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
N DIV MUX OPERATION
0
1
VCO FEEDBACK TO N DIVIDER.
MUX FEEDBACK TO N DIVIDER.
.
.
.
.
.
.
.
.
1
0
0
28
1
1
1
..........
..........
..........
0
1
1
1
0
1
29
30
31
B12
B12
B11
B3
B2
0
0
1
1
.
B1
0
1
0
1
.
B COUNTER DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........
0
NOT ALLOWED
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
.
NOT ALLOWED
NOT ALLOWED
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
CP GAIN
0
OPERATION
USE THE PROGRAMMED CHARGE PUMP
CURRENT SETTING FROM CONTROL REGISTER
1
USE THE MAXIMUM CHARGE PUMP CURRENT
SETTING
N = BP + A, P IS THE PRESCALER VALUE SET IN THE FUNCTION LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
2
IS (P – P).
MIN
ADJACENT VALUES OF (N × F
) AT THE OUTPUT, N
REF
P2
P1
PRESCALER VALUE
0
0
1
1
0
1
0
1
8/9
16/17
32/33
32/33
Figure 25. LO Latch
Rev. 0 | Page 19 of 28
ADF9010
CONTROL
BITS
Rx FILTER
BANDWIDTH
Rx FILTER
GAIN STEPS
TEST MODES
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
T16
T15 T14
T13 T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
HP
BW2 BW1 G3
G2
G1
C2 (1) C1 (1)
G3
0
G2
G1
0
FILTER GAIN
3dB
0
0
1
1
0
0
1
1
0
1
6dB
0
0
9dB
0
1
12dB
15dB
18dB
21dB
24dB
1
0
1
1
THESE BITS ARE USED FOR FACTORY
TESTING AND SHOULD NOT BE
PROGRAMMED BY THE USER.
THEY SHOULD BE SET TO 0.
1
0
1
1
HP
0
HPF BOOST
DISABLED
ENABLED
1
BW2
BW1
Rx FILTER BANDWIDTH
0
0
1
1
0
1
0
1
LOW
1MHz
2MHz
BYPASSED
Figure 26. Rx Latch
Rev. 0 | Page 20 of 28
ADF9010
CONTROL LATCH
Tx LATCH
With (C2, C1) = (0, 0), the control latch is programmed.
Figure 22 shows the input data format for programming
the control latch.
With (C3, C2, C1) = (0, 0, 1), the Tx latch is programmed.
Figure 23 shows the input data format for programming
the Tx latch.
Power-Down
LO Phase Select
Programming a 1 to PD4, PD3, PD2, PD1 powers down
the circuitry for the Rx filters, PLL, VCO, and Tx sections,
respectively. Programming a 0 enables normal operation for
each section.
Bit P3, Bit P2, and Bit P1 set the phase of the LO output to the
demodulator. This enables the user to select the phase delay of
the Rx LO signal to the demodulator in 90° steps. See the truth
table in Figure 23. The Rx LO output can be disabled if desired.
Tx Output Power
Tx Modulation LO Phase Select
Bit TP1 and Bit TP2 set the output power level of the VCO.
See the truth table in Figure 22.
Bit T3, Bit T2, and Bit T1 set the input modulation of the
VCO. Normal quadrature to each mixer can be replaced by
choosing one LO phase to both mixers if desired. The normal
(I) or quadrature (Q) phase can be chosen. See the truth table
in Figure 23.
Charge Pump Current
Bit CPI3, Bit CPI2, and Bit CPI1 determine Current Setting 2.
See the truth table in Figure 22.
Band Select Clock
LO Output Power
Bits BSC2 and Bit BSC1 set a divider for the band select logic
clock input. The recommended setting is 1, 1, which programs
a value of 8 to the divider. No other setting is allowed.
Bit P1 and Bit P2 set the output power level of the LO. See the
truth table in Figure 22.
Mute LO Until Lock Detect
Reference Counter
Bit F5 is the mute until lock detect bit. This function, when
enabled, ensures that the LO outputs are not switched on
until the PLL is locked.
R13 to R1 set the counter divide ratio. The divide range is 1
(00 … 001) to 8191 (111 … 111).
Rx CALIBRATION LATCH
Mute Tx Until Lock Detect
With (C3, C2, C1) = (1, 0, 1), the Rx calibration latch is
programmed. Figure 24 shows the input data format for
programming the Rx calibration latch.
Bit F4 is the mute Tx until lock detect bit. This function, when
enabled, ensures that the Tx outputs are not switched on until
the PLL is locked.
LO Phase Select
Charge Pump Three-State
Bit P3, Bit P2, and Bit P1 set the phase of the LO output to the
demodulator. This enables the user to select the phase delay of
the Rx LO signal to the demodulator in 90° steps. See the truth
table in Figure 24. The Rx LO output can be disabled if desired.
Bit F3 puts the charge pump into three-state mode when pro-
grammed to a 1. It should be set to 0 for normal operation.
Phase Detector Polarity
Bit F2 sets the phase detector polarity. The positive setting
enabled by programming a 1 is used when using the on-chip
VCO with a passive loop filter or with an active noninverting
filter. It can also be set to 0. This is required if an active inverting
loop filter is used.
Tx Modulation LO Phase Select
Bit T3, Bit T2, and Bit T1 set the input modulation of the VCO.
Normal quadrature to each mixer can be replaced by choosing
one LO phase to both mixers if desired. The normal (I) or quad-
rature (Q) phase can be chosen. See the truth table in Figure 24.
MUXOUT Control
Band Select Clock
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Figure 22.
Bit BSC2 and Bit BSC1 set a divider for the band select logic
clock input. The recommended setting is 1, 1, which programs
a value of 8 to the divider. No other setting is allowed.
Counter Reset
Bit F1 is the counter reset bit for the PLL of the ADF9010.
When this bit is set to 1, the R, A, and B counters are held
in reset. For normal operation, this bit should be 0.
Rx Filter Calibration
Setting Bit R13 high performs a calibration of the Rx filters’
cutoff frequency, fC. Setting this bit to 0 ensures the filter cutoff
frequency calibration sequence is not initiated if this latch is
programmed.
Reserved Bits
DB3 and DB2 are spare bits that are reserved. They should
be programmed to 0 and 1, respectively.
Rev. 0 | Page 21 of 28
ADF9010
Rx Calibration Divider
A Counter Latch
Bit RC6 to Bit RC1 program a 6-bit divider, which outputs
a divided REFIN signal to assist calibration of the cutoff
frequency, fC, of the Rx filters. The calibration circuit uses
this divideddown PLL reference frequency to ensure an
accurate cutoff frequency in the Rx filter. The divider value
should be chosen to ensure that the frequency of the divided
down signal is exactly 2 MHz, that is, if a 32 MHz crystal is
used as the PLL REFIN frequency, then a value of 16 should
be programmed to the counter to ensure accurate calibration.
Bit A5 to Bit A1 program the 5-bit A counter. The divide range
is 0 (00000) to 31 (11111).
Rx LATCH
Program the Rx latch with (C2, C1) = (1, 1). Figure 26 shows
the input data format for programming the LO latch.
High-Pass Filter Boost
This function is enabled by setting the HP bit to 1. A 0 disables
this function. This is used to reduce settling time on the high-
pass filter from the Rx demodulator. This is usually used in
conjunction with the high-pass filter boost counter (See the
Rx Calibration Latch section).
High-Pass Filter Boost Timeout Counter
In most applications of the ADF9010, a high-pass filter is placed
between the demodulator outputs and the ADF9010 Rx inputs.
The capacitors used in these filters may require a long charge
up time, and to address this, a filter boost function exists that
charges up the capacitor to ~1.6 V. The duration for this boost
is set by the product of the period of the Rx calibration signal,
(REFIN divided by the Rx calibration divider) and the 6-bit value
programmed to these registers. This value can be as large as 63.
Programming a value of 000000 leads to the calibration time
being manually set by the HPF boost in the Rx latch. It becomes
necessary in such cases to program this bit to 0 for normal Rx
operation.
Rx Filter Bandwidth
The Rx filter bandwidth is programmable and is controlled by
Bit BW2 and Bit BW1. See the truth table in Figure 26.
Rx Filter Gain Steps
Bit G3 to Bit G1 set the gain of the Rx filters. The gain can
vary from 3 dB to 24 dB in 3 dB steps. See the truth table in
Figure 26.
INITIALIZATION
The correct initialization sequence for the ADF9010 is as follows:
LO LATCH
1. Power-down all blocks: Tx, Rx, PLL, and VCO. Set the Tx
output power off control latch to (1, 1). Set the LO phase
select off (P1, P2, P3) in Tx latch to (1, 1, 1).
2. Program the R1 latch with the desired R counter and
Tx values.
Program the LO latch with (C2, C1) = (1, 0). Figure 25 shows
the input data format for programming the LO latch.
Prescaler
Bit P2 and Bit P1 in the LO latch set the prescaler values.
3. Program R5 with Rx calibration data for frequency
calibration and high-pass filter boost.
CP Gain
4. Program R0 to power up all LO and Tx/Rx blocks.
5. Program R2 to encode correct LO frequency.
6. Program R3 to power up Rx filter.
Setting G1 to 0 chooses the programmed charge pump current
setting from the control latch. Setting this bit to 1 chooses the
maximum possible setting.
N Div Mux
INTERFACING
The ADF9010 has a simple SPI®-compatible interface for
writing to the device. SCLK, SDATA, and SLE control the data
transfer. See Figure 2 for the timing diagram.
Setting M1 to 0 feeds the VCO signals back to the N divider.
Setting this bit to 1 allows the mux signal to be fed back instead.
B Counter Latch
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device
is 833 kHz or one update every 1.2 μs. This is certainly more
than adequate for systems that have typical lock times in
hundreds of microseconds.
Bit B13 to Bit B1 program the B counter. The divide range is
3 (00 … 0011) to 8191 (11 … 111).
Rev. 0 | Page 22 of 28
ADF9010
APPLICATIONS INFORMATION
CE
VP
RXVDD
VCM
AVDD
DVDD
ADF9010
MxFE
SHA
RxBBIP
RxINIP
RxININ
RxBBIN
OVF
ADC
AGC
DC OFFSET
CORRECTION
VCM
SHA
RxBBQP
RxINQP
RxINQN
RxBBQN
SCLK
SDATA
SLE
24-BIT
INPUT SHIFT
REGISTER
DC OFFSET
CORRECTION
Tx BASEBAND
Rx BASEBAND
MUXOUT
RSET
PLL
REFIN
R
DIGITAL
CONTROL
PHASE
FREQUENCY
DETECTOR
COUNTER
CP
CHARGE
PUMP
N COUNTER
N = BP + A
B
CEXT
1
COUNTER
CEXT2
CEXT3
CEXT4
VTUNE
PRESCALER
P/P + 1
A
COUNTER
CT
CLK
DATA
LE
24-BIT
INPUT SHIFT
REGISTER
BALUN
LOOUTP
EN
TxBBIP
TxBBIN
TxBBQP
TxBBQN
LOOUT
N
DAC
DAC
PA MODULE
TxOUT
P
AUX
DAC
AUX
DAC
AUX
DAC
BALUN
TxOUT
N
DGND
AGND
Figure 27. Applications Diagram
The diagram in Figure 27 shows the ADF9010 in an RFID appli-
cation. The demodulator is driven by the LOOUTx pins of the
ADF9010. This demodulator produces quadrature baseband
signals that are gained up in the ADF9010 Rx filters. These
filtered analog baseband signals are then digitized by the ADC
on a mixed signal front-end (MxFE) part. The digital signals
are then processed by DSP.
shunt capacitors and series inductors. Due to the large self-
blocker, a 100 nF capacitor removes the dc generated by the
self-blocker inherent to RFID systems. This system is used
on the EVAL-ADF9010EBZ1 evaluation board.
100nF
0Ω
IHI
RxINIP
DEMOD
ADL5382
47pF
ADF9010
1.2nF
On the transmit side, the MxFE generates quadrature analog
baseband signals, which are upconverted to RF using the inte-
grated PLL and VCO. The modulated RF signals are combined
using a balun and gained up to 30 dBm by a power amplifier.
100nF
0Ω
RxININ
ILO
Figure 28. ADL5382 to ADF9010 Rx Interface
DEMODULATOR CONNECTION
To receive the back-scattered signals from an RFID tag,
the ADF9010 needs to be used with a high dynamic range
demodulator, such as the ADL5382 that is suitable for RFID
applications. Some extra filtration is provided by the optional
Rev. 0 | Page 23 of 28
ADF9010
pad. This ensures that the solder joint size is maximized. The
bottom of the chip scale package has a central thermal pad.
LO AND Tx OUTPUT MATCHING
The LO and Tx output stages are each connected to the collectors
of an NPN differential pair driven by buffered outputs from the
VCO or mixer outputs, respectively.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
The recommended matching for each of these circuits consists
of a 7.5 nH shunt inductor to VDD, a 100 pF series capacitor, and
in the case of the Tx output a 50:100 balun to combine the Tx
outputs. The Anaren BD0810J50100A00 is ideally suited to this
task.
PCB DESIGN GUIDELINES
The lands on the chip scale package (CP-48-1) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
The user should connect the printed circuit board thermal pad
to AGND.
Rev. 0 | Page 24 of 28
ADF9010
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
SECTION OF THIS DATA SHEET.
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 29. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-48-1
ADF9010BCPZ1
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
ADF9010BCPZ-RL1
ADF9010BCPZ-RL71
EVAL-ADF9010EBZ1
CP-48-1
CP-48-1
1 Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
ADF9010
NOTES
Rev. 0 | Page 26 of 28
ADF9010
NOTES
Rev. 0 | Page 27 of 28
ADF9010
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07373-0-8/08(0)
Rev. 0 | Page 28 of 28
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