ADG1212YCP [ADI]
1 pF Off Capacitance, 1 pC Charge Injection, 【15 V/12 V iCMOS⑩ Quad SPST Switches; 1 pF的关断电容， 1 pC的电荷注入， 【 15 V / 12 V iCMOS⑩四通道SPST开关
| 型号： | ADG1212YCP |
| 厂家： | 
ADI |
| 描述： | 1 pF Off Capacitance, 1 pC Charge Injection, 【15 V/12 V iCMOS⑩ Quad SPST Switches |
| 文件： | 总16页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 pF Off Capacitance, 1 pC Charge Injection,
1ꢀ ꢁV1ꢂ ꢁ
i
CMOS™ Quad SPST Switches
Preliminary Technical Data
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
FUNCTIONAL BLOCK DIAGRAM
FEATURES
S1
S1
S1
2 pF off capacitance
1 pC charge injection
33 V supply range
150 Ω on resistance
Fully specified at +12 V, 15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages
Typical power consumption: <0.03 µW
IN1
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
D1
S2
IN2
IN3
IN4
D2
S3
D2
S3
D2
S3
ADG1211
ADG1212
ADG1213
D3
S4
D3
S4
D3
S4
D4
D4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
APPLICATIONS
Figure 1.
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on the
other two switches. Each switch conducts equally well in both
directions when on, and has an input signal range that extends
to the supplies. In the off condition, signal levels up to the
supplies are blocked.
Video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1211/ADG1212/ADG1213 are monolithic CMOS
devices containing four independently selectable switches
designed on an iCMOS process. iCMOS (industrial-CMOS) is a
modular manufacturing process combining high voltage CMOS
(complementary metal-oxide semiconductor) and bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 30 V operation in a footprint
that no previous generation of high voltage parts has been able
to achieve. Unlike analog ICs using conventional CMOS proc-
esses, iCMOS components can tolerate high supply voltages,
while providing increased performance, dramatically lower
power consumption, and reduced package size.
The ADG1213 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
PRODUCT HIGHLIGHTS
1. 2 pF off capacitance ( 1ꢀ V supply).
2. 1 pC charge injection.
3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4. No VL logic power supply required.
ꢀ. Ultralow power dissipation: <0.03 µW.
6. 16-lead TSSOP and 4 mm × 4 mm LFCSP packages.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Terminology .......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits ..................................................................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Single Supply ................................................................................. 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
REVISION HISTORY
11/04—Revision PrE: Preliminary Version
Rev. PrE | Page 2 of 16
Preliminary Technical Data
ADADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
SPECIFICATIONS
SINGLE SUPPLY
VDD = 1ꢀ V 10ꢁ, VSS = −1ꢀ V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
25°C
85°C
Y Version1
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VDD to VSS
180
V
120
5
160
VS = 10 Vꢀ IS = −10 mA; Figure 20
VS = 10 V ꢀ IS = −10 mA
Ω typ
Ω max
Ω typ
On Resistance Match between
Channels (∆RON)
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON)
)
25
VS = −5 V/0 V/+5 V; IS = −10 mA
50
5
Ω max
LEAKAGE CURRENTS
Source Off Leakageꢀ IS (Off)
VDD = +10 Vꢀ VSS = −10 V
VS = 0 V/10 Vꢀ VD = 10 V/0 V; Figure 21
0.01
0.5
0.01
nA typ
nA max
nA typ
1
Drain Off Leakageꢀ ID (Off)
VS = 0 V/10 Vꢀ VD = 10 V/0 V; Figure 21
VS = VD = 0 V or 10 V; Figure 22
0.5
0.0ꢁ
1
nA max
nA typ
nA max
1
ꢀ
Channel On Leakageꢀ IDꢀ IS (On)
2
ꢀ
DIGITAL INPUTS
Input High Voltageꢀ VINH
Input Low Voltageꢀ VINL
Input Currentꢀ IINL or IINH
2.0
0.8
2.5
0.5
V min
V max
µA typ
µA max
pF typ
0.005
5
VIN = VINL or VINH
Digital Input Capacitanceꢀ CIN
DYNAMIC CHARACTERISTICS2
tON
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
RL = 300 Ωꢀ CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ωꢀ CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ωꢀ CL = 35 pF
VS1 = VS2 = 10 V; Figure 2ꢁ
VS = 0 Vꢀ RS = 0 Ωꢀ CL = 1 nF; Figure 25
RL = 50 Ωꢀ CL = 5 pFꢀ f = 1 MHz; Figure 26
RL = 50 Ωꢀ CL = 5 pFꢀ f = 1 MHz; Figure 27
RL = 600 Ωꢀ 5 V rmsꢀ f = 20 Hz to 20 kHz
RL = 50 Ωꢀ CL = 5 pF; Figure 28
tOFF
15
Break-before-Make Time Delayꢀ tD
15
1
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise 0.002
−3 dB Bandwidth
CS (Off)
CD (Off)
1
75
85
700
2
2
MHz typ
pF typ
pF typ
pF typ
CDꢀ CS (On)
ꢁ
POWER REQUIREMENTS
IDD
VDD = +16.5 Vꢀ VSS = −16.5 V
Digital Inputs = 0 V or VDD
0.001
0.001
0.001
µA typ
µA max
µA typ
µA max
µA typ
µA max
5.0
5.0
5.0
IDD
ISS
Digital Inputs = 5 V
Digital Inputs = 0 V or VDD
Rev. PrE | Page 3 of 16
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
Preliminary Technical Data
Parameter
25°C
85°C
Y Version1
Unit
Test Conditions/Comments
IGND
0.001
µA typ
µA max
µA typ
µA max
Digital Inputs = 0 V or VDD
5.0
5.0
IGND
0.001
Digital Inputs = 5 V
1 Temperature range for Y Version is −ꢁ0°C to +125°C.
2 Guaranteed by designꢀ not subject to production test.
VDD = 12 V 10ꢁ, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
25°C
85°C
Y Version1
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
V
220
1
250
Ω typ
Ω max
Ω typ
VS = +10 Vꢀ IS = −10 mA; Figure 20
VS = +10 Vꢀ IS = −10 mA
On Resistance Match between
Channels (∆RON)
Ω max
Ω typ
On -Resistance Flatness (RFLAT(ON)
)
12
VS = −5 V/0 V/+5 Vꢀ IS = −10 mA
VDD = 12 V
LEAKAGE CURRENTS
Source Off Leakageꢀ IS (Off)
0.01
0.5
0.01
0.5
0.0ꢁ
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 Vꢀ VD = 10 V/0 V; Figure 21
2.5
2.5
5
Drain Off Leakageꢀ ID (Off)
VS = 1 V/10 Vꢀ VD = 10 V/0 V; Figure 21
VS = VD = 1 V or 10 V; Figure 22
Channel On Leakageꢀ IDꢀ IS (On)
DIGITAL INPUTS
Input High Voltageꢀ VINH
Input Low Voltageꢀ VINL
Input Currentꢀ IINLor IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.001
5
VIN = VINL or VINH
0.5
Digital Input Capacitanceꢀ CIN
DYNAMIC CHARACTERISTICS2
tON
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ωꢀ CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ωꢀ CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ωꢀ CL = 35 pF
VS1 = VS2 = 8 V; Figure 2ꢁ
VS = 0 Vꢀ RS = 0 Ωꢀ CL = 1 nF; Figure 25
RL = 50 Ωꢀ CL = 5 pFꢀ f = 1 MHz; Figure 267
RL = 50 Ωꢀ CL = 5 pFꢀ f = 1 MHz; Figure 27
RL = 50 Ωꢀ CL = 5 pF; Figure 28
tOFF
15
Break-before-Make Time Delayꢀ tD
15
1
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
5
75
85
100
2
2
ꢁ
CD (Off)
CDꢀ CS (On)
Rev. PrE | Page ꢁ of 16
Preliminary Technical Data
ADADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
Parameter
25°C
85°C
Y Version1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
IDD
VDD = 13.2 V
Digital Inputs = 0 V or VDD
0.001
0.001
µA typ
µA max
µA typ
µA max
5.0
5.0
IDD
Digital Inputs = 5 V
1 Temperature range for Y Version is −ꢁ0°C to +125°C.
2 Guaranteed by designꢀ not subject to production test.
Rev. PrE | Page 5 of 16
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 2ꢀ°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS – 0.3 V to VDD + 0.3 V
GND – 0.3 V to VDD + 0.3 V or
30 mAꢀ whichever occurs first
Peak Currentꢀ S or D
100 mA (pulsed at 1 msꢀ 10%
duty cycle max)
Table 4. ADG1211/ADG1212 Truth Table
ADG1211 In
ADG1212 In
Switch Condition
Continuous Currentꢀ S or D
Operating Temperature Range
Industrial (B Version)
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
30 mA
0
1
1
0
On
Off
−ꢁ0°C to +85°C
−ꢁ0°C to +125°C
−65°C to +150°C
150°C
Table 5. ADG1213 Truth Table
Logic
Switch 1, 4
Switch 2, 3
16-Lead TSSOPꢀ θJA Thermal
Impedance
16-Lead LFCSPꢀ θJA Thermal
Impedance
150.ꢁ°C/W
0
1
Off
On
On
Off
30.ꢁ°C/W
Lead Temperatureꢀ Soldering
Vapor Phase (60 s)
Infrared (15 s)
215°C
220°C
1 Overvoltages at INꢀ Sꢀ or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as ꢁ000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitryꢀ permanent damage may occur on devices subjected to high energy
electrostatic discharges. Thereforeꢀ proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 6 of 16
Preliminary Technical Data
ADADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG1211/ADG1212/ADG1213
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
D1
S1
IN2
D2
S2
V
PIN 1
INDICATOR
12 S2
S1
VSS
GND
S4
1
2
3
4
ADG1211/
ADG1212/
ADG1213
TOP VIEW
11 VDD
10 NC
V
SS
DD
TOP VIEW
(Not to Scale)
GND
NC
S3
9
S3
S4
D4
D3
IN3
IN4
NC = NO CONNECT
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP
Mnemonic
IN1
D1
Function
TSSOP
1
2
3
15
16
1
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
S1
ꢁ
2
VSS
5
6
3
ꢁ
GND
Sꢁ
7
5
Dꢁ
8
0
6
7
8
9
10
11
12
13
1ꢁ
INꢁ
IN3
D3
S3
NC
VDD
S2
D2
Logic Control Input.
10
11
12
13
1ꢁ
15
16
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
No Connection.
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
IN2
Rev. PrE | Page 7 of 16
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
TERMINOLOGY
Preliminary Technical Data
IDD
CD (Off)
The positive supply current.
The off switch drain capacitance, measured with reference to
ground.
ISS
The negative supply current.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
VD (VS)
The analog voltage on Terminals D and S.
CIN
The digital input capacitance.
RON
The ohmic resistance between D and S.
tON
The delay between applying the digital control input and the
output switching on. See Figure 23.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
tOFF
The delay between applying the digital control input and the
output switching off.
IS (Off)
The source leakage current with the switch off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
ID, IS (On)
A measure of unwanted signal coupling through an off switch.
The channel leakage current with the switch on.
Crosstalk
VINL
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
The maximum input voltage for Logic 0.
VINH
Bandwidth
The minimum input voltage for Logic 1.
The frequency at which the output is attenuated by 3 dB.
IINL (IINH
)
On Response
The frequency response of the on switch.
The input current of the digital input.
CS (Off)
Insertion Loss
The loss due to the on resistance of the switch.
The off switch source capacitance, measured with reference to
ground.
Rev. PrE | Page 8 of 16
Preliminary Technical Data
ADADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 9. Leakage Currents as a Function of VD (VS)
Rev. PrE | Page 9 of 16
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 11. Leakage Currents as a Function of VD (VS)
Figure 12. Leakage Currents as a Function of Temperature
Preliminary Technical Data
Figure 13. Leakage Currents as a Function of Temperature
Figure 14. Supply Current vs. Input Switching Frequency
Figure 15. Charge Injection vs. Source Voltage
Rev. PrE | Page 10 of 16
Preliminary Technical Data
Figure 16. TON/TOFF Times vs. Temperature
Figure 17. Off Isolation vs. Frequency
ADADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
Figure 18. Crosstalk vs. Frequency
Figure 19. On Response vs. Frequency
Rev. PrE | Page 11 of 16
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
TEST CIRCUITS
Preliminary Technical Data
I
DS
V1
I
D
(ON)
A
I
(OFF)
A
I
(OFF)
A
S
D
S
D
S
D
S
D
NC
V
R
= V1/I
DS
V
D
V
V
D
S
ON
S
NC = No Connect
Figure 20. Test Circuit 1—On Resistance
Figure 21. Test Circuit 2—Off Leakage
Figure 22. Test Circuit 3 —On Leakage
V
V
DD
DD
SS
0.1µF
0.1µF
ADG1211
V
50%
50%
50%
IN
V
V
SS
V
L
OUT
S
D
V
50%
90%
IN
ADG1212
R
300V
C
L
V
S
35pF
IN
90%
V
OUT
GND
tOFF
tON
Figure 23. Test Circuit 4—Switching Times
V
V
DD
DD
SS
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
V
SS
90%
90%
V
V
S1
D1
OUT1
OUT2
V
V
V
S1
OUT1
C
35pF
R
300V
L
L
S2
D2
V
S2
OUT2
C
35pF
R
300V
L
L
90%
90%
IN1,
IN2
0V
ADG1213
GND
tD
tD
Figure 24. Test Circuit 5—Break Before Make Time Delay
V
V
V
DD
SS
V
DD
SS
V
V
ADG1212
ADG1211
IN
IN
ON
OFF
V
R
S
OUT
S
D
C
L
V
S
1nF
IN
V
OUT
DV
OUT
GND
Q
= C 3 DV
L
OUT
INJ
Figure 25. Test Circuit 6—Charge Injection
Rev. PrE | Page 12 of 16
Preliminary Technical Data
ADADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
V
V
V
DD
V
DD
SS
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
V
V
V
DD
V
DD
ANALYZER
SS
SS
S
S
50Ω
50Ω
50Ω
IN
IN
V
S
V
S
D
D
V
V
OUT
OUT
V
V
IN
R
50Ω
IN
R
L
50Ω
L
GND
GND
V
V
WITH SWITCH
OUT
OUT
OFF ISOLATION = 20 LOG
INSERTION LOSS = 20 LOG
V
S
V
WITHOUT SWITCH
OUT
Figure 26. Test Circuit 7—Off Isolation
Figure 28. Test Circuit 9—Bandwidth
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
OUT
S1
R
L
50Ω
ꢀ
D
R
50Ω
S2
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
S
Figure 27. Test Circuit 8—Channel-to-Channel Crosstalk
Rev. PrE | Page 13 of 16
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
OUTLINE DIMENSIONS
Preliminary Technical Data
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 29. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
13
16
12
1
0.65 BSC
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
TOP
VIEW
EXPOSED
3.75
BSC SQ
PAD
(BOTTOM VIEW)
0.75
0.60
0.50
4
9
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 30. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−ꢁ0°C to +125°C
−ꢁ0°C to +125°C
−ꢁ0°C to +125°C
−ꢁ0°C to +125°C
−ꢁ0°C to +125°C
−ꢁ0°C to +125°C
Package Description
Package Option
RU-16
CP-16-ꢁ
RU-16
CP-16-ꢁ
RU-16
CP-16-ꢁ
ADG1211YRU
ADG1211YCP
ADG1212YRU
ADG1212YCP
ADG1213YRU
ADG1213YCP
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Rev. PrE | Page 1ꢁ of 16
Preliminary Technical Data
NOTES
ADADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
Rev. PrE | Page 15 of 16
ADG1ꢂ11VADG1ꢂ1ꢂVADG1ꢂ13
NOTES
Preliminary Technical Data
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04778–0–11/04(PrE)
Rev. PrE | Page 16 of 16
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