ADG1221BRMZ-REEL7 [ADI]
Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS® Dual SPST Switches; 低电容，低电荷注入，A ±15 V / 12 V iCMOS®双通道SPST开关
| 型号： | ADG1221BRMZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS® Dual SPST Switches |
| 文件： | 总16页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Capacitance, Low Charge Injection,
± ±1 ꢀV/±ꢁ ꢀ iCMOS® Dual SPST Switches
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
FEATURES
FUNCTIONAL BLOCK DIAGRAM
<0.5 pC charge injection over full signal range
Off capacitance: 2 pF
Off leakage: 20 pA
Supply range: 33 V
On resistance: 120 Ω
ADG1221
ADG1222
S1
D1
S1
D1
IN1
D2
S2
IN1
D2
S2
IN2
Fully specified at 15 V, +12 V
No VL supply required
IN2
3 V logic-compatible inputs
Rail-to-rail operation
10-lead MSOP package
ADG1223
APPLICATIONS
S1
D1
IN1
D2
S2
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
IN2
Video signal routing
Communication systems
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 1.
GENERAL DESCRIPTION
ADG1222. The ADG1223 has one switch with digital control
logic similar to that of the ADG1221; the logic is inverted on
the other switch. The ADG1223 exhibits break-before-make
switching action for use in multiplexer applications. Each
switch conducts equally well in both directions when on and
The ADG1221/ADG1222/ADG1223 are monolithic, complemen-
tary metal-oxide semiconductor (CMOS) devices containing
four independently selectable switches designed on an iCMOS
(industrial CMOS) process. iCMOS is a modular manufacturing
process combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs, capable of 33 V operation, in a footprint that no
previous generation of high voltage parts has been able to achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lower power consumption,
and reduced package size.
has an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked.
0.5
T
= 25ºC
A
0.4
0.3
V
V
= +15V
= –15V
DD
SS
0.2
0.1
The ultralow capacitance and exceptionally low charge injection
of these switches make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Figure 2 shows that there is minimum
charge injection over the full signal range of the device.
0
V
V
= 12V
= 0V
DD
SS
–0.1
–0.2
–0.3
–0.4
–0.5
V
V
= +5V
= –5V
DD
SS
The ADG1221/ADG1222/ADG1223 contain two independent
single-pole/single-throw (SPST) switches. The ADG1221 and
ADG1222 differ only in that the digital control logic is inverted.
The ADG1221 switches are turned on with Logic 1 on the appro-
priate control input, and Logic 0 is required for the
–15
–10
–5
0
5
10
15
INPUT VOLTAGE (V)
Figure 2. Charge Injection vs. Input Voltage
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.......................................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Terminology.......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 13
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 1............................................................................. 4
Changes to tON Parameter and Power Requirements, IDD, Digital
Inputs = 5 V Parameter, Table 2...................................................... 5
2/07—Rev. 0: Initial Version
Rev. A | Page 2 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = –15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Temperature
Parameter
25°C
–40°C to +85°C –40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
VDD = +13.5 V, VSS = –13.5 V,
VS = 1ꢀ V, IS = –1 mA (see Figure 23)
12ꢀ
2ꢀꢀ
Ω typ
Ω max
24ꢀ
27ꢀ
On Resistance Match
VS = 1ꢀ V, IS = –1 mA
Between Channels, ∆RON
2.5
6
Ω typ
Ω max
1ꢀ
76
12
83
On Resistance Flatness, RFLAT(ON)
VS = –5 V/ꢀ V/+5 V; IS = –1 mA
2ꢀ
64
Ω typ
Ω max
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = –16.5 V
Source Off Leakage, IS (Off)
VS = 1ꢀ V, VD = 1ꢀ V (see Figure 24)
ꢀ.ꢀꢀ2
nA typ
ꢀ.1
ꢀ.6
ꢀ.6
ꢀ.6
1
1
1
nA max
Drain Off Leakage, ID (Off)
VS = 1ꢀ V, VD = 1ꢀ V (see Figure 24)
VS = VD = 1ꢀ V (see Figure 25)
ꢀ.ꢀꢀ2
ꢀ.1
nA typ
nA max
Channel On Leakage, ID, IS (On)
ꢀ.ꢀ1
ꢀ.2
nA typ
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.ꢀ
ꢀ.8
V min
V max
VIN = VINL or VINH
ꢀ.ꢀꢀ5
μA typ
μA max
pF typ
ꢀ.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
2.5
RL = 3ꢀꢀ Ω, CL = 35 pF, VS = 1ꢀ V
(see Figure 26)
13ꢀ
17ꢀ
ns typ
ns max
21ꢀ
13ꢀ
24ꢀ
14ꢀ
1ꢀ
tOFF
RL = 3ꢀꢀ Ω, CL = 35 pF, VS = 1ꢀ V
(see Figure 26)
85
1ꢀ5
ns typ
ns max
Break-Before-Make Time Delay
(ADG1223 Only), tBBM
RL = 3ꢀꢀ Ω, CL = 35 pF, VS1 = VS2 = 1ꢀ V
(see Figure 27)
4ꢀ
ns typ
ns min
pC typ
dB typ
Charge Injection, QINJ
Off Isolation
ꢀ.1
75
VS = ꢀ V, RS = ꢀ Ω, CL = 1 nF (see Figure 28)
RL = 5ꢀ Ω, CL = 1 pF, f = 1 MHz
(see Figure 29)
Rev. A | Page 3 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
Temperature
Parameter
25°C
–40°C to +85°C –40°C to +125°C Unit
Test Conditions/Comments
Channel-to-Channel
Crosstalk
9ꢀ
dB typ
RL = 5ꢀ Ω, CL = 1 pF, f = 1 MHz
(see Figure 3ꢀ)
Total Harmonic
Distortion + Noise, THD + N
–3 dB Bandwidth
CS (Off)
ꢀ.15
96ꢀ
% typ
RL = 1ꢀ kΩ, 5 V rms, f = 2ꢀ Hz to 2ꢀ kHz
MHz typ
RL = 5ꢀ Ω, CL = 1 pF (see Figure 31)
VS = ꢀ V, f = 1 MHz
1.7
2.2
pF typ
pF max
CD (Off)
VS = ꢀ V, f = 1 MHz
1.7
2.2
pF typ
pF max
CD, CS (On)
VS = ꢀ V, f = 1 MHz
3
4
pF typ
pF max
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = –16.5 V
ꢀ.ꢀꢀ1
14ꢀ
μA typ
μA max
μA typ
μA max
Digital inputs = ꢀ V or VDD
Digital inputs = ꢀ V or VDD
Digital inputs = 5 V
1.ꢀ
19ꢀ
Digital inputs = 5 V
ISS
Digital inputs = ꢀ V, 5 V, or VDD
ꢀ.ꢀꢀ1
μA typ
1.ꢀ
μA max
VDD/VSS
5/ 16.5
V min/max GND = ꢀ V
1 Guaranteed by design, not subject to production test.
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Temperature
–40°C to +85°C –40°C to +125°C Unit
Parameter
25°C
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
ꢀ V to VDD
V
VDD = 1ꢀ.8 V, VSS = ꢀ V, VS = ꢀ V to 1ꢀ V,
IS = –1 mA (see Figure 23)
3ꢀꢀ
475
Ω typ
Ω max
567
26
625
On Resistance Match
VS = ꢀ V to 1ꢀ V, IS = –1 mA
Between Channels, ∆RON
4.5
16
6ꢀ
Ω typ
Ω max
Ω typ
27
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
VS = 3 V/6 V/9 V, IS = –1 mA
VDD = 13.2 V, VSS = ꢀ V
Source Off Leakage, IS (Off)
VS = 1 V/1ꢀ V, VD = 1ꢀ V/1 V
(see Figure 24)
ꢀ.ꢀꢀ2
nA typ
ꢀ.1
ꢀ.6
ꢀ.6
1
nA max
Drain Off Leakage, ID (Off)
VS = 1 V/1ꢀ V, VD = 1ꢀ V/1 V
(see Figure 24)
ꢀ.ꢀꢀ2
ꢀ.1
nA typ
nA max
1
Rev. A | Page 4 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
Temperature
Parameter
25°C
–40°C to +85°C –40°C to +125°C Unit
Test Conditions/Comments
Channel On Leakage, ID, IS (On)
VS = VD = 1 V or 1ꢀ V (see Figure 25)
ꢀ.ꢀ1
ꢀ.2
nA typ
nA max
ꢀ.6
1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.ꢀ
ꢀ.8
V min
V max
VIN = VINL or VINH
ꢀ.ꢀꢀ1
3
μA typ
μA max
pF typ
ꢀ.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
RL = 3ꢀꢀ Ω, CL = 35 pF, VS = 8 V
(see Figure 26)
19ꢀ
25ꢀ
ns typ
ns max
3ꢀꢀ
19ꢀ
345
225
1ꢀ
tOFF
RL = 3ꢀꢀ Ω, CL = 35 pF, VS = 8 V
(see Figure 26)
12ꢀ
15ꢀ
ns typ
ns max
Break-Before-Make Time Delay
(ADG1223 Only), tBBM
RL = 3ꢀꢀ Ω, CL = 35 pF, VS1 = VS2 = 8 V
(see Figure 27)
7ꢀ
ns typ
ns min
pC typ
Charge Injection, QINJ
Off Isolation
ꢀ.2
75
VS = 6 V, RS = ꢀ Ω, CL = 1 nF
(see Figure 28)
RL = 5ꢀ Ω, CL =1 pF, f = 1 MHz
(see Figure 29)
dB typ
dB typ
MHz typ
Channel-to-Channel Crosstalk
9ꢀ
RL = 5ꢀ Ω, CL = 1 pF, f = 1 MHz
(see Figure 3ꢀ)
−3 dB Bandwidth
CS (Off)
55ꢀ
RL = 5ꢀ Ω, CL = 1 pF (see Figure 31)
VS = 6 V, f = 1 MHz
2.1
2.6
pF typ
pF max
CD (Off)
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
2.1
2.6
pF typ
pF max
CD, CS (On)
3.8
4.6
pF typ
pF max
POWER REQUIREMENTS
IDD
VDD = 13.2 V
ꢀ.ꢀꢀ1
14ꢀ
μA typ
μA max
μA typ
μA max
Digital inputs = ꢀ V or VDD
Digital inputs = ꢀ V or VDD
Digital inputs = 5 V
Digital inputs = 5 V
1.ꢀ
19ꢀ
VDD
5/16.5
V min/max VSS = ꢀ V, GND = ꢀ V
1 Guaranteed by design, not subject to production test.
Rev. A | Page 5 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3.
Parameter
Rating
VDD to VSS
35 V
–ꢀ.3 V to +25 V
+ꢀ.3 V to −25 V
Table 4. Thermal Resistance
Package Type
1ꢀ-Lead MSOP (4-Layer Board)
VDD to GND
VSS to GND
Analog Inputs1
θJA
θJC
Unit
2ꢀ6
44
°C/W
VSS – ꢀ.3 V to VDD + ꢀ.3 V or
3ꢀ mA, whichever occurs first
GND – ꢀ.3 V to VDD + ꢀ.3 V or
3ꢀ mA, whichever occurs first
Digital Inputs1
ESD CAUTION
Peak Current, S or D
1ꢀꢀ mA (pulsed at 1 ms,
1ꢀ% duty cycle max)
Continuous Current per
Channel, S or D
3ꢀ mA
Operating Temperature Range –4ꢀ°C to +125°C
Storage Temperature Range
Junction Temperature
–65°C to +15ꢀ°C
15ꢀ°C
Reflow Soldering Peak
Temperature, Pb free
26ꢀ°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current must be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1
S1
D1
D2
S2
1
2
3
4
5
10 IN2
ADG1221/
ADG1222/
ADG1223
9
8
7
6
V
DD
GND
NC
TOP VIEW
(Not to Scale)
V
SS
NC = NO CONNECT
Figure 3. 10-Lead MSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
9
1ꢀ
IN1
S1
D1
D2
S2
VSS
NC
GND
VDD
Logic Control Input.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
No Connect.
Ground (ꢀ V) Reference.
Most Positive Power Supply Potential.
Logic Control Input.
IN2
Table 6. ADG1221/ADG1222 Truth Table
ADG1221 INx
ADG1222 INx
Switch Condition
1
ꢀ
ꢀ
1
On
Off
Table 7. ADG1223 Truth Table
ADG1223 INx
Switch 1 Condition
Switch 2 Condition
ꢀ
1
Off
On
On
Off
Rev. A | Page 7 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
TERMINOLOGY
IDD
tON
The positive supply current.
The delay between applying the digital control input and the
output switching on (see Figure 26).
ISS
The negative supply current.
tOFF
The delay between applying the digital control input and the
output switching off (see Figure 26).
VD (VS)
The analog voltage on Terminal D and Terminal S.
tBBM
RON
Off time or on time measured between the 90% points of both
switches, when switching from one address state to another
(ADG1223 only).
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
Q
INJ (Charge Injection)
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (Off)
Off Isolation
The source leakage current with the switch off.
A measure of unwanted signal coupling through an off switch.
ID (Off)
Crosstalk
The drain leakage current with the switch off.
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
ID, IS (On)
The channel leakage current with the switch on.
–3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINL
The maximum input voltage for Logic 0.
On Response
The frequency response of the on switch.
VINH
The minimum input voltage for Logic 1.
Insertion Loss
The loss due to the on resistance of the switch.
IINL (IINH
)
The input current of the digital input.
THD + N (Total Harmonic Noise Plus Distortion)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
CS (Off)
The off switch source capacitance, measured with reference
to ground.
ACPSRR (AC Power Supply Rejection Ratio)
Measures the ability of a part to avoid coupling noise and spurious
signals that appear on the supply voltage pin to the output of the
switch. The dc voltage on the device is modulated by a sine wave
of 0.62 V p-p. The ratio of the amplitude of signal on the output
to the amplitude of the modulation is the ACPSRR.
CD (Off)
The off switch drain capacitance, measured with reference
to ground.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
Rev. A | Page 8 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
200
150
100
V
V
= +15V
= –15V
T
= 25°C
DD
SS
A
180
160
140
120
100
80
V
V
= +13.5V
= –13.5V
DD
SS
T
= +125°C
A
T
= +85°C
A
V
V
= +15V
= –15V
V
V
= +16.5V
= –16.5V
DD
SS
DD
SS
T
= +25°C
A
T
= –40°C
A
60
40
50
0
20
0
–18 –15 –12 –9 –6
–3
0
3
6
9
12 15 18
–15
–10
–5
0
5
10
15
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 4. On Resistance as a Function of VS (VD), Dual Supply
Figure 7. On Resistance as a Function of VS (VD)
for Different Temperatures, Dual Supply
450
600
500
400
300
200
T
= 25°C
V
V
= 12V
= 0V
A
DD
SS
400
350
300
250
200
T
= +125°C
A
T
= +85°C
A
V
V
= +5.5V
= –5.5V
DD
SS
150
100
T
= –40°C
A
T
= +25°C
A
100
0
50
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 5. On Resistance as a Function of VS (VD), Dual Supply
Figure 8. On Resistance as a Function of VS (VD)
for Different Temperatures, Single Supply
450
200
150
T
= 25°C
A
V
V
V
= +15V
= –15V
DD
400
350
300
250
200
150
100
SS
V
V
= 12V
= 0V
100
DD
SS
= ±10V
BIAS
V
V
= 10.8V
= 0V
DD
50
SS
0
–50
–100
–150
–200
–250
–300
–350
–400
–450
V
V
= 13.2V
= 0V
DD
SS
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
S
D
50
0
D
I
, I (ON) + +
I
, I (ON) – –
D S
D
S
0
2
4
6
8
10
12
0
20
40
60
80
100
120
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (ºC)
Figure 6. On Resistance as a Function of VS (VD), Single Supply
Figure 9. Leakage Current as a Function of Temperature, Dual Supply
Rev. A | Page 9 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
0.5
0.4
150
T
= 25ºC
A
V
V
V
= +5V
= –5V
DD
SS
100
50
= ±4.5V
V
V
= +15V
= –15V
BIAS
DD
SS
0.3
0.2
0
0.1
–50
–100
–150
–200
–250
0
V
V
= 12V
= 0V
DD
SS
–0.1
–0.2
–0.3
–0.4
–0.5
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
S
D
V
V
= +5V
= –5V
DD
SS
D
I
, I (ON) + +
I
, I (ON) – –
D S
D
S
0
20
40
60
80
100
120
–10
–5
0
5
10
–15
15
TEMPERATURE (ºC)
INPUT VOLTAGE (V)
Figure 10. Leakage Current as a Function of Temperature, Dual Supply
Figure 13. Charge Injection vs. Input Voltage
300
300
250
200
150
100
50
V
V
V
= 12V
= 0V
DD
SS
15V DS t
OFF
250
200
150
100
50
15V DS t
12V SS t
12V SS t
ON
OFF
ON
= 1/10V
BIAS
0
–50
–100
–150
–200
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
S
D
D
I
, I (ON) + +
I
, I (ON) – –
D S
D
S
0
20
40
60
80
100
120
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (ºC)
TEMPERATURE (ºC)
Figure 11. Leakage Current as a Function of Temperature, Single Supply
Figure 14. tON/tOFF vs. Temperature
120
0
–10
–20
–30
–40
–50
–60
–70
–80
I
PER CHANNEL
= 25ºC
DD
V
= +15V
DD
T
V
= –15V
A
SS
100
80
60
40
20
0
T = 25ºC
A
V
V
= +15V
= –15V
DD
SS
V
4
= 12V
DD
V
= 0V
SS
–90
–100
0
2
6
8
10
12
14
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
LOGIC LEVEL, INx (V)
Figure 12. IDD vs. Logic Level
Figure 15. Off Isolation vs. Frequency
Rev. A | Page 1ꢀ of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–20
–40
–60
–80
V
V
= +15V
= –15V
DD
SS
V
V
T
= +15V
= –15V
= 25ºC
DD
SS
NO DECOUPLING CAPS ON
Vp-p = 0.63V
= 25ºC
A
T
A
DECOUPLING CAPS ON
–100
–120
100k
1M
10M
FREQUENCY (Hz)
100M
10k
1G
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 16. Crosstalk vs. Frequency
Figure 18. ACPSRR vs. Frequency
10
0
–2
LOAD = 10kꢀ
= 25°C
V
V
= +15V
= –15V
DD
SS
T
A
–4
T = 25ºC
A
–6
1
–8
V
V
= +5V, V = –5V, V = +3.5V rms
SS
DD
DD
S
–10
–12
–14
–16
–18
–20
–22
–24
= +15V, V = –15V, V = +5V rms
SS
S
0.1
0.01
10
100
1k
FREQUENCY (Hz)
10k
100k
10k
100k
1M
10M
100M
100M
1G
FREQUENCY (Hz)
Figure 17. Insertion Loss vs. Frequency
Figure 19. THD + N vs. Frequency
Rev. A | Page 11 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
T
= +15V
= –15V
SOURCE OFF
DRAIN OFF
V
V
T
= +5V
= –5V
SOURCE OFF
DRAIN OFF
DD
SS
DD
SS
0.5
0
= 25ºC
= 25ºC
SOURCE/DRAIN ON
SOURCE/DRAIN ON
A
A
–15
–10
–5
0
5
10
15
–5
–4
–3
–2
–1
0
1
2
3
4
5
BIAS VOLTAGE (V)
BIAS VOLTAGE (V)
Figure 20. Capacitance vs. Bias Voltage
Figure 22. Capacitance vs. Bias Voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
T
= 12V
= 0V
SOURCE OFF
DRAIN OFF
DD
SS
= 25ºC
SOURCE/DRAIN ON
A
0
2
4
6
8
10
12
BIAS VOLTAGE (V)
Figure 21. Capacitance vs. Bias Voltage
Rev. A | Page 12 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
TEST CIRCUITS
I
(OFF)
A
I
(OFF)
A
S
D
Sx
Dx
V
V
D
S
I
DS
Figure 24. Test Circuit 2—Off Leakage
V1
I
(ON)
A
D
Sx
Dx
Sx
Dx
NC
V
D
V
S
R
= V1/I
ON
DS
NC = NO CONNECT
Figure 25. Test Circuit 3—On Leakage
Figure 23. Test Circuit 1—On Resistance
V
V
DD
SS
0.1µF
0.1µF
ADG1222
ADG1221
V
V
50%
50%
50%
50%
IN
V
V
SS
DD
V
L
OUT
Sx
Dx
IN
R
300ꢀ
C
L
V
ADG1221/
ADG1222
S
35pF
INx
90%
90%
V
OUT
GND
tOFF
tON
Figure 26. Test Circuit 4—Switching Times
V
V
SS
DD
DD
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
V
SS
90%
90%
V
V
S1
D1
OUT1
OUT2
V
V
V
S1
OUT1
C
35pF
R
300ꢀ
L
L
S2
D2
V
S2
OUT2
C
35pF
R
300ꢀ
L
L
90%
90%
IN1,
IN2
0V
ADG1223
GND
tD
tD
Figure 27. Test Circuit 5—Break-Before-Make Time Delay
V
V
DD
SS
V
V
SS
DD
V
V
ADG1222
ADG1221
IN
IN
ON
OFF
V
R
S
OUT
Sx
Dx
C
L
V
S
ADG1221/
ADG1222
1nF
INx
V
OUT
ΔV
OUT
GND
Q
= C × ΔV
L
OUT
INJ
Figure 28. Test Circuit 6—Charge Injection
Rev. A | Page 13 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
V
V
DD
SS
0.1µF
0.1µF
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
NETWORK
ANALYZER
V
V
DD
SS
Sx
50ꢀ
50ꢀ
INx
Sx
50ꢀ
V
S
INx
V
S
Dx
V
Dx
OUT
V
IN
R
50ꢀ
L
V
OUT
ADG1221/ADG1222/
ADG1223 GND
V
IN
R
L
ADG1221/ADG1222/
ADG1223
50ꢀ
GND
V
OUT
OFF ISOLATION = 20 LOG
V
WITH SWITCH
OUT
V
S
INSERTION LOSS = 20 LOG
V
WITHOUT SWITCH
OUT
Figure 29. Test Circuit 7—Off Isolation
Figure 31. Test Circuit 9—Bandwidth
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
V
SS
DD
0.1µF
0.1µF
V
OUT
S1
R
L
50ꢀ
AUDIO PRECISION
V
V
DD
SS
Dx
R
S
50ꢀ
50ꢀ
S2
Sx
ADG1221/ADG1222/
INx
V
S
V
V p-p
S
ADG1223
GND
Dx
V
OUT
V
IN
R
L
10kꢀ
ADG1221/ADG1222/
V
OUT
ADG1223
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
S
Figure 30. Test Circuit 8—Channel-to-Channel Crosstalk
Figure 32. Test Circuit 10—Total Harmonic Distortion + Noise
Rev. A | Page 14 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 33. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−4ꢀ°C to +125°C
−4ꢀ°C to +125°C
−4ꢀ°C to +125°C
−4ꢀ°C to +125°C
−4ꢀ°C to +125°C
−4ꢀ°C to +125°C
Package Description
Package Option
RM-1ꢀ
RM-1ꢀ
Branding
S27
S27
ADG1221BRMZ1
ADG1221BRMZ-REEL71
ADG1222BRMZ1
ADG1222BRMZ-REEL71
ADG1223BRMZ1
ADG1223BRMZ-REEL71
1ꢀ-Lead Mini Small Outline Package (MSOP)
1ꢀ-Lead Mini Small Outline Package (MSOP)
1ꢀ-Lead Mini Small Outline Package (MSOP)
1ꢀ-Lead Mini Small Outline Package (MSOP)
1ꢀ-Lead Mini Small Outline Package (MSOP)
1ꢀ-Lead Mini Small Outline Package (MSOP)
RM-1ꢀ
RM-1ꢀ
S28
S28
RM-1ꢀ
RM-1ꢀ
S2J
S2J
1 Z = Pb-free part.
Rev. A | Page 15 of 16
ADG±ꢁꢁ±VADG±ꢁꢁꢁVADG±ꢁꢁ3
NOTES
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06574-0-3/09(A)
Rev. A | Page 16 of 16
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