ADG1311 [ADI]
+-15 V/12 V Quad SPST Switches; ±15 V / 12 V四通道SPST开关
| 型号： | ADG1311 |
| 厂家： | 
ADI |
| 描述： | +-15 V/12 V Quad SPST Switches |
| 文件： | 总12页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
± ±1 V/±2 V Quad SPST Switches
ADG±3±±/ADG±3±2/ADG±3±3
FEATURES
FUNCTIONAL BLOCK DIAGRAM
33 V supply range
S1
S1
S1
IN1
IN2
IN3
IN4
Fully specified at +12 V, 15 V
130 Ω on resistance
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead SOIC
Typical power consumption: <0.03 μW
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
D1
S2
D2
S3
D2
S3
D2
S3
ADG1311
ADG1312
ADG1313
D3
S4
D3
S4
D3
S4
D4
D4
D4
APPLICATIONS
Signal switching
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Battery-powered systems
Communication systems
Audio/video signal routing
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
2. No VL logic power supply required.
3. 16-lead TSSOP and SOIC packages.
The ADG1311/ADG1312/ADG1313 are monolithic CMOS
devices containing four independently selectable switches
designed on a CMOS process.
The ADG1311/ADG1312/ADG1313 contain four independent
single-pole/single-throw (SPST) switches. The ADG1311 and
ADG1312 differ only in that the digital control logic is inverted.
The ADG1311 switches are turned on with Logic 0 on the appro-
priate control input, while Logic 1 is required for the ADG1312.
The ADG1313 has two switches with digital control logic similar
to the ADG1311; the logic is inverted on the other two switches.
The ADG1313 exhibits break-before-make switching action for
use in multiplexer applications.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADG±3±±/ADG±3±2/ADG±3±3
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Terminology.......................................................................................7
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 10
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
Single Supply................................................................................. 4
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADG±3±±/ADG±3±2/ADG±3±3
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Y Version1
Parameter
25°C
−40°C to +105°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VDD to VSS
230
V
130
200
5
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −1 mA; Figure 10
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
On Resistance Match Between
Channels (∆RON)
10
25
65
Ω max
Ω typ
Ω max
On Resistance Flatness (RFLAT(ON)
)
VS = −5 V/0 V/+5 V; IS = −1 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
10
10
10
nA typ
nA typ
nA typ
VS = 10 V, VD = ∓10 V; Figure 11
VS = 10V, VD = ∓10 V; Figure 11
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
VS = VD = 10 V; Figure 12
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
2.5
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
105
125
40
50
25
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = +10 V; Figure 13
RL = 300 Ω, CL = 35 pF
VS = +10 V; Figure 13
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 14
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 15
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 16
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 17
RL = 50 Ω, CL = 5 pF; Figure 18
180
60
tOFF
Break-Before-Make Time Delay, tD
(ADG1313 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
10
2
80
90
600
5
5
10
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
0.001
220
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
1.0
320
1.0
1.0
IDD
ISS
ISS
Digital inputs = 5 V
0.001
0.001
Digital inputs = 0 V or VDD
Digital inputs = 5 V
1 Temperature range for Y Version is −40°C to +105°C.
2 Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 12
ADG±3±±/ADG±3±2/ADG±3±3
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Y Version1
Parameter
25°C
−40°C to +105°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
520
V
325
500
10
Ω typ
Ω max
Ω typ
VS = 0 V − 10 V, IS = −1 mA; Figure 10
VDD = 10.8 V, VSS = 0 V
VS = 0 V − 10 V, IS = −1 mA
On Resistance Match Between
Channels (∆RON)
15
65
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON)
)
VS = +3 V/+6 V/+9 V, IS = −1 mA
VDD = 13.2 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
10
10
10
nA typ
nA typ
nA typ
VS = +1 V/+10 V, VD = +10 V/+1 V; Figure 11
VS = +1 V/+10 V, VD = +10 V/+1 V Figure 11
VS = VD = +1 V or +10 V; Figure 12
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.001
3
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
120
155
45
65
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 13
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 13
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; Figure 14
VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 15
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 16
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 17
RL = 50 Ω, CL = 5 pF; Figure 18
210
80
tOFF
Break-Before-Make Time Delay, tD
(ADG1313 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
10
2
80
90
500
5
5
10
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 13.2 V
Digital inputs = 0 V or VDD
0.001
220
μA typ
μA max
μA typ
μA max
1.0
IDD
Digital inputs = 5 V
320
1 Temperature range for Y Version is −40°C to +105°C.
2 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 12
ADG±3±±/ADG±3±2/ADG±3±3
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
Analog Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Table 4. ADG1311/ADG1312 Truth Table
Digital Inputs1
ADG1311 INx
ADG1312 INx
Switch Condition
0
1
1
0
On
Off
Peak Current, S or D
100 mA (pulsed at 1 ms,
10% duty cycle max)
Continuous Current per
Channel, S or D
25 mA
Table 5. ADG1313 Truth Table
Operating Temperature Range
Automotive
Storage Temperature Range
Junction Temperature
ADG1313 INx
Switch 1, 4
Switch 2, 3
−40°C to +105°C
−65°C to +150°C
150°C
0
1
Off
On
On
Off
16-Lead TSSOP, θJA Thermal
Impedance (4-layer board)
112°C/W
16-Lead SOIC, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb free
77°C/W
260°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 12
ADG±3±±/ADG±3±2/ADG±3±3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
D1
S1
IN2
D2
S2
V
ADG1311/
ADG1312/
ADG1313
TOP VIEW
V
SS
DD
GND
NC
S3
S4
D4
D3
IN3
IN4
NC = NO CONNECT
Figure 2. SOIC/TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
NC
VDD
S2
D2
Description
1
2
3
4
5
6
7
8
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
9
Logic Control Input.
10
11
12
13
14
15
16
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
No Connection.
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
IN2
Rev. 0 | Page 6 of 12
ADG±3±±/ADG±3±2/ADG±3±3
TERMINOLOGY
IDD
CD, CS (On)
The positive supply current.
The on switch capacitance, measured with reference to ground.
ISS
CIN
The negative supply current.
The digital input capacitance.
VD (VS)
tON
The analog voltage on Terminal D and Terminal S.
The delay between applying the digital control input and the
output switching on. See Figure 13.
RON
The ohmic resistance between D and S.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 13.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (Off)
The source leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID (Off)
The drain leakage current with the switch off.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
ID, IS (On)
The channel leakage current with the switch on.
Bandwidth
VINL
The frequency at which the output is attenuated by 3 dB.
The maximum input voltage for Logic 0.
On Response
The frequency response of the on switch.
VINH
The minimum input voltage for Logic 1.
Insertion Loss
The loss due to the on resistance of the switch.
IINL (IINH
)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
Rev. 0 | Page 7 of 12
ADG±3±±/ADG±3±2/ADG±3±3
TYPICAL PERFORMANCE CHARACTERISTICS
200
600
500
400
300
200
T
= 25°C
V
V
= 12V
= 0V
A
DD
SS
180
160
140
120
100
80
T
= +85°C
A
V
V
= +15V
= –15V
DD
SS
60
40
T
= –40°C
A
T
= +25°C
A
100
0
20
0
–15 –12
–9
–6
–3
0
3
6
9
12
15
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 3. On Resistance as a Function of VD (VS) for Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different
Temperatures, Single Supply
200
180
450
T
= 25°C
A
400
350
300
250
200
150
12V SS T
ON
160
140
120
100
15V DS T
V
V
= 12V
= 0V
ON
DD
SS
80
60
40
12V SS T
OFF
100
15V DS T
OFF
50
0
20
0
–40
–20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
TEMPERATURE (°C)
SOURCE OR DRAIN VOLTAGE (V)
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. TON/TOFF Times vs. Temperature
0
250
V
V
= +15V
= –15V
DD
SS
V
V
= +15V
= –15V
DD
SS
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
= 25°C
A
200
150
100
T
= +85°C
A
T
= +25°C
A
T
= –40°C
A
50
0
–100
–110
10k
100k
1M
10M
100M
1G
–15
–10
–5
0
5
10
15
FREQUENCY (Hz)
SOURCE OR DRAIN VOLTAGE (V)
Figure 8. Off Isolation vs. Frequency
Figure 5. On Resistance as a Function of VD (VS) for Different
Temperatures, Dual Supply
Rev. 0 | Page 8 of 12
ADG±3±±/ADG±3±2/ADG±3±3
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
V
= +15V
= –15V
= 25°C
DD
SS
T
A
–110
–120
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 9. Crosstalk vs. Frequency
Rev. 0 | Page 9 of 12
ADG±3±±/ADG±3±2/ADG±3±3
TEST CIRCUITS
I
DS
V1
I
D
(ON)
A
I
(OFF)
A
I
(OFF)
A
S
D
S
D
S
D
S
D
NC
V
R
= V1/I
DS
V
D
V
V
D
S
ON
S
NC = NO CONNECT
Figure 10. Test Circuit 1—On Resistance
Figure 11. Test Circuit 2—Off Leakage
Figure 12. Test Circuit 3 —On Leakage
V
V
DD
SS
0.1μF
0.1μF
ADG1312
ADG1311
V
V
50%
50%
50%
IN
V
V
SS
DD
V
L
OUT
S
D
50%
90%
IN
R
300Ω
C
L
V
S
35pF
IN
90%
V
OUT
GND
tOFF
tON
Figure 13. Test Circuit 4—Switching Times
V
V
DD
DD
SS
V
0.1μF
0.1μF
IN
50%
50%
0V
0V
V
V
SS
90%
90%
V
V
S1
D1
OUT1
OUT2
V
V
V
S1
OUT1
C
35pF
R
300Ω
L
L
S2
D2
V
S2
OUT2
C
35pF
R
300Ω
L
L
90%
90%
IN1,
IN2
0V
ADG1313
GND
tD
tD
Figure 14. Test Circuit 5—Break-Before-Make Time Delay
V
V
V
DD
SS
V
DD
SS
V
V
ADG1312
ADG1311
IN
IN
ON
OFF
V
R
S
OUT
S
D
C
L
V
S
1nF
IN
V
OUT
ΔV
OUT
GND
Q
= C × ΔV
L
OUT
INJ
Figure 15. Test Circuit 6—Charge Injection
Rev. 0 | Page 10 of 12
ADG±3±±/ADG±3±2/ADG±3±3
V
V
V
DD
V
DD
SS
SS
0.1μF
0.1μF
0.1μF
0.1μF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
DD
V
DD
SS
SS
S
S
50Ω
50Ω
50Ω
IN
IN
V
S
V
S
D
D
V
V
OUT
OUT
V
V
IN
R
50Ω
IN
R
50Ω
L
L
GND
GND
V
V
WITH SWITCH
OUT
OUT
OFF ISOLATION = 20 log
INSERTION LOSS = 20 log
V
S
V
WITHOUT SWITCH
OUT
Figure 16. Test Circuit 7—Off Isolation
Figure 18. Test Circuit 9—Bandwidth
V
V
DD
SS
0.1μF
0.1μF
NETWORK
ANALYZER
V
V
DD
SS
V
OUT
S1
R
L
50Ω
D2
R
50Ω
S2
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 17. Test Circuit 8—Channel-to-Channel Crosstalk
Rev. 0 | Page 11 of 12
ADG±3±±/ADG±3±2/ADG±3±3
OUTLINE DIMENSIONS
5.10
5.00
4.90
10.00 (0.3937)
9.80 (0.3858)
16
9
16
1
9
8
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
4.50
4.40
4.30
6.40
BSC
1
8
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
× 45°
PIN 1
0.25 (0.0098)
0.10 (0.0039)
1.20
MAX
8°
0°
0.15
0.05
0.20
0.09
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AC
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 20. 16-Lead Standard Small Outline Package [SOIC_N]
Figure 19. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Narrow Body
(R-16)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
RU-16
RU-16
R-16
ADG1311YRUZ1
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Narrow Body Small Outline Package [SOIC_N]
ADG1311YRUZ-REEL71
ADG1311YRZ1
ADG1311YRZ-REEL71
ADG1312YRUZ1
ADG1312YRUZ-REEL71
ADG1312YRZ1
ADG1312YRZ-REEL71
ADG1313YRUZ1
ADG1313YRUZ-REEL71
ADG1313YRZ1
ADG1313YRZ-REEL71
1 Z = Pb-free part.
R-16
RU-16
RU-16
R-16
R-16
RU-16
RU-16
R-16
R-16
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05676-0-10/05(0)
Rev. 0 | Page 12 of 12
相关型号：
©2020 ICPDF网 联系我们和版权申明