ADG212AKP-REEL [ADI]
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PQCC20, PLASTIC, LCC-20, Multiplexer or Switch;
| 型号： | ADG212AKP-REEL |
| 厂家： | 
ADI |
| 描述： | IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PQCC20, PLASTIC, LCC-20, Multiplexer or Switch 开关 |
| 文件： | 总16页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
Quad SPST Switches
Data Sheet
ADG211A/ADG212A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
44 V supply maximum rating
1ꢀ V analog signal range
ADG211A
S1
IN1
Low RON: 11ꢀ Ω maximum
D1
Low leakage: 0.ꢀ nA typical
S2
IN2
Break-before-make switching
D2
Single supply operation possible
Extended plastic temperature range: −40°C to +8ꢀ°C
TTL/CMOS compatible
S3
IN3
D3
Available in 16-lead PDIP/SOIC and 20-pead PLCC packages
Pin compatible to DG211/DG212
S4
IN4
D4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
ADG212A
S1
IN1
D1
S2
IN2
D2
S3
IN3
D3
S4
IN4
D4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 2.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG211A and ADG212A are monolithic CMOS devices
comprising four independently selectable switches. They are
designed on an enhanced LC2MOS process, which gives an
increased signal handling capability of 1ꢀ ꢁ. These switches
1. Extended Signal Range.
These switches are fabricated on an enhanced LC2MOS
process, resulting in high breakdown and an increased
analog signal range of 1ꢀ ꢁ.
also feature high switching speeds and low RON
.
2. Single Supply Operation.
For applications where the analog signal is unipolar (0 ꢁ to
1ꢀ ꢁ), the switches can be operated from a single 1ꢀ ꢁ
supply.
The ADG211A and ADG212A consist of four SPST switches.
They differ only in that the digital control logic is inverted. In
multiplexer applications, all switches exhibit break-before-make
switching action when driven simultaneously. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
3. Low Leakage.
Leakage currents in the range of ꢀ00 pA make these
switches suitable for high precision circuits. The added
feature of break-before-make allows for multiple outputs
to be tied together for multiplexer applications while
keeping leakage errors to a minimum.
Rev. C
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ADG211A/ADG212A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................4
Pin Configurations and Function Descriptions............................5
Typical Performance Characteristics ..............................................6
Terminology .......................................................................................9
Test Circuits..................................................................................... 10
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 13
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
REVISION HISTORY
10/12—Rev. B to Rev. C
Updated Format..................................................................Universal
Added Pin Descriptions, Table 3 .................................................... 5
Moved Table 4 ................................................................................... 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9................. 6
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
9/02—Rev. A to Rev. B
Rev. C | Page 2 of 16
Data Sheet
ADG211A/ADG212A
SPECIFICATIONS
VDD = +15 V, VSS = −15 V, VL = 5 V, unless otherwise noted.
Table 1.
25°C
−40°C to +85°C
Parameter
Min Typ Max Min Typ Max Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
RON vs. VD (VS)
RON Drift
15
20
0.5
5
15
V
Ω
%
%/°C
%
115
175
−10 V ≤ VS ≤ +10 V, IDS = 1 mA, see Figure 21
VS = 0 V, IDS = 1 mA
RON Match
LEAKAGE CURRENTS
IS (Off)
0.5
0.5
0.5
nA
nA
nA
nA
nA
nA
VD = 14 V; VS =
VD = 14 V; VS =
14 V; see Figure 22
14 V; see Figure 22
Off Input Leakage
ID (Off)
5
5
5
100
100
200
Off Output Leakage
ID (On)
VD = VS = 14 V; see Figure 23
On Channel Leakage
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
INL or INH
2.4
V
V
µA
pF
TTL compatibility is independent of VL
0.8
1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
5
1
tOPEN
30
ns
ns
ns
dB
See Figure 24
See Figure 25
See Figure 25
1
tON
600
450
1
tOFF
Off Isolation
80
VS = 10 V (p-p); f = 100 kHz;
RL = 75 Ω; see Figure 26
Channel-to-Channel Crosstalk
CS (Off)
CD (Off)
CS, CD (On)
80
5
5
16
20
dB
pF
pF
pF
pC
See Figure 27
QINJ, Charge Injection
RS = 0 Ω; CL = 1000 pF; VS = 0 V; see Figure 28
Digital inputs = VINL or VINH
POWER SUPPLY
IDD
IDD
ISS
ISS
IL
0.6
0.1
mA
mA
mA
mA
mA
1
0.2
0.9
1 Sample tested at 25°C to ensure compliance.
Rev. C | Page 3 of 16
ADG211A/ADG212A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise stated.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
44 V
VDD to VSS
VDD to GND
25 V
VSS to GND
−25 V
VL to GND
−0.3 V, 25 V
Analog Inputs1
Voltage at S, D
Continuous Current, S or D
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle
Digital Inputs1
Voltage at IN
ESD CAUTION
VSS − 0.3 V to VDD + 0.3 V
30 mA
70 mA
VSS − 2 V to VDD + 2 V or
20 mA, Whichever
Occurs First
Power Dissipation (Any Package)
Up to +75°C
470 mW
Derates above +75°C by
Operating Temperature
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
6 mW/°C
−40°C to +85°C
−65°C to +150°C
+300°C
1 Overvoltage at IN, S, or D will be clamped by diodes. Current should be
limited to the Maximum Rating listed in Table 2.
Rev. C | Page 4 of 16
Data Sheet
ADG211A/ADG212A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
3
2
1
20 19
PIN 1
4
5
6
7
8
18
17
S1
S2
INDENTFIER
V
V
DD
SS
IN1
D1
S1
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
ADG211A/
ADG212A
TOP VIEW
(Not to Scale)
NIC
16 NIC
ADG211A/
ADG212A
GND
S4
15
14
V
L
S3
V
13
12
V
V
SS
DD
TOP VIEW
(Not to Scale)
GND
L
9
11 12 13
10
S4
D4
11 S3
10 D3
NOTES
IN4
9
IN3
1. NIC = NO INTERNAL CONNECTION.
Figure 3. PDIP, SOIC Pin Configuration
Figure 4. PLCC Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
PLCC
PD I P, SOIC
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
VL
VDD
S2
D2
Description
1
2
Logic Control Input.
2
3
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
3
4
4
5
5
7
6
8
7
9
8
10
9
12
Logic Control Input.
10
11
12
13
14
15
16
13
14
15
17
18
19
20
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Logic Supply Voltage.
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
IN2
NIC
1, 6, 11, 16
No Internal Connection.
Table 4. Truth Table
ADG211A In
ADG212A In
Switch Condition
0
1
1
0
On
Off
Rev. C | Page 5 of 16
ADG211A/ADG212A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
The switches can comfortably operate anywhere in the 10 V to 15 V single or dual supply range, with only a slight degradation in
performance. The following graphs show the relevant performance curves. The test circuits and test conditions are given in a following
section, Test Circuits.
120
90
60
30
0
120
90
60
30
0
V
V
= +15V
= –15V
V
V
= 15V
= 0V
DD
SS
DD
SS
70°C
25°C
0°C
70°C
25°C
0°C
–15
–10
–5
0
5
10
15
0
5
10
15
V
(V ) (V)
S
V
(V ) (V)
S
D
D
Figure 5. RON as a Function of VD (VS), Dual 15 V Supplies
Figure 8. RON as a Function of VD (VS), Single +15 V Supply
120
90
60
30
0
150
120
90
60
30
0
V
V
= +10V
= –10V
V
V
= 10V
= 0V
DD
SS
DD
SS
70°C
25°C
0°C
70°C
25°C
0°C
–10
–5
0
5
10
0
5
10
V
(V ) (V)
V (V ) (V)
D S
D
S
Figure 6. RON as a Function of VD (VS), Dual 10 V Supplies
Figure 9. RON as a Function of VD (VS), Single +10 V Supply
100
2.5
V
V
= +15V
= –15V
TEMP = 0°C TO 70°C
DD
SS
2.0
1.5
1.0
0.5
0
10
I
(ON)
D
1
I
(OFF)
S
I
(OFF)
D
0.1
0.01
20
30
40
50
60
70
80
90
10
11
12
13
14
15
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 7. Leakage Current as a Function of Temperature
(Note That Leakage Current Reduces as the Supply Voltages Reduce)
Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply
Voltage
Rev. C | Page 6 of 16
Data Sheet
ADG211A/ADG212A
220
200
180
160
140
120
100
220
200
180
160
140
120
100
80
70°C
25°C
0°C
70°C
25°C
0°C
80
10
10
11
12
13
14
15
11
12
13
14
15
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (±V)
Figure 14. tON vs. Supply Voltage (Single Supply)
Figure 11. tON vs. Supply Voltage (Dual Supply)
80
60
40
20
0
80
60
40
20
0
70°C
25°C
0°C
25°C
70°C
0°C
10
11
12
13
14
15
10
11
12
13
14
15
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (±V)
Figure 15. tOFF vs. Supply Voltage (Single Supply)
Figure 12. tOFF vs. Supply Voltage (Dual Supply)
60
40
50
60
70
80
90
V
V
= +15V
= –15V
DD
SS
20
V
V
= +15V
= 0V
DD
SS
0
SINGLE SUPPLY
DUAL SUPPLY
–20
–40
–16
–12
–8
–4
0
4
8
12
16
10
11
12
13
14
15
V
(V)
SUPPLY VOLTAGE (V)
S
Figure 16. Charge Injection vs. Source Voltage (VS) for Dual and Single 15 V
Supplies
Figure 13. Off Isolation and Channel-to-Channel Crosstalk vs. Supply Voltage
Rev. C | Page 7 of 16
ADG211A/ADG212A
Data Sheet
60
0.7
0.6
0.5
0.4
0.3
0.2
0.1
40
0°C
V
V
= +10V
= –10V
DD
SS
25°C
70°C
20
V
V
= +10V
= 0V
DD
SS
0
–20
–40
–16
–12
–8
–4
0
4
8
12
16
10
11
12
13
14
15
V
(V)
SUPPLY VOLTAGE (±V)
S
Figure 17. Charge Injection vs. Source Voltage for Dual and Single 10 V
Supplies
Figure 19. IDD vs. Supply Voltage, (Dual Supply)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.4
0°C
0.3
0°C
25°C
70°C
0.2
0.1
70°C
25°C
0
10
11
12
13
14
15
10
11
12
13
14
15
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (±V)
Figure 18. ISS vs. Supply Voltage (Dual Supply)
Figure 20. IDD vs. Supply Voltage (Single Supply)
Rev. C | Page 8 of 16
Data Sheet
ADG211A/ADG212A
TERMINOLOGY
tOFF
RON
Delay time between the 50% and 90% points of the digital input
and switch off condition.
Ohmic resistance between the out and S terminals.
RON Match
tOPEN
Difference between the RON of any two channels.
Off time measured between 50% points of both switches, which
are connected as a multiplexer when switching from one
address state to another.
IS (Off)
Source terminal leakage current when the switch is off.
ID (Off)
VINL
Drain terminal leakage current when the switch is off.
Maximum input voltage for a logic low.
ID (On)
VINH
Leakage current that flows from the closed switch into the body.
Minimum input voltage for a logic high.
VD (VS)
I
INL (IINH)
Analog voltage on the D, S terminals.
Input current of the digital input.
CS (Off)
VDD
Switch input capacitance off condition.
Most positive voltage supply.
CD (Off)
VSS
Switch output capacitance off condition.
Most negative voltage supply.
CIN
VL
Digital input capacitance.
Logic supply voltage.
CD, CS (On)
IDD
Input or output capacitance when the switch is on.
Positive supply current.
tON
ISS
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Negative supply current.
Rev. C | Page 9 of 16
ADG211A/ADG212A
TEST CIRCUITS
Data Sheet
I
DS
V1
I
(ON)
A
D
S
D
S
D
V
V
V
D
S
S
R
= V1/I
ON
DS
Figure 21.
Figure 23.
I
(OFF)
I
(OFF)
A
S
D
S
D
A
V
V
D
S
Figure 22.
+5V +15V
V
3V
ADG211A
ADG212A
V
L
DD
V
IN
S1
D1
D2
V
OUT
2V
3V
S2
14pF 330Ω
V
IN
*
*
IN1
IN2
V
IN
V
OUT
50%
V
GND
SS
–15V
tOPEN
*BOTH THE BUFFER AND INVERTER SHOULD
HAVE THE SAME PROPAGATION DELAY.
Figure 24.
3V
V
V
+5V
DD
ADG211A
V
IN
50%
50%
50%
V
L
DD
S
D
V
3V
OUT
2V
50%
V
V
IN
330Ω
14pF
IN
ADG212A
V
IN
V
V
GND
SS
90%
90%
OUT
SS
tON
tOFF
Figure 25.
Rev. C | Page 10 of 16
Data Sheet
ADG211A/ADG212A
+5V
V
V
DD
DD
V
L
75Ω
S
D
D
S
+5V
V
V
DD
DD
V
IN
V
L
V
S
V
OUT
V
S
D
IN
R
75Ω
L
V
NC
OUT
V
IN
R
75Ω
V
V
L
GND
SS
V
S
V
V
GND
SS
SS
ADG211A: V = 5V
IN
ADG212A: V = 0V
OFF ISOLATION =
20 × log |V /V
ADG211A: V = 0V
IN
ADG212A: V = 5V
CHANNEL-TO-CHANNEL
CROSSTALK = 20 × log |V /V
|
|
SS
IN
S
OUT
IN
S
OUT
Figure 27. Channel-to-Channel Crosstalk
Figure 26. Off Isolation
+5V
V
V
DD
DD
5V
V
L
AD711
V
V
R
IN
S
S
D
V
OUT
0V
C
1µF
L
V
S
V
IN
ΔV
OUT
OUT
V
V
GND
SS
Q
= C × ΔV
L OUT
INJ
SS
Figure 28. Charge Injection
Rev. C | Page 11 of 16
ADG211A/ADG212A
Data Sheet
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 29. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 30.16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Rev. C | Page 12 of 16
Data Sheet
ADG211A/ADG212A
0.180 (4.57)
0.165 (4.19)
0.048 (1.22 )
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.20 (0.51)
MIN
0.020 (0.50)
R
3
4
19
0.021 (0.53)
0.013 (0.33)
0.048 (1.22)
0.042 (1.07)
18
14
PIN 1
0.050
(1.27)
BSC
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
0.330 (8.38)
0.290 (7.37)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
8
9
13
0.020
(0.51)
R
0.045 (1.14)
0.025 (0.64)
R
0.356 (9.04)
0.350 (8.89)
SQ
0.120 (3.04)
0.090 (2.29)
0.395 (10.03)
0.385 (9.78)
SQ
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
ADG211AKN
ADG211AKNZ
ADG211AKPZ
ADG211AKR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead PDIP
16-Lead PDIP
Package Option
N-16
N-16
P-20
R-16
R-16
R-16
R-16
20-Lead PLCC
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead PDIP
20-Lead PLCC
20-Lead PLCC
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
ADG211AKRZ
ADG211AKRZ-REEL
ADG211AKRZ-REEL7
ADG212AKNZ
ADG212AKPZ
ADG212AKPZ-REEL
ADG212AKR
N-16
P-20
P-20
R-16
R-16
R-16
ADG212AKRZ
ADG212AKRZ-REEL
1 Z = RoHS Compliant Part.
Rev. C | Page 13 of 16
ADG211A/ADG212A
NOTES
Data Sheet
Rev. C | Page 14 of 16
Data Sheet
NOTES
ADG211A/ADG212A
Rev. C | Page 15 of 16
ADG211A/ADG212A
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10950-0-10/12(C)
Rev. C | Page 16 of 16
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