ADG2188YCPZ-R2 [ADI]
IC CMOS 8 】 8 Unbuffered Analog Switch Array with Dual/Single Supplies; IC CMOS 8 】 8无缓冲模拟开关与双阵列/单电源供电
| 型号： | ADG2188YCPZ-R2 |
| 厂家： | 
ADI |
| 描述： | IC CMOS 8 】 8 Unbuffered Analog Switch Array with Dual/Single Supplies |
| 文件： | 总28页 (文件大小：667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
I2C® CMOS 8 × 8 Unbuffered Analog
Switch Array with Dual/Single Supplies
ADG2188
FEATURES
GENERAL DESCRIPTION
I2C-compatible interface
The ADG2188 is an analog cross point switch with an
array size of 8 × 8. The switch array is arranged so that
there are eight columns by eight rows, for a total of 64
switch channels. The array is bidirectional, and the rows and
columns can be configured as either inputs or outputs. Each
of the 64 switches can be addressed and configured through
the I2C-compatible interface. Standard, full speed, and high
speed (3.4 MHz) I2C interfaces are supported. Any
3.4 MHz high speed I2C option
32-lead LFCSP_VQ (5 mm × 5 mm)
Double-buffered input logic
Simultaneous update of multiple switches
Up to 300 MHz bandwidth
Fully specified at dual 5 V/single +12 V operation
On resistance 35 Ω maximum
Low quiescent current < 20 μA
simultaneous switch combination is allowed. An additional
feature of the ADG2188 is that switches can be updated
simultaneously, using the LDSW command. In addition,
APPLICATIONS
AV switching in TV
Automotive infotainment
AV receivers
RESET
a
option allows all of the switch channels to be
reset/off. At power on, all switches are in the off condition.
The device is packaged in a 32-lead, 5 mm × 5 mm
LFCSP_VQ.
CCTV
Ultrasound applications
KVM switching
Telecom applications
Test equipment/instrumentation
PBX systems
FUNCTIONAL BLOCK DIAGRAM
V
V
V
L
DD
SS
ADG2188
1
1
INPUT
SCL
REGISTER
AND
7 TO 64
LATCHES
8 × 8 SWITCH ARRAY
X0 TO X7 (I/O)
SDA
DECODER
64
64
LDSW
LDSW
A2 A1 A0
GND
Y0 TO Y7 (I/O)
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG2188
TABLE OF CONTENTS
Features .............................................................................................. 1
Load Switch (LDSW)................................................................. 18
Readback ..................................................................................... 18
Serial Interface ................................................................................ 19
High Speed I2C Interface........................................................... 19
Serial Bus Address...................................................................... 19
Writing to the ADG2188............................................................... 20
Input Shift Register .................................................................... 20
Write Operation.......................................................................... 22
Read Operation........................................................................... 22
Evaluation Board ............................................................................ 24
Using the ADG2188 Evaluation Board ................................... 24
Power Supply............................................................................... 24
Schematics................................................................................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I2C Timing Specifications............................................................ 7
Timing Diagram ........................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits..................................................................................... 15
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
RESET
/Power-On Reset ............................................................ 18
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADG2188
SPECIFICATIONS
VDD = 12 V 10%, VSS = 0 V, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 1.
B Version
−40°C to
Y Version
−40°C to
Parameter
+25°C
+85°C
+25°C
+125°C
Unit
Conditions
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD − 2 V
VDD − 2 V
V max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
30
35
32
37
45
50
4.5
8
2.3
3.5
14.5
18
30
35
32
37
45
50
4.5
8
2.3
3.5
14.5
18
VDD = 10.8 V, VIN = 0 V, IS = −10 mA
VDD = 10.8 V, VIN = 1.4 V, IS = −10 mA
VDD = 10.8 V, VIN = 5.4 V, IS = −10 mA
VDD = 10.8 V, VIN = 0 V, IS = −10 mA
VDD = 10.8 V, VIN = 0 V to 1.4 V, IS = −10 mA
VDD = 10.8 V, VIN = 0 V to 5.4 V, IS = −10 mA
40
42
57
9
42
47
62
10
5
On Resistance Matching
Between Channels, ∆RON
On Resistance Flatness, RFLAT(ON)
4
20
22
LEAKAGE CURRENTS
VDD = 13.2 V
Channel Off Leakage, IOFF
Channel On Leakage, ION
0.03
0.03
0.03
0.03
μA typ
μA typ
VX = 7 V/1 V, VY = 1 V/7 V
VX = VY = 1 V or 7 V
DYNAMIC CHARACTERISTICS2
COFF
CON
tON
11
11
pF typ
pF typ
ns typ
ns max
ns typ
ns max
% typ
18.5
170
185
210
250
0.04
18.5
170
185
210
250
0.04
RL = 300 Ω, CL = 35 pF
RL = 300 Ω, CL = 35 pF
190
255
195
260
tOFF
THD + N
RL = 10 kΩ, f = 20 Hz to 20 kHz,
VS = 1 V p-p
PSRR
90
dB typ
f = 20 kHz; without decoupling;
see Figure 24
−3 dB Bandwidth
210
16.5
−69
210
16.5
−69
MHz typ
MHz typ
dB typ
Individual inputs to outputs
8 inputs to 1 output
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Differential Gain
Differential Phase
−63
−76
0.4
0.6
−3.5
−63
−76
0.4
0.6
−3.5
dB typ
dB typ
% typ
° typ
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
VS = 4 V, RS = 0 Ω, CL = 1 nF
Charge Injection
pC typ
LOGIC INPUTS (Ax, RESET)2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
2.0
0.8
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
7
0.005
7
1
1
Input Capacitance, CIN
Rev. 0 | Page 3 of 28
ADG2188
B Version
−40°C to
Y Version
−40°C to
Parameter
LOGIC INPUTS (SCL, SDA)2
+25°C
+85°C
+25°C
+125°C
Unit
Conditions
Input High Voltage, VINH
0.7 VL
VL + 0.3
−0.3
0.7 VL
VL + 0.3
−0.3
V min
V max
V min
V max
μA typ
μA max
V min
pF typ
Input Low Voltage, VINL
0.3 VL
0.3 VL
Input Leakage Current, IIN
0.005
7
0.005
7
VIN = 0 V to VL
1
1
Input Hysteresis
0.05 VL
0.05 VL
Input Capacitance, CIN
LOGIC OUTPUT (SDA)2
Output Low Voltage, VOL
0.4
0.6
1
0.4
0.6
1
V max
V max
μA max
ISINK = 3 mA
ISINK = 6 mA
Floating State Leakage Current
POWER REQUIREMENTS
IDD
0.05
0.05
0.05
0.05
μA typ
μA max
μA typ
μA max
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
1
1
1
1
ISS
IL
Interface Inactive
0.3
0.1
0.4
0.3
0.1
0.4
μA typ
2
2
μA max
mA typ
mA max
mA typ
mA max
Interface Active: 400 kHz fSCL
Interface Active: 3.4 MHz fSCL
0.2
0.2
-HS model only
1.2
1.7
1 Temperature range is as follows: B version: −40°C to +85°C; Y version: −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 28
ADG2188
VDD = +5 V 10% , VSS = −5 V 10% , VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
B Version
−40°C to
+25°C +85°C
Y Version
−40°C to
+25°C +125°C
Parameter
Unit
Conditions
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD − 2 V V max
Ω typ
34
34
40
50
55
66
75
4.5
8
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = 0 V, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = +1.4 V, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS to 0 V, IS = −10 mA
40
50
55
66
75
4.5
8
17
20
34
45
65
85
9
50
70
95
10
25
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
On Resistance Matching
Between Channels, ∆RON
On Resistance Flatness, RFLAT(ON)
17
20
34
23
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS to +1.4 V,
IS = −10 mA
42
45
42
48
Ω max
LEAKAGE CURRENTS
VDD = 5.5 V, VSS = 5.5 V
Channel Off Leakage, IOFF
Channel On Leakage, ION
0.03
0.03
0.03
0.03
μA typ
μA typ
VX = +4.5 V/−2 V, VY = −2 V/+4.5 V
VX = VY = −2 V or +4.5 V
DYNAMIC CHARACTERISTICS2
COFF
CON
tON
6
9.5
6
9.5
pF typ
pF typ
ns typ
ns max
ns typ
ns max
% typ
170
200
210
250
0.04
170
200
210
250
0.04
90
RL = 300 Ω, CL = 35 pF
RL = 300 Ω, CL = 35 pF
215
255
220
260
tOFF
THD + N
PSRR
RL = 10 kΩ, f = 20 Hz to 20 kHz, VS = 1 V p-p
f = 20 kHz; without decoupling; see Figure 24
dB typ
−3 dB Bandwidth
300
18
300
18
MHz typ Individual inputs to outputs
MHz typ 8 inputs to 1 output
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Differential Gain
Differential Phase
−66
−64
dB typ
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
−62
−79
1.5
1.8
−3
−62
−79
1.5
1.8
−3
dB typ
dB typ
% typ
° typ
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
VS = 0 V, RS = 0 Ω, CL = 1 nF
Charge Injection
pC typ
LOGIC INPUTS (Ax, RESET)2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
2.0
0.8
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
7
0.005
7
1
1
Input Capacitance, CIN
LOGIC INPUTS (SCL, SDA)2
Input High Voltage, VINH
0.7 VL
VL + 0.3
−0.3
0.7 VL
VL + 0.3
−0.3
V min
V max
V min
Input Low Voltage, VINL
0.3 VL
0.3 VL
V max
μA typ
μA max
Input Leakage Current, IIN
0.005
0.005
VIN = 0 V to VL
1
1
Rev. 0 | Page 5 of 28
ADG2188
B Version
−40°C to
+25°C +85°C
Y Version
−40°C to
+25°C +125°C
Parameter
Unit
Conditions
Input Hysteresis
0.05 VL
0.05 VL
V min
pF typ
Input Capacitance, CIN
LOGIC OUTPUT (SDA)2
Output Low Voltage, VOL
7
7
0.4
0.6
1
0.4
0.6
1
V max
V max
μA max
ISINK = 3 mA
ISINK = 6 mA
Floating State Leakage Current
POWER REQUIREMENTS
IDD
0.05
1
0.05
1
0.005
1
0.005
1
μA typ
μA max
μA typ
μA max
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
ISS
IL
Interface Inactive
0.3
0.3
μA typ
2
2
μA max
mA typ
mA max
mA typ
mA max
Interface Active: 400 kHz fSCL
Interface Active: 3.4 MHz fSCL
0.1
0.1
0.4
0.3
0.1
0.1
0.4
0.3
-HS model only
1 Temperature range is as follows: B version: –40°C to +85°C; Y version: –40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 28
ADG2188
I2C TIMING SPECIFICATIONS
VDD = 5 V to 12 V; VSS = −5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2).
Table 3.
ADG2188 Limit at TMIN, TMAX
Parameter1 Conditions
Min
Max
100
400
Unit
kHz
kHz
Description
fSCL
Standard mode
Fast mode
Serial clock frequency
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
3.4
1.7
MHz
MHz
μs
t1
4
0.6
tHIGH, SCL high time
tLOW, SCL low time
μs
60
ns
ns
μs
μs
120
4.7
1.3
t2
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
Standard mode
Fast mode
160
320
250
100
10
ns
ns
ns
ns
ns
μs
μs
t3
tSU;DAT, data setup time
tHD;DAT, data hold time
3
t4
0
0
3.45
0.9
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
Standard mode
Fast mode
0
0
70
150
ns
ns
μs
μs
ns
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
t5
t6
4.7
0.6
160
4
0.6
160
4.7
1.3
4
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time for a (repeated) start condition
High speed mode2
Standard mode
Fast mode
t7
t8
tBUF, bus free time between a stop and a start condition
tSU;STO, setup time for a stop condition
Standard mode
Fast mode
High speed mode2
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
0.6
160
t9
1000
300
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
20 + 0.1 CB
10
20
80
ns
ns
ns
ns
160
300
300
t10
20 + 0.1 CB
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
10
20
80
160
ns
ns
Rev. 0 | Page 7 of 28
ADG2188
ADG2188 Limit at TMIN, TMAX
Parameter1 Conditions
Min
Max
1000
300
Unit
ns
ns
Description
t11
t11A
t12
tSP
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
tRCL, rise time of SCL signal
20 + 0.1 CB
10
20
40
80
ns
ns
ns
ns
1000
300
tRCL1, rise time of SCL signal after a repeated start condition
and after an acknowledge bit
Fast mode
20 + 0.1 CB
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
10
20
80
ns
ns
ns
ns
160
300
300
tFCL, fall time of SCL signal
Fast mode
20 + 0.1 CB
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Fast mode
10
20
0
40
80
50
10
ns
ns
ns
ns
Pulse width of suppressed spike
High speed mode2
0
1 Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line; tR and tF are measured between
0.3 VDD and 0.7 VDD
.
2 High speed I2C is available only in -HS models
3 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
t11
t12
t2
t6
SCL
SDA
t6
t5
t10
t3
t8
t4
t1
t9
t7
S
P
S
P
S = START CONDITION
P = STOP CONDITION
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. 0 | Page 8 of 28
ADG2188
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to VSS
15 V
VDD to GND
VSS to GND
VL to GND
Analog Inputs
Digital Inputs
−0.3 V to +15 V
+0.3 V to −7 V
−0.3 V to +7 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to VL + 0.3 V or 30 mA,
whichever occurs first
Continuous Current
10 V on Input; Single Input
Connected to Single Output
1 V on Input; Single Input
Connected to Single Output
10 V on Input; Eight Inputs
Connected to Eight Outputs
65 mA
90 mA
25 mA
Operating Temperature Range
Industrial (B Version)
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
32-Lead LFCSP_VQ
–40°C to +85°C
–40°C to +125°C
–65°C to +150°C
150°C
θJA Thermal Impedance
Reflow Soldering (Pb Free)
Peak Temperature
108.2°C/W
260°C (+0/–5)
Time at Peak Temperature
10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 28
ADG2188
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
V
24
23
22
21
20
19
18
V
SS
DD
PIN 1
INDICATOR
NC
NC
NC
NC
NC
X7
NC
X0
X1
X2
X3
X4
X5
ADG2188
8 × 8
TOP VIEW
(Not to Scale)
X6
17
9
10 11 12 13 14 15 16
NC = NO CONNECT
Exposed Paddle Soldered to VSS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions1
Pin No.
Mnemonic Description
1
VSS
Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin should be tied to GND.
2, 19 to 23 NC
No Connect.
3 to 8,
17, 18
X0 to X7
Can be inputs or outputs.
9 to 16
24
Y0 to Y7
VDD
Can be inputs or outputs.
Positive Power Supply Input.
25
VL
Logic Power Supply Input.
26
27
SDA
SCL
Digital I/O. Bidirectional open drain data line. External pull-up resistor required.
Digital Input, Serial Clock Line. Open drain input that is used in conjunction with SDA to clock data into the
device. External pull-up resistor required.
28
29
30
31
32
A0
A1
A2
RESET
GND
Logic Input. Address pin that sets the least significant bit of the 7-bit slave address.
Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address.
Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address.
Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0.
Ground. Reference point for all circuitry on the ADG2188.
1 It is recommended that the exposed paddle be soldered to VSS to improve heat dissipation and crosstalk.
Rev. 0 | Page 10 of 28
ADG2188
TYPICAL PERFORMANCE CHARACTERISTICS
90
80
70
60
50
40
30
200
T
= 25°C
= 10mA
A
T
I
= 25°C
= 10mA
A
I
DS
180 DS
160
140
120
100
80
V
= 7.2V
DD
V
DD
= 0V
SS
V
= +8V
V
= 8V
DD
V
= –5V
= +5V
SS
DD
V
60
V
= 8.8V
DD
V
DD
= 0V
SS
= +12V
40
V
8
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
9 10 11 12
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 4. Signal Range
Figure 7. RON vs. Source Voltage, VDD = 8 V 10%
85
75
65
55
45
35
25
80
V
V
= +5V
= –5V
= 10mA
DD
SS
T
= 25°C
= 10mA
A
I
DS
70
60
50
40
30
20
10
0
I
DS
T
= +125°C
A
V
/V = ±4.5V
DD SS
T
= +85°C
A
V
/V = ±5V
DD SS
T
= +25°C
A
T
= –40°C
A
V
/V = ±5.5V
DD SS
–5
–4
–3
–2
–1
0
1
–5.5
–4.5
–3.5
–2.5
–1.5
–0.5
0.5
1.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 8. RON vs. Temperature, Dual 5 V Supplies
Figure 5. RON vs. Source Voltage, Dual 5 V Supplies
70
65
60
55
50
45
40
35
30
25
20
60
50
40
30
20
10
0
V
V
= 12V
= 0V
= 10mA
T
I
= 25°C
= 10mA
DD
SS
A
T
= +125°C
A
DS
I
DS
V
= 10.8V
DD
T
= +85°C
A
V
= 12V
DD
T
= +25°C
A
T
= –40°C
A
V
6
= 13.2V
DD
0
1
2
3
4
5
7
8
0
1
2
3
4
5
6
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 6. RON vs. Supplies, VDD = 12 V 10%
Figure 9. RON vs. Temperature, VDD = 12 V
Rev. 0 | Page 11 of 28
ADG2188
80
18
16
14
12
10
8
V
V
= 12V
= 0V
DD
SS
V
V
= 8V
= 0V
= 10mA
DD
SS
70
60
50
40
30
20
10
0
Y CHANNELS, V
= 7V
BIAS
I
DS
T
= +125°C
A
X CHANNELS, V
= 7V
BIAS
T
= +85°C
A
Y CHANNELS, V
= 1V
BIAS
T
= +25°C
A
6
T
= –40°C
A
4
2
0
–2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
20
40
60
80
100
120
SOURCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 10. RON vs. Temperature, VDD = 8 V
Figure 13. On Leakage vs. Temperature, 12 V Single Supply
16
14
12
10
8
9
V
V
= 12V
= 0V
V
V
= +5V
= –5V
DD
SS
DD
SS
8
7
X, Y CHANNELS;
= 7V ON X CHANNEL;
V
BIAS
1V ON Y CHANNEL
6
5
X CHANNELS,
= +4V
V
BIAS
4
3
6
X, Y CHANNELS;
V = 1V ON X CHANNEL;
Y CHANNELS,
= –2V
2
V
BIAS
7V ON Y CHANNEL
BIAS
4
1
2
0
0
–1
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. On Leakage vs. Temperature, Dual 5 V Supplies
Figure 14. Off Leakage vs. Temperature, 12 V Single Supply
12
0
V
V
= +5V
= –5V
DD
SS
–0.5
10
8
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
X, Y CHANNELS;
= +4V ON X CHANNEL;
V
BIAS
–2V ON Y CHANNEL
6
4
X, Y CHANNELS;
= –2V ON X CHANNEL;
V
BIAS
+4V ON Y CHANNEL
V
= +5V, V = –5V
SS
2
DD
V
= +12V, V = 0V
SS
DD
0
–2
0
20
40
60
80
100
120
–5
–3
–1
1
3
5
7
9
11
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 12. Off Leakage vs. Temperature, Dual 5 V Supplies
Figure 15. Charge Injection vs. Supply Voltage
Rev. 0 | Page 12 of 28
ADG2188
0
–1
–2
–3
–4
–5
–6
–7
–8
240
220
200
180
160
140
120
100
tOFF
V
= +5V, V = –5V
SS
DD
tON
V
= 12V, V = 0V
SS
DD
V
V
= +5V
= –5V
= 25°C
DD
SS
T
A
–40
–20
0
20
40
60
80
100
120
10
1k
100k
10M
1G
10G
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. tON/tOFF Times vs. Temperature
Figure 19. One Input to Eight Outputs Bandwidth, 5 V Dual Supply
–2
–3
–4
–5
–6
–7
–8
–10
V
V
= +5V TO +12V
= –5V TO 0V
= 25°C
DD
SS
–20
–30
T
A
–40
–50
–60
–70
–80
–90
V
V
= +5V
= –5V
= 25°C
DD
SS
–100
–110
T
A
10
1k
100k
10M
1G 10G
10
1k
100k
10M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Individual Inputs to Individual Outputs Bandwidth,
Dual 5 V Supply
Figure 20. Off Isolation vs. Frequency
–1
–2
–3
–4
–5
–6
V
V
T
= +5V TO +12V
= –5V TO 0V
= 25°C
DD
SS
–20
–40
A
ADJACENT
CHANNELS
–60
–80
NON-ADJACENT
CHANNELS
–100
V
V
= 12V
= 0V
–7
DD
SS
T
= 25°C
A
–8
10
–120
1k
100k
10M
1G
10G
10
1k
100k
10M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Individual Inputs to Individual Outputs Bandwidth,
12 V Single Supply
Figure 21. Crosstalk vs. Frequency
Rev. 0 | Page 13 of 28
ADG2188
0.35
0
–20
V
V
= +5V
= –5V
DD
SS
V
V
A
= 5V/12V
= –5V/0V
DD
SS
T
= 25°C
0.30
0.25
0.20
0.15
0.10
0.05
0
0.2V p-p RIPPLE
V
= 5V
L
SWITCH ON,
WITHOUT DECOUPLING
–40
SWITCH OFF,
WITHOUT DECOUPLING
–60
–80
WITH DECOUPLING
V
= 3V
L
–100
–120
0
0.5
1.0
1.5
2.0
2.5
3.0
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 24. ACPSRR
Figure 22. Digital Current (IL) vs. Frequency
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 5V
L
V
= 3V
L
0
1
2
3
4
5
6
V
(V)
LOGIC
Figure 23. Digital Current (IL) vs. VLOGIC for Varying Digital Supply Voltage
Rev. 0 | Page 14 of 28
ADG2188
TEST CIRCUITS
The test circuits show measurements on one channel for clarity, but the circuit applies to any of the switches in the matrix.
I
DS
V1
I
I
OFF
A
OFF
X
Y
X
Y
A
I
ON
A
X
Y
NC
V
V
V
R
= V1/I
V
Y
S
X
Y
ON
DS
Figure 25. On Resistance
Figure 26. Off Leakage
Figure 27. On Leakage
V
V
V
V
DD
SS
0.1µF
0.1µF
50%
9TH DATA BIT
DD
SS
V
OUT
X
Y
90%
V
R
300Ω
OUT
C
35pF
L
L
V
X
tOFF AND tON
GND
Figure 28. Switching Times, tON, tOFF
V
V
SS
DD
DD
0.1
µF
0.1µF
SW OFF
SW ON
V
V
SS
Y
R
X
DATA BIT
X
V
OUT
C
L
V
X
1nF
V
ΔV
OUT
OUT
GND
Q
= C × ΔV
L OUT
INJ
Figure 29. Charge Injection
V
V
V
V
V
V
SS
DD
DD
SS
DD
DD
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
SS
SS
X
X
50Ω
50Ω
50Ω
V
X
V
X
Y
Y
V
V
OUT
OUT
V
V
R
R
L
L
50Ω
50Ω
GND
GND
V
V
WITH SWITCH
OUT
OUT
OFF ISOLATION = 20 log
INSERTION LOSS = 20 log
V
V
WITHOUT SWITCH
OUT
S
Figure 30. Off Isolation
Figure 31. Bandwidth
Rev. 0 | Page 15 of 28
ADG2188
V
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
DD
SS
V
OUT
Y1
X2
X1
Y2
R
50Ω
R
50Ω
L
R
50Ω
50Ω
DATA
BIT
V
X
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 32. Channel-to-Channel Crosstalk
Rev. 0 | Page 16 of 28
ADG2188
TERMINOLOGY
On Resistance (RON
)
Total Harmonic Distortion + Noise (THD + N)
The series on-channel resistance measured between the
X input/output and the Y input/output.
The ratio of the harmonic amplitudes plus noise of a signal to
the fundamental.
On Resistance Match (ΔRON
)
−3 dB Bandwidth
The channel-to-channel matching of on resistance when
channels are operated under identical conditions.
The frequency at which the output is attenuated by 3 dB.
Off Isolation
On Resistance Flatness (RFLAT(ON)
)
The measure of unwanted signal coupling through an off switch.
The variation of on resistance over the specified range produced
by the specified analog input voltage change with a constant
load current.
Crosstalk
The measure of unwanted signal that is coupled through from
one channel to another as a result of parasitic capacitance.
Channel Off Leakage (IOFF
The sum of leakage currents into or out of an off channel input.
)
Differential Gain
The measure of how much color saturation shift occurs when
the luminance level changes. Both attenuation and amplification
can occur; therefore, the largest amplitude change between any
two levels is specified and is expressed as a percentage of the
largest chrominance amplitude.
Channel On Leakage (ION
The current loss/gain through an on-channel resistance,
creating a voltage offset across the device.
)
Input Leakage Current (IIN)
The current flowing into a digital input when a specified low
level or high level voltage is applied to that input.
Differential Phase
The measure of how much hue shift occurs when the luminance
level changes. It can be a negative or positive value and is
expressed in degrees of subcarrier phase.
Input Off Capacitance (COFF
)
The capacitance between an analog input and ground when the
switch channel is off.
Charge Injection
The measure of the glitch impulse transferred from the digital
input to the analog output during on/off switching.
Input/Output On Capacitance (CON
The capacitance between the inputs or outputs and ground
when the switch channel is on.
)
Input High Voltage (VINH
The minimum input voltage for Logic 1.
)
Digital Input Capacitance (CIN)
The capacitance between a digital input and ground.
Input Low Voltage (VINL
)
The maximum input voltage for Logic 0.
Output On Switching Time (tON
)
The time required for the switch channel to close. The time is
measured from 50% of the logic input change to the time the
output reaches 10% of the final value.
Output Low Voltage (VOL
The minimum input voltage for Logic 1.
)
Input Low Voltage (VINL
)
Output Off Switching Time (tOFF
)
The maximum output voltage for Logic 0.
The time required for the switch to open. This time is measured
from 50% of the logic input change to the time the output
reaches 90% of the switch off condition.
IDD
Positive supply current.
ISS
Negative supply current.
Rev. 0 | Page 17 of 28
ADG2188
THEORY OF OPERATION
The ADG2188 is an analog cross point switch with an array size
of 8 × 8. The eight rows are referred to as the X input/output
lines, and the eight columns are referred to as the Y input/output
lines. The device is fully flexible in that it connects any X line or
number of X lines with any Y line when turned on. Similarly, it
connects any X line with any number of Y lines when turned on.
LOAD SWITCH (LDSW)
LDSW is an active high command that allows a number of
switches to be simultaneously updated. This is useful in
applications where it is important to have synchronous
transmission of signals. There are two LDSW modes: the
transparent mode and the latched mode.
Control of the ADG2188 is carried out via an I2C interface.
The device can be operated from single supplies of up to 13.2 V
or from dual 5 V supplies. The ADG2188 has many attractive
features, such as the ability to reset all the switches, the ability to
update many switches at the same time, and the option of reading
back the status of any switch. All of these features are described
in more detail here in the Theory of Operation section.
Transparent Mode
In this mode, the switch position changes after the new word is
written into the input shift register. LDSW is set to 1.
Latched Mode
In this mode, the switch positions are not updated at the same
time that the input registers are written to. This is achieved by
setting LDSW to 0 for each word (apart from the last word)
written to the device. Then, setting LDSW to 1 for the last word
allows all of the switches in that sequence to be simultaneously
updated.
RESET/POWER-ON RESET
The ADG2188 offers the ability to reset all of the 64 switches
RESET
to the off state. This is done through the
pin. When the
RESET
pin is low, all switches are open (off), and appropriate
registers are cleared. Note that the ADG2188 also has a power-
on reset block. This ensures that all switches are in the off
condition at power-up of the device. In addition, all internal
registers are filled with 0s and remain so until a valid write to
the ADG2188 takes place.
READBACK
Readback of the switch array conditions is also offered when in
standard mode and fast mode. Readback enables the user to
check the status of the switches of the ADG2188. This is very
useful when debugging a system.
Rev. 0 | Page 18 of 28
ADG2188
SERIAL INTERFACE
The ADG2188 is controlled via an I2C-compatible serial bus.
The parts are connected to this bus as a slave device (no clock
is generated by the switch).
2. The peripheral whose address corresponds to the trans-
mitted address responds by pulling the SDA line low
during the ninth clock pulse, known as the acknowledge
bit. At this stage, all other devices on the bus remain idle
while the selected device waits for data to be written to
HIGH SPEED I2C INTERFACE
In addition to standard and full speed I2C, the ADG2188 also
supports the high speed (3.4 MHz) I2C interface. Only the –HS
models provide this added performance. See the Ordering
Guide for details.
W
or read from its serial register. If the R/ bit is 1 (high), the
W
master reads from the slave device. If the R/ bit is 0
(low), the master writes to the slave device.
3. Data is transmitted over the serial bus in sequences of
nine clock pulses: eight data bits followed by an acknowl-
edge bit from the receiver of the data. Transitions on the
SDA line must occur during the low period of the clock
signal, SCL, and remain stable during the high period of
SCL, because a low-to-high transition when the clock is
high can be interpreted as a stop signal.
SERIAL BUS ADDRESS
The ADG2188 has a 7-bit slave address. The four MSBs are
hard coded to 1110, and the three LSBs are determined by the
state of Pin A0, Pin A1, and Pin A2. By offering the facility to
hardware configure Pin A0, Pin A1, and Pin A2, up to eight
of these devices can be connected to a single serial bus.
4. When all data bits have been read or written, a stop
condition is established by the master. A stop condition
is defined as a low-to-high transition on the SDA line
while SCL is high. In write mode, the master pulls the
SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line
low before the 10th clock pulse and then high during the
10th clock pulse to establish a stop condition.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as when a high-to-low transition on
the SDA line occurs while SCL is high. This indicates
that an address/data stream follows. All slave peripherals
connected to the serial bus respond to the start condition
and shift in the next eight bits, consisting of a 7-bit
W
address (MSB first) plus an R/ bit that determines the
direction of the data transfer, that is, whether data is
written to or read from the slave device.
Refer to Figure 33 and Figure 34 for a graphical explanation
of the serial data transfer protocol.
Rev. 0 | Page 19 of 28
ADG2188
WRITING TO THE ADG2188
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial
clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6.
DB16 (LSB)
A0 R/W
DB8 (LSB)
DB0 (LSB)
X LDSW
DB23 (MSB)
DB15 (MSB)
DB7 (MSB)
1
1
1
0
A2
A1
DATA
X
AX3 AX2 AX1 AX0 AY2 AY1 AY0
X
X
X
X
X
DEVICE ADDRESS
DATA BITS
DATA BITS
Figure 33. Data-Words
Table 6. Input Shift Register Bit Function Descriptions
Bit
Mnemonic
Description
DB23 to DB17
1110xxx
The MSBs of the ADG2188 are set to 1110. The LSBs of the address byte are set by the
state of the three address pins, Pin A0, Pin A1, and Pin A2.
DB16
DB15
R/W
Controls whether the ADG2188 slave device is read from or written to.
If R/W = 1, the ADG2188 is being read from.
If R/W = 0, the ADG2188 is being written to.
Data
Controls whether the switch is to be open (off) or closed (on).
If Data = 0, the switch is open/off.
If Data = 1, the switch is closed/on.
DB14 to DB11
DB10 to DB8
DB7 to DB1
DB0
AX3 to AX0
AY2 to AY0
X
Controls I/Os X0 to X7. See Table 7 for the decode truth table.
Controls I/Os Y0 to Y7. See Table 7 for the decode truth table.
Don’t care.
This bit is useful when a number of switches need to be updated simultaneously.
If LDSW = 1, the switch position changes after the new word is read in.
If LDSW = 0, the input data is latched, but the switch position is not changed.
LDSW
As shown in Table 6, Bit DB11 to Bit DB14 control the X input/output lines, while Bit DB8 to Bit DB10 control the Y input/output lines.
Table 7 shows the truth table for these bits. Note that the full coding sequence is written out for Channel Y0, and Channel Y1 to Channel Y7
RESET
follow a similar pattern. Note also that the
pin must be high when writing to the device.
Table 7. Address Decode Truth Table
DB15
DATA
DB14
AX3
DB13
AX2
DB12
AX1
DB11
AX0
DB10
AY2
DB9
AY1
DB8
AY0
Switch Configuration
X0 to Y0 (on)
X0 to Y0 (off)
X1 to Y0 (on)
X1 to Y0 (off)
X2 to Y0 (on)
X2 to Y0 (off)
X3 to Y0 (on)
X3 to Y0 (off)
X4 to Y0 (on)
X4 to Y0 (off)
X5 to Y0 (on)
X5 to Y0 (off)
Reserved
1
0
1
0
1
0
1
0
1
0
1
0
X
X
1
0
1
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
X6 to Y0 (on)
X6 to Y0 (off)
X7 to Y0 (on)
X7 to Y0 (off)
Reserved
1
1
0
1
Reserved
Rev. 0 | Page 20 of 28
ADG2188
DB15
DATA
DB14
AX3
DB13
AX2
DB12
AX1
DB11
AX0
DB10
AY2
DB9
AY1
DB8
AY0
Switch Configuration
Reserved
Reserved
Reserved
Reserved
X
X
X
X
1
0
..
1
1
1
1
0
0
..
1
1
1
1
0
0
..
0
0
1
1
0
0
..
0
1
0
1
0
0
..
0
0
0
0
0
0
..
0
0
0
0
0
0
..
0
0
0
0
1
1
..
X0 to Y1 (on)
X0 to Y1 (off)
1
1
0
..
1
0
0
..
0
0
0
..
0
0
0
..
1
0
0
..
0
0
0
..
0
1
1
..
1
0
0
..
X7 to Y1 (on)
X0 to Y2 (on)
X0 to Y2 (off)
1
1
0
..
1
0
0
..
0
0
0
..
0
0
0
..
1
0
0
..
0
0
0
..
1
1
1
..
0
1
1
..
X7 to Y2 (on)
X0 to Y3 (on)
X0 to Y3 (off)
1
1
0
..
1
0
0
..
0
0
0
..
0
0
0
..
1
0
0
..
0
1
1
..
1
0
0
..
1
0
0
..
X7 to Y3 (on)
X0 to Y4 (on)
X0 to Y4 (off)
1
1
0
..
1
0
0
..
0
0
0
..
0
0
0
..
1
0
0
..
1
1
1
..
0
0
0
..
0
1
1
..
X7 to Y4 (on)
X0 to Y5 (on)
X0 to Y5 (off)
1
1
0
..
1
0
0
..
0
0
0
..
0
0
0
..
1
0
0
..
1
1
1
..
0
1
1
..
1
0
0
..
X7 to Y5 (on)
X0 to Y6 (on)
X0 to Y6 (off)
1
1
0
..
1
0
0
..
0
0
0
..
0
0
0
..
1
0
0
..
1
1
1
..
1
1
1
..
0
1
1
..
X7 to Y6 (on)
X0 to Y7 (on)
X0 to Y7 (off)
1
1
0
0
1
1
1
1
X7 to Y7 (on)
Rev. 0 | Page 21 of 28
ADG2188
b. Enter the readback address for the X line of interest,
the addresses of which are shown in Table 8. Note that
the ADG2188 is expecting a 2-byte write; therefore, be
sure to also enter another byte of don’t cares (see
Figure 35).
WRITE OPERATION
When writing to the ADG2188, the user must begin with an
W
address byte and R/ bit, after which the switch acknowledges
that it is prepared to receive data by pulling SDA low. This
address byte is followed by the two 8-bit words. The write
operations for the switch array are shown in Figure 34. Note
that it is only the condition of the switch corresponding to the
bits in the data bytes that changes state. All other switches retain
their previous condition.
c. The ADG2188 then places the status of those eight
switches in a register than can be read back.
2. The second step involves reading back from the register
that holds the status of the eight switches associated with
the X line of choice.
READ OPERATION
Readback on the ADG2188 is designed to work as a tool for
debug and can be used to output the status of any of the
64 switches of the device. The readback function is a two-step
sequence that works as follows:
a. As before, enter the I2C address of the ADG2188. This
W
time, set the R/ to 1 to indicate a read back from the
device.
d. As with a write to the device, the ADG2188 outputs a
2-byte sequence during readback. Therefore, the first
eight bits of data out that are read back are all 0s. The
next eight bits of data that come back are the status of
the eight Y lines attached to that particular X line. If
the bit is a 1, then the switch is closed (on); similarly, if
the bit is a 0, the switch is open (off).
1. Select the relevant X line to be read back from. Note that
there are eight switches connecting that X line to the eight
Y lines. The next step involves writing to the ADG2188 to
tell the part to reveal the status of those eight switches.
a. Enter the I2C address of the ADG2188, and set the
W
R/ to 0 to indicate a write to the device.
The entire read sequence is shown in Figure 35.
SCL
SDA
A2
A1
DATA AX3 AX2
AX1
AX0
AY2
AY1
AY0
A0
R/W
x
x
x
x
x
x
x
LDSW
STOP
COND
BY
ACK
BY
SWITCH
START
COND
BY
ACK
BY
SWITCH
ACK
BY
SWITCH
ADDRESS BYTE
DATA BYTE
DATA BYTE
MASTER
MASTER
Figure 34. Write Operation
Table 8. Readback Addresses for Each X Line
X Line
RB7
RB6
RB5
1
1
1
1
1
1
1
1
RB4
1
1
1
1
1
1
1
1
RB3
RB2
1
1
1
1
1
1
1
1
RB1
0
0
0
0
0
0
0
0
RB0
X0
X1
X2
X3
X4
X5
X6
X7
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Rev. 0 | Page 22 of 28
ADG2188
SCL
SDA
A2
A1
RB7
ACK
BY
SWITCH
RB6 RB5
RB4 RB3
RB2
RB1 RB0
A0
R/W
x
x
x
x
x
x
x
x
STOP
COND
BY
NO ACK
BY
SWITCH
START
COND
BY
ACK
BY
SWITCH
ADDRESS BYTE
DATA BYTE
DATA BYTE
MASTER
MASTER
SCL
SDA
A2
A1
A0
R/W
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
STOP
COND
BY
NO ACK
BY
MASTER
START
COND
BY
ACK
BY
SWITCH
ACK
BY
MASTER
ADDRESS BYTE
DUMMY READBACK BYTE
READBACK BYTE
MASTER
MASTER
Figure 35. Read Operation
Rev. 0 | Page 23 of 28
ADG2188
EVALUATION BOARD
The ADG2188 evaluation board allows designers to evaluate the
high performance 8 × 8 switch array of the ADG2188 with a
minimum of effort.
USING THE ADG2188 EVALUATION BOARD
The ADG2188 evaluation kit is a test system designed to
simplify the evaluation of the ADG2188. Each input/output
of the part comes with a socket specifically chosen for easy
audio/video evaluation. An application note is also available
with the evaluation board that gives full information on
operating the evaluation board.
The evaluation kit includes a populated, tested ADG2188
printed circuit board. The evaluation board interfaces to the
USB port of a PC, or it can be used as a standalone evaluation
board. Software is available with the evaluation board that
allows the user to easily program the ADG2188 through the USB
port. Schematics of the evaluation board are shown in Figure 36
and Figure 37. The software runs on any PC that has Microsoft®
Windows® 2000 or Windows XP installed.
POWER SUPPLY
The ADG2188 evaluation board can be operated with both
single and dual supplies. VDD and VSS are supplied externally by
the user. The VL supply can be applied externally, or the USB
port can be used to power the digital circuitry.
Rev. 0 | Page 24 of 28
ADG2188
SCHEMATICS
Figure 36. EVAL-ADG2188EB Schematic, USB Controller Section
Rev. 0 | Page 25 of 28
ADG2188
Figure 37. EVAL-ADG2188EB Schematic, Chip Section
Rev. 0 | Page 26 of 28
ADG2188
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm x 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model
I2C Speed
Package Description
ADG2188BCPZ-R21
ADG2188BCPZ-REEL71
−40°C to +85°C
−40°C to +85°C
100 kHz, 400 kHz
100 kHz, 400 kHz
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
ADG2188BCPZ-HS-RL71 −40°C to +85°C
100 kHz, 400 kHz, 3.4 MHz 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
−40°C to +125°C 100 kHz, 400 kHz 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
−40°C to +125°C 100 kHz, 400 kHz
ADG2188YCPZ-R21
ADG2188YCPZ-REEL71
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
ADG2188YCPZ-HS-RL71 −40°C to +125°C 100 kHz, 400 kHz, 3.4 MHz 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
EVAL-ADG2188EB
8 x 8 Evaluation Board
1 Z = Pb-free part.
Rev. 0 | Page 27 of 28
ADG2188
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05897-0-4/06(0)
Rev. 0 | Page 28 of 28
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