ADG3304SRU-EP-RL7 [ADI]
Low Voltage 1.15 V to 5.5 V, 4 Channel, Bidirectional, Logic Level Translator;
| 型号： | ADG3304SRU-EP-RL7 |
| 厂家： | 
ADI |
| 描述： | Low Voltage 1.15 V to 5.5 V, 4 Channel, Bidirectional, Logic Level Translator 光电二极管 接口集成电路 |
| 文件： | 总8页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage, 1.15 V to 5.5 V, 4-Channel,
Bidirectional Logic Level Translator
ADG3304-EP
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
V
CCY
Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 5 μA
No direction pin
Supports defense and aerospace applications
(AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly and test site
CCA
A1
A2
A3
A4
EN
Y1
Y2
Y3
Y4
One fabrication site
Enhanced product change notification
Qualification data available on request
GND
Figure 1.
APPLICATIONS
SPI®, MICROWIRE™ level translation
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communications devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
GENERAL DESCRIPTIONS
logic levels applied to the Y side of the device appear as VCCA
compatible logic levels on the A side.
-
The ADG3304-EP is a bidirectional logic level translator that
contains four bidirectional channels. It can be used in
multivoltage digital system applications, such as data transfer,
between a low voltage digital signal processing controller and a
higher voltage device using SPI and MICROWIRE interfaces.
The internal architecture allows the device to perform
bidirectional logic level translation without an additional signal
to set the direction in which the translation takes place.
The enable pin (EN) provides three-state operation on both the
A side and the Y side pins. When the EN pin is pulled low, the
terminals on both sides of the device are in the high impedance
state. The EN pin is referred to the VCCA supply voltage and
driven high for normal operation.
The ADG3304-EP is available in compact 14-lead TSSOP
package.
The voltage applied to VCCA sets the logic levels on the A side of
the device, while VCCY sets the levels on the Y side. For proper
operation, VCCA must always be less than VCCY. The VCCA-com-
patible logic signals applied to the A side of the device appear as
Full details about this enhanced product are available in the
ADG3304 data sheet, which should be consulted in conjunction
with this data sheet.
VCCY-compatible levels on the Y side. Similarly, VCCY-compatible
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2010 Analog Devices, Inc. All rights reserved.
ADG3304-EP
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Descriptions ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions............................7
Outline Dimensions..........................................................................8
Ordering Guide .............................................................................8
REVISION HISTORY
10/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
ADG3304-EP
SPECIFICATIONS
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V, TA = −55°C to +125°C unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage2
VIHA
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA = 2.5 V 0.2 V
VCCA = 3.3 V 0.3 V
VCCA = 5 V 0.5 V
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA = 2.5 V 0.2 V
VCCA = 3.3 V 0.3 V
VCCA = 5 V 0.5 V
VCCA × 0.88
VCCA × 0.72
1.7
2.2
VCCA × 0.7
V
V
V
V
V
V
Input Low Voltage2
VILA
VCCA × 0.35
VCCA × 0.35
0.7
0.8
VCCA × 0.3
V
V
V
V
Output High Voltage
Output Low Voltage
Capacitance2
VOHA
VOLA
CA
VY = VCCY, IOH = 20 μA
VY = 0 V, IOL = 20 μA
f = 1 MHz, EN = 0
VCCA − 0.4
V
V
pF
μA
0.4
1
9
Leakage Current
Y Side
Input High Voltage2
ILA, Hi-Z
VA = 0 V/VCCA, EN = 0
VIHY
VCCY = 1.8 V 0.15 V
VCCY = 2.5 V 0.2 V
VCCY = 3.3 V 0.3 V
VCCY = 5 V 0.5 V
VCCY = 1.8 V 0.15 V
VCCY = 2.5 V 0.2 V
VCCY = 3.3 V 0.3 V
VCCY = 5 V 0.5 V
VCCY × 0.67
V
1.7
2
VCCY × 0.7
V
V
V
V
Input Low Voltage2
VILY
VCCY × 0.35
0.7
0.8
V
V
V
VCCY × 0.25
Output High Voltage
Output Low Voltage
Capacitance2
VOHY
VOLY
CY
VA = VCCA, IOH = 20 μA
VA = 0 V, IOL = 20 μA
f = 1 MHz, EN = 0
VY = 0 V/VCCY, EN = 0
VCCY − 0.4
V
V
pF
μA
0.4
1
6
Leakage Current
Enable (EN)
Input High Voltage2
ILY, Hi-Z
VIHEN
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA = 2.5 V 0.2 V
VCCA = 3.3 V 0.3 V
VCCA = 5 V 0.5 V
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA = 2.5 V 0.2 V
VCCA = 3.3 V 0.3 V
VCCA = 5 V 0.5 V
VCCA × 0.88
VCCA × 0.72
1.7
2.2
VCCA × 0.7
V
V
V
V
V
Input Low Voltage2
VILEN
VCCA × 0.35
VCCA × 0.35
0.7
0.8
VCCA × 0.3
1
V
V
V
V
V
μA
pF
μs
Leakage Current
Capacitance2
Enable Time2
ILEN
CEN
tEN
VEN = 0 V/VCCA, VA = 0 V
3
1
RS = RT = 50 Ω
1.8
VA = 0 V/VCCA (A→Y)
VY = 0 V/VCCY (Y→A)
Rev. 0 | Page 3 of 8
ADG3304-EP
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
SWITCHING CHARACTERISTICS2
3.3 V 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V 0.5 V
A→Y Level Translation
Propagation Delay
RS = RT = 50 Ω, CL = 50 pF
6
15
5
ns
tP, A→Y
Rise Time
2
ns
tR, A→Y
Fall Time
2
5
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
2
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
3
ns
RS = RT = 50 Ω, CL = 15 pF
Y→A Level Translation
Propagation Delay
Rise Time
4
10
5
ns
tP, Y→A
1
ns
tR, Y→A
Fall Time
3
10
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
1.8 V 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
50
2
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
ns
RS = RT = 50 Ω, CL = 50 pF
Propagation Delay
Rise Time
8
15
8
ns
tP, A→Y
2
ns
tR, A→Y
Fall Time
2
8
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y→A Translation
50
2
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
4
ns
RS = RT = 50 Ω, CL = 15 pF
Propagation Delay
Rise Time
5
12
5
ns
tP, Y→A
2
ns
tR, Y→A
Fall Time
2
5
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
50
2
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
3
ns
RS = RT = 50 Ω, CL = 50 pF
Propagation Delay
Rise Time
9
27
8
ns
tP, A→Y
3
ns
tR, A→Y
Fall Time
2
8
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y→A Translation
40
2
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
10
ns
RS = RT = 50 Ω, CL = 15 pF
Propagation Delay
Rise Time
5
13
6
ns
tP, Y→A
2
ns
tR, Y→A
Fall Time
2
6
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
40
2
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
4
ns
Rev. 0 | Page 4 of 8
ADG3304-EP
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V 0.3 V
A→Y Translation
RS = RT = 50 Ω, CL = 50 pF
Propagation Delay
Rise Time
12
7
35
18
8
ns
tP, A→Y
ns
tR, A→Y
Fall Time
3
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y→A Translation
25
2
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
15
ns
RS = RT = 50 Ω, CL = 15 pF
Propagation Delay
Rise Time
14
5
40
24
10
ns
tP, Y→A
ns
tR, Y→A
Fall Time
2.5
25
3
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
2.5 V 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
23.5
ns
RS = RT = 50 Ω, CL = 50 pF
Propagation Delay
Rise Time
7
15
6
ns
tP, A→Y
2.5
2
ns
tR, A→Y
Fall Time
8
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y→A Translation
60
1.5
4
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
ns
RS = RT = 50 Ω, CL = 15 pF
Propagation Delay
5
12
6
ns
tP, Y→A
Rise Time
1
ns
tR, Y→A
Fall Time
3
8
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
60
2
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
3
ns
POWER REQUIREMENTS
Power Supply Voltages
VCCA
VCCY
ICCA
VCCA ≤ VCCY
1.15
1.65
5.5
5.5
5
V
V
μA
Quiescent Power Supply Current
VA = 0 V/VCCA, VY = 0 V/VCCY
VCCA = VCCY = 5.5 V, EN = 1
VA = 0 V/VCCA, VY = 0 V/VCCY
VCCA = VCCY = 5.5 V, EN = 1
,
,
0.17
0.27
ICCY
5
μA
Three-State Mode Power Supply Current
IHi-Z, A
IHi-Z, Y
VCCA = VCCY = 5.5 V, EN = 0
VCCA = VCCY = 5.5 V, EN = 0
0.1
0.1
5
5
μA
μA
1 TA for typical specifications is +25°C.
2 Guaranteed by design, not production tested.
Rev. 0 | Page 5 of 8
ADG3304-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VCCA to GND
VCCY to GND
−0.3 V to +7 V
VCCA to +7 V
Digital Inputs (A)
Digital Inputs (Y)
EN to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (4-Layer Board)
14-Lead TSSOP
−0.3 V to (VCCA + 0.3 V)
−0.3 V to (VCCY + 0.3 V)
−0.3 V to +7 V
−55°C to +125°C
−65°C to +150°C
150°C
Only one absolute maximum rating can be applied at any one
time.
ESD CAUTION
112.6°C/W
Lead Temperature, Soldering
Vapor phase(60 sec)
Infrared (15 sec)
215°C
220°C
Rev. 0 | Page 6 of 8
ADG3304-EP
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
V
14
13
12
11
V
CCA
CCY
A1
A2
Y1
Y2
Y3
ADG3304-EP
TOP VIEW
(Not to Scale)
A3
A4
10 Y4
9
8
NC
NC
EN
GND
NC = NO CONNECT
Figure 2. 14-Lead TSSOP
Pin Configuration
Table 3. 14-Lead TSSOP Pin Function Descriptions
Pin No.
Mnemonic
VCCA
A1
A2
A3
A4
NC
GND
EN
Description
1
2
3
4
5
6, 9
7
Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ VCCA ≤ VCCY).
Input/Output A1. Referenced to VCCA
Input/Output A2. Referenced to VCCA
Input/Output A3. Referenced to VCCA
Input/Output A4. Referenced to VCCA
No Connect.
.
.
.
.
Ground.
Active High Enable Input.
8
10
11
12
13
14
Y4
Y3
Y2
Y1
Input/Output Y4. Referenced to VCCY
Input/Output Y3. Referenced to VCCY
Input/Output Y2. Referenced to VCCY
Input/Output Y1. Referenced to VCCY
.
.
.
.
VCCY
Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCC ≤ 5.5 V).
Table 4. Truth Table
EN
Y I/O Pins
A I/O Pins
Hi-Z1
Normal operation2
0
1
Hi-Z1
Normal operation2
1 High impedance state.
2 In normal operation, the ADG3304-EP performs level translation.
Rev. 0 | Page 7 of 8
ADG3304-EP
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 3. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG3304SRU-EP-RL7
−55°C to +125°C
14-Lead Thin Shrink Small Outline Package [TSSOP]
RU-14
©
2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08845-0-10/10(0)
Rev. 0 | Page 8 of 8
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