ADG3308_15 [ADI]
Low Voltage, 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translators;
| 型号： | ADG3308_15 |
| 厂家： | 
ADI |
| 描述： | Low Voltage, 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translators |
| 文件： | 总20页 (文件大小：501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage, 1.15 V to 5.5 V, 8-Channel
Bidirectional Logic Level Translators
Data Sheet
ADG3308/ADG3308-1
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
CCY
CCA
Bidirectional logic level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 1 µA
No direction pin
ADG3308/ADG3308-1
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
APPLICATIONS
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
A8
EN
Portable POS systems
Low cost serial interfaces
GND
Figure 1.
GENERAL DESCRIPTION
The ADG3308/ADG3308-1 are bidirectional level translators
containing eight bidirectional channels. They can be used in
multivoltage digital system applications, such as a data transfer
between a low voltage DSP controller and a higher voltage device.
The internal architecture allows the device to perform
bidirectional level translation without an additional signal to set
the direction in which the translation takes place.
The ADG3308 is available in a compact 20-lead TSSOP and
a 20-lead LFCSP. The ADG3308-1 is available in a 20-ball
WLCSP. The EN pin is referred to the VCCY supply voltage
for the ADG3308 and to the VCCA supply voltage for the
ADG3308-1.
The ADG3308/ADG3308-1 are guaranteed to operate over the
1.15 V to 5.5 V supply voltage range and the extended −40°C to
+85°C temperature range.
The voltage applied to VCCA sets the logic levels on the A side
of the device, and VCCY sets the levels on the Y side. For proper
operation, VCCA must always be less than VCCY. The VCCA
compatible logic signals applied to the A side of the device
appear as VCCY compatible levels on the Y side. Similarly, VCCY
compatible logic levels applied to the Y side of the device appear
as VCCA compatible logic levels on the A side.
PRODUCT HIGHLIGHTS
1. Bidirectional logic level translation.
2. Fully guaranteed over the 1.15 V to 5.5 V supply range.
3. No direction pin.
4. Packages: 20-lead TSSOP and 20-lead LFCSP (ADG3308)
and 20-ball WLCSP (ADG3308-1).
The enable pin (EN) provides three-state operation on both the
A side and the Y side pins. When the EN pin is pulled low, the
terminals on both sides of the device are in the high impedance
state. For normal operation, EN should be driven high.
Rev. D
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ADG3308/ADG3308-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 16
Level Translator Architecture ................................................... 16
Input Driving Requirements..................................................... 16
Output Load Requirements ...................................................... 16
Enable Operation ....................................................................... 16
Power Supplies............................................................................ 16
Data Rate ..................................................................................... 17
Applications..................................................................................... 18
Layout Guidelines....................................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 12
Terminology .................................................................................... 15
REVISION HISTORY
10/13—Rev. C to Rev. D
Removed ADG3308-2 (Throughout) ............................................ 1
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
9/07—Rev. B to Rev. C
Updated Outline Dimensions....................................................... 19
7/07—Rev. A to Rev. B
Added Backside-Coated WLCSP Package ......................Universal
Changes to Input Driving Requirements Section ...................... 16
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
7/06—Rev. 0 to Rev. A
Added WLCSP Package…………………………..……Universal
Added Figure 4………………………………………………......7
Updated Outline Dimensions……………………………….…19
Changes to Ordering Guide………………………………....…19
1/05—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
ADG3308/ADG3308-1
SPECIFICATIONS
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. 1
Table 1.
Parameter
Symbol Conditions
Min
Typ 2 Max
Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage3
VIHA
VIHA
VILA
VOHA
VOLA
CA
VCCA = 1.15 V
VCCA = 1.2 V to 5.5 V
VCCA − 0.3
0.65 × VCCA
V
V
V
V
V
pF
µA
Input Low Voltage3
Output High Voltage
Output Low Voltage
Capacitance3
Leakage Current
Y Side
0.35 × VCCA
VY = VCCY, IOH = 20 µA, see Figure 29
VY = 0 V, IOL = 20 µA, see Figure 29
f = 1 MHz, EN = 0, see Figure 34
VCCA − 0.4
0.4
1
10
ILA, HIGH-Z VA = 0 V or VCCA, EN = 0, see Figure 31
Input High Voltage3
Input Low Voltage3
Output High Voltage
Output Low Voltage
Capacitance3
Leakage Current
Enable (EN)
Input High Voltage3
VIHY
VILY
VOHY
VOLY
CY
ILY, HIGH-Z
0.65 × VCCY
VCCY − 0.4
V
V
V
V
pF
µA
0.35 × VCCY
VA = VCCA, IOH = 20 µA, see Figure 30
VA = 0 V, IOL = 20 µA, see Figure 30
f = 1 MHz, EN = 0, see Figure 35
VY = 0 V or VCCY, EN = 0, see Figure 32
0.4
1
6.8
VIHEN
ADG3308 (TSSOP, LFCSP)
ADG3308-1 (WLCSP)
0.65 × VCCY
VCCA − 0.3
0.65 × VCCA
V
V
V
VCCA = 1.15 V
VCCA = 1.2 V to 5.5 V
Input Low Voltage3
ADG3308 (TSSOP, LFCSP)
ADG3308-1 (WLCSP)
Leakage Current
Capacitance3
VILEN
0.35 × VCCY
0.35 × VCCA
1
V
V
µA
pF
µs
ILEN
CEN
tEN
VEN = 0 V or VCCY, VA = 0 V, see Figure 33
RS = RT = 50 Ω, VA = 0 V or
4.5
1
Enable Time3
1.8
V
CCA (A→Y), VY = 0 V or VCCY (Y→A),
see Figure 36
SWITCHING CHARACTERISTICS3
3.3 V 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V 0.5 V
A→Y Level Translation
Propagation Delay
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
6
2
2
10
ns
tP, A →Y
Rise Time
3.5
3.5
ns
tR, A→Y
Fall Time
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
4
3
ns
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
Y→A Level Translation
Propagation Delay
Rise Time
4
1
3
7
3
7
ns
tP, Y →A
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
3.5
2
ns
Rev. D | Page 3 of 20
ADG3308/ADG3308-1
Data Sheet
Parameter
Symbol Conditions
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
Min
Typ 2 Max
Unit
1.8 V 0.15 V ≤VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Level Translation
Propagation Delay
Rise Time
8
2
2
11
5
ns
tP, A →Y
ns
tR, A→Y
Fall Time
5
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
4
4
ns
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
Y→A Level Translation
Propagation Delay
Rise Time
5
2
2
8
ns
tP, Y →A
3.5
3.5
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
3
3
ns
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Level Translation
Propagation Delay
Rise Time
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
9
3
2
18
5
ns
tP, A →Y
ns
tR, A→Y
Fall Time
5
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
40
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
5
10
ns
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
Y→A Level Translation
Propagation Delay
Rise Time
5
2
2
9
4
4
ns
tP, Y →A
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
40
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
4
4
ns
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V 0.3 V
A→Y Level Translation
Propagation Delay
Rise Time
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
12
7
25
12
5
ns
tP, A →Y
ns
tR, A→Y
Fall Time
3
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
25
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
5
15
ns
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
Y→A Level Translation
Propagation Delay
Rise Time
14
5
35
16
6.5
ns
tP, Y →A
ns
tR, Y→A
Fall Time
2.5
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
25
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
3
6.5
23.5
ns
Rev. D | Page 4 of 20
Data Sheet
ADG3308/ADG3308-1
Parameter
Symbol Conditions
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
Min
Typ 2 Max
Unit
2.5 V 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Level Translation
Propagation Delay
Rise Time
7
10
4
ns
tP, A →Y
2.5
2
ns
tR, A→Y
Fall Time
5
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
60
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
1.5
2
4
ns
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
Y→A Level Translation
Propagation Delay
Rise Time
5
1
3
8
4
5
ns
tP, Y →A
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
60
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
3
3
ns
POWER REQUIREMENTS
Power Supply Voltages
VCCA
VCCY
ICCA
VCCA ≤ VCCY
1.15
1.65
5.5
5.5
1
V
V
µA
Quiescent Power Supply Current
VA = 0 V or VCCA, VY = 0 V or VCCY
CCA = VCCY = 5.5 V, EN = VCCY
VA = 0 V or VCCA, VY = 0 V or VCCY
CCA = VCCY = 5.5 V, EN = VCCY
,
,
0.17
0.27
V
ICCY
1
µA
V
Three-State Mode Power Supply Current
IHIGH-ZA
IHIGH-ZY
VCCA = VCCY = 5.5 V, EN = 0
VCCA = VCCY = 5.5 V, EN = 0
0.1
0.1
1
1
µA
µA
1 Temperature range is −40°C to +85°C (B Version) for the TSSOP, the LFCSP, the WLCSP, and the backside-coated WLCSP.
2 All typical values are at TA = 25°C, unless otherwise noted.
3 Guaranteed by design; not subject to production test.
Rev. D | Page 5 of 20
ADG3308/ADG3308-1
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
VCCA to GND
−0.3 V to +7 V
VCCY to GND
VCCA to +7 V
Digital Inputs (A)
Digital Inputs (Y)
EN to GND
−0.3 V to (VCCA + 0.3 V)
−0.3 V to (VCCY + 0.3 V)
−0.3 V to +7 V
Only one absolute maximum rating may be applied at any
one time.
Operating Temperature Range
Extended Industrial Range (B Version) −40°C to +85°C
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
20-Lead TSSOP
−65°C to +150°C
150°C
ESD CAUTION
78°C/W
20-Lead LFCSP
20-Ball WLCSP
30.4°C/W
100°C/W
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
300°C
260°C (+0°C/−5°C)
Rev. D | Page 6 of 20
Data Sheet
ADG3308/ADG3308-1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL a1
INDICATOR
1
2
3
4
a
b
c
d
e
V
Y1
A1
V
CCA
CCY
1
2
20
19
18
17
16
15
14
13
12
11
V
V
CCY
CCA
A1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
Y2
Y4
Y6
Y8
Y3
Y5
A3
A5
A7
EN
A2
A4
A6
A8
PIN 1
3
A2
A3
A4
A5
A6
A7
A8
EN
INDICATOR
1
2
3
4
5
15 Y3
14 Y4
13 Y5
12 Y6
11 Y7
A2
A3
A4
A5
A6
4
ADG3308
TOP VIEW
(Not to Scale)
ADG3308
TOP VIEW
(Not to Scale)
5
6
Y7
7
8
GND
9
THE EXPOSED PAD CAN BE TIED TO
GND OR IT CAN BE LEFT FLOATING.
10
ADG3308-1
TOP VIEW
DO NOT TIE IT TO V
OR V .
CCA
CCY
(Not to Scale)
(BALLS AT THE BOTTOM)
Figure 2. 20-Lead TSSOP
Figure 3. 20-Lead LFCSP
Figure 4. 20-Ball WLCSP
Table 3. Pin Function Descriptions
Pin/Ball No.
TSSOP
LFCSP
WLCSP
Mnemonic
Description
1
19
a4
VCCA
Power Supply. Power supply voltage input for the A1 I/O pin to the A8 I/O pin
(1.15 V ≤ VCCA < VCCY).
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
20
1
2
3
4
5
6
7
8
a3
b4
b3
c4
c3
d4
d3
e4
e3
e2
e1
d2
d1
c2
c1
b2
b1
a2
a1
A1
A2
A3
A4
A5
A6
A7
A8
EN
GND
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
VCCY
Input/Output A1. Referenced to VCCA
Input/Output A2. Referenced to VCCA
Input/Output A3. Referenced to VCCA
Input/Output A4. Referenced to VCCA
Input/Output A5. Referenced to VCCA
Input/Output A6. Referenced to VCCA
Input/Output A7. Referenced to VCCA
Input/Output A8. Referenced to VCCA
Active High Enable Input.
.
.
.
.
.
.
.
.
9
Ground.
10
11
12
13
14
15
16
17
18
Input/Output Y8. Referenced to VCCY
Input/Output Y7. Referenced to VCCY
Input/Output Y6. Referenced to VCCY
Input/Output Y5. Referenced to VCCY
Input/Output Y4. Referenced to VCCY
Input/Output Y3. Referenced to VCCY
Input/Output Y2. Referenced to VCCY
Input/Output Y1. Referenced to VCCY
.
.
.
.
.
.
.
.
Power Supply. Power supply voltage input for the Y1 I/O pin to the Y8 I/O pin
(1.65 V ≤ VCCY ≤ 5.5 V).
Rev. D | Page 7 of 20
ADG3308/ADG3308-1
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
C
1 CHANNEL
C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
= 50pF
= 15pF
L
L
V
= 3.3V, V
CCY
= 5V
CCA
V
= 3.3V, V = 5V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCA
CCY
V
= 1.8V, V
= 3.3V
CCA
CCY
V
= 1.2V, V
= 1.8V
40
V
= 1.2V, V
CCY
= 1.8V
CCA
CCY
CCA
25
DATA RATE (Mbps)
0
5
10
15
20
30
35
40
45
50
0
5
10
15
20
25
30
35
45
50
DATA RATE (Mbps)
Figure 5. ICCA vs. Data Rate (A→Y Level Translation)
Figure 8. ICCY vs. Data Rate (Y→A Level Translation)
10
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
C
1 CHANNEL
V
V
9
8
7
6
5
4
3
2
1
0
= 50pF
L
= 1.2V
= 1.8V
CCA
CCY
20Mbps
V
= 3.3V, V = 5V
CCY
CCA
10Mbps
5Mbps
V
= 1.8V, V = 3.3V
CCY
CCA
V
= 1.2V, V = 1.8V
CCY
CCA
1Mbps
53
0
5
10
15
20
25
30
35
40
45
50
13
23
33
43
63
73
DATA RATE (Mbps)
CAPACITIVE LOAD (pF)
Figure 9. ICCY vs. Capacitive Load at Pin Y
for A→Y (1.2 V→1.8 V) Level Translation
Figure 6. ICCY vs. Data Rate (A→Y Level Translation)
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
C
1 CHANNEL
V
V
= 15pF
L
= 1.2V
= 1.8V
CCA
CCY
V
= 3.3V, V = 5V
CCY
CCA
20Mbps
10Mbps
V
= 1.8V, V
= 3.3V
CCA
CCY
5Mbps
1Mbps
V
= 1.2V, V
CCY
= 1.8V
CCA
0
5
10
15
20
25
30
35
40
45
50
13
23
33
CAPACITIVE LOAD (pF)
43
53
DATA RATE (Mbps)
Figure 10. ICCA vs. Capacitive Load at Pin A
for Y→A (1.8 V→1.2 V) Level Translation
Figure 7. ICCA vs. Data Rate (Y→A Level Translation)
Rev. D | Page 8 of 20
Data Sheet
ADG3308/ADG3308-1
7
6
5
4
3
2
1
0
9
T
= 25°C
A
T = 25°C
A
1 CHANNEL
1 CHANNEL
V
V
50Mbps
8
7
6
5
4
3
2
1
0
= 1.8V
= 3.3V
CCA
CCY
V
V
= 3.3V
= 5V
CCA
CCY
50Mbps
30Mbps
20Mbps
30Mbps
20Mbps
10Mbps
5Mbps
10Mbps
5Mbps
63
13
23
33
43
53
73
13
23
33
43
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 11. ICCY vs. Capacitive Load at Pin Y
Figure 14. ICCA vs. Capacitive Load at Pin A
for A→Y (1.8 V→3.3 V) Level Translation
for Y→A (5 V→3.3 V) Level Translation
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
T
= 25°C
T = 25°C
A
1 CHANNEL
DATA RATE = 50kbps
A
1 CHANNEL
V
V
9
8
7
6
5
4
3
2
1
0
= 1.8V
= 3.3V
V
= 1.2V, V = 1.8V
CCY
CCA
CCY
CCA
50Mbps
V
= 1.8V, V
= 3.3V, V
= 3.3V
= 5V
30Mbps
CCA
CCY
20Mbps
10Mbps
V
CCA
CCY
5Mbps
13
23
33
43
53
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 12. ICCA vs. Capacitive Load at Pin A
for Y→A (3.3 V→1.8 V) Level Translation
Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation)
4.0
12
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
V
V
50Mbps
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 3.3V
= 5V
CCA
CCY
V
= 1.2V, V = 1.8V
CCY
10
8
CCA
30Mbps
20Mbps
V
= 1.8V, V = 3.3V
CCY
CCA
6
4
V
= 3.3V, V = 5V
CCY
CCA
10Mbps
5Mbps
2
0
13
13
23
33
43
53
63
73
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation)
Figure 13. ICCY vs. Capacitive Load at Pin Y
for A→Y (3.3 V→5 V) Level Translation
Rev. D | Page 9 of 20
ADG3308/ADG3308-1
Data Sheet
10
12
10
8
T
= 25°C
T
= 25°C
A
A
V
= 1.2V, V = 1.8V
CCY
CCA
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
DATA RATE = 50kbps
9
8
7
6
5
4
3
2
1
0
V
= 1.2V, V = 1.8V
CCY
CCA
6
V
= 1.8V, V = 3.3V
CCY
CCA
4
V
= 1.8V, V = 3.3V
CCY
CCA
2
V
= 3.3V, V
63
= 5V
73
CCA
CCY
V
= 3.3V, V
CCY
= 5V
53
CCA
0
13
23
33
43
53
13
18
23
28
33
38
43
48
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 20. Propagation Delay (tPHL) vs. Capacitive Load
Figure 17. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation)
at Pin Y (A→Y Level Translation)
9
8
7
6
5
4
3
2
1
0
4.0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
DATA RATE = 50kbps
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 1.2V, V = 1.8V
CCY
CCA
V
= 1.2V, V = 1.8V
CCY
CCA
V
= 1.8V, V
CCY
= 3.3V
= 5V
CCA
V
V
= 1.8V, V = 3.3V
CCY
= 3.3V, V
CCY
CCA
CCA
V
= 3.3V, V
43
= 5V
CCA
CCY
13
18
23
28
33
38
48
53
13
18
23
28
33
38
43
48
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 21. Propagation Delay (tPLH) vs. Capacitive Load
Figure 18. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation)
at Pin A (Y→A Level Translation)
9
8
7
6
5
4
3
2
1
0
14
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
DATA RATE = 50kbps
12
10
8
V
= 1.2V, V = 1.8V
CCY
CCA
V
= 1.2V, V = 1.8V
CCY
CCA
6
V
= 1.8V, V = 3.3V
CCY
CCA
V
= 1.8V, V = 3.3V
CCY
CCA
4
V
= 3.3V, V = 5V
CCY
CCA
V
= 3.3V, V = 5V
CCY
CCA
2
0
13
18
23
28
33
38
43
48
53
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 19. Propagation Delay (tPLH) vs. Capacitive Load
Figure 22. Propagation Delay (tPHL) vs. Capacitive Load
at Pin Y (A→Y Level Translation)
at Pin A (Y→A Level Translation)
Rev. D | Page 10 of 20
Data Sheet
ADG3308/ADG3308-1
T
= 25°C
A
T
= 25°C
A
DATA RATE = 25Mbps
= 50pF
DATA RATE = 50Mbps
= 15pF
C
L
C
L
1 CHANNEL
1 CHANNEL
400mV/DIV
5ns/DIV
400mV/DIV
3ns/DIV
Figure 23. Eye Diagram at Y Output
(1.2 V→1.8 V Level Translation, 25 Mbps)
Figure 26. Eye Diagram at A Output
(3.3 V→1.8 V Level Translation, 50 Mbps)
T
= 25°C
C
= 50pF
T
= 25°C
A
L
A
DATA RATE = 25Mbps
1 CHANNEL
DATA RATE = 50Mbps
C
= 50pF
L
1 CHANNEL
1V/DIV
200mV/DIV
3ns/DIV
5ns/DIV
Figure 24. Eye Diagram at A Output
Figure 27. Eye Diagram at Y Output
(1.8 V→1.2 V Level Translation, 25 Mbps)
(3.3 V→5 V Level Translation, 50 Mbps)
T
= 25°C
T
= 25°C
C = 50pF
L
A
A
DATA RATE = 50Mbps
C
DATA RATE = 50Mbps 1 CHANNEL
= 15pF
L
1 CHANNEL
500mV/DIV
3ns/DIV
3ns/DIV
800mV/DIV
Figure 25. Eye Diagram at Y Output
Figure 28. Eye Diagram at A Output
(1.8 V→3.3 V Level Translation, 50 Mbps)
(5 V→3.3 V Level Translation, 50 Mbps)
Rev. D | Page 11 of 20
ADG3308/ADG3308-1
TEST CIRCUITS
Data Sheet
EN
V
ADG3308/
V
CCA
ADG3308-1
CCY
ADG3308/
ADG3308-1
V
V
CCY
CCA
0.1µF
0.1µF
0.1µF
0.1µF
Ax
Yx
K2
Yx
Ax
K1
GND
K
EN
A
GND
I
I
OL
OH
Figure 29. VOH/VOL Voltages at Pin A
Figure 33. EN Pin Leakage Current
EN
ADG3308/
ADG3308-1
V
CCA
V
CCY
EN
ADG3308/
ADG3308-1
V
CCA
0.1µF
V
0.1µF
CCY
K2
x A
Yx
Ax
Yx
K1
GND
CAPACITANCE
METER
GND
I
OH
I
OL
Figure 30. VOH/VOL Voltages at Pin Y
Figure 34. Capacitance at Pin A
EN
EN
ADG3308/
ADG3308-1
ADG3308/
ADG3308-1
V
V
V
V
CCA
CCY
CCA
CCY
0.1µF
0.1µF
Ax
Yx
Ax
Yx
A
K
CAPACITANCE
METER
GND
GND
Figure 31. Three-State Leakage Current at Pin A
Figure 35. Capacitance at Pin Y
EN
ADG3308/
ADG3308-1
V
CCA
V
CCY
0.1µF
0.1µF
K
Ax
Yx
A
GND
Figure 32. Three-State Leakage Current at Pin Y
Rev. D | Page 12 of 20
Data Sheet
ADG3308/ADG3308-1
A→Y DIRECTION
V
V
CCA
ADG3308/
ADG3308-1
CCY
+
+
0.1µF
10µF
0.1µF
10µF
1MΩ
V
Ax
x Y
V
A
Y
K1
K2
50pF
1MΩ
SIGNAL SOURCE
EN
GND
Z
= 50Ω
0
R
S
V
EN
50Ω
R
T
50Ω
Y→A DIRECTION
V
V
CCA
CCY
ADG3308/
ADG3308-1
+
+
0.1µF
10µF
0.1µF
10µF
1MΩ
V
Ax
x Y
V
A
Y
K1
1MΩ
K2
15pF
SIGNAL SOURCE
EN
GND
Z
= 50Ω
0
R
S
V
EN
50Ω
R
T
50Ω
V
CCY
tEN1
V
EN
0V
V
/V
CCA CCY
V
/V
A
Y
A
0V
V
/V
CCY CCA
90%
V /V
Y
0V
V
CCY
tEN2
V
EN
0V
V
/V
Y
A
V
/V
CCA CCY
0V
V
/V
CCY CCA
V /V
Y
A
10%
0V
NOTES
1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2
IN BOTH A→Y AND Y→A DIRECTIONS.
Figure 36. Enable Time
Rev. D | Page 13 of 20
ADG3308/ADG3308-1
Data Sheet
EN
V
ADG3308/
ADG3308-1
V
+
CCA
CCY
+
SIGNAL
SOURCE
0.1µF
= 50Ω
10µF
0.1µF
10µF
Z
R
S
0
V
V
x Y
A
A x
Y
R
50Ω
50Ω
T
50pF
GND
V
A
50%
90%
tP, A→Y
tP, A→Y
V
Y
50%
10%
tF, A→Y
tR, A→Y
Figure 37. Switching Characteristics (A→Y Level Translation)
EN
ADG3308/
ADG3308-1
V
V
CCA
CCY
+
+
SIGNAL
SOURCE
0.1µF
10µF
10µF
0.1µF
x Y
Z
0
= 50Ω
R
S
A x
V
V
R
A
Y
50Ω
T
15pF
50Ω
GND
V
Y
50%
90%
tP, Y→A
tP, Y→A
V
A
50%
10%
tF, Y→A
tR, Y→A
Figure 38. Switching Characteristics (Y→A Level Translation)
Rev. D | Page 14 of 20
Data Sheet
ADG3308/ADG3308-1
TERMINOLOGY
VIHA
DMAX, A→Y
Logic input high voltage at Pin A1 to Pin A8.
Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
Table 1.
VILA
Logic input low voltage at Pin A1 to Pin A8.
tSKE W, A→Y
VOHA
Difference between propagation delays on any two channels
when translating logic levels in the A→Y direction.
Logic output high voltage at Pin A1 to Pin A8.
VOLA
tPPSKEW, A→Y
Logic output low voltage at Pin A1 to Pin A8.
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the A→Y direction.
CA
Capacitance measured at Pin A1 to Pin A8 (EN = 0).
ILA, HIGH-Z
tP, Y →A
Leakage current at Pin A1 to Pin A8 when EN = 0 (high
impedance state at Pin A1 to Pin A8).
Propagation delay when translating logic levels in the Y→A
direction.
VIHY
tR, Y→A
Logic input high voltage at Pin Y1 to Pin Y8.
Rise time when translating logic levels in the Y→A direction.
VILY
tF, Y→A
Logic input low voltage at Pin Y1 to Pin Y8.
Fall time when translating logic levels in the Y→A direction.
VOHY
DMAX, Y→A
Logic output high voltage at Pin Y1 to Pin Y8.
Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
Table 1.
VOLY
Logic output low voltage at Pin Y1 to Pin Y8.
CY
tSKE W, Y→A
Capacitance measured at Pin Y1 to Pin Y8 (EN = 0).
Difference between propagation delays on any two channels
when translating logic levels in the Y→A direction.
ILY, HIGH-Z
Leakage current at Pin Y1 to Pin Y8 when EN = 0 (high
impedance state at Pin Y1 to Pin Y8).
tPPSKEW, Y→A
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the Y→A direction.
VIHEN
Logic input high voltage at the EN pin.
VCCA
VILEN
V
CCA supply voltage.
Logic input low voltage at the EN pin.
VCCY
CEN
VCCY supply voltage.
Capacitance measured at EN pin.
ICCA
ILEN
VCCA supply current.
Enable (EN) pin leakage current.
ICCY
tEN
VCCY supply current.
Three-state enable time for Pin A1 to Pin A8/Pin Y1 to Pin Y8.
IHIGH-ZA
tP, A →Y
VCCA supply current during three-state mode (EN = 0).
Propagation delay when translating logic levels in the A→Y
direction.
IHIGH-ZY
VCCY supply current during three-state mode (EN = 0).
tR, A→Y
Rise time when translating logic levels in the A→Y direction.
tF, A→Y
Fall time when translating logic levels in the A→Y direction.
Rev. D | Page 15 of 20
ADG3308/ADG3308-1
Data Sheet
THEORY OF OPERATION
The ADG3308/ADG3308-1 level translators allow the level
shifting necessary for data transfer in a system where multiple
supply voltages are used. The device requires two supplies, VCCA
and VCCY (VCCA ≤ VCCY). These supplies set the logic levels on
each side of the device. When driving the A pins, the device
translates the VCCA compatible logic levels to VCCY compatible
logic levels available at the Y pins. Similarly, because the device
is capable of bidirectional translation, when driving the Y pins
the VCCY compatible logic levels are translated to the VCCA
compatible logic levels available at the A pins. When EN = 0,
the A1 pin to the A8 pin and the Y1 pin to the Y8 pin are three-
stated. When EN is driven high, the ADG3308/ADG3308-1 go
into normal operation mode and perform level translation.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3308/ADG3308-1,
the circuit that drives the input of the device should be able
to ensure rise/fall times of less than 3 ns when driving a
load consisting of a 6 kΩ resistor in parallel with the input
capacitance of the ADG3308/ADG3308-1 channel.
OUTPUT LOAD REQUIREMENTS
The ADG3308/ADG3308-1 level translators are designed to
drive CMOS-compatible loads. If current-driving capability
is required, it is recommended to use buffers between the
ADG3308/ADG3308-1 outputs and the load.
ENABLE OPERATION
LEVEL TRANSLATOR ARCHITECTURE
The ADG3308/ADG3308-1 provide three-state operation at the
A I/O pins and the Y I/O pins by using the enable (EN) pin, as
shown in Table 4.
The ADG3308/ADG3308-1 consist of eight bidirectional
channels. Each channel can translate logic levels in either the
A→Y or the Y→A direction. They use a one-shot accelerator
architecture, ensuring excellent switching characteristics.
Figure 39 shows a simplified block diagram of a bidirectional
channel.
Table 4. Truth Table
EN
Y I/O Pins
High-Z1
Normal operation2
A I/O Pins
High-Z1
Normal operation2
0
1
V
V
CCA
CCY
1 High impedance state.
2 In normal operation, the ADG3308/ADG3308-1 perform level translation.
T1
T2
When EN = 0, the ADG3308/ADG3308-1 enter into three-state
mode. In this mode, the current consumption from both the
6kΩ
V
CCA and VCCY supplies is reduced, allowing the user to save
U1
U2
power, which is critical, especially in battery-operated systems.
The EN input pin can only be driven with VCCY compatible logic
levels for the ADG3308, whereas the ADG3308-1 can be driven
with either VCCA- or VCCY compatible logic levels.
P
A
ONE-SHOT GENERATOR
Y
N
U4
U3
6kΩ
POWER SUPPLIES
For proper operation of the device, the voltage applied to the
T4
T3
V
CCA must always be less than or equal to the voltage applied
to VCCY. To meet this condition, the recommended power-up
sequence is VCCY first and then VCCA. The ADG3308/ADG3308-1
operate properly only after both supply voltages reach their
nominal values. It is not recommended to use the part in a system
where, during power-up, VCCA may be greater than VCCY due to
a significant increase in the current taken from the VCCA supply.
For optimum performance, the VCCA and VCCY pins should be
decoupled to GND as close as possible to the device.
Figure 39. Simplified Block Diagram of an
ADG3308/ADG3308-1 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), whereas the
translation in the Y→A direction is performed using the U3
inverter and U4 inverter. The one-shot generator detects a rising
or falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS transistors
(T1 and T2) for a rising edge, or the NMOS transistors (T3 and
T4) for a falling edge. This charges/discharges the capacitive load
faster, resulting in fast rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding VCC rail (VCCA or VCCY) or to GND.
Rev. D | Page 16 of 20
Data Sheet
ADG3308/ADG3308-1
DATA RATE
The maximum data rate at which the device is guaranteed to
operate is a function of the VCCA and VCCY supply voltage
combination and the load capacitance. It represents the maximum
frequency of a square wave that can be applied to the I/O pins,
ensuring that the device operates within the data sheet
specifications in terms of output voltage (VOL and VOH) and
power dissipation (the junction temperature does not exceed
the value specified under the Absolute Maximum Ratings
section). Table 5 shows the guaranteed data rates at which the
ADG3308/ADG3308-1 can operate in both directions (A→Y
level translation or Y→A level translation) for various VCCA
and VCCY supply combinations.
Table 5. Guaranteed Data Rates1
VCCY
3.3 V (3.0 V to 3.6 V)
40 Mbps
VCCA
1.8 V (1.65 V to 1.95 V)
2.5 V (2.3 V to 2.7 V)
30 Mbps
45 Mbps
5 V (4.5 V to 5.5 V)
40 Mbps
50 Mbps
50 Mbps
50 Mbps
1.2 V (1.15 V to 1.3 V)
1.8 V (1.65 V to 1.95 V)
2.5 V (2.3 V to 2.7 V)
3.3 V (3.0 V to 3.6 V)
5 V (4.5 V to 5.5 V)
25 Mbps
50 Mbps
60 Mbps
1 The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.
Rev. D | Page 17 of 20
ADG3308/ADG3308-1
Data Sheet
APPLICATIONS
The ADG3308/ADG3308-1 are designed for digital circuits
that operate at different supply voltages; therefore, logic level
translation is required. The lower voltage logic signals are
connected to the A pins, and the higher voltage logic signals
to the Y pins. The ADG3308/ADG3308-1 can provide level
translation in both directions (A→Y or Y→A) on all eight
channels, eliminating the need for a level translator IC for
each direction. The internal architecture allows the ADG3308/
ADG3308-1 to perform bidirectional level translation without
an additional signal to set the direction in which the translation
is made. It also allows simultaneous data flow in both directions
on the same part, for example, when two channels translate in the
A→Y direction while the other two translate in the Y→A
direction. This simplifies the design by eliminating the timing
requirements for the direction signal and reduces the number of
ICs used for level translation.
100nF
100nF
ADG3308/
ADG3308-1
V
V
CCY
CCA
A1
A2
A3
A4
A5
A6
A7
A8
3.3V
1.8V
I/O 1
L
I/O 1
H
Y1
I/O 2
L
I/O 2
H
Y2
Y3
I/O 3
L
I/O 3
H
I/O 4
L
I/O 4
H
Y4
Y5
Y6
Y7
Y8
EN
I/O 5
L
I/O 5
H
I/O 6
L
I/O 6
H
I/O 7
L
I/O 7
H
I/O 8
H
I/O 8
L
GND
GND
CS
GND
100nF
100nF
Figure 40 shows an application where a 3.3 V microprocessor
can read or write data to and from a 1.8 V peripheral device
using an 8-bit bus.
ADG3308/
ADG3308-1
V
V
CCY
CCA
1.8V
I/O 1
L
Y1
A1
100nF
100nF
V
I/O 2
L
Y2
Y3
A2
A3
A4
A5
A6
A7
A8
V
CCY
CCA
I/O 3
L
3.3V
1.8V
I/O 4
L
Y4
Y5
Y6
Y7
Y8
EN
I/O 1
L
Y1
A1
I/O 1
H
I/O 5
L
ADG3308/
ADG3308-1
I/O 6
L
I/O 7
L
I/O 2
L
Y2
Y3
A2
A3
I/O 2
H
I/O 8
L
GND
GND
I/O 3
L
I/O 3
H
Figure 41. 1.8 V to 3.3 V Level Translation Circuit
Using the Three-State Feature
Y4
Y5
A4
A5
I/O 4
L
I/O 4
H
I/O 5
L
I/O 5
H
LAYOUT GUIDELINES
I/O 6
L
As with any high speed digital IC, the printed circuit board
layout is important in the overall performance of the circuit. Care
should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each VCC pin (VCCA and
Y6
A6
A7
I/O 6
H
I/O 7
L
Y7
Y8
EN
I/O 7
H
A8
I/O 8
L
I/O 8
H
V
CCY) should be bypassed using low effective series resistance
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the VCCA and VCCY pins. The parasitic induc-
tance of the high speed signal track can cause significant overshoot.
This effect can be reduced by keeping the length of the tracks as
short as possible. A solid copper plane for the return path
(GND) is also recommended.
GND
GND
GND
Figure 40. 1.8 V to 3.3 V 8-Bit Level Translation Circuit
When the application requires level translation between
a microprocessor and multiple peripheral devices, the
ADG3308/ADG3308-1 I/O pins can be three-stated by setting
EN = 0. This feature allows the ADG3308/ADG3308-1 to share
the data buses with other devices without causing contention
issues. Figure 41 shows an application where a 3.3 V micro-
processor is connected to 1.8 V peripheral devices using the
three-state feature.
Rev. D | Page 18 of 20
Data Sheet
ADG3308/ADG3308-1
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
4.10
4.00 SQ
0.60 MAX
3.90
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
EXPOSED
PAD
3.75
BCS SQ
10
6
11
0.75
0.60
0.50
0.25 MIN
BOTTOM VIEW
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 43. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
Rev. D | Page 19 of 20
ADG3308/ADG3308-1
Data Sheet
2.06
2.00
1.94
4
3
2
1
A
B
C
D
E
BALL A1
IDENTIFIER
2.56
2.50
2.44
2.00 REF
0.50
BSC
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
0.370
0.350
0.330
1.50 REF
0.650
0.590
0.530
SIDE VIEW
COPLANARITY
0.05
SEATING
PLANE
0.360
0.320
0.280
0.280
0.240
0.200
Figure 44. 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
RU-20
RU-20
ADG3308BRUZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Ball Wafer Level Chip Scale Package [WLCSP]
20-Ball Wafer Level Chip Scale Package [WLCSP]
ADG3308BRUZ-REEL
ADG3308BRUZ-REEL7
ADG3308BCPZ-REEL
ADG3308BCPZ-REEL7
ADG3308BCBZ-1-RL7
ADG3308BCBZ-1-REEL
RU-20
CP-20-1
CP-20-1
CB-20-2
CB-20-2
1 Z = RoHS Compliant Part.
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04865-0-10/13(D)
Rev. D | Page 20 of 20
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