ADG333ABRZ1 [ADI]
Quad SPDT Switch; 四路SPDT开关
| 型号： | ADG333ABRZ1 |
| 厂家： | 
ADI |
| 描述： | Quad SPDT Switch |
| 文件： | 总12页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad SPDT Switch
ADG333A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
44 V supply maximum ratings
VSS to VDD analog signal range
Low on resistance (45 Ω max)
Low ∆RON (5 Ω max)
S4A
D2
S1A
D1
S4B
S1B
IN1
IN4
Low RON match (4 Ω max)
Low power dissipation
Fast switching times
tON < 175 ns
ADG333A
IN2
IN3
S2B
D2
S3B
D3
tOFF < 145 ns
S2A
S3A
Low leakage currents (5 nA max)
Low charge injection (10 pC max)
Break-before-make switching action
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
APPLICATIONS
Audio and video switching
Battery-powered systems
Test equipment
Communication systems
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG333A is a monolithic CMOS device comprising four
independently selectable SPDT switches. It is designed on an
LC2MOS process, which provides low power dissipation yet
achieves a high switching speed and a low on resistance.
1. Extended signal range.
The ADG333A is fabricated on an enhanced LC2MOS
process, giving an increased signal range which extends to
the supply rails.
2. Low power dissipation.
The on resistance profile is very flat over the full analog input
range, ensuring good linearity and low distortion when
switching audio signals. High switching speed also makes the
part suitable for video signal switching. CMOS construction
ensures ultralow power dissipation, making the part ideally
suited for portable, battery-powered instruments.
3. Low RON
.
4. Single-supply operation.
For applications where the analog signal is unipolar, the
ADG333A can be operated from a single rail power supply.
The part is fully specified with a single 12 V supply.
When they are on, each switch conducts equally well in both
directions and has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked. All switches exhibit break-before-make
switching action for use in multiplexer applications. Inherent
in the design is low charge inject
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADG333A
TABLE OF CONTENTS
Specifications..................................................................................... 3
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 10
Application Information................................................................ 11
ADG333A Supply Voltages....................................................... 11
Power Supply Sequencing ......................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Terminology ...................................................................................... 6
Pin Configurations and Function Descriptions ........................... 7
REVISION HISTORY
3/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Specifications Tables.................................................... 3
Updated Outline Dimensions....................................................... 12
Changes to Ordering Guide .......................................................... 12
10/95—Revision 0: Initial Version
Rev. A | Page 2 of 12
ADG333A
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V, VSS = −15 V, GND = 0 V, unless otherwise noted.1
Table 1.
Parameter
+25°C
−40°C to +85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
VSS to VDD
V
20
45
Ω typ
Ω max
Ω max
Ω max
VD = 10 Vꢀ IS = –1 mA
45
5
VD = 5 Vꢀ IS = –10 mA
VD = 10 Vꢀ IS = –10 mA
VDD = +16.5 Vꢀ VSS = –16.5 V
VD = 15.5 Vꢀ VS = +15.5 V
Figure 15
∆RON
RON Match
4
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
0.1
nA typ
nA max
nA typ
nA max
0.25
0.1
3
5
Channel ON Leakage IDꢀ IS (ON)
VS = VD = 15.5 V
0.4
Figure 16
DIGITAL INPUTS
Input High Voltageꢀ VINH
Input Low Voltageꢀ VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
0.5
µA typ
µA max
VIN = 0 V or VDD
DYNAMIC CHARACTERISTICS2
tON
90
80
10
ns typ
ns max
ns typ
ns max
ns min
RL= 300 Ωꢀ CL = 35 pF;
VS = 10 V; Figure 17
RL = 300 Ωꢀ CL = 35 pF;
VS = 10 V; Figure 17
RL = 300 Ωꢀ CL= 35 pF;
VS = +5 V; Figure 18
175
145
tOFF
Break-Before-Make Delayꢀ tOPEN
Charge Injection
2
10
72
pC typ
pC max
dB typ
VD = 0 Vꢀ RD = 0 Ωꢀ CL= 10 nF;
VDD = +15 Vꢀ VSS = –15 V; Figure 19
RL = 75 Ωꢀ CL = 5 pFꢀ f = 1 MHz;
VS = 2.3 V rms; Figure 20
OFF Isolation
Channel-to-Channel Crosstalk
85
dB typ
RL = 75 Ωꢀ CL = 5 pFꢀ f = 1 MHz;
VS = 2.3 V rms; Figure 21
CS (OFF)
CDꢀ CS (ON)
7
26
pF typ
pF typ
POWER REQUIREMENTS
IDD
0.05
0.25
0.01
1
mA typ
mA max
µA typ
Digital inputs = 0 V or 5 V
0.35
ISS
5
µA max
VDD/VSS
3/ 20
V min/V max
|VDD| = |VSS|
1 Temperature range is as follows: B version: −40°C to +85°C.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 12
ADG333A
SINGLE SUPPLY
VDD = +12 V, VSS = 0 V 10ꢀ, GND = 0 V, unless otherwise noted.1
Table 2.
Parameter
+25°C
−40°C to +85°C
0 V to VDD
75
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
V
35
Ω typ
Ω max
VD = 1 Vꢀ 10 Vꢀ IS = –1 mA
LEAKAGE CURRENTS
VDD = 13.2 V
Source OFF Leakage IS (OFF)
0.1
0.25
0.1
nA typ
nA max
nA typ
nA max
VD = 12.2 V/1 Vꢀ VS = 1 V/12.2 V
Figure 15
VS = VD = 12.2 V/1 V
Figure 16
3
5
Channel ON Leakage IDꢀ IS (ON)
0.4
DIGITAL INPUTS
Input High Voltageꢀ VINH
Input Low Voltageꢀ VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
0.5
µA typ
µA max
VIN = 0 V or VDD
DYNAMIC CHARACTERISTICS2
tON
110
100
10
5
ns typ
ns max
ns typ
ns max
ns min
ns min
pC typ
RL = 300 Ωꢀ CL = 35 pF;
VS = 8 V; Figure 17
RL = 300 Ωꢀ CL = 35 pF;
VS = 8 V; Figure 17
RL = 300 Ωꢀ CL = 35 pF;
VS = 5 V; Figure 18
VD = 6 Vꢀ RD = 0 Wꢀ CL = 10 nF;
VDD = 12 Vꢀ VSS = 0 V; Figure 19
RL = 75 Ωꢀ CL = 5 pFꢀ f = 1 MHz;
VS = 1.15 V rms; Figure 20
RL = 75 Ωꢀ CL = 5 pFꢀ f = 1 MHz;
VS = 1.15 V rms; Figure 21
200
180
tOFF
Break-Before-Make Delayꢀ tOPEN
Charge Injection
OFF Isolation
72
85
dB typ
dB typ
Channel-to-Channel Crosstalk
CS (OFF)
CDꢀ CS (ON)
12
25
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 13.5 V
Digital inputs = 0 V or 5 V
0.05
0.25
mA typ
mA max
0.35
VDD
3/ 30
V min/V max
1 Temperature range is as follows: B Version: −40°C to +85°C.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 12
ADG333A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Min
VDD to VSS
+44 V
VDD to GND
VSS to GND
Analogꢀ Digital Inputs1
–0.3 V to +30 V
+0.3 V to –30 V
VSS – 2 V to VDD + 2 V or 20 mAꢀ
whichever occurs first
Continuous Currentꢀ S or D
Peak Currentꢀ S or D (Pulsed at
1 msꢀ 10% Duty Cycle Max)
20 mA
40 mA
Table 4. Truth Table
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
θJAꢀ Thermal Impedance
PDIP Package
SOIC Package
SSOP Package
Lead Temperatureꢀ Soldering
(10 sec)
Logic
Switch A
Switch B
On
Off
−40°C to +85°C
−65°C to +125°C
150°C
0
1
Off
On
103°C/W
74°C/W
130°C/W
260°C
Lead Temperatureꢀ Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
Lead Temperatureꢀ Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
1 Overvoltage at INꢀ Sꢀ or D is clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitryꢀ permanent damage may occur on devices subjected to high energy
electrostatic discharges. Thereforeꢀ proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 12
ADG333A
TERMINOLOGY
RON
tON
Ohmic resistance between D and S.
Delay between applying the digital control input and the output
switching on.
∆RON
tOFF
RON variation due to a change in the analog input voltage with a
constant load current.
Delay between applying the digital control input and the output
switching off.
RON Match
tOPEN
Difference between the RON of any two channels.
IS (OFF)
Break-before-make delay when switches are configured as a
multiplexer.
Source leakage current with the switch off.
ID (OFF)
VINL
Maximum input voltage for Logic 0.
VINH
Drain leakage current with the switch off.
ID, IS (ON)
Minimum input voltage for Logic 1.
Channel leakage current with the switch on.
VD (VS)
IINL (IINH
)
Input current of the digital input.
Analog voltage on Terminals D, S.
CS (OFF)
Crosstalk
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
OFF switch source capacitance.
CD (OFF)
Off Isolation
A measure of unwanted signal coupling through an OFF switch.
OFF switch drain capacitance.
CD, CS (ON)
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ON switch capacitance.
Rev. A | Page 6 of 12
ADG333A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
S1A
D1
1
2
3
4
5
6
7
8
9
20 IN4
19 S4A
18 D4
IN1
S1A
D1
1
2
3
4
5
6
7
8
9
20 IN4
19 S4A
18 D4
IN1
S1A
D1
1
2
3
4
5
6
7
8
9
20 IN4
19 S4A
18 D4
S1B
17 S4B
ADG333A
TOP VIEW
(Not to Scale)
S1B
ADG333A
TOP VIEW
(Not to Scale)
17 S4B
ADG333A
S1B
17 S4B
V
16
V
DD
SS
TOP VIEW
V
16
V
DD
V
16
V
DD
SS
SS
GND
S2B
D2
15 NC
14 S3B
13 D3
(Not to Scale)
GND
S2B
D2
15 NC
14 S3B
13 D3
GND
S2B
D2
15 NC
14 S3B
13 D3
S2A
12 S3A
11 IN3
S2A
12 S3A
11 IN3
S2A
12 S3A
11 IN3
IN2 10
IN2 10
IN2 10
NC = NO CONNECT
NC = NO CONNECT
NC = NO CONNECT
Figure 2. PDIP Pin Configuration
Figure 3. SOIC Pin Configuration
Figure 4. SSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1ꢀ 10ꢀ 11ꢀ 20
IN1ꢀ IN2ꢀ IN3ꢀ IN4
Logic Control Input.
2ꢀ 4ꢀ 7ꢀ 9ꢀ 12ꢀ 14ꢀ
17ꢀ 19
S1Aꢀ S1Bꢀ S2Bꢀ S2Aꢀ
S3Aꢀ S3Bꢀ S4Bꢀ S4A
Source Terminal. Can be an input or output.
3ꢀ 8ꢀ 13ꢀ 18
5
D1ꢀ D2ꢀ D3ꢀ D4
VSS
Drain Terminal. Can be an input or output.
Most Negative Power Supply Potential in Dual Supplies. In single-supply applicationsꢀ it can be
connected to ground.
6
15
16
GND
NC
VDD
Ground (0 V) Reference.
No Connect.
Most Positive Power Supply Potential.
Rev. A | Page 7 of 12
ADG333A
TYPICAL PERFORMANCE CHARACTERISTICS
60
60
V
V
= 15V
= 0V
T
= 25°C
DD
SS
A
50
40
30
50
40
30
V
V
= +5V
= –5V
DD
SS
+125°C
+85°C
V
V
= +10V
= –10V
DD
SS
20
10
20
10
+25°C
–40°C
V
V
= +15V
= –15V
DD
SS
–15
–10
–5
0
5
10
15
0
3
6
9
12
15
V
, V (V)
V
, V (V)
DD
S
DD S
Figure 5. RON as a Function of VD (VS):
Dual Supply
Figure 8. RON as a Function of VD (VS) for Different Temperatures:
Single Supply
100
0.004
T
= 25°C
A
V
V
T
= +16.5V
= –16.5V
= 25°C
DD
SS
90
80
0.002
0
I
(OFF)
A
S
V
V
= +5V
= –5V
DD
SS
70
60
–0.002
–0.004
–0.006
I
(ON)
S
50
40
V
V
= +10V
= –10V
DD
SS
I
(ON)
D
V
V
= +15V
= –15V
DD
SS
–0.008
–0.010
30
20
0
3
6
9
12
15
–15
–10
–5
0
5
10
15
V
, V (V)
V , V (V)
D S
DD
S
Figure 6. RON as a Function of VD (VS):
Single Supply
Figure 9. Leakage Currents as a Function of VD (VS):
Dual Supply
45
0.001
0
V
V
= +15V
= –15V
DD
SS
I (OFF)
S
40
35
V
V
= +16.5V
= –16.5V
= 25°C
DD
SS
T
A
+125°C
–0.001
–0.002
30
25
20
+85°C
I
(ON)
D
I
(ON)
S
–0.003
–0.004
15
10
–40°C
+25°C
–15
–10
–5
0
5
10
15
0
3
6
9
12
V
, V (V)
V , V (V)
D S
DD
S
Figure 7. RON as a Function of VD (VS) for Different Temperatures:
Dual Supply
Figure 10. Leakage Currents as a Function of VD (VS):
Single Supply
Rev. A | Page 8 of 12
ADG333A
20
1
0.8
0.6
0.4
C
= 10nF
L
V
V
= +16.5V
= –16.5V
DD
SS
15
10
5
T
= 25°C
A
V
V
= +16.5V
= –16.5V
DD
SS
0
V
V
= +12V
= 0V
DD
SS
–5
–10
0.2
0
–15
–20
–15
–10
–5
0
5
10
15
0
200
400
600
800
1000
V
(V)
S
SWITCHING FREQUENCY (kHz)
Figure 11. Charge Injection as a Function of VS
Figure 13. IDD as a Function of Switching Frequency
160
140
120
100
V
V
= +2V
= –2V
D
S
80
60
0
5
10
(V)
15
20
V
DD
Figure 12. Switching Time as a Function of VD
Rev. A | Page 9 of 12
ADG333A
TEST CIRCUITS
I
DS
V
1
I
(ON)
A
I
(OFF)
A
D
S
NC
S
D
S
D
S
D
V
V
D
V
V
D
D
S
R
= V /I
DS
NC = NO CONNECT
ON
1
Figure 14. On Resistance
Figure 15. Off Leakage
Figure 16. On Leakage
V
DD
0.1µF
+3V
V
DD
50%
50%
–10V
SB
V
V
IN
D
0V
V
S
V
OUT
R
300Ω
C
L
SA
L
+10V
35pF
+10V
0V
tOFF
IN
S
V
V
GND
SS
50%
50%
tON
–10V
0.1µF
SS
Figure 17. Switching Times
V
V
DD
0.1µF
3V
DD
V
V
IN
V
S
SB
SA
D
V
0V
V
OUT
R
L
300Ω
C
L
35pF
V
S
IN
50%
50%
OUT
GND
SS
tOPEN
0.1µF
V
SS
Figure 18. Break-Before-Make Delay, tOPEN
V
V
DD
DD
3V
R
D
V
IN
V
OUT
V
D
0V
0V
D
SA
C
L
10nF
IN
V
OUT
Q
= C
×
∆V
OUT
∆V
OUT
INJ
L
V
V
GND
SS
SS
Figure 19. Charge Injection
V
V
DD
0.1µF
DD
V
DD
75Ω
0.1µF
S
D
V
DD
V
V
IN2
IN1
V
S
V
OUT
S
D
R
L
S
D
75Ω
V
V
NC
IN
OUT
R
75Ω
L
V
V
SS
GND
GND
SS
V
S
CHANNEL-TO-CHANNEL
CROSSTALK
0.1µF
0.1µF
20
×
LOG |V /V |
V
V
S
OUT
SS
SS
Figure 20. Off Isolation
Figure 21. Channel-to-Channel Crosstalk
Rev. A | Page 10 of 12
ADG333A
APPLICATION INFORMATION
ADG333A SUPPLY VOLTAGES
POWER SUPPLY SEQUENCING
The ADG333A can operate from a dual or signal supply. VSS
should be connected to GND when operating with a single
supply. When using a dual supply, the ADG333A can also
operate with unbalanced supplies; for example VDD = 20 V and
When using CMOS devices, care must be taken to ensure
correct power-supply sequencing. Incorrect power-supply
sequencing can result in the device being subjected to stresses
beyond those listed in the Absolute Maximum Ratings. This is
also true for the ADG333A. Always turn on VDD first, followed
by VSS and the logic signals. An external signal within the maxi-
mum specified ratings can then be safely presented to the source
or drain of the switch
VSS = −5 V. The only restrictions are that VDD to GND must not
exceed 30 V, VSS to GND must not drop below −30 V, and VDD
to VSS must not exceed +44 V. It is important to remember that
the ADG333A supply voltage directly affects the input signal
range, the switch on resistance and the switching times of the
part. The effects of the power supplies on these characteristics
can be clearly seen from the Typical Performance Characteristics
curves.
Rev. A | Page 11 of 12
ADG333A
OUTLINE DIMENSIONS
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)
13.00 (0.5118)
12.60 (0.4961)
20
1
11
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
10
20
1
11
10
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
7.60 (0.2992)
7.40 (0.2913)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
10.65 (0.4193)
10.00 (0.3937)
0.210
(5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.015 (0.38)
GAUGE
PLANE
0.130 (3.30)
0.115 (2.92)
2.65 (0.1043)
2.35 (0.0925)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.75 (0.0295)
0.25 (0.0098)
SEATING
PLANE
× 45°
0.30 (0.0118)
0.10 (0.0039)
0.022 (0.56)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.018 (0.46)
0.014 (0.36)
8°
0°
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
1.27
(0.0500)
BSC
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-001-AD
COMPLIANT TO JEDEC STANDARDS MS-013AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 22. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-20)
Figure 23. 20-Lead Standard Small Outline Package [SOIC]
Wide Body (R-20)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
7.50
7.20
6.90
20
11
5.60
5.30
5.00
8.20
7.80
7.40
1
10
PIN 1
1.85
1.75
1.65
2.00 MAX
0.25
0.09
8°
4°
0°
0.65
0.95
0.75
0.55
0.38
0.22
0.05 MIN
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-150AE
Figure 24. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG333ABN
Temperature Range
Package Description
Package Option
N-20
R-20
R-20
R-20
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
20-Lead Plastic Dual In-Line Package (PDIP)
20-Lead Standard Small Outline Package (SOIC)
20-Lead Standard Small Outline Package (SOIC)
20-Lead Standard Small Outline Package (SOIC)
20-Lead Standard Small Outline Package (SOIC)
20-Lead Shrink Small Outline Package (SSOP)
20-Lead Shrink Small Outline Package (SSOP)
20-Lead Shrink Small Outline Package (SSOP)
20-Lead Shrink Small Outline Package (SSOP)
ADG333ABR
ADG333ABR-REEL
ADG333ABRZ1
ADG333ABRZ-REEL1
ADG333ABRS
ADG333ABRS-REEL
ADG333ABRSZ1
ADG333ABRSZ-REEL1
R-20
RS-20
RS-20
RS-20
RS-20
1 Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01212–0–3/05(A)
Rev. A | Page 12 of 12
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