ADG411_15 [ADI]
LC MOS Precision Quad SPST Switches;
| 型号： | ADG411_15 |
| 厂家： | 
ADI |
| 描述： | LC MOS Precision Quad SPST Switches |
| 文件： | 总16页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
Precision Quad SPST Switches
ADG411/ADG412/ADG413
The ADG411, ADG412, and ADG413 contain four independent
SPST switches. The ADG411 and ADG412 differ only in that
the digital control logic is inverted. The ADG411 switches are
turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG412. The ADG413
has two switches with digital control logic similar to that of the
ADG411 while the logic is inverted on the other two switches.
FEATURES
44 V supply maximum ratings
1ꢀ V analog signal range
Low on resistance (< 3ꢀ Ω)
Ultralow power dissipation (3ꢀ μW)
Fast switching times
t
t
ON < 17ꢀ ns
OFF < 14ꢀ ns
Each switch conducts equally well in both directions when on,
and each has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
All switches exhibit break-before-make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital
inputs.
TTL-/CMOS-compatible
Plug-in replacement for DG411/DG412/DG413
APPLICATIONS
Audio and video switching
Automatic test equipment
Precision data acquisition
Battery-powered systems
Sample-and-hold systems
Communication systems
PRODUCT HIGHLIGHTS
1. Extended signal range
The ADG411, ADG412, and ADG413 are fabricated on an
enhanced LC2MOS, giving an increased signal range which
extends fully to the supply rails.
GENERAL DESCRIPTION
The ADG411, ADG412, and ADG413 are monolithic CMOS
devices comprising four independently selectable switches.
They are designed on an enhanced LC2MOS process which
provides low power dissipation yet gives high switching speed
and low on resistance.
2. Ultralow power dissipation
3. Low RON
4. Break-before-make switching
This prevents channel shorting when the switches are
configured as a multiplexer.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery-powered instruments.
5. Single-supply operation
For applications where the analog signal is unipolar, the
ADG411, ADG412, and ADG413 can be operated from a
single-rail power supply. The parts are fully specified with a
single 12 V power supply and remain functional with single
supplies as low as 5 V.
FUNCTIONAL BLOCK DIAGRAMS
S1
S1
S1
IN1
IN1
IN2
IN3
IN4
IN1
D1
S2
D1
S2
D1
S2
IN2
IN2
D2
S3
D2
D2
S3
ADG412
ADG411
ADG413
S3
IN3
IN3
D3
S4
D3
S4
D3
S4
IN4
IN4
D4
D4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
SWITCHES SHOWN FOR A LOGIC 1 INPUT
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1. ADG411
Figure 2. ADG412
Figure 3. ADG413
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADG411/ADG412/ADG413
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Terminology.......................................................................................9
Applications..................................................................................... 10
Test Circuits..................................................................................... 11
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
REVISION HISTORY
6/10—Rev. C to Rev. D
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 15
11/04—Rev. B to Rev. C
Format Updated..................................................................Universal
Change to Package Drawing (Figure 23)..................................... 13
Changes to Ordering Guide .......................................................... 14
7/04—Rev. A to Rev. B
Changes to ORDERING GUIDE .....................................................5
Updated OUTLINE DIMENSIONS ...............................................11
Rev. D | Page 2 of 16
ADG411/ADG412/ADG413
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = –15 V 10%, VL = 5 V 10%, ꢀND = 0 V, unless otherwise noted.1
Table 1.
B Version
−40°C to
+25°C +85°C
T Version
−55°C to
+25°C +125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
VDD to VSS
VDD to VSS
V
25
35
25
35
Ω typ
Ω max
VD = ±±.5 V, IS = −10 mA;
VDD = +13.5 V, VSS = −13.5 V
VDD = +16.5 V, VSS = −16.5 V
45
45
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
±0.1
±0.1
nA typ
VD = +15.5 V/−15.5 V,
VS = −15.5 V/+15.5 V;
±0.25
±0.1
±0.25
±0.25
±0.1
±20
nA max
nA typ
Figure 15
VD = +15.5 V/−15.5 V,
VS = −15.5 V/+15.5 V;
Drain OFF Leakage ID (OFF)
±0.25
±0.1
±0.4
±5
±0.25
±0.1
±0.4
±20
nA max
nA typ
nA max
Figure 15
VD = VS = +15.5 V/−15.5 V;
Figure 16
Channel ON Leakage ID, IS (ON)
±10
± 40
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.±
2.4
0.±
V min
V max
IINL or IINH
0.005
0.005
μA typ
VIN = VINL or VINH
±0.5
±0.5
μA max
DYNAMIC CHARACTERISTICS2
tON
110
100
110
100
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF;
VS = ±10 V; Figure 17
RL = 300 Ω, CL = 35 pF;
VS = ±10 V; Figure 17
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = 10 V; Figure 1±
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 20
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 21
175
145
175
145
tOFF
Break-Before-Make Time Delay, tD
(ADG413 Only)
Charge Injection
25
5
25
5
pC typ
dB typ
dB typ
OFF Isolation
6±
±5
6±
±5
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
VDD = +16.5 V, VSS = −16.5 V; Digital
inputs = 0 V or 5 V
IDD
ISS
IL
0.0001
1
0.0001
1
0.0001
1
0.0001
1
0.0001
1
0.0001
1
μA typ
μA max
μA typ
μA max
μA typ
μA max
5
5
5
5
5
5
1 Temperature ranges are as follows: B versions: −40°C to +±5°C; T versions: −55°C to +125°C.
2 Guaranteed by design; not subject to production test.
Rev. D | Page 3 of 16
ADG411/ADG412/ADG413
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, VL = 5 V 10%, ꢀND = 0 V, unless otherwise noted.1
Table 2.
B Version
−40°C to + 85°C
T Version
−55°C to +125°C Unit
Parameter
+25°C
+25°C
Test Conditions/Comments
ANALOG SIGNAL RANGE
RON
0 V to VDD
0 V to VDD
V
40
±0
40
±0
Ω typ
Ω max
0 < VD = ±.5 V, IS = −10 mA;
VDD = 10.± V
100
100
LEAKAGE CURRENTS
VDD = 13.2 V
Source OFF Leakage IS (OFF)
±0.1
±0.25
±0.1
±0.1
±0.25
±0.1
±0.25
±0.1
±0.4
nA typ
nA max Figure 15
nA typ
nA max Figure 15
nA typ
nA max Figure 16
VD = 12.2 V/1 V, VS = 1 V/12.2 V;
±5
±20
±20
±40
Drain OFF Leakage ID (OFF)
VD = 12.2 V/1 V, VS = 1 V/12.2 V;
±0.25
±5
Channel ON Leakage ID, IS (ON) ±0.1
±0.4
VD = VS = 12.2 V/1 V;
±10
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.±
2.4
0.±
V min
V max
IINL or IINH
0.005
0.005
μA typ
VIN = VINL or VINH
±0.5
±0.5
μA max
DYNAMIC CHARACTERISTICS2
tON
175
95
175
95
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF;
VS = ± V; Figure 17
RL = 300 Ω, CL = 35 pF;
VS = ± V; Figure 17
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +10 V; Figure 1±
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 20
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 21
250
125
250
125
tOFF
Break-Before-Make Time
Delay, tD (ADG413 Only)
Charge Injection
25
25
6±
25
25
6±
±5
pC typ
dB typ
dB typ
OFF Isolation
Channel-to-Channel Crosstalk ±5
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
VDD = 13.2 V;
Digital inputs = 0 V or 5 V
IDD
IL
0.0001
1
0.0001
1
0.0001
1
0.0001
1
μA typ
μA max
μA typ
5
5
5
5
μA max VL = 5.25 V
1 Temperature ranges are as follows: B versions:−40°C to +±5°C; T versions: −55°C to +125°C.
2 Guaranteed by design; not subject to production test.
Table 4. Truth Table (ADG413)
Table 3. Truth Table (ADG411/ADG412)
Logic
Switch 1, 4
Switch 2, 3
ON
OFF
ADG411 In
ADG412 In
Switch Condition
0
1
OFF
ON
0
1
1
0
ON
OFF
Rev. D | Page 4 of 16
ADG411/ADG412/ADG413
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameters
VDD to VSS
VDD to GND
VSS to GND
VL to GND
Analog, Digital Inputs1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Ratings
44 V
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to VDD + 0.3 V
VSS − 2 V to VDD + 2 V or
30 mA, whichever
occurs first
Continuous Current, S or D
30 mA
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle max)
100 mA
ESD CAUTION
Operating Temperature Range
Industrial (B Version)
Extended (T Version)
Storage Temperature Range
Junction Temperature
−40°C to +±5°C
−55°C to +125°C
−65°C to +150°C
150°C
PDIP, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering (10 s)
SOIC Package, Power Dissipation
θJA Thermal Impedance
TSSOP Package, Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
470 mW
117°C/W
260°C
600 mW
77°C/W
450 mW
115°C/W
35°C/W
215°C
220°C
Infrared (15 s)
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Rev. D | Page 5 of 16
ADG411/ADG412/ADG413
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
D1
S1
IN2
D2
S2
V
ADG411/
ADG412/
ADG413
V
SS
GND
S4
DD
TOP VIEW
V
(Not to Scale)
L
S3
D4
D3
IN3
IN4
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1, ±, 9, 16
2, 7, 10, 15
3, 6, 11, 14
4
Mnemonic
IN1–IN4
D1–D4
S1–S4
Description
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential in Dual Supplies. In single supply applications, it may be
connected to GND.
VSS
5
12
13
GND
VL
VDD
Ground (0 V) Reference.
Logic Power Supply (5 V).
Most Positive Power Supply Potential.
Rev. D | Page 6 of 16
ADG411/ADG412/ADG413
TYPICAL PERFORMANCE CHARACTERISTICS
50
40
30
20
10
0
50
T
V
= 25°C
= +5V
A
T
V
= 25°C
= +5V
A
L
L
V
V
= +5V
= 0V
DD
SS
40
30
20
10
0
V
V
= +10V
= 0V
DD
SS
V
V
= +5V
= –5V
DD
SS
V
V
= +12V
= 0V
DD
SS
V
V
= +10V
= –10V
DD
SS
V
V
= +12V
= –12V
DD
SS
V
V
= +15V
= 0V
DD
SS
V
V
= +15V
= –15V
DD
SS
0
5
10
15
20
–20
–10
0
10
20
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 8. On Resistance as a Function of VD (VS) Single Supply
Figure 5. On Resistance as a Function of VD (VS) Dual Supplies
100m
50
V
V
V
= +15V
= –15V
= +5V
4 SW
1 SW
DD
V
V
V
= +15V
= –15V
= +5V
DD
SS
SS
L
10m
1m
L
40
30
20
10
0
I+, I–
100μ
10μ
1μ
125°C
85°C
25°C
I
L
100n
10
100
1k
10k
100k
1M
10M
–20
–15
V
–10
–5
0
5
10
15
20
FREQUENCY (Hz)
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 9. Supply Current vs. Input Switching Frequency
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures
0.04
0.02
0
V
V
T
= +15V
= –15V
= 25°C
= +5V
10
DD
SS
V
V
V
= +15V
= –15V
= +5V
DD
SS
I
(ON)
D
A
V
L
L
1
0.1
I
(OFF)
S
V
V
= ±15V
= ±15V
D
S
I (OFF)
S
I
(OFF)
I
(OFF)
D
D
I
(ON)
–0.02
D
0.01
0.001
–0.04
–20
–10
0
10
20
100
1k
10k
100k
1M
100M
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
FREQUENCY (Hz)
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 7. Leakage Currents as a Function of Temperature
Rev. D | Page 7 of 16
ADG411/ADG412/ADG413
120
110
100
90
V
V
V
= +15V
= –15V
= +5V
DD
SS
V
V
V
= +15V
= –15V
= +5V
DD
SS
L
L
100
80
80
60
70
40
100
60
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Off Isolation vs. Frequency
Figure 12. Crosstalk vs. Frequency
Rev. D | Page ± of 16
ADG411/ADG412/ADG413
TERMINOLOGY
RON
tON
Ohmic resistance between D and S.
IS (OFF)
Delay between applying the digital control input and the output
switching on.
tOFF
Source leakage current with the switch OFF.
ID (OFF)
Delay between applying the digital control input and the output
switching off.
Drain leakage current with the switch OFF.
ID, IS (ON)
tD
OFF time or ON time measured between the 90% points of
both switches, when switching from one address state to
another.
Channel leakage current with the switch ON.
VD (VS)
Analog voltage on terminals D, S.
CS (OFF)
Crosstalk
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
OFF switch source capacitance.
CD (OFF)
Off Isolation
A measure of unwanted signal coupling through an OFF switch.
OFF switch drain capacitance.
CD, CS (ON)
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ON switch capacitance.
Rev. D | Page 9 of 16
ADG411/ADG412/ADG413
APPLICATIONS
Figure 13 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold
capacitor CH.
the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the 10 V
input range. Both the acquisition and settling times are 850 ns.
+15V
+5V
2200pF
+15V
AD711
–15V
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADꢀ411/ADꢀ412/ADꢀ413
minimizes this droop due to its low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
SW1
SW2
+15V
AD845
–15V
S
S
D
D
C
C
R
C
V
OUT
V
1000pF
IN
75
Ω
C
H
2200pF
ADG411
ADG412
ADG413
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches are at the same potential, they have a differential effect
on the op amp AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network RC and CC. This compensation network also reduces
–15V
Figure 13. Fast, Accurate Sample-and-Hold
Rev. D | Page 10 of 16
ADG411/ADG412/ADG413
TEST CIRCUITS
I
DS
V1
I
(OFF)
A
I
(OFF)
A
I
D
(ON)
A
S
D
S
D
S
D
S
D
V
R
= V1/I
V
V
V
V
D
S
ON
DS
S
D
S
Figure 14. On Resistance
Figure 15. Off Leakage
Figure 16. On Leakage
+15V
+5V
0.1μF
0.1μF
3V
ADG411
V
V
L
DD
V
50%
50%
50%
50%
IN
S
D
V
OUT
3V
ADG412
V
R
300
C
L
IN
L
V
S
Ω
35pF
IN
90%
90%
V
V
GND
SS
OUT
0.1μF
tON
tOFF
–15V
Figure 17. Switching Times
+15V
+5V
0.1μF
0.1μF
3V
0V
V
IN
50%
50%
V
V
L
DD
S1
S2
D1
D2
V
V
S1
OUT1
90%
90%
V
OUT1
R
300Ω
C
L1
35pF
L1
V
OUT2
0V
V
S2
R
C
L2
IN1, IN2
L2
300Ω
35pF
90%
V
90%
GND
SS
V
V
OUT2
IN
0V
tD
tD
0.1μF
–15V
Figure 18. Break-Before-Make Time Delay
+15V
+5V
3V
V
V
L
DD
V
R
S
OUT
S
D
V
IN
C
10nF
L
V
S
IN
V
OUT
ΔV
OUT
V
GND
SS
Q
= C × ΔV
L OUT
INJ
–15V
Figure 19. Charge Injection
Rev. D | Page 11 of 16
ADG411/ADG412/ADG413
+15V
0.1μF
+5V
+15V
F
+5V
0.1μ
0.1μF
0.1μF
V
V
L
DD
V
V
L
DD
50Ω
S
D
S
D
V
OUT
R
50
L
Ω
V
IN1
V
S
V
IN2
IN
V
V
S
IN
D
S
V
V
OUT
V
NC
GND
SS
GND
SS
R
L
50Ω
0.1μF
CHANNEL-TO-CHANNEL
CROSSTALK = 20 × LOG V /V
–15V
0.1μF
–15V
S
OUT
Figure 20. Off Isolation
Figure 21. Channel-to-Channel Crosstalk
Rev. D | Page 12 of 16
ADG411/ADG412/ADG413
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 22. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. D | Page 13 of 16
ADG411/ADG412/ADG413
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 24. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
Rev. D | Page 14 of 16
ADG411/ADG412/ADG413
ORDERING GUIDE
Model1
ADG411BN
ADG411BNZ
ADG411BR
Temperature Range
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
Package Description
16-Lead P-DIP
16-Lead P-DIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
DIE
Package Option
N-16
N-16
R-16
R-16
R-16
R-16
R-16
R-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
ADG411BR-REEL
ADG411BR-REEL7
ADG411BRZ
ADG411BRZ-REEL
ADG411BRZ-REEL7
ADG411BRU
ADG411BRU-REEL
ADG411BRU-REEL7
ADG411BRUZ
ADG411BRUZ-REEL
ADG411BRUZ-REEL7
ADG411BCHIPS
ADG412BN
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
16-Lead P-DIP
16-Lead P-DIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead P-DIP
16-Lead P-DIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
N-16
N-16
R-16
R-16
R-16
R-16
R-16
R-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
N-16
N-16
R-16
R-16
R-16
R-16
RU-16
RU-16
RU-16
RU-16
ADG412BNZ
ADG412BR
ADG412BR-REEL
ADG412BR-REEL7
ADG412BRZ
ADG412BRZ-REEL
ADG412BRZ-REEL7
ADG412BRU
ADG412BRU-REEL
ADG412BRU-REEL7
ADG412BRUZ
ADG412BRUZ-REEL
ADG412BRUZ-REEL7
ADG413BN
ADG413BNZ
ADG413BR
ADG413BR-REEL
ADG413BRZ
ADG413BRZ-REEL
ADG413BRUZ
ADG413BRUZ-500RL7
ADG413BRUZ-REEL
ADG413BRUZ-REEL7
1 Z = RoHS Compliant Part.
Rev. D | Page 15 of 16
ADG411/ADG412/ADG413
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00024-0-6/10(D)
Rev. D | Page 16 of 16
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