ADG411 [ADI]
LC2MOS Precision Quad SPST Switches; LC2MOS精密四通道SPST开关
| 型号： | ADG411 |
| 厂家： | 
ADI |
| 描述： | LC2MOS Precision Quad SPST Switches |
| 文件： | 总8页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
Precision Quad SPST Switches
ADG411/ADG412/ADG413
FUNCTIO NAL BLO CK D IAGRAMS
FEATURES
44 V Supply Maxim um Ratings
؎15 V Analog Signal Range
Low On Resistance (<35 ⍀)
Ultralow Pow er Dissipation (35 W)
Fast Sw itching Tim es
S1
S1
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
tON <175 ns
tOFF <145 ns
D2
S3
D2
S3
ADG411
ADG412
TTL/ CMOS Com patible
Plug-In Replacem ent for DG411/ DG412/ DG413
D3
S4
D3
S4
APPLICATIONS
Audio and Video Sw itching
Autom atic Test Equipm ent
Precision Data Acquisition
Battery Pow ered System s
Sam ple Hold System s
Com m unication System s
D4
D4
S1
IN1
D1
S2
IN2
IN3
IN4
D2
S3
ADG413
D3
S4
GENERAL D ESCRIP TIO N
T he ADG411, ADG412 and ADG413 are monolithic CMOS
devices comprising four independently selectable switches. T hey
are designed on an enhanced LC2MOS process which provides
low power dissipation yet gives high switching speed and low on
resistance.
D4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
P RO D UCT H IGH LIGH TS
1. Extended Signal Range
T he on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion making the parts ideally suited for portable and battery
powered instruments.
T he ADG411, ADG412 and ADG413 are fabricated on an
enhanced LC 2MOS, giving an increased signal range which
extends fully to the supply rails.
2. Ultralow Power Dissipation
3. Low RON
T he ADG411, ADG412 and ADG413 contain four indepen-
dent SPST switches. T he ADG411 and ADG412 differ only in
that the digital control logic is inverted. T he ADG411 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG412. T he ADG413
has two switches with digital control logic similar to that of the
ADG411 while the logic is inverted on the other two switches.
4. Break-Before-Make Switching
T his prevents channel shorting when the switches are
configured as a multiplexer.
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG411, ADG412 and ADG413 can be operated from a
single rail power supply. T he parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.
Each switch conducts equally well in both directions when ON
and each has an input signal range that extends to the supplies.
In the OFF condition, signal levels up to the supplies are
blocked. All switches exhibit break-before-make switching ac-
tion for use in multiplexer applications. Inherent in the design is
low charge injection for minimum transients when switching the
digital inputs.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
1
ADG411/ADG412/ADG413–SPECIFICATIONS
(V = +15 V ؎ 10%, V = –15 V ؎ 10%, V = +5 V ؎ 10%, GND = 0 V, unless otherwise noted)
Dual Supply
DD
SS
L
B Version
T Version
–55؇C to
–40؇C to
P aram eter
+25؇C
+85؇C
+25؇C
+125؇C
Units
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
RON
VDD to VSS
45
VDD to VSS
45
V
25
35
25
35
Ω typ
Ω max
VD = ±8.5 V, IS = –10 mA;
VDD = +13.5 V, VSS = –13.5 V
LEAKAGE CURRENT S
VDD = +16.5 V, VSS = –16.5 V
Source OFF Leakage IS (OFF)
±0.1
±0.25
±0.1
±0.25
±0.1
±0.4
±0.1
±0.25
±0.1
±0.25
±0.1
±0.4
nA typ
nA max T est Circuit 2
nA typ
nA max T est Circuit 2
nA typ
nA max T est Circuit 3
VD = ±15.5 V, VS = ϯ15.5 V;
±5
±20
±20
±40
Drain OFF Leakage ID (OFF)
VD = ±15.5 V, VS = ϯ15.5 V;
±5
Channel ON Leakage ID, IS (ON)
VD = VS = ±15.5 V;
±10
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
0.005
0.005
µA typ
VIN = VINL or VINH
±0.5
±0.5
µA max
DYNAMIC CHARACT ERIST ICS2
tON
110
100
110
100
25
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, C L = 35 pF;
VS = ±10 V; T est Circuit 4
RL = 300 Ω, C L = 35 pF;
VS = ±10 V; T est Circuit 4
RL = 300 Ω, C L = 35 pF;
VS1 = VS2 = +10 V;
T est Circuit 5
175
145
175
145
tOFF
Break-Before-Make T ime Delay, tD 25
(ADG413 Only)
Charge Injection
5
5
pC typ
dB typ
dB typ
VS = 0 V, RS = 0 Ω, CL = 10 nF;
T est Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 8
OFF Isolation
68
85
68
85
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENT S
VDD = +16.5 V, VSS = –16.5 V
Digital Inputs = 0 V or 5 V
IDD
ISS
IL
0.0001
1
0.0001
1
0.0001
1
0.0001
1
0.0001
1
0.0001
1
µA typ
µA max
µA typ
µA max
µA typ
µA max
5
5
5
5
5
5
NOT ES
1T emperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. A
ADG411/ADG412/ADG413
(V = +12 V ؎ 10%, V = 0 V, V = +5 V ؎ 10%, GND = 0 V, unless otherwise noted)
Single Supply
DD
SS
L
B Version
T Version
–55؇C to
–40؇C to
+85؇C
P aram eter
+25؇C
+25؇C
+125؇C
Units
Test Conditions/Com m ents
ANALOG SIGNAL RANGE
RON
0 V to VDD
100
0 V to VDD
V
40
80
40
80
Ω typ
Ω max
0 < VD = 8.5 V, IS = –10 mA;
VDD = +10.8 V
100
LEAKAGE CURRENT S
VDD = +13.2 V
Source OFF Leakage IS (OFF)
±0.1
±0.25
±0.1
±0.25
±0.1
±0.4
±0.1
±0.25
±0.1
±0.25
±0.1
±0.4
nA typ
nA max T est Circuit 2
nA typ
nA max T est Circuit 2
nA typ
nA max T est Circuit 3
VD = 12.2/1 V, VS = 1/12.2 V;
±5
±20
±20
±40
Drain OFF Leakage ID (OFF)
VD = 12.2/1 V, VS = 1/12.2 V;
±5
Channel ON Leakage ID, IS (ON)
VD = VS = +12.2 V/+1 V;
±10
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
0.005
0.005
µA typ
VIN = VINL or VINH
±0.5
±0.5
µA max
DYNAMIC CHARACT ERIST ICS2
tON
175
95
175
95
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, C L = 35 pF;
VS = +8 V; T est Circuit 4
RL = 300 Ω, C L = 35 pF;
VS = +8 V; T est Circuit 4
RL = 300 Ω, C L = 35 pF;
VS1 = VS2 = +10 V;
T est Circuit 5
250
125
250
125
tOFF
Break-Before-Make T ime Delay, tD 25
(ADG413 Only)
25
Charge Injection
25
68
85
25
68
85
pC typ
dB typ
dB typ
VS = 0 V, RS = 0 Ω, CL = 10 nF;
T est Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 8
OFF Isolation
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENT S
VDD = +13.2 V
Digital Inputs = 0 V or 5 V
IDD
IL
0.0001
1
0.0001
1
0.0001
1
0.0001
1
µA typ
µA max
µA typ
5
5
5
5
µA max VL = +5.25 V
NOT ES
1T emperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
Truth Table (AD G411/AD G412)
Truth Table (AD G413)
AD G411 In
AD G412 In
Switch Condition
Logic
Switch 1, 4
Switch 2, 3
0
1
1
0
ON
OFF
0
1
OFF
ON
ON
OFF
REV. A
–3–
ADG411/ADG412/ADG413
ABSO LUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
TERMINO LO GY
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog, Digital Inputs2 . . . . . . . . . . . VSS –2 V to VDD +2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
VDD
VSS
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to GND.
VL
Logic power supply (+5 V).
GND
Ground (0 V) reference.
S
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
D
Operating T emperature Range
IN
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead T emperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead T emperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W
T SSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 115°C/W
θJC T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . 35°C/W
Lead T emperature, Soldering
RON
Ohmic resistance between D and S.
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D, S.
“OFF” switch source capacitance.
“OFF” switch drain capacitance.
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
CS (OFF)
CD (OFF)
CD, CS (ON) “ON” switch capacitance.
tON
tOFF
tD
Delay between applying the digital control
input and the output switching on.
Delay between applying the digital control
input and the output switching off.
“OFF” time or “ON” time measured between
the 90% points of both switches, when switching
from one address state to another.
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” switch.
Charge
Injection
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
O RD ERING GUID E
P IN CO NFIGURATIO N
(D IP /SO IC)
Modell
Tem perature Range
P ackage O ption2
ADG411BN
ADG411BR
ADG411T Q
ADG411BRU
ADG412BN
ADG412BR
ADG412T Q
ADG413BN
ADG413BR
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
Q-16
RU-16
N-16
R-16A
Q-16
IN1
D1
S1
IN2
D2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADG411
ADG412
ADG413
TOP VIEW
(Not to Scale)
V
V
V
SS
DD
L
GND
S4
D4
S3
N-16
R-16A
D3
IN3
IN4
NOT ES
1T o order MIL-ST D-883, Class B processed parts, add /883B to T grade part
numbers.
2N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); RU= T hin Shrink Small
Outline (T SSOP); Q = Cerdip.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG411/ADG412/ADG413 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
ADG411/ADG412/ADG413
Typical Performance Graphs
50
40
30
20
50
T
V
= +25؇C
= +5V
T
V
= +25؇C
= +5V
A
A
L
L
40
V
V
= +5V
= 0V
DD
SS
V
V
= +5V
= –5V
DD
SS
30
20
V
V
= +10V
DD
SS
V
V
= +12V
= 0V
DD
SS
V
V
= +10V
= –10V
DD
SS
= 0V
V
V
= +12V
= –12V
DD
SS
10
0
10
0
V
V
= +15V
= 0V
V
V
= +15V
= –15V
DD
SS
DD
SS
0
5
10
15
20
–20
–10
0
10
20
V
OR V – DRAIN OR SOURCE VOLTAGE – V
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
S
D
Figure 4. On Resistance as a Function of VD (VS ) Single
Supply
Figure 1. On Resistance as a Function of VD (VS) Dual
Supplies
50
100mA
V
V
V
= +15V
= –15V
= +5V
V
V
V
= +15V
= –15V
= +5V
4 SW
1 SW
DD
SS
DD
SS
10mA
1mA
L
40
30
20
L
I+, I–
100A
10A
+125؇C
+85؇C
+25؇C
I
L
10
0
1A
100nA
–20
–10
0
10
20
100
1k
10k
100k
1M
10M
10
V
OR V – DRAIN OR SOURCE VOLTAGE – V
FREQUENCY – Hz
D
S
Figure 2. On Resistance as a Function of VD (VS) for
Different Tem peratures
Figure 5. Supply Current vs. Input Switching Frequency
0.04
10
V
V
= +15V
= –15V
DD
SS
V
V
V
= +15V
= –15V
= +5V
DD
SS
T
= +25؇C
= +5V
A
I
(ON)
D
L
V
L
0.02
1
0.1
V
V
= ؎15V
= ؎15V
I (OFF)
S
S
D
I
(OFF)
S
0.00
–0.02
–0.04
I
(OFF)
D
I
(OFF)
D
0.01
0.001
I
(ON)
D
–20
–10
0
10
20
100
1k
10k
100k
1M
10M
10M
V
OR V – DRAIN OR SOURCE VOLTAGE – V
FREQUENCY – Hz
D
S
Figure 3. Leakage Currents as a Function of Tem perature
Figure 6. Leakage Currents as a Function of VD (VS)
REV. A
–5–
ADG411/ADG412/ADG413
120
AP P LICATIO N
V
V
V
= +15V
= –15V
= +5V
DD
SS
Figure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal V . In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor CH.
L
100
80
IN
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifica-
tions. T he droop rate is further minimized by the use of a poly-
styrene hold capacitor. T he droop rate for the circuit shown is
typically 30 µV/µs.
60
40
100
1k
10k
100k
1M
10M
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. T his compensation network also re-
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the ±10 V input
range. Both the acquisition and settling times are 850 ns.
FREQUENCY – Hz
Figure 7. Off Isolation vs. Frequency
110
V
V
V
= +15V
= –15V
= +5V
DD
SS
100
90
80
70
60
L
+15V
+5V
2200pF
+15V
AD711
–15V
SW1
SW2
+15V
S
S
D
D
C
C
R
C
V
V
OUT
1000pF
IN
75⍀
AD845
C
H
2200pF
–15V
100
1k
10k
100k
1M
10M
ADG411
ADG412
ADG413
FREQUENCY – Hz
Figure 8. Crosstalk vs. Frequency
–15V
Figure 9. Fast, Accurate Sam ple-and-Hold
–6–
REV. A
ADG411/ADG412/ADG413
Test Circuits
I
DS
V1
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
D
S
S
D
S
D
S
D
V
V
V
D
V
V
S
S
D
S
R
= V1/I
DS
ON
Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
+15V
0.1F
+5V
0.1F
3V
V
V
L
DD
V
V
50%
50%
50%
50%
ADG411
IN
S
D
V
OUT
3V
ADG412
R
C
L
IN
L
V
S
35pF
300⍀
IN
90%
90%
V
V
OUT
GND
SS
0.1F
–15V
tON
tOFF
Test Circuit 4. Switching Tim es
+15V
+5V
0.1F
0.1F
3V
V
IN
50%
50%
V
V
L
DD
0V
0V
S1
S2
D1
D2
V
V
S1
OUT1
90%
90%
V
V
OUT1
R
C
L1
35pF
L1
V
OUT2
300⍀
V
S2
V
R
C
L2
35pF
IN1, IN2
L2
300⍀
90%
V
90%
GND
SS
OUT2
IN
0V
tD
tD
0.1F
–15V
Test Circuit 5. Break-Before-Make Tim e Delay
+15V
+5V
3V
V
V
DD
L
V
R
OUT
S
S
D
V
IN
C
10nF
L
V
S
IN
V
OUT
⌬V
OUT
V
GND
SS
Q
= C
؋
⌬V L OUT
INJ
–15V
Test Circuit 6. Charge Injection
REV. A
–7–
ADG411/ADG412/ADG413
+15V
0.1F
+5V
+15V
+5V
0.1F
0.1F
0.1F
V
V
L
DD
V
V
L
DD
50⍀
S
D
S
D
V
OUT
R
L
V
IN1
50⍀
V
S
V
IN2
IN
V
V
S
IN
D
S
V
OUT
NC
V
GND
SS
V
GND
R
SS
L
50⍀
0.1F
–15V
CHANNEL TO CHANNEL
CROSSTALK = 20
؋
LOG V /V 0.1F
–15V
S
OUT
Test Circuit 7. Off Isolation
Test Circuit 8. Channel-to-Channel Crosstalk
MECH ANICAL INFO RMATIO N
D imensions are shown in inches and (mm).
16-Lead Cerdip
(Q-16)
16-Lead SO IC
(R-16A)
0.005 (0.13) MIN
16
0.080 (2.03) MAX
0.3937 (10.00)
0.3859 (9.80)
9
0.310 (7.87)
16
1
9
8
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.220 (5.59)
1
8
0.320 (8.13)
0.290 (7.37)
PIN 1
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45؇
0.0098 (0.25)
0.0040 (0.10)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
8؇
0؇
0.015 (0.38)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
15°
0°
0.008 (0.20)
16-Lead TSSO P
(RU-16)
16-Lead P lastic D IP (Narrow)
(N-16)
0.840 (21.34)
0.745 (18.92)
0.201 (5.10)
0.193 (4.90)
16
1
9
0.280 (7.11)
16
0.240 (6.10)
8
9
8
0.325 (8.26)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
1
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
PIN 1
PLANE
0.045 (1.15)
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0256 0.0118 (0.30)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
(0.65)
0.0075 (0.19)
BSC
–8–
REV. A
相关型号：
©2020 ICPDF网 联系我们和版权申明