ADG444 [ADI]
LC2MOS Quad SPST Switches; LC2MOS QUAD SPST开关型号: | ADG444 |
厂家: | ADI |
描述: | LC2MOS Quad SPST Switches |
文件: | 总9页 (文件大小:326K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LC2MOS Quad SPST Switches
a
ADG441/ADG442/ADG444
FEATURES
44 V Supply Maximum Ratings
FUNCTIONAL BLOCK DIAGRAMS
V
SS to VDD Analog Signal Range
Low On Resistance (< 70 Ω)
Low ∆RON (9 Ω max)
Low RON Match (3 Ω max)
Low Power Dissipation
Fast Switching Times
tON < 110 ns
S1
S1
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
D2
S3
D2
S3
ADG441
ADG444
ADG442
tOFF < 60 ns
Low Leakage Currents ( 3 nA max)
Low Charge Injection (6 pC max)
Break-Before-Make Switching Action
Latch-Up Proof
D3
S4
D3
S4
Plug-In Upgrade for
D4
D4
DG201A/ADG201A, DG202A/ADG202A,
DG211/ADG211A
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Plug in Replacement for DG441/DG442/DG444
APPLICATIONS
Each switch conducts equally well in both directions when ON
and has an input signal range that extends to the power sup-
plies. In the OFF condition, signal levels up to the supplies are
blocked. All switches exhibit break-before-make switching action
for use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
GENERAL DESCRIPTION
The ADG441, ADG442 and ADG444 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC2MOS process that provides
low power dissipation yet gives high switching speed and low on
resistance.
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG441/ADG442/ADG444 are fabricated on an en-
hanced LC2MOS, trench-isolated process, giving an in-
creased signal range that extends to the supply rails.
The on resistance profile is very flat over the full analog input
range ensuring good linearity and low distortion when switching
audio signals. High switching speed also makes the parts suit-
able for video signal switching. CMOS construction ensures
ultralow power dissipation making the parts ideally suited for
portable and battery powered instruments.
2. Low Power Dissipation
3. Low RON
4. Trench Isolation Guards Against Latch Up
A dielectric trench separates the P and N channel transistors
thereby preventing latch up even under severe overvoltage
conditions.
The ADG441, ADG442 and ADG444 contain four indepen-
dent SPST switches. Each switch of the ADG441 and ADG444
turns on when a logic low is applied to the appropriate control
input. The ADG442 switches are turned on with a logic high on
the appropriate control input. The ADG441 and ADG444
switches differ in that the ADG444 requires a 5 V logic power
supply which is applied to the VL pin. The ADG441 and
ADG442 do not have a VL pin, the logic power supply being
generated internally by an on-chip voltage generator.
5. Break-Before-Make Switching
This prevents channel shorting when the switches are config-
ured as a multiplexer.
6. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG441/ADG442/ADG444 can be operated from a single
rail power supply. The parts are fully specified with a single
+12 V power supply.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADG441/ADG442/ADG444–SPECIFICATIONS1
Dual Supply (VDD = +15 V ± 10%, VSS = –15 V ± 10%, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted)
B Version
T Version
–55°C to
–40°C to
+85°C
Parameter
+25°C
+25°C
+125°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
VSS to VDD
VSS to VDD
V
40
70
40
70
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VD = ±8.5 V, IS = –10 mA
VDD = +13.5 V, VSS = –13.5 V
–8.5 V ≤ VD ≤ +8.5 V
85
4
9
1
3
85
4
9
1
3
∆RON
RON Match
VD = 0 V, IS = –10 mA
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = +16.5 V, VSS = –16.5 V
VD = ±15.5 V, VS = ϯ15.5 V;
Test Circuit 2
VD = ±15.5 V, VS = ϯ15.5 V;
Test Circuit 2
VS = VD = ±15.5 V;
Test Circuit 3
±0.01
±0.5
±0.01
±0.5
±0.08
±0.5
±0.01
±0.5
±0.01
±0.5
±0.08
±0.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
±3
±3
±3
±20
±20
±40
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
±0.00001
±0.5
±0.00001
±0.5
µA typ
µA max
VIN = VINL or VINH
DYNAMIC CHARACTERISTICS2
tON
85
110
45
60
30
1
85
110
45
60
30
1
ns typ
ns max
ns typ
ns max
ns typ
pC typ
pC max
RL = 1 kΩ, CL = 35 pF;
VS = ±10 V; Test Circuit 4
RL = 1 kΩ, CL = 35 pF;
VS = ±10 V; Test Circuit 4
RL = 1 kΩ, CL = 35 pF;
VS = 0 V, RS = 0 Ω, CL= 1 nF;
VDD = +15 V, VSS = –15 V;
Test Circuit 5
170
80
170
80
tOFF
tOPEN
Charge Injection
6
6
OFF Isolation
60
60
dB typ
dB typ
RL = 50 Ω, CL = 5 pF;
f = 1 MHz; Test Circuit 6
RL = 50 Ω, CL = 5 pF;
f = 1 MHz; Test Circuit 7
f = 1 MHz
f = 1 MHz
f = 1 MHz
Channel-to-Channel Crosstalk
100
100
CS (OFF)
CD (OFF)
CD, CS (ON)
4
4
16
4
4
16
pF typ
pF typ
pF typ
POWER REQUIREMENTS
IDD
V
DD = +16.5 V, VSS = –16.5 V
Digital Inputs = 0 V or 5 V
ADG441/ADG442
ADG444
80
80
µA max
µA typ
0.001
0.001
1
2.5
2.5
2.5
1
2.5
2.5
2.5
µA max
µA typ
µA max
µA typ
ISS
0.0001
1
0.001
1
0.0001
1
0.001
1
IL (ADG444 Only)
VL = +5.5 V
µA max
NOTES
1Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG441/ADG442/ADG444
Single Supply
(VDD = +12 V ± 10%, VSS = 0 V, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted)
B Version
–40°C to
T Version
–55°C to
Parameter
+25°C
+85°C
+25°C
+125°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
0 to VDD
0 to VDD
V
70
110
70
110
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VD = +3 V, +8 V, IS = –10 mA;
VDD = +10.8 V
+3 V ≤ VD ≤ +8 V
130
4
9
1
3
130
4
9
1
3
∆RON
RON Match
VD = 6 V, IS = –10 mA
LEAKAGE CURRENT
Source OFF Leakage IS (OFF)
VDD = +13.2 V
VD = 12.2 V/1 V, VS = 1 V/12.2 V;
Test Circuit 2
VD = 12.2 V/1 V, VS = 1 V/12.2 V;
Test Circuit 2
VS = VD = 12.2 V/1 V;
Test Circuit 3
±0.01
±0.5
±0.01
±0.5
±0.08
±0.5
±0.01
±0.5
±0.01
±0.5
±0.08
±0.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
±3
±3
±3
±20
±20
±40
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
±0.00001
±0.5
±0.00001
±0.5
µA typ
µA max
VIN = VINL or VINH
DYNAMIC CHARACTERISTICS2
tON
105
150
40
60
50
2
105
150
40
60
50
2
ns typ
ns max
ns typ
ns max
ns typ
pC typ
pC max
RL = 1 kΩ, CL = 35 pF;
VS = +8 V; Test Circuit 4
RL = 1 kΩ, CL = 35 pF;
VS = +8 V; Test Circuit 4
RL = 1 kΩ, CL = 35 pF;
VS = 6 V, RS = 0 Ω, CL = 1 nF;
VDD = +12 V, VSS = 0 V;
Test Circuit 5
220
100
220
100
tOFF
tOPEN
Charge Injection
6
6
OFF Isolation
60
60
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk
100
100
CS (OFF)
CD (OFF)
CD, CS (ON)
7
10
16
7
10
16
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +13.2 V
Digital Inputs = 0 V or 5 V
ADG441/ADG442
ADG444
80
80
µA max
µA typ
µA max
µA typ
µA max
0.001
1
0.001
1
0.001
1
0.001
1
2.5
2.5
2.5
2.5
IL (ADG444 Only)
NOTES
VL = +5.5 V
1Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
ORDERING GUIDE
Temperature Range
Specifications subject to change without notice.
Model1
Package Option2
Table I. Truth Table
ADG441BN
ADG441BR
ADG441TQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16A
Q-16
ADG441/ADG444
IN
ADG442
IN
Switch
Condition
0
1
1
0
ON
OFF
ADG442BN
ADG442BR
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
ADG444BN
ADG444BR
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
N
OTES
1To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.
2N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip.
REV. 0
–3–
ADG441/ADG442/ADG444
ABSOLUTE MAXIMUM RATINGS1
TERMINOLOGY
(TA = +25°C unless otherwise noted)
VDD
VSS
Most Positive Power Supply Potential.
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog, Digital Inputs2 . . . . . . . . . . . . VSS – 2 V to VDD + 2 V
or 30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Most Negative Power Supply Potential in dual
supplies. In single supply applications, it may be
connected to ground.
VL
Logic Power Supply (+5 V).
GND
Ground (0 V) Reference.
S
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
D
IN
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 177°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
RON
Ohmic resistance between D and S.
Difference between the RON of any two channels.
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D, S.
RON Match
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
CS (OFF)
CD (OFF)
“OFF” Switch Source Capacitance.
“OFF” Switch Drain Capacitance.
CD, CS (ON) “ON” Switch Capacitance.
tON
Delay between applying the digital control
input and the output switching on.
Delay between applying the digital control
input and the output switching off.
Break-Before-Make Delay when switches are
configured as a multiplexer.
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
tOFF
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
tOPEN
Crosstalk
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one absolute maximum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
Charge
A measure of the glitch impulse transferred from
the digital input to the analog output during
switching.
Injection
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ADG441/ADG442 PIN CONFIGURATION (DIP/SOIC)
ADG444 PIN CONFIGURATION (DIP/SOIC)
IN1
D1
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
13 VDD
12 VL
11 S3
10 D3
IN1
D1
S1
1
2
3
4
5
6
7
8
16 IN2
15 D2
S1
ADG441 14 S2
ADG442
ADG444
VSS
GND
S4
V
13 V
DD
SS
GND
S4
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
12 NC
11 S3
10 D3
D4
D4
IN4
9
IN3
IN4
9
IN3
NC = NO CONNECT
–4–
REV. 0
ADG441/ADG442/ADG444
TRENCH ISOLATION
NMOS
PMOS
In the ADG441, ADG442 and ADG444, an insulating oxide
layer (trench) is placed between the NMOS and the PMOS
transistors of each CMOS switch. Parasitic junctions, which oc-
cur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
LOCOS
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a sig-
nificant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.
P-WELL
N-WELL
TRENCH
Trench isolation also leads to lower leakage currents. The
ADG441, ADG442 and ADG444 have a leakage current
of 0.5 nA as compared with a leakage current of several
nanoamperes in non-trench isolated switches. Leakage current is
an important parameter in sample-and-hold circuits, this current
being responsible for the discharge of the holding capacitor with
time causing droop. The ADG441/ADG442/ADG444’s low
leakage current, along with its fast switching speeds, make it
suitable for fast and accurate sample-and-hold circuits.
BURIED OXIDE LAYER
SUBSTRATE (BACK GATE)
Figure 1. Trench Isolation
Typical Performance Characteristics
170
150
130
110
90
100
V
V
= +5V
= 0V
DD
SS
T
= +25°C
A
V
V
= +5V
= –5V
DD
SS
T
= +25°C
A
80
60
40
20
V
V
= +12V
= 0V
DD
SS
V
V
= +12V
= –12V
DD
V
V
= +10V
= 0V
DD
SS
SS
V
V
= +10V
= –10V
DD
SS
70
50
V
V
= +15V
= 0V
DD
SS
30
V
V
= +15V
DD
= –15V
SS
10
0
3
6
9
12
15
–15
–10
–5
0
5
10
15
V
(V ) – Volts
S
V
(V
) – Volts
S
D
D
Figure 2. RON as a Function of VD (VS): Dual Supply
Figure 3. RON as a Function of VD (VS): Single Supply
REV. 0
–5–
ADG441/ADG442/ADG444
100
120
100
80
VDD = +12V
SS = 0V
V
V
= +15V
= –15V
DD
SS
V
80
60
+125°C
+125°C
+85°C
60
+25°C
+85°C
40
20
40
+25°C
20
–15
–10
–5
0
5
10
15
0
2
4
6
8
10
12
V
D (VS) – Volts
V
(V ) – Volts
S
D
Figure 4. RON as a Function of VD (VS) for Different
Temperatures
Figure 7. RON as a Function of VD (VS) for Different
Temperatures
0.010
0.02
VDD = +12V
VDD = +15V
VSS = 0V
VSS = –15V
ID (OFF)
°
°
TA = +25 C
ID (ON)
TA = +25 C
0.005
0.000
0.01
IS (OFF)
ID (ON)
0.00
IS (OFF)
ID (OFF)
–0.005
–0.010
–0.01
–0.02
0
2
4
6
8
10
12
–15
–10
–5
0
5
10
15
VS, VD – Volts
VS, VD – Volts
Figure 5. Leakage Currents as a Function of VS (VD)
Figure 8. Leakage Currents as a Function of VS (VD)
20
120
V
V
= +15V
= –15V
DD
SS
C
= 1nF
L
110
100
90
10
0
CROSSTALK
V
V
= +12V
= 0V
V
V
= +15V
= –15V
DD
SS
DD
SS
80
OFF ISOLATION
70
–10
–20
60
50
1k
–15 –12
–9
–6
–3
0
3
6
9
12
15
10k
100k
1M
10M
V
– Volts
FREQUENCY – Hz
S
Figure 6. Crosstalk and Off Isolation vs. Frequency
Figure 9. Charge Injection vs. Source Voltage
–6–
REV. 0
ADG441/ADG442/ADG444
120
100
80
160
140
120
100
80
V
= +8V
IN
VIN = +8V
tON
tON
60
60
tOFF
40
tOFF
40
±10
20
±12
±14
±16
±18
±20
8
10
12
14
16
18
20
SUPPLY VOLTAGE – Volts
SUPPLY VOLTAGE – Volts
Figure 10. Switching Time vs. Bipolar Supply
Figure 11. Switching Time vs. Single Supply
Test Circuits
IDS
V1
I
(ON)
I
(OFF)
A
I
(OFF)
A
D
S
D
S
D
S
D
S
D
A
VS
V
V
S
D
V
V
D
S
RON = V1/IDS
Test Circuit 2. Off Leakage
Test Circuit 1. On Resistance
Test Circuit 3. On Leakage
+15V
+5V
3V
0.1µF
0.1µF
V
IN
50%
50%
50%
50%
V
V
L
DD
ADG441/ADG444
S
D
V
OUT
3V
R
1kΩ
C
35pF
L
L
V
S
V
IN
IN
ADG442
V
GND
SS
90%
90%
V
OUT
0.1µF
–15V
tON
tOFF
Test Circuit 4. Switching Times
REV. 0
–7–
ADG441/ADG442/ADG444
+15V
+5V
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
V
V
L
DD
R
S
S
D
Plastic DIP (N-16)
V
OUT
C
1nF
L
V
S
IN
16
1
9
0.25 0.31
(6.35) (7.87)
PIN 1
V
GND
SS
8
0.87 (22.1) MAX
0.035
–15V
0.18
(4.57)
MAX
(0.89)
3V
0.125
(3.18)
MIN
0.011
(0.28)
0.18 (4.57)
V
IN
0.3 (7.62)
SEATING
PLANE
0.018 (0.46)
0.033 (0.84)
0.1 (2.54)
BSC
V
OUT
∆V
OUT
Small Outline IC (R-16A)
Q
= C × ∆V
L OUT
INJ
Test Circuit 5. Charge Injection
0.2440 (6.20)
16
9
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
+15V
+5V
0.1µF
0.1µF
1
8
V
V
L
DD
0.0196 (0.50)
0.0099 (0.25)
0.3937 (10.00)
0.3859 (9.80)
× 45°
S
D
V
OUT
0° – 8°
0.0688 (1.75)
0.0532 (1.35)
R
L
50Ω
IN
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
V
S
0.0500 (1.27)
0.0160 (0.41)
V
GND
SS
SEATING
PLANE
V
IN
0.1µF
–15V
Cerdip (Q-16)
9
Test Circuit 6. Off Isolation
16
0.310 (7.87)
PIN 1
0.220 (5.59)
+15V
+5V
1
8
0.1µF
0.1µF
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
V
V
L
DD
0.200
(5.08)
MAX
50Ω
S
D
0.150
(3.81)
MIN
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
V
IN1
V
S
0.070 (1.78)
0.30 (0.76)
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
V
IN2
S
V
NC
OUT
V
R
GND
SS
L
50Ω
0.1µF
–15V
CHANNEL-TO-CHANNEL CROSSTALK = 20 × LOG V /V
S
OUT
Test Circuit 7. Channel-to-Channel Crosstalk
–8–
REV. 0
ADG441/ADG442/ADG444
FOR CATALOG
ORDERING GUIDE
Temperature Range
Model1
Package Option2
ADG441BN
ADG441BR
ADG441TQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16A
Q-16
ADG442BN
ADG442BR
ADG444BN
ADG444BR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
N-16
R-16A
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.
2N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip. For outline
information see Package Information section.
REV. 0
–9–
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