ADG452BRZ [ADI]
LC2MOS 5Ω RON SPST Switch;
| 型号： | ADG452BRZ |
| 厂家： | 
ADI |
| 描述： | LC2MOS 5Ω RON SPST Switch 光电二极管 输出元件 |
| 文件： | 总16页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
5 Ω RON SPST Switches
ADG451/ADG452/ADG453
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
S1
Low on resistance (4 Ω)
On resistance flatness (0.2 Ω)
44 V supply maximum ratings
1ꢀ V analog signal range
Fully specified at ꢀ V, 12 V, 1ꢀ V
Ultralow power dissipation (18 μW)
ESD 2 kV
IN1
D1
S2
IN2
D2
S3
ADG451
IN3
D3
S4
IN4
Continuous current (100 mA)
Fast switching times
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
tON 70 ns
tOFF 60 ns
Figure 1. ADG451
S1
TTL-/CMOS-compatible
Pin-compatible upgrade for ADG411/ADG412/ADG413
and ADG431/ADG432/ADG433
IN1
D1
S2
IN2
D2
S3
APPLICATIONS
ADG452
IN3
Relay replacement
D3
S4
Audio and video switching
Automatic test equipment
Precision data acquisition
Battery-powered systems
Sample-and-hold systems
Communication systems
PBX, PABX systems
IN4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 2. ADG452
S1
IN1
D1
S2
Avionics
IN2
GENERAL DESCRIPTION
D2
S3
ADG453
IN3
The ADG451/ADG452/ADG453 are monolithic CMOS
devices comprising four independently selectable switches.
They are designed on an enhanced LC2MOS process that
provides low power dissipation yet gives high switching
speed and low on resistance.
D3
S4
IN4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 3. ADG453
The on resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed, coupled with high
signal bandwidth, makes the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion, making the parts ideally suited for portable and battery-
powered instruments.
The ADG453 has two switches with digital control logic similar
to that of the ADG451, while the logic is inverted on the other
two switches.
Each switch conducts equally well in both directions when on,
and each has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
The ADG451/ADG452/ADG453 contain four independent,
single-pole/single-throw (SPST) switches. The ADG451 and
ADG452 differ only in that the digital control logic is inverted. The
ADG451 switches are turned on with a logic low on the appropriate
control input, while a logic high is required for the ADG452.
The ADG453 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG451/ADG452/ADG453
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Typical Performance Characteristics ..............................................9
Terminology.................................................................................... 11
Applications..................................................................................... 12
Test Circuits..................................................................................... 13
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
15 V Dual Supply.......................................................................... 4
12 V Single Supply........................................................................ 5
5 V Dual Supply............................................................................ 6
REVISION HISTORY
10/06—Rev. B to Rev. C
2/98—Rev. 0 to Rev. A
Changes to Table 4............................................................................ 9
Changes to Ordering Guide .......................................................... 18
10/97—Revision 0: Initial Version
12/04—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Specifications Section.................................................. 3
Changes to Absolute Maximum Ratings Section......................... 8
Changes to Pin Configuration and Function
Descriptions Section ........................................................................ 9
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 17
Rev. C | Page 2 of 16
ADG451/ADG452/ADG453
PRODUCT HIGHLIGHTS
1. Low RON (5 Ω maximum).
5. Single-Supply Operation.
For applications in which the analog signal is unipolar, the
ADG451/ADG452/ADG453 can be operated from a single
rail power supply. The parts are fully specified with a single
12 V power supply and remain functional with single supplies
as low as 5.0 V.
2. Ultralow Power Dissipation.
3. Extended Signal Range.
The ADG451/ADG452/ADG453 are fabricated on an enhanced
LC2MOS process, giving an increased signal range that fully
extends to the supply rails.
6. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG451/ADG452/ADG453 can be operated from a dual
power supply ranging from 4.5 V to 20 V.
4. Break-Before-Make Switching.
This prevents channel shorting when the switches are
configured as a multiplexer (ADG453 only.)
Rev. C | Page 3 of 16
ADG451/ADG452/ADG453
SPECIFICATIONS
1ꢀ V DUAL SUPPLY
VDD = 15 V, VSS = −15 V, VL = 5 V, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version1
Parameter
2ꢀ°C
TMIN to TMAX Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VSS to VDD
V
4
5
0.1
0.5
0.2
0.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VD = −10 V to +10 V, IS = −10 mA
VD = 10 V, IS = −10 mA
7
On Resistance Match Between Channels (ΔRON)
0.5
0.5
On Resistance Flatness (RFLAT(ON)
)
VD = −5 V, 0 V, +5 V, IS = −10 mA
LEAKAGE CURRENTS2
Source Off Leakage, IS (OFF)
0.02
0.5
0.02
0.5
0.04
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 10 V, VS = 10 V; see Figure 17
VD = 10 V, VS = 10 V; see Figure 17
VD = VS = 10 V; see Figure 18
2.5
2.5
5
Drain Off Leakage, ID (OFF)
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.4
0.8
V min
V max
μA typ
μA max
0.005
VIN = VINL or VINH; all others = 2.4 V or 0.8 V, respectively
0.5
DYNAMIC CHARACTERISTICS3
tON
70
180
60
140
15
5
20
30
65
−90
37
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF, VS = 10 V; see Figure 19
RL = 300 Ω, CL = 35 pF, VS = 10 V; see Figure 19
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = +10 V; see Figure 20
VS = 0 V, RS = 0 Ω, CL = 1.0 nF; see Figure 21
220
180
5
tOFF
Break-Before-Make Time Delay, tD (ADG453 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
CD, CS (ON)
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 22
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 23
f = 1 MHz
f = 1 MHz
f = 1 MHz
37
140
POWER REQUIREMENTS
IDD
VDD = 16.5 V, VSS = −16.5 V; digital inputs = 0 V or 5 V
0.0001
0.5
0.0001
0.5
0.0001
0.5
0.0001
0.5
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
5
5
5
5
ISS
IL
3
IGND
1 Temperature range for B version is −40°C to +85°C.
2 TMAX = 70°C.
3 Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 16
ADG451/ADG452/ADG453
12 V SINGLE SUPPLY
VDD = 12 V, VSS = 0 V, VL = 5 V, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Version1
Parameter
2ꢀ°C
TMIN to TMAX Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
10
V
6
8
0.1
0.5
1.0
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VD = 0 V to +10 V, IS = −10 mA
VD = 10 V, IS = −10 mA
On Resistance Match Between Channels (ΔRON)
0.5
1.0
On Resistance Flatness (RFLAT(ON)
)
VD = 0 V, 5 V, IS = −10 mA
LEAKAGE CURRENTS2, 3
Source Off Leakage, IS (OFF)
0.02
0.5
0.02
0.5
0.04
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 0 V, 10 V, VS = 0 V, 10 V; see Figure 17
VD = 0 V, 10 V, VS = 0 V, 10 V; see Figure 17
VD = VS = 0 V, 10 V; see Figure 18
2.5
2.5
5
Drain Off Leakage, ID (OFF)
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.4
0.8
V min
V max
μA typ
μA max
0.005
VIN = VINL or VINH
0.5
DYNAMIC CHARACTERISTICS4
tON
100
220
80
160
15
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF, VS = 8 V; see Figure 19
RL = 300 Ω, CL = 35 pF, VS = 8 V; see Figure 19
260
200
tOFF
Break-Before-Make Time Delay, tD (ADG453 Only)
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 8 V;
see Figure 20
10
10
−90
60
60
10
ns min
pC typ
dB typ
pF typ
pF typ
pF typ
Charge Injection
Channel-to-Channel Crosstalk
CS (OFF)
VS = 6 V, RS = 0 Ω, CL = 1.0 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 23
f = 1 MHz
CD (OFF)
f = 1 MHz
CD, CS (ON)
100
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 13.2 V; digital inputs = 0 V or 5 V
0.0001
0.5
0.0001
0.5
0.0001
0.5
μA typ
μA max
μA typ
μA max
μA typ
μA max
5
5
5
IL
VL = 5.5 V
VL = 5.5 V
4
IGND
1 Temperature range for B version is −40°C to +85°C.
2 TMAX = 70°C.
3 Tested with dual supplies.
4 Guaranteed by design, not subject to production test.
Rev. C | Page 5 of 16
ADG451/ADG452/ADG453
ꢀ V DUAL SUPPLY
VDD = +5 V, VSS = −5 V, VL = +5 V, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version1
Parameter
2ꢀ°C
TMIN to TMAX Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VSS to VDD
15
V
7
12
Ω typ
Ω max
Ω typ
Ω max
VD = −3.5 V to +3.5 V, IS = −10 mA
VD = 3.5 V, IS = −10 mA
On Resistance Match Between Channels (ΔRON) 0.3
0.5
0.5
LEAKAGE CURRENTS2, 3
Source Off Leakage, IS (OFF)
Drain Off Leakage, ID (OFF)
Channel On Leakage, ID, IS (ON)
0.02
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5, VS = 4.5; see Figure 17
VD = 0 V, 5 V, VS = 0 V, 5 V; see Figure 17
VD = VS = 0 V, 5 V; see Figure 18
0.5
0.02
0.5
0.04
1
2.5
2.5
5
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.4
0.8
V min
V max
μA typ
μA max
0.005
VIN = VINL or VINH
0.5
DYNAMIC CHARACTERISTICS4
tON
160
220
60
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 19
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 19
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 20
300
180
5
tOFF
140
Break-Before-Make Time Delay, tD (ADG453 Only) 50
5
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
10
65
−76
48
48
VS = 0 V, RS = 0 Ω, CL = 1.0 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 22
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 23
f = 1 MHz
f = 1 MHz
f = 1 MHz
CD, CS (ON)
148
POWER REQUIREMENTS
IDD
VDD = 5.5 V; digital inputs = 0 V or 5 V
0.0001
0.5
0.0001
0.5
0.0001
0.5
0.0001
0.5
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
5
5
5
5
ISS
IL
VL = 5.5 V
VL = 5.5 V
4
IGND
1 Temperature range for B version is −40°C to +85°C.
2 TMAX = 70°C.
3 Tested with dual supplies.
4 Guaranteed by design, not subject to production test.
Rev. C | Page 6 of 16
ADG451/ADG452/ADG453
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameters
Ratings
VDD to VSS
44 V
VDD to GND
VSS to GND
VL to GND
Analog, Digital Inputs1
−0.3 V to +32 V
+0.3 V to −32 V
−0.3 V to VDD + 0.3 V
VSS − 2 V to VDD + 2 V or 30 mA,
whichever occurs first
Only one absolute maximum rating may be applied at any one
time.
Continuous Current, S or D
Peak Current, S or D (pulsed at
1 ms, 10% duty cycle maximum)
100 mA
300 mA
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
−40°C to +85°C
−65°C to +150°C
150°C
ESD CAUTION
Plastic DIP Package,
Power Dissipation
470 mW
θJA Thermal Impedance
Lead Temperature, Soldering
(10 sec)
117°C/W
260°C
SOIC Package, Power Dissipation 600 mW
θJA Thermal Impedance 77°C/W
TSSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
115°C/W
35°C/W
215°C
220°C
2 kV
ESD
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. C | Page 7 of 16
ADG451/ADG452/ADG453
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1
D1
S1
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
ADG451/
ADG452/
ADG453
TOP VIEW
V
13
12
V
V
SS
DD
L
GND
S4
D4
11 S3
10 D3
(Not to Scale)
IN4
9
IN3
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
IN1
D1
S1
Logic Control Input.
Drain Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Most Negative Power Supply Potential in Dual Supplies. In single-supply applications,
it can be connected to GND.
VSS
5
6
7
8
GND
S4
Ground (0 V) Reference.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Logic Control Input.
D4
IN4
IN3
D3
S3
VL
VDD
S2
9
Logic Control Input.
10
11
12
13
14
15
16
Drain Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Logic Power Supply (5 V).
Most Positive Power Supply Potential.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Logic Control Input.
D2
IN2
Table 6. Truth Table (ADG451/ADG452)
Table 7. Truth Table (ADG453)
ADG4ꢀ1 In
ADG4ꢀ2 In
Switch Condition
Logic
Switch 1, Switch 4
Switch 2, Switch 3
0
1
1
0
On
Off
0
1
Off
On
On
Off
Rev. C | Page 8 of 16
ADG451/ADG452/ADG453
TYPICAL PERFORMANCE CHARACTERISTICS
9
10
T
= 25°C
= 5V
V
V
V
V
V
= +15V
= –15V
= +5V
= +15V
= –15V
A
DD
SS
V
L
8
7
6
5
4
3
2
1
0
L
D
S
V
V
= +5V
= –5V
DD
SS
1
V
= +13.5V
= –13.5V
DD
I
(ON)
D
V
SS
0.1
I
(OFF)
D
V
V
= +15V
= –15V
DD
SS
V
V
= +16.5V
= –16.5V
DD
SS
I
(OFF)
45
S
0.01
25
35
55
65
75
85
TEMPERATURE (°C)
V
OR V DRAIN OR SOURCE VOLTAGE (V)
S
D
Figure 5. On Resistance as a Function of VD (VS) for Various
Dual Supplies
Figure 8. Leakage Currents as a Function of Temperature
100k
10k
1k
7
V
V
V
= +15V
= –15V
= +5V
DD
SS
V
V
V
= +15V
= –15V
= +5V
DD
4SW
SS
+85°C
6
5
4
3
L
L
+25°C
–40°C
100
10
I+, I+
I
L
1
2
1SW
0.1
0.01
1
0
10
100
1k
10k
100k
1M
10M
–15
–10
–5
0
5
10
15
FREQUENCY (Hz)
V
OR V DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 6. On Resistance as a Function of VD (VS) for Different
Temperatures with Dual Supplies
Figure 9. Supply Current vs. Input Switching Frequency
16
14
12
10
8
12
11
10
9
V
V
V
= 15V
= 0V
= 5V
T
V
= 25°C
= 5V
DD
A
SS
L
V
V
= 5V
= 0V
DD
SS
L
+85°C
8
V
V
= 16.5V
= 0V
DD
SS
7
V
V
= 15V
= 0V
DD
SS
+25°C
–40°C
V
V
= 13.5V
= 0V
DD
SS
6
5
6
4
4
3
2
2
1
0
0
0
3
6
9
12
15
18
0
2
4
6
8
10
V OR V DRAIN OR SOURCE VOLTAGE (V)
D
12
14
16
V
OR V DRAIN OR SOURCE VOLTAGE (V)
D
S
S
Figure 7. On Resistance as a Function of VD (VS) for Various
Single Supplies
Figure 10. On Resistance as a Function of VD (VS) for Different
Temperatures with Single Supplies
Rev. C | Page 9 of 16
ADG451/ADG452/ADG453
0.5
120
100
80
60
40
20
0
V
V
= +15V
= –15V
= +25°C
= +5V
DD
V
V
V
= +15V
= –15V
= +5V
DD
SS
SS
0.4
0.3
T
A
L
V
L
R
= 50Ω
LOAD
0.2
I
(ON)
D
0.1
I
(OFF)
S
0
I
(OFF)
D
–0.1
–0.2
–0.3
–0.4
–0.5
–15 –12
–9
–6
–3
0
3
6
9
12
15
100
1k
10k
100k
1M
10M
100M
V
OR V DRAIN OR SOURCE VOLTAGE (V)
D
S
FREQUENCY (Hz)
Figure 11. Leakage Currents as a Function of VD (VS)
Figure 13. Crosstalk vs. Frequency
70
60
50
40
30
20
10
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
= +15V
= –15V
= +5V
V
V
V
= +15V
= –15V
= +5V
DD
DD
SS
V
SS
V
L
L
1
10
100
1
10
100
200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Off Isolation vs. Frequency
Figure 14. Frequency Response with Switch On
Rev. C | Page 10 of 16
ADG451/ADG452/ADG453
TERMINOLOGY
RON
CD (ON), CS (ON)
Ohmic resistance between D and S.
On switch capacitance.
ΔRON
tON
On resistance match between any two channels, that is, RON
maximum minus RON minimum.
Delay between applying the digital control input and the output
switching on. See Figure 19.
RFLAT(ON)
tOFF
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
Delay between applying the digital control input and the output
switching off.
tD
IS (OFF)
Off time or on time measured between the 90% points of both
switches, when switching from one address state to another. See
Figure 20.
Source leakage current with the switch off.
ID (OFF)
Drain leakage current with the switch off.
Crosstalk
A measure of unwanted signal coupled through from one
channel to another as a result of parasitic capacitance.
ID, IS (ON)
Channel leakage current with the switch on.
Off Isolation
VD (VS)
A measure of unwanted signal coupling through an off switch.
Analog voltage on Terminal D and Terminal S.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CS (OFF)
Off switch source capacitance.
CD (OFF)
Off switch drain capacitance.
Rev. C | Page 11 of 16
ADG451/ADG452/ADG453
APPLICATIONS
Figure 15 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer, and the output operational
amplifier is an AD711. During track mode, SW1 is closed, and
the output, VOUT, follows the input signal, VIN. In hold mode,
SW1 is opened, and the signal is held by the hold capacitor, CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG451/ADG452/ADG453
minimize this droop due to their low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
+15V
13
+5V
12
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Because both
switches are at the same potential, they have a differential effect
on the op amp, AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network, RC and CC. This compensation network reduces the
hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the 10 V input
range. Both the acquisition and settling times are 850 ns.
2200pF
+15V
SW2
S
D
C
C
AD711
–15V
CH
2200pF
V
OUT
+15V
AD845
–15V
1000pF
R
75Ω
C
V
IN
S
D
SW1
ADG451/
ADG452/
ADG453
5
4
–15V
Figure 15. Fast, Accurate Sample-and-Hold Circuit
Rev. C | Page 12 of 16
ADG451/ADG452/ADG453
TEST CIRCUITS
I
DS
V
1
I
(OFF)
A
I
(OFF)
A
S
D
I
(ON)
A
D
S
D
S
D
S
D
V
S
V
V
D
S
V
V
D
S
R
= V /I
1 DS
ON
Figure 16. On Resistance
Figure 17. Off Leakage
Figure 18. On Leakage
+15V
+5V
3V
0.1µF
0.1µF
ADG451
V
V
50%
50%
50%
50%
IN
IN
V
V
L
DD
S
D
V
OUT
3V
R
300Ω
C
L
35pF
L
V
S
ADG452
IN
90%
90%
GND
V
SS
V
V
OUT
IN
0.1µF
tON
tOFF
–15V
Figure 19. Switching Times
+15V
+5V
0.1µF
0.1µF
3V
0V
V
V
L
DD
ADG453
S1
V
50%
50%
IN
D1
V
V
V
S1
S2
OUT1
R
C
L1
300Ω
L1
35pF
S2
D2
V
OUT2
90%
90%
R
C
L2
300Ω
L2
35pF
V
V
OUT1
0V
0V
IN1, IN2
GND
V
SS
90%
90%
V
IN
OUT2
0.1µF
tD
tD
–15V
+15V
Figure 20. Break-Before-Make Time Delay
+5V
3V
V
S
V
L
R
S
D
V
V
OUT
IN
C
L
V
S
10nF
IN
V
ΔV
OUT
OUT
GND
V
DD
V
= C × ΔV
OUT
IN
L
–15V
Figure 21. Charge Injection
Rev. C | Page 13 of 16
ADG451/ADG452/ADG453
+15V
+5V
0.1µF
0.1µF
+15V
+5V
0.1µF
0.1µF
V
V
L
DD
50Ω
S
D
V
V
L
DD
S
D
V
OUT
V
IN1
V
R
S
L
V
IN2
50Ω
V
S
S
D
V
NC
OUT
R
50Ω
L
GND
V
SS
IN
GND
V
SS
V
IN
0.1µF
–15V
0.1µF
–15V
CHANNEL-TO-CHANNEL CROSSTALK = 20 × log |V /V
OUT
|
S
Figure 22. Off Isolation
Figure 23. Channel-to-Channel Crosstalk
Rev. C | Page 14 of 16
ADG451/ADG452/ADG453
OUTLINE DIMENSIONS
5.10
5.00
4.90
10.00 (0.3937)
9.80 (0.3858)
16
9
16
1
9
8
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
4.50
4.40
4.30
6.40
BSC
1
8
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
× 45°
PIN 1
0.25 (0.0098)
0.10 (0.0039)
1.20
MAX
0.20
8°
0°
0.15
0.05
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
0.75
0.60
0.45
0.09
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AC
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Figure 24. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
PLANE
SEATING
PLANE
0.008 (0.20)
0.430 (10.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.005 (0.13)
MIN
MAX
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 26. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
Rev. C | Page 15 of 16
ADG451/ADG452/ADG453
ORDERING GUIDE
Model
ADG451BN
ADG451BNZ1
Temperature Range
Package Description
Package Option
N-16
N-16
R-16
R-16
R-16
R-16
R-16
R-16
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
DIE
ADG451BR
ADG451BR-REEL
ADG451BR-REEL7
ADG451BRZ1
ADG451BRZ-REEL1
ADG451BRZ-REEL71
ADG451BRUZ1
ADG451BRUZ- REEL1
ADG451BRUZ- REEL71
ADG451BCHIPS
ADG452BN
ADG452BNZ1
ADG452BR
ADG452BR-REEL
ADG452BR-REEL7
ADG452BRZ1
ADG452BRZ-REEL1
ADG452BRZ-REEL71
ADG452BRUZ1
ADG452BRUZ-REEL1
ADG452BRUZ-REEL71
ADG453BN
RU-16
RU-16
RU-16
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
N-16
N-16
R-16
R-16
R-16
R-16
R-16
R-16
RU-16
RU-16
RU-16
N-16
N-16
R-16
R-16
R-16
R-16
R-16
ADG453BNZ1
ADG453BR
ADG453BR-REEL
ADG453BR-REEL7
ADG453BRZ1
ADG453BRZ-REEL1
ADG453BRZ-REEL71
ADG453BRUZ1
ADG453BRUZ-REEL1
ADG453BRUZ-REEL71
R-16
RU-16
RU-16
RU-16
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C0ꢀ239-0-10/06(C)
Rev. C | Page 16 of 16
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