ADG5298HFRZ [ADI]
High Temperature, High Voltage, Latch-Up Proof, 8-Channel Multiplexer;
| 型号： | ADG5298HFRZ |
| 厂家： | 
ADI |
| 描述： | High Temperature, High Voltage, Latch-Up Proof, 8-Channel Multiplexer CD 开关 输出元件 |
| 文件： | 总20页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Temperature, High Voltage,
Latch-Up Proof, 8-Channel Multiplexer
Data Sheet
ADG5298
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Extreme high temperature operation up to 210°C
Latch-up proof
JESD78D Class II rating
ADG5298
S1
Low leakage
Ultralow capacitance and charge injection
Source capacitance, off: 2.9 pF at 15 V dual supply
Drain capacitance, off: 34 pF at 15 V dual supply
Charge injection: 0.2 pC at 15 V dual supply and
+12 V single supply
D
S8
Low on resistance: 290 Ω typical for dual supply at 210°C
9 V to 22 V dual-supply operation
1-OF-8
DECODER
9 V to 40 V single-supply operation
48 V supply maximum rating
Fully specified at 15 V, 20 V, +12 V, and +36 V
A0 A1 A2 EN
Figure 1.
V
SS to VDD analog signal range
APPLICATIONS
Downhole drilling and instrumentation
Avionics
Heavy industrial
High temperature environments
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5298 is a latch-up proof, monolithic, complementary
metal-oxide semiconductor (CMOS) analog multiplexer designed
for operation up to 210°C. The ADG5298 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2.
1. Trench Isolation Guards Against Latch-Up and Minimizes
Parasitic Leakage.
A dielectric trench separates the P channel and N channel
transistors to prevent latch-up even under severe overvoltage
conditions.
An EN input enables or disables the device. When EN is disabled,
all channels switch off. The ultralow capacitance and charge
injection of this switch makes it an ideal solution for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required.
The switch conducts equally well in both directions when on,
and it has an input signal range that extends to the power supplies.
In the off condition, signal levels up to the supplies are blocked.
This multiplexer is available in a 16-lead ceramic flat package
(FLATPACK) and a 16-lead ceramic flat package with reverse
formed gullwing leads (FLATPACK_RF). Both packages are
designed for robustness at extreme temperatures and are
qualified for up to 1000 hours of operation at the maximum
temperature rating.
2. Achieved JESD78D Class II rating.
The ADG5298 was stressed to 500 mA with a 10 ms pulse
at the maximum temperature of the device (210°C).
3. 0.2 pC Charge Injection.
4. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5298 can operate from dual supplies of up to 22 ꢀ.
5. Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5298 can operate from a single rail power supply of
up to 40 ꢀ.
6. 3 ꢀ Logic-Compatible Digital Inputs.
ꢀ
INH = 2.0 ꢀ, ꢀINL = 0.8 ꢀ.
7. No Logic Power Supply (ꢀL) Required.
The ADG5298 is a member of a growing series of high temperature
qualified products offered by Analog Devices, Inc. For a complete
selection table of available high temperature products, see the
high temperature product list and qualification data available at
www.analog.com/hightemp.
Rev. 0
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Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
ADG5298
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.......................................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions............................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 14
Terminology.................................................................................... 16
Theory of Operation ...................................................................... 17
Trench Isolation.......................................................................... 17
Applications Information .............................................................. 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual-Supply....................................................................... 3
20 V Dual Supply ....................................................................... 4
12 V Single Supply........................................................................ 5
36 V Single Supply........................................................................ 6
Continuous Current per Channel (Sx or D)............................. 6
Absolute Maximum Ratings............................................................ 7
REVISION HISTORY
9/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
ADG5298
SPECIFICATIONS
15 V DUAL-SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 1.
Parameter
Symbol1
Test Conditions/Comments1
Min Typ 2
Max Unit
ANALOG SWITCH
Analog Signal Range
On Resistance
VSS
VDD
400
V
Ω
RON
Supply voltage (VS) = 10 V, drain source
current (IDS) = −1 mA, see Figure 31; for
maximum RON, VDD = +13.5 V, VSS = −13.5 V
290
On-Resistance Match Between Channels
On-Resistance Flatness
LEAKAGE CURRENTS
Source Off Leakage
ΔRON
RFLAT (ON)
VS = 10 V, IDS = −1 mA
VS = 10 V, IDS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
2.0
60
10
130
Ω
Ω
IS (off)
−8
0.005 +8
nA
VS = 10 V, VD =
VS = 10 V, VD =
10 V, see Figure 32
10 V, see Figure 32
Drain Off Leakage
ID (off)
−60
−70
0.005 +60 nA
Channel On Leakage
DIGITAL INPUTS
ID (on), IS (on)
VS = VD = 10 V, see Figure 30
0.01
+70 nA
Input High Voltage
VINH
2.0
V
Input Low Voltage
VINL
0.8
V
Input Current
IINL or IINH
CIN
Input voltage (VIN) = ground voltage (VGND) or VDD −0.1 +0.002 +0.1 µA
Digital Input Capacitance
DYNAMIC CHARACTERISTICS3
Transition Time
3
pF
ns
tTRANSITION
Load resistance (RL) = 300 Ω, load capacitance
(CL) = 35 pF, VS = 10 V, see Figure 36
150
335
On Time
Off Time
Break-Before-Make Time Delay
tON (EN)
tOFF (EN)
tD
RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38
RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38
RL = 300 Ω, CL = 35 pF, S1 voltage (VS1) =
S2 voltage (VS2) = 10 V, see Figure 37
125
160
55
275
275
ns
ns
ns
25
Charge Injection
Off Isolation
QINJ
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 35
VS = 0 V, frequency (f) = 1 MHz
VS = 0 V, f = 1 MHz
0.2
86
−80
110
2.9
34
pC
dB
dB
MHz
pF
Channel to Channel Crosstalk
−3 dB Bandwidth
Source Capacitance, Off
Drain Capacitance, Off
Source/Drain Capacitance, On
CS (off)
CD (off)
CD (on), CS
(on)
pF
pF
VS = 0 V, f = 1 MHz
37
POWER REQUIREMENTS
Supply Current
Positive
Negative
Ground Current
Supply Range
VDD = +16.5 V, VSS = −16.5 V
IDD
ISS
IGND
VDD/VSS
Digital inputs = 0 V or 5 V, see Figure 28
Digital inputs = 0 V or 5 V, see Figure 29
Digital inputs = 0 V or 5 V
60
10
60
80
20
80
22
µA
µA
µA
V
GND = 0 V
9
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 20
ADG5298
Data Sheet
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = −20 V 10%, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 2.
Parameter
Symbol1
Test Conditions/Comments1
Min Typ 2
Max Unit
ANALOG SWITCH
Analog Signal Range
On Resistance
VSS
VDD
350
V
Ω
RON
VS = 15 V, IDS = −1 mA, see Figure 31;
240
for maximum RON, VDD = +18 V, VSS = −18 V
On-Resistance Match Between Channels ΔRON
VS = 15 V, IDS = −1 mA
VS = 15 V, IDS = −1 mA
VDD = +22 V, VSS = −22 V
1.5
55
10
110
Ω
Ω
On-Resistance Flatness
LEAKAGE CURRENTS
Source Off Leakage
Drain Off Leakage
Channel On Leakage
DIGITAL INPUTS
RFLAT (ON)
IS (off)
−8
0.005 +8
nA
VS = 15 V, VD =
VS = 15 V, VD =
15 V, see Figure 32
15 V, see Figure 32
ID (off)
−60
−70
0.005 +60 nA
ID (on), IS (on)
VS = VD = 15 V, see Figure 30
0.01
+70 nA
Input High Voltage
Input Low Voltage
Input Current
Digital Input Capacitance
DYNAMIC CHARACTERISTICS3
Transition Time
On Time
Off Time
Break-Before-Make Time Delay
VINH
VINL
IINL or IINH
CIN
2.0
V
V
0.8
VIN = VGND or VDD
−0.1 +0.002 +0.1 µA
3
pF
tTRANSITION
tON (EN)
tOFF (EN)
tD
RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 36
RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38
RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 10 V,
see Figure 37
140
120
160
45
305
245
260
ns
ns
ns
ns
20
Charge Injection
Off Isolation
QINJ
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 35
VS = 0 V, f = 1 MHz
0.4
86
−80
121
2.8
33
pC
dB
dB
MHz
pF
Channel to Channel Crosstalk
−3 dB Bandwidth
Source Capacitance, Off
Drain Capacitance, Off
Source/Drain Capacitance, On
POWER REQUIREMENTS
Supply Current
CS (off)
CD (off)
CD (on), CS (on)
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
pF
pF
36
VDD = +22 V, VSS = −22 V
Positive
Negative
Ground Current
Supply Range
IDD
ISS
IGND
VDD/VSS
Digital inputs = 0 V or 5 V, see Figure 28
Digital inputs = 0 V or 5 V, see Figure 29
Digital inputs = 0 V or 5 V
60
10
60
120
20
120
22
µA
µA
µA
V
GND = 0 V
9
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 20
Data Sheet
ADG5298
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 3.
Parameter
Symbol1
Test Conditions/Comments1
Min Typ 2
Max Unit
ANALOG SWITCH
Analog Signal Range
On Resistance
VSS
VDD
800
V
Ω
RON
VS = 0 V to 10 V, IDS = −1 mA, see Figure 31;
for maximum RON, VDD = 10.8 V, VSS = 0 V
650
On-Resistance Match Between Channels
On-Resistance Flatness
LEAKAGE CURRENTS
Source Off Leakage
Drain Off Leakage
ΔRON
RFLAT (ON)
VS = 0 V to 10 V, IDS = −1 mA
VS = 0 V to 10 V, IDS = −1 mA
3
240
24
380
Ω
Ω
VDD = 13.2 V, VSS = 0 V
IS (off)
ID (off)
ID (on), IS (on)
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = VD = 1 V/10 V, see Figure 30
−8
−60
−70
0.005 +8
0.005 +60 nA
nA
Channel On Leakage
DIGITAL INPUTS
0.01
+70 nA
Input High Voltage
Input Low Voltage
VINH
VINL
2.0
V
V
0.8
Input Current
IINL or IINH
CIN
VIN = VGND or VDD
−0.1 +0.002 +0.1 µA
Digital Input Capacitance
DYNAMIC CHARACTERISTICS3
Transition Time
On Time
Off Time
3
pF
tTRANSITION
tON (EN)
tOFF (EN)
tD
RL = 300 Ω, CL = 35 pF, VS = 8 V, see Figure 36
RL = 300 Ω, CL = 35 pF, VS = 8 V, see Figure 38
RL = 300 Ω, CL = 35 pF, VS = 8 V, see Figure 38
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 8 V,
see Figure 37
200
180
165
95
490
435
305
ns
ns
ns
ns
Break-Before-Make Time Delay
40
Charge Injection
Off Isolation
QINJ
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 35
VS = 6 V, f = 1 MHz
0.2
−86
−80
95
3.3
38
pC
dB
dB
MHz
pF
Channel to Channel Crosstalk
−3 dB Bandwidth
Source Capacitance, Off
Drain Capacitance, Off
Source/Drain Capacitance, On
POWER REQUIREMENTS
Supply Current
CS (off)
CD (off)
CD (on), CS (on)
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
pF
pF
41
VDD = 13.2 V
Positive
Negative
Ground Current
Supply Range
IDD
ISS
IGND
VDD/VSS
Digital inputs = 0 V or 5 V, see Figure 28
Digital inputs = 0 V or 5 V, see Figure 29
Digital inputs = 0 V or 5 V
50
7.5
50
75
15
75
40
µA
µA
µA
V
GND = 0 V, VSS = 0 V
9
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 5 of 20
ADG5298
Data Sheet
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 4.
Parameter
Symbol1
Test Conditions/ Comments1
Min Typ 2
Max Unit
ANALOG SWITCH
Analog Signal Range
On Resistance
VSS
VDD
350
V
Ω
RON
VS = 0 V to 30 V, IDS = −1 mA, see Figure 31;
for maximum RON, VDD = 32.4 V, VSS = 0 V
260
On-Resistance Match Between Channels
On-Resistance Flatness
LEAKAGE CURRENTS
Source Off Leakage
Drain Off Leakage
ΔRON
RFLAT (ON)
VS = 0 V to 30 V, IDS = −1 mA
VS = 0 V to 30 V, IDS = −1 mA
1.5
55
10
110
Ω
Ω
VDD = 13.2 V, VSS = 0 V
IS (off)
ID (off)
ID (on), IS (on)
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
VS = VD = 1 V/10 V, see Figure 30
−8
−60
−70
0.005 +8
0.005 +60
0.01
nA
nA
nA
Channel On Leakage
DIGITAL INPUTS
+70
Input High Voltage
Input Low Voltage
VINH
VINL
2.0
V
V
0.8
Input Current
IINL or IINH
CIN
VIN = VGND or VDD
−0.1 +0.002 +0.1 µA
Digital Input Capacitance
DYNAMIC CHARACTERISTICS3
Transition Time
On Time
Off Time
3
pF
tTRANSITION
tON (EN)
tOFF (EN)
tD
RL = 300 Ω, CL = 35 pF, VS = 18 V, see Figure 36
RL = 300 Ω, CL = 35 pF, VS = 18 V, see Figure 38
RL = 300 Ω, CL = 35 pF, VS = 18 V, see Figure 38
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 18 V,
see Figure 37
170
150
180
55
320
265
265
ns
ns
ns
ns
Break-Before-Make Time Delay
20
Charge Injection
Off Isolation
QINJ
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 35
VS = 6 V, f = 1 MHz
0.3
−86
−80
105
2.7
32
pC
dB
dB
MHz
pF
Channel to Channel Crosstalk
−3 dB Bandwidth
Source Capacitance, Off
Drain Capacitance, Off
Source/Drain Capacitance, On
POWER REQUIREMENTS
Supply Current
CS (off)
CD (off)
CD (on), CS (on)
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
pF
pF
35
VDD = 13.2 V
Positive
Negative
Ground Current
Supply Range
IDD
ISS
IGND
VDD/VSS
Digital inputs = 0 V or 5 V, see Figure 28
Digital inputs = 0 V or 5 V, see Figure 29
Digital inputs = 0 V or 5 V
80
10
80
155
20
155
40
µA
µA
µA
V
GND = 0 V, VSS = 0 V
9
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL (Sx OR D)
Table 5.
Parameter
Test Conditions/Comments
175°C
210°C
Unit
CONTINUOUS CURRENT (Sx OR D)
VDD = +15 V, VSS = −15 V
VDD = +20 V, VSS = −20 V
VDD = 12 V, VSS = 0 V
θJA = 70 °C/W
10
10
6
10
10
6
mA maximum
mA maximum
mA maximum
mA maximum
VDD = 36 V, VSS = 0 V
10
10
Rev. 0 | Page 6 of 20
Data Sheet
ADG5298
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 6.
Parameter
Rating
VDD to VSS
48 V
VDD to GND
VSS to GND
Analog Inputs1
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
31 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Table 7. Thermal Resistance
Package Type
F-16-11
FR-16-11
θJA
70
70
θJC
22
10
Unit
°C/W
°C/W
Digital Inputs1
1 Thermal impedance simulated values are based on JEDEC 2s2p thermal test
board. See JEDEC JESD51.
Peak Current, Sx or D Pins
ESD CAUTION
Continuous Current, Sx or D Pins2
Temperature Range
Junction Temperature
Data + 5%
−55°C to +210°C
212°C
Reflow Soldering Peak Temperature,
Pb Free
260°C (+ 0°C/− 5°C)
1 Overvoltages at the Ax, EN, Sx, or D pins are clamped by internal diodes.
Limit the current to the maximum ratings given.
2 See Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
Rev. 0 | Page 7 of 20
ADG5298
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
A0
EN
V
A1
A2
A0
1
2
3
4
5
6
7
8
16 A1
EN
15 A2
GND
SS
V
14 GND
ADG5298
SS
V
S1
S2
S3
S4
D
DD
TOP VIEW
ADG5298
S1
13
V
DD
S5
S6
S7
S8
(Not to Scale)
TOP VIEW
S2
S3
S4
D
12 S5
11 S6
10 S7
(Not to Scale)
9
S8
Figure 3. Reversed Formed FLATPACK Pin Configuration
Figure 2. FLATPACK Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
A0
EN
Logic Control Input 0.
Active High Digital Input. When low, the device is disabled and all switches are off. When high, the Ax logic inputs
determine the on switches.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input 2.
Logic Control Input 1.
Table 9. Truth Table
A2
X1
0
0
0
0
1
1
1
A1
A0
X1
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch
X1
0
0
1
1
0
0
1
1
None
S1
S2
S3
S4
S5
S6
S7
S8
1
1
1
1 X is don’t care.
Rev. 0 | Page 8 of 20
Data Sheet
ADG5298
TYPICAL PERFORMANCE CHARACTERISTICS
160
160
140
T
= 25°C
T
= 25°C
A
A
V
V
= 32.4V
= 0V
DD
SS
140
120
100
80
V
V
= +18V
= –18V
DD
SS
120
100
80
V
V
= 36V
= 0V
V
V
= 39.6V
= 0V
DD
SS
DD
SS
V
V
= +22V
= –22V
V
V
= +20V
= –20V
DD
SS
DD
SS
60
40
60
40
20
0
20
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
V , V (V)
S
D
V , V (V)
S
D
Figure 4. On Resistance (RON) as a Function of VS, VD ( 20 V Dual Supply)
Figure 7. On Resistance (RON) as a Function of VS, VD (36 V Single Supply)
250
350
+210°C
+175°C
+125°C
+85°C
+25°C
–40°C
–55°C
V
V
= +15V
= –15V
T
= 25°C
DD
SS
A
V
V
= +9V
= –9V
DD
SS
300
250
200
150
100
50
200
150
100
50
V
V
= +13.5V
= –13.5V
DD
SS
V
= +16.5V
V
V
= +15V
= –15V
DD
SS
DD
SS
V
= –16.5V
0
–20
0
–15 –12
–9
–6
–3
0
3
6
9
12
15
–15
–10
–5
0
5
10
15
20
V , V (V)
V , V (V)
S D
S
D
Figure 5. On Resistance (RON) as a Function of VS, VD ( 15 V Dual Supply)
Figure 8. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, 15 V Dual Supply
450
300
T
= 25°C
+210°C
+175°C
+125°C
+85°C
+25°C
–40°C
–55°C
V
V
= +20V
= –20V
A
DD
SS
V
V
= 9V
= 0V
DD
SS
400
350
300
250
200
150
250
200
150
100
50
V
V
= 10.8V
= 0V
DD
SS
V
V
= 12V
= 0V
DD
SS
V
V
= 13.2V
= 0V
DD
SS
100
50
0
0
–20
–15
–10
–5
0
5
10
15
20
V , V (V)
S
D
V , V (V)
S
D
Figure 9. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, 20 V Dual Supply
Figure 6. On Resistance (RON) as a Function of VS, VD (12 V Single Supply)
Rev. 0 | Page 9 of 20
ADG5298
Data Sheet
700
10
0
+210°C
+175°C
+125°C
+85°C
+25°C
–40°C
–55°C
V
V
= 12V
= 0V
V
V
V
= +20V
= –20V
BIAS
DD
SS
DD
SS
= +15V, –15V
600
500
400
300
200
100
0
–10
–20
–30
–40
–50
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
S
I
D
I
S
I
D
I , I (ON) + +
S
D
I , I (ON) – –
S
D
0
2
4
6
8
10
12
–55
–25
5
35
65
95
125
155
185
215
V , V (V)
TEMPERATURE (°C)
S
D
Figure 13. Leakage Current vs. Temperature, 20 V Dual Supply
Figure 10. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, 12 V Single Supply
5
0
300
+210°C
+175°C
+125°C
+85°C
250
+25°C
–40°C
–55°C
–5
200
150
100
50
–10
–15
–20
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
S
D
S
D
–25
–30
–35
V
V
V
= 12V
= 0V
BIAS
DD
SS
I , ID (ON) + +
I , ID (ON) – –
S
S
V
V
= 36V
= 0V
DD
SS
= 1V, 10V
0
–55
–25
5
35
65
95
125
155
185
215
0
4
8
12
16
20
24
28
32
36
V , V (V)
S
D
TEMPERATURE (°C)
Figure 11. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, 36 V Single Supply
Figure 14. Leakage Current vs. Temperature, 12 V Single Supply
5
0
5
V
V
V
= +15V
= –15V
BIAS
DD
SS
= +10V, –10V
0
–5
–5
–10
–15
–20
–25
–30
–10
–15
–20
–25
I
(OFF) + –
(OFF) + –
(OFF) – +
I (OFF) – +
D
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
S
S
I
I
D
D
–35
–40
–45
I
I
S
S
I
V
V
V
= 36V
= 0V
BIAS
D
DD
SS
I , I (ON) + +
I , I (ON) + +
S
D
S
D
= 1V, 30V
I , I (ON) – –
I , I (ON) – –
S
D
S
D
–55
–25
5
35
65
95
125
155
185
215
–55
–25
5
35
65
95
125
155
185
215
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 15. Leakage Current vs. Temperature, 36 V Single Supply
Rev. 0 | Page 10 of 20
Data Sheet
ADG5298
0
–5
–6
T
V
V
= 25°C
= +15V
T
V
V
= 25°C
= +15V
A
A
DD
DD
–20
–40
–60
= –15V
= –15V
SS
SS
–7
–8
–9
–80
–100
–120
–140
–10
–11
–12
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Attenuation vs. Frequency, 15 V Dual Supply
Figure 16. Off Isolation vs. Frequency, 15 V Dual Supply
0
0
–20
–40
–60
T
= 25°C
A
T
V
V
= 25°C
A
V
V
= +15V
= –15V
DD
SS
= +15V
= –15V
DD
SS
–20
–40
NO DECOUPLING
CAPACITORS
–60
BETWEEN S1 AND S2
–80
–100
–120
–140
BETWEEN S1 AND S8
–80
DECOUPLING
CAPACITORS
–100
–120
1k
10k
100k
1M
10M
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. ACPSRR vs. Frequency, 15 V Dual Supply
Figure 17. Crosstalk vs. Frequency, 15 V Dual Supply
5
4
3
2
1
40
T
= 25°C
A
T
= 25°C
A
MUX (SOURCE TO DRAIN)
DEMUX (DRAIN TO SOURCE)
35
30
25
V
V
= +15V
= –15V
V
V
= +15V
= –15V
DD
SS
DD
SS
20
15
10
5
V
V
= +20V
= –20V
DD
SS
V
V
= +20V
= –20V
DD
SS
V
SS
= +36V
= 0V
DD
V
0
–1
–2
V
V
= +36V
= 0V
DD
SS
V
V
= +12V
V
= +12V
= 0V
DD
SS
DD
SS
= 0V
V
0
–20
–10
0
10
–20
20
30
–10
0
10
20
30
V
(V)
V
(V)
S
S
Figure 21. Charge Injection (QINJ) vs. Source Voltage (VS), Source to Drain
Figure 18. Charge Injection (QINJ) vs. Source Voltage (VS), Drain to Source
Rev. 0 | Page 11 of 20
ADG5298
Data Sheet
5
4
400
V
= 12V, V = 0V
SS
V
V
= +20V
= −20V
+25°C
+175°C
+210°C
DD
DD
SS
V
V
V
= 36V, V = 0V
SS
DD
DD
DD
= +15V, V = –15V
SS
= +20V, V = –20V
SS
350
300
250
200
150
100
50
3
2
1
0
–1
–20
0
–40
–15
–10
–5
0
5
10
15
20
10
60
110
160
210
V
(V)
TEMPERATURE (°C)
S
Figure 22. tTRANSITION Time vs. Temperature
Figure 21. Charge Injection as a Function of VS for Various Temperatures, ± 20
V Dual Supply
80
0.8
T
= 25°C
+25°C
+175°C
+210°C
A
V
V
= +15V
= –15V
DD
SS
70
60
50
40
30
20
10
0
0.6
0.4
0.2
SOURCE/DRAIN ON
DRAIN OFF
0
–0.2
–0.4
V
V
= 12V
= 0V
DD
SS
SOURCE OFF
–0.6
–15
–10
–5
0
5
10
15
0
2
4
6
8
10
12
V
(V)
V
(V)
S
S
Figure 23. Capacitance vs. Source Voltage(VS), ±±1 V Dual Supply
Figure 26. Charge Injection as a Function of VS for Various Temperatures,
±2 V Single Supply
3.0
4.0
+25°C
+25°C
+175°C
+175°C
3.5
+210°C
2.5
2.0
1.5
1.0
0.5
0
+210°C
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
V
V
= +15V
–0.5
DD
SS
V
V
= 36V
= 0V
DD
SS
= −15V
–1.0
–15
–10
–5
0
5
10
15
0
5
10
15
20
(V)
25
30
35
V
(V)
S
V
S
Figure 24. Charge Injection as a Function of VS for Various Temperatures, ± ±1
V Dual Supply
Figure 27. Charge Injection as a Function of VS for Various Temperatures,
36 V Single Supply
Rev. 0 | Page 12 of 20
Data Sheet
ADG5298
120
100
80
60
40
20
0
7
6
V
V
= 12V, V = 0V
SS
V
V
V
V
= 12V, V = 0V
SS
DD
DD
DD
DD
DD
DD
= 36V, V = 0V
= 36V, V = 0V
SS
SS
= +15V, V = –15V
SS
= +20V, V = –20V
SS
V
V
= +15V, V = –15V
SS
= +20V, V = –20V
SS
DD
DD
5
4
3
2
1
0
–1
–55
–55
–25
5
35
65
95
125
155
185
215
–25
5
35
65
95
125
155
185
215
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 28. IDD vs Temperature
Figure 29. ISS vs Temperature
Rev. 0 | Page 13 of 20
ADG5298
Data Sheet
TEST CIRCUITS
V
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
DD
SS
S1
V
OUT
I
(ON)
A
D
R
50Ω
L
S1
S2
D
D
NC
S2
R
50Ω
L
V
S
GND
V
S8
V
V
D
S
NC = NO CONNECT
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 30. On Leakage
Figure 33. Channel-to-Channel Crosstalk
V
DD
SS
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
50Ω
Sx
50Ω
V
S
V
V
OUT
R
L
Sx
D
50Ω
GND
I
DS
S
R
= V ÷ I
DS
ON
V
V
OUT
OFF ISOLATION = 20 log
S
Figure 31. On Resistance
Figure 34. Off Isolation
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
Sx
50Ω
I
(OFF)
A
I
(OFF)
A
S
D
S1
S8
D
V
S
D
V
OUT
R
L
50Ω
A
GND
V
V
D
S
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 32. Off Leakage
Figure 35. −3 dB Bandwidth
Rev. 0 | Page 14 of 20
Data Sheet
ADG5298
V
V
V
V
DD
SS
SS
3V
tR < 20ns
tF < 20ns
DD
ADDR ESS
DRIVE (V
50%
50%
)
A0
A1
A2
IN
S1
V
V
S1
S8
0V
V
IN
50Ω
S2 TO S7
tTRANSITION
tTRANSITION
90%
S8
ADG5298
OUTPUT
D
2.0V
EN
OUTPUT
GND
300Ω
35pF
10%
Figure 36. Address to Output Switching Times, tTRANSITION
V
V
V
DD
SS
3V
V
DD
SS
ADDRESS
A0
A1
A2
DRIVE (V
)
IN
S1
V
S
V
IN
50Ω
0V
S2 TO S7
S8
80%
80%
ADG5298
OUTPUT
OUTPUT
D
2.0V
EN
GND
300Ω
35pF
tD
Figure 37. Break-Before-Make Time Delay, tD
V
V
V
DD
DD
SS
SS
3V
V
A0
A1
A2
ENABLE
DRIVE (V
50%
50%
)
S1
S2 TO S8
V
IN
S
0V
ADG5298
tON (EN)
tOFF (EN)
OUTPUT
0.9V
D
EN
OUT
OUTPUT
V
35pF
IN
50Ω
GND
300Ω
0.1V
OUT
Figure 38. Enable Delay, tON (EN), tOFF (EN)
V
V
V
V
DD
DD
SS
SS
3V
A0
A1
A2
V
V
IN
ADG5298
R
S
Sx
D
OUT
V
OUT
∆V
OUT
EN
C
1nF
L
GND
V
Q
= C × ∆V
L OUT
S
INJ
V
IN
Figure 39. Charge Injection, QINJ
Rev. 0 | Page 15 of 20
ADG5298
Data Sheet
TERMINOLOGY
IDD
CIN
I
DD represents the positive supply current.
CIN represents the digital input capacitance.
ISS
t
t
ON (EN)
ON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
OFF (EN)
OFF (EN) represents the delay time between the 50% and 90%
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal Sx, respectively.
t
t
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal D and
tTRANSITION
Terminal Sx.
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
Break-Before-Make Time Delay (tD)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range is represented by RFLAT (ON)
.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
IS (Off)
IS (off) is the source leakage current with the switch off.
Charge Injection
ID (Off)
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (on) and IS (on) represent the channel leakage currents with
the switch on.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
VINL
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH represent the low and high input currents of the
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by −3 dB.
V
I
I
On Response
On response is the frequency response of the on switch.
digital inputs.
AC Power Supply Rejection Ratio (ACPSRR)
CD (Off)
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude
of signal on the output to the amplitude of the modulation is the
ACPSRR.
CD (off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (on) and CS (on) represent on switch capacitances, which are
measured with reference to ground.
Rev. 0 | Page 16 of 20
Data Sheet
ADG5298
THEORY OF OPERATION
NMOS
PMOS
The ADG5298 is a latch-up proof, bidirectional, 8:1 CMOS
multiplexer that is designed to operate at very high temperatures.
The device is controlled by four parallel digital inputs (EN, A0,
A1, and A2). The EN input allows for the ADG5298 to be enabled
or disabled. When the ADG5298 is disabled, the source pins (S1
to S8) disconnect from the drain pin (D). When the ADG5298
is enabled, the address lines (A0, A1, and A2) can determine
which source pin (S1 to S8) is connected to the drain pin (D).
P WELL
N WELL
TRENCH ISOLATION
In the ADG5298, an insulating oxide layer (trench) is placed
between the negative channel metal-oxide semiconductor
(NMOS) and the positive channel metal-oxide semiconductor
(PMOS) transistors of each CMOS switch. Parasitic junctions,
which occur between the transistors in junction isolated switches,
are eliminated, and the result is a completely latch-up proof
switch that has minimal leakage over temperature.
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 40. Trench Isolation
In junction isolation, the N well and P well of the PMOS and
NMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
Rev. 0 | Page 17 of 20
ADG5298
Data Sheet
APPLICATIONS INFORMATION
The ultralow capacitance and charge injection of this switch
makes it an ideal solution for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
latch-up immune and low leakage features makes the ADG5298
perfect for use in harsh environments, such as downhole drilling
and avionics. The ADG5298 has achieved a JESD78D Class II
rating, handling stresses to 500 mA with a 10 ms pulse at the
maximum operating temperature of the device (210°C).
The ADG5298 can operate in a wide ambient temperature
range from −55°C to +210°C. Its wide range coupled with its
Rev. 0 | Page 18 of 20
Data Sheet
ADG5298
OUTLINE DIMENSIONS
25.65
25.40
25.15
7.01
6.86
6.71
8.89 MIN
5.23
5.08
4.93
1.34
1.27
1.20
1
16
10.36
10.16
9.96
7.40
7.24
7.09
1.02
MIN
8
9
0.48
0.43
0.38
0.89
BSC
R 0.32
BSC
TOP VIEW
END VIEW
BOTTOM VIEW
0.70 REF
2.32
2.11
1.90
0.152
0.127
0.102
0.20 MIN
SIDE VIEW
0.66 MIN
Figure 41. 16-Lead Ceramic Flat Package [FLATPACK]
(F-16-1)
Dimensions shown in millimeters
10.36
10.16
9.96
7.40
7.24
7.09
8
1
5.23
5.08
4.93
7.01
6.86
6.71
12.446
REF
16
9
BOTTOM VIEW
SIDE VIEW
4.978
4.826
4.673
2.32
2.11
1.90
0.66 MIN
1.524
1.397
1.270
3.02
0.254
2.74
2.46
0.203
0.152
END VIEW
0.432
0.381
0.330
0.152
0.127
0.102
0.254
0.203
0.152
1.524
1.397
1.270
0.48
0.43
0.38
SEATING
PLANE
1.34
1.27
1.20
Figure 42. 16-Lead Ceramic Flat Package with Reverse Formed Gullwing Leads [FLATPACK_RF]
Cavity Down
(FR-16-1)
Dimensions shown in millimeters
Rev. 0 | Page 19 of 20
ADG5298
Data Sheet
ORDERING GUIDE
Package
Option
Model1
Temperature Range Package Description
ADG5298HFZ
ADG5298HFRZ
EVAL-ADG5298EB1Z
−55°C to +210°C
−55°C to +210°C
16-Lead Ceramic Flat Package [FLATPACK]
F-16-1
16-Lead Ceramic Flat Package with Reverse Formed Gullwing Leads [FLATPACK_RF] FR-16-1
Evaluation Board
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14872-0-9/16(0)
Rev. 0 | Page 20 of 20
相关型号：
ADG5298HFZ
High Temperature (up to 210°C), High Voltage, Latch-Up Proof, 8-Channel Multiplexer
ADI
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