ADG5412FTRUZ-EP [ADI]
Fault Protection and Detection, 10 Ω RON, Quad SPST Switches;
| 型号： | ADG5412FTRUZ-EP |
| 厂家： | 
ADI |
| 描述： | Fault Protection and Detection, 10 Ω RON, Quad SPST Switches 开关 |
| 文件： | 总20页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage Latch-Up Proof,
Quad SPST Switches
ADG5412/ADG5413
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Latch-up proof
S1
S1
8 kV human body model (HBM) ESD rating
Low on resistance (<10 Ω)
9 V to 22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
D2
S3
D2
S3
ADG5412
ADG5413
Fully specified at 1ꢀ V, 20 V, +12 V, and +36 V
VSS to VDD analog signal range
D3
S4
D3
S4
APPLICATIONS
Relay replacement
Automatic test equipment
Data acquisition
D4
D4
Instrumentation
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Avionics
Figure 1.
Audio and video switching
Communication systems
exhibits break-before-make switching action for use in
multiplexer applications.
GENERAL DESCRIPTION
The ADG5412/ADG5413 contain four independent single-
pole/single-throw (SPST) switches. The ADG5412 switches
turn on with Logic 1. The ADG5413 has two switches with
digital control logic similar to that of the ADG5412; however,
the logic is inverted on the other two switches. Each switch
conducts equally well in both directions when on, and each
switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench
separates the P and N channel transistors thereby preventing
latch-up even under severe overvoltage conditions.
2. Low RON
.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5412/ADG5413 can be operated
from dual supplies up to 22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5412/ADG5413 can be operated
from a single rail power supply up to 40 V.
The ADG5412 and ADG5413 do not have a VL pin. The digital
inputs are compatible with 3 V logic inputs over the full
operating supply range.
The on-resistance profile is very flat over the full analog input
range, which ensures good linearity and low distortion when
switching audio signals. High switching speed also makes the
devices suitable for video signal switching. The ADG5413
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADG5412/ADG5413
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per Channel, Sx or Dx..............................7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions............................9
Typical Performance Characteristics ........................................... 1ꢂ
Test Circuits..................................................................................... 14
Terminology.................................................................................... 16
Trench Isolation.............................................................................. 17
Applications Information.............................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
1ꢀ ꢁ Dual Supply ....................................................................... 3
2ꢂ ꢁ Dual Supply ....................................................................... 4
12 ꢁ Single Supply........................................................................ ꢀ
36 ꢁ Single Supply........................................................................ 6
REVISION HISTORY
7/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG5412/ADG5413
SPECIFICATIONS
1ꢀ V DUAL SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
9.8
Ω typ
VS = ±±0 V, IS = −±0 mA;
see Figure 24
±±
0.35
±4
±6
Ω max
Ω typ
VDD = +±3.5 V, VSS = −±3.5 V
VS = ±±0 V, IS = −±0 mA
On-Resistance Match Between Channels,
∆RON
0.7
±.2
±.6
0.9
2
±.±
2.2
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = ±±0 V, IS = −±0 mA
LEAKAGE CURRENTS
VDD = +±6.5 V, VSS = −±6.5 V
Source Off Leakage, IS (Off)
±0.05
nA typ
VS = ±±0 V, VD = m ±0 V;
see Figure 27
±0.25 ±0.75
±0.05
±3.5
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = ±±0 V, VD = m ±0 V;
see Figure 27
±0.25 ±0.75
±0.±
±3.5
±±2
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = ±±0 V; see Figure 23
±0.4
±2
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
2.5
VIN = VGND or VDD
±0.±
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS±
tON
±70
202
±20
±45
±5
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = ±0 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = ±0 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
236
±70
262
±82
tOFF
Break-Before-Make Time Delay, tD
(ADG54±3 Only)
6
ns min
pC typ
VS± = VS2 = ±0 V; see Figure 30
VS = 0 V, RS = 0 Ω, CL = ± nF;
see Figure 32
Charge Injection, QINJ
Off Isolation
240
−78
−70
0.009
±67
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 26
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 25
RL = ± kΩ, ±5 V p-p, f = 20 Hz
to 20 kHz; see Figure 28
RL = 50 Ω, CL = 5 pF; see
Figure 29
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
MHz typ
dB typ
Insertion Loss
−0.7
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 29
CS (Off)
CD (Off)
CD (On), CS (On)
±8
±8
60
pF typ
pF typ
pF typ
VS = 0 V, f = ± MHz
VS = 0 V, f = ± MHz
VS = 0 V, f = ± MHz
Rev. 0 | Page 3 of 20
ADG5412/ADG5413
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
VDD = +±6.5 V, VSS = −±6.5 V
Digital inputs = 0 V or VDD
POWER REQUIREMENTS
IDD
45
μA typ
55
0.00±
70
μA max
μA typ
μA max
ISS
Digital inputs = 0 V or VDD
±
VDD/VSS
±9/±22
V min/V max GND = 0 V
± Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = −20 V 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
9
Ω typ
VS = ±±5 V, IS = −±0 mA;
see Figure 24
±0
0.35
±3
±5
Ω max
Ω typ
VDD = +±8 V, VSS = −±8 V
VS = ±±5 V, IS = −±0 mA
On-Resistance Match Between
Channels, ∆RON
0.7
±.5
±.8
0.9
2.2
±.±
2.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = ±±5 V, IS = −±0 mA
VDD = +22 V, VSS = −22 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.05
nA typ
VS = ±±5 V, VD = m ±5 V;
see Figure 27
±0.25 ±0.75
±0.05
±3.5
±3.5
±±2
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = ±±5 V, VD = m ±5 V;
see Figure 27
±0.25 ±0.75
±0.±
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
VS = VD = ±±5 V; see
Figure 23
±0.4
±2
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
2.5
VIN = VGND or VDD
±0.±
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS±
tON
±58
±87
±±0
±38
±2
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = ±0 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = ±0 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
2±7
±54
240
±70
tOFF
Break-Before-Make Time Delay, tD
(ADG54±3 Only)
5
ns min
pC typ
dB typ
dB typ
VS± = VS2 = ±0 V; see
Figure 30
VS = 0 V, RS = 0 Ω, CL = ± nF;
see Figure 32
RL = 50 Ω, CL = 5 pF, f = ± MHz; see
Figure 26
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 25
Charge Injection, QINJ
Off Isolation
3±0
−78
−70
Channel-to-Channel Crosstalk
Rev. 0 | Page 4 of 20
ADG5412/ADG5413
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
Total Harmonic Distortion + Noise
0.007
% typ
RL = ± kΩ, 20 V p-p, f = 20 Hz to
20 kHz; see Figure 28
−3 dB Bandwidth
Insertion Loss
±60
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF;
see Figure 29
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 29
−0.6
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
±7
±7
60
pF typ
pF typ
pF typ
VS = 0 V, f = ± MHz
VS = 0 V, f = ± MHz
VS = 0 V, f = ± MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
50
70
0.00±
μA typ
μA max
μA typ
±±0
ISS
Digital inputs = 0 V or VDD
VDD/VSS
±9/±22
V min/V max GND = 0 V
± Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
3±
V
±9
Ω typ
VS = 0 V to ±0 V, IS = −±0 mA;
see Figure 24
VDD = ±0.8 V, VSS = 0 V
22
0.4
27
Ω max
Ω typ
On-Resistance Match Between Channels,
∆RON
VS = 0 V to ±0 V, IS = −±0 mA
0.8
4.4
5.5
±
±.2
7.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to ±0 V, IS = −±0 mA
VDD = ±3.2 V, VSS = 0 V
6.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.05
nA typ
VS = ± V/±0 V, VD = ±0 V/± V;
see Figure 27
±0.25 ±0.75
±0.05
±3.5
±3.5
±±2
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = ± V/±0 V, VD = ±0 V/± V;
see Figure 27
±0.25 ±0.75
±0.±
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
VS = VD = ± V/±0 V; see
Figure 23
±0.4
±2
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
2.5
VIN = VGND or VDD
±0.±
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS±
tON
225
296
±50
±87
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 3±
358
222
403
247
tOFF
Rev. 0 | Page 5 of 20
ADG5412/ADG5413
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
Break-Before-Make Time Delay, tD
(ADG54±3 Only)
70
ns typ
RL = 300 Ω, CL = 35 pF
38
ns min
pC typ
VS± = VS2 = 8 V; see Figure 30
VS = 6 V, RS = 0 Ω, CL = ± nF;
see Figure 32
Charge Injection, QINJ
Off Isolation
95
−78
−70
0.07
±80
−±.3
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 26
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 25
RL = ± kΩ, 6 V p-p, f = 20 Hz
to 20 kHz; see Figure 28
RL = 50 Ω, CL = 5 pF; see
Figure 29
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 29
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
22
22
58
pF typ
pF typ
pF typ
VS = 6 V, f = ± MHz
VS = 6 V, f = ± MHz
VS = 6 V, f = ± MHz
VDD = ±3.2 V
40
μA typ
Digital inputs = 0 V or VDD
65
μA max
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
± Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
±7
V
±0.6
Ω typ
VS = 0 V to 30 V, IS = −±0 mA;
see Figure 24
VDD = 32.4 V, VSS = 0 V
±2
0.35
±5
Ω max
Ω typ
On-Resistance Match Between Channels,
∆RON
VS = 0 V to 30 V, IS = −±0 mA
0.7
2.7
3.2
0.9
3.8
±.±
4.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 0 V to 30 V, IS = −±0 mA
VDD = 39.6 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.05
nA typ
VS = ± V/30 V, VD = 30 V/± V;
see Figure 27
±0.25 ±0.75
±0.05
±3.5
±3.5
±±2
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = ± V/30 V, VD = 30 V/± V;
see Figure 27
±0.25 ±0.75
±0.±
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
VS = VD = ± V/30 V; see
Figure 23
±0.4
±2
nA max
Rev. 0 | Page 6 of 20
ADG5412/ADG5413
Parameter
2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
2.5
VIN = VGND or VDD
±0.±
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS±
tON
±80
220
±30
±69
25
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = ±8 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = ±8 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
230
±67
248
±74
tOFF
Break-Before-Make Time Delay, tD
(ADG54±3 Only)
8
ns min
pC typ
VS± = VS2 = ±8 V; see Figure 30
VS = ±8 V, RS = 0 Ω, CL = ± nF;
see Figure 32
Charge Injection, QINJ
Off Isolation
280
−78
−70
0.03
±74
−0.8
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 26
RL = 50 Ω, CL = 5 pF, f = ± MHz;
Figure 25
RL = ± kΩ, ±8 V p-p, f = 20 Hz
to 20 kHz; see Figure 28
RL = 50 Ω, CL = 5 pF; see
Figure 29
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = ± MHz;
see Figure 29
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
±8
±8
58
pF typ
pF typ
pF typ
VS = ±8 V, f = ± MHz
VS = ±8 V, f = ± MHz
VS = ±8 V, f = ± MHz
VDD = 39.6 V
80
μA typ
Digital inputs = 0 V or VDD
±00
±30
μA max
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
± Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
2ꢀ°C
8ꢀ°C
12ꢀ°C
Unit
CONTINUOUS CURRENT, Sx OR Dx
VDD = +±5 V, VSS = −±5 V
TSSOP (θJA = ±±2.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = ±±2.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = ±2 V, VSS = 0 V
89
±60
59
94
37
49
mA maximum
mA maximum
95
±70
63
98
39
50
mA maximum
mA maximum
TSSOP (θJA = ±±2.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
6±
±±0
43
70
29
42
mA maximum
mA maximum
TSSOP (θJA = ±±2.6°C/W)
LFCSP (θJA = 30.4°C/W)
80
±44
54
87
35
47
mA maximum
mA maximum
Rev. 0 | Page 7 of 20
ADG5412/ADG5413
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VDD to VSS
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
278 mA (pulsed at ± ms, ±0%
duty cycle maximum)
Data + ±5%
VDD to GND
VSS to GND
Analog Inputs±
Digital Inputs±
Only one absolute maximum rating can be applied at any
one time.
Peak Current, Sx or Dx Pins
ESD CAUTION
Continuous Current, Sx or Dx2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
−40°C to +±25°C
−65°C to +±50°C
±50°C
±6-Lead TSSOP (4-Layer
Board)
±6-Lead LFCSP (4-Layer
Board)
±±2.6°C/W
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
± Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2 See Table 5.
Rev. 0 | Page 8 of 20
ADG5412/ADG5413
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
D1
S1
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
PIN 1
ADG5412/
ADG5413
TOP VIEW
(Not to Scale)
INDICATOR
12 S2
11 V
S1
1
2
3
4
V
13 V
DD
SS
ADG5412/
ADG5413
V
DD
SS
GND
12 NC
11 S3
10 D3
GND
10 NC
9 S3
S4
D4
TOP VIEW
S4
(Not to Scale)
IN4
9
IN3
NC = NO CONNECT
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
.
SS
2. NC = NO CONNECT.
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
Mnemonic
Description
±
2
3
4
±5
±6
±
2
3
IN±
D±
S±
VSS
Logic Control Input ±.
Drain Terminal ±. This pin can be an input or output.
Source Terminal ±. This pin can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
5
GND
6
7
8
4
5
6
S4
D4
IN4
Source Terminal 4. This pin can be an input or output.
Drain Terminal 4. This pin can be an input or output.
Logic Control Input 4.
9
7
IN3
Logic Control Input 3.
±0
±±
±2
±3
±4
±5
±6
8
9
D3
S3
NC
VDD
S2
D2
Drain Terminal 3. This pin can be an input or output.
Source Terminal 3. This pin can be an input or output.
No Connection.
Most Positive Power Supply Potential.
Source Terminal 2. This pin can be an input or output.
Drain Terminal 2. This pin can be an input or output.
Logic Control Input 2.
±0
±±
±2
±3
±4
EP
IN2
Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the
substrate, VSS.
Table 8. ADG5412 Truth Table
INx
Switch Condition
±
0
On
Off
Table 9. ADG5413 Truth Table
INx
S1, S4
S2, S3
On
Off
0
±
Off
On
Rev. 0 | Page 9 of 20
ADG5412/ADG5413
TYPICAL PERFORMANCE CHARACTERISTICS
16
12
10
8
T
= 25°C
V
V
= +10V
= –10V
T = 25°C
A
A
DD
V
V
= +9V
= –9V
DD
SS
SS
14
12
10
8
V
V
= 32.4V
= 0V
DD
SS
V
V
= 36V
= 0V
DD
SS
V
V
= +11V
= –11V
DD
SS
6
V
V
= 39.6V
= 0V
DD
SS
V
V
=+13.5V
= –13.5V
DD
SS
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +15V
= –15V
6
DD
SS
4
4
2
2
0
0
–20
–15
–10
–5
0
V , V (V)
5
10
15
20
0
5
10
15
20
25
30
35
40
45
V , V (V)
S
D
S
D
Figure 4. RON as a Function of VS, VD (Dual Supply)
Figure 7. RON as a Function of VS, VD (Single Supply)
12
10
8
18
16
14
12
10
8
V
V
= +18V
= –18V
DD
SS
T
= +125°C
= +85°C
A
V
V
= +22V
= –22V
T
DD
SS
A
V
= +20V
= –20V
DD
SS
V
6
T
= +25°C
= –40°C
A
T
A
4
6
4
2
2
V
V
= +15V
= –15V
DD
SS
T
= 25°C
A
0
0
–15
–25 –20 –15 –10
–5
0
5
10
15
20
25
–10
–5
0
5
10
15
V , V (V)
V , V (V)
S
D
S
D
Figure 5. RON as a Function of VS, VD (Dual Supply)
Figure 8. RON as a Function of VS (VD) for Different Temperatures,
15 V Dual Supply
16
14
12
25
20
15
10
5
T
= 25°C
A
V
V
= +10V
= 0V
DD
SS
V
V
= 10.8V
= 0V
DD
SS
V
V
= +9V
= 0V
DD
SS
T
= +125°C
= +85°C
A
10
8
T
A
T
= +25°C
= –40°C
A
V
V
= 11V
= 0V
DD
SS
V
V
= 12V
= 0V
6
DD
SS
T
A
V
V
= 13.2V
= 0V
DD
SS
4
2
V
V
= +20V
= –20V
DD
SS
0
–20
0
–15
–10
–5
0
5
10
15
20
0
2
4
6
8
10
12
14
V , V (V)
V , V (V)
S
D
S
D
Figure 6. RON as a Function of VS, VD (Single Supply)
Figure 9. RON as a Function of VS (VD) for Different Temperatures,
20 V Dual Supply
Rev. 0 | Page ±0 of 20
ADG5412/ADG5413
30
25
20
15
10
5
0.8
0.6
V
V
= 12V
= 0V
V
V
V
= +20V
= –20V
BIAS
DD
SS
DD
SS
= +15V/–15V
I
, I (ON) + +
S
D
I
, I (ON) – –
S
D
T
= +125°C
0.4
A
I
(OFF) + –
S
T
= +85°C
A
0.2
I
(OFF) – +
D
T
= +25°C
= –40°C
A
0
T
A
–0.2
–0.4
–0.6
I
(OFF) – +
S
I
(OFF) + –
D
0
0
2
4
6
8
10
12
0
25
50
75
100
125
V , V (V)
TEMPERATURE (°C)
S
D
Figure 10. RON as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
Figure 13. Leakage Currents vs. Temperature, 20 V Dual Supply
16
14
12
0.6
V
V
V
= 12V
= 0V
BIAS
DD
SS
I
, I (ON) + +
S
D
= 1V/10V
0.4
0.2
0
T
= +125°C
= +85°C
A
T
I
, I (ON) – –
S
A
10
8
D
I
(OFF) + –
S
T
= +25°C
= –40°C
A
I
(OFF) – +
D
T
6
A
4
2
I
(OFF) + –
D
V
V
= 36V
= 0V
DD
SS
I
(OFF) – +
S
0
–0.2
0
5
10
15
20
25
30
35
40
0
25
50
75
100
125
V , V (V)
TEMPERATURE (°C)
S
D
Figure 11. RON as a Function of VS (VD) for Different Temperatures,
36 V Single Supply
Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply
0.8
0.8
V
V
V
= +15V
= –15V
BIAS
V
V
V
= 36V
= 0V
BIAS
DD
SS
DD
SS
I
, I (ON) + +
S
D
= +10V/–10V
= 1V/30V
0.6
0.4
I
, I (ON) + +
S
D
0.6
0.4
0.2
0
I
, I (ON) – –
S
D
I
, I (ON) – –
S
D
I
(OFF) – +
D
I
(OFF) + –
S
0.2
0
I
(OFF) + –
S
–0.2
–0.4
–0.6
I
(OFF) – +
S
I
(OFF) – +
D
–0.2
–0.4
I
(OFF) + –
D
I
(OFF) – +
S
I
(OFF) + –
D
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. 0 | Page ±± of 20
ADG5412/ADG5413
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
V
= 25°C
= +15V
SS
T
V
V
= 25°C
= +15V
DD
A
DD
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= –15V
= –15V
SS
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
1k
10k
100k
1M
10M
100M
1G
1G
40
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 16. Off Isolation vs. Frequency, 15 V Dual Supply
Figure 19. ACPSRR vs. Frequency, 15 V Dual Supply
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
LOAD = 1kΩ
A
T
= 25°C
= +15V
SS
A
DD
T
= 25°C
V
V
= –15V
V
= 12V, V = 0V, V = 6V p-p
SS
DD
S
V
= 36V, V = 0V, V = 18V p-p
SS
DD
S
V
V
= 15V, V = 15V, V = 15V p-p
SS
DD
S
= 20V, V = 20V, V = 20V p-p
SS
DD
S
0
5
10
FREQUENCY (MHz)
15
20
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 17. Crosstalk vs. Frequency, 15 V Dual Supply
Figure 20. THD + N vs. Frequency, 15 V Dual Supply
500
450
400
350
300
250
200
150
100
50
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
T
V
V
= 25°C
T
= 25°C
A
A
= +15V
= –15V
DD
SS
V
V
= +20V
= –20V
DD
SS
V
V
= +36V
= 0V
DD
SS
V
DD
= +15V
= –15V
V
V
= +12V
= 0V
DD
SS
V
SS
0
–20
–10
0
10
(V)
20
30
1k
10k
100k
1M
10M
100M
1G
V
FREQUENCY (Hz)
S
Figure 18. Charge Injection vs. Source Voltage
Figure 21. Bandwidth
Rev. 0 | Page ±2 of 20
ADG5412/ADG5413
350
300
250
200
150
100
50
tON (12V)
tON (±20V)
tOFF (±15V)
tON (±15V)
tON (36V)
tOFF (12V)
tOFF (36V)
tOFF (±20V)
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 22. tON, tOFF Times vs. Temperature
Rev. 0 | Page ±3 of 20
ADG5412/ADG5413
TEST CIRCUITS
I
(OFF)
A
I
(OFF)
A
S
D
Sx
Dx
I
(ON)
A
D
Sx
Dx
V
V
D
V
S
S
V
D
Figure 23. On Leakage
Figure 27. Off Leakage
V
V
SS
DD
0.1µF
0.1µF
AUDIO PRECISION
V
V
DD
SS
R
S
I
DS
Sx
Dx
INx
V
S
V p-p
V1
V
OUT
V
IN
R
L
1kꢀ
Sx
Dx
GND
V
S
R
= V /I
DS
ON
1
Figure 24. On Resistance
Figure 28. THD + Noise
V
V
DD
SS
V
V
SS
0.1µF
0.1µF
DD
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
V
OUT
DD
SS
S1
R
L
50Ω
Sx
Dx
50ꢀ
Dx
R
50Ω
L
INx
S2
V
S
V
V
S
OUT
V
IN
GND
R
L
50ꢀ
GND
V
OUT
V
WITH SWITCH
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
OUT
V
S
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 25. Channel-to-Channel Crosstalk
Figure 29. Bandwidth
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
Sx
Dx
50Ω
50Ω
INx
IN
V
S
V
OUT
V
R
L
50Ω
GND
V
OUT
OFF ISOLATION = 20 log
V
S
Figure 26. Off Isolation
Rev. 0 | Page ±4 of 20
ADG5412/ADG5413
V
V
DD
SS
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
S1
V
SS
D1
90%
DD
90%
V
V
OUT1
OUT2
V
V
V
S1
OUT1
C
35pF
R
300ꢀ
L
L
S2
D2
V
S2
OUT2
C
35pF
R
300ꢀ
L
L
90%
90%
IN1,
IN2
0V
ADG5413
GND
tD
tD
Figure 30. Break-Before-Make Time Delay, tD
V
V
DD
DD
SS
0.1µF
0.1µF
ADG5412
V
50%
50%
IN
V
V
SS
V
L
OUT
Sx
Dx
R
300ꢀ
C
L
V
S
35pF
INx
90%
90%
V
OUT
GND
tOFF
tON
Figure 31. Switching Times
V
V
DD
DD
SS
V
V
SS
V
ADG5412
IN
V
R
S
OUT
Sx
Dx
ON
OFF
C
1nF
L
V
S
IN
V
OUT
ΔV
OUT
Q
= C × ΔV
L
OUT
INJ
GND
Figure 32. Charge Injection
Rev. 0 | Page ±5 of 20
ADG5412/ADG5413
TERMINOLOGY
IDD
CIN
I
DD represents the positive supply current.
CIN is the digital input capacitance.
ISS
tON
t
I
SS represents the negative supply current.
ON represents the delay between applying the digital control
input and the output switching on.
VD, VS
VD and VS represent the analog voltage on Terminal D and
tOFF
Terminal S, respectively.
tOFF represents the delay between applying the digital control
input and the output switching off.
RON
RON represents the ohmic resistance between Terminal D and
tD
Terminal S.
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
Charge Injection
analog signal range is represented by RFLAT (ON)
.
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINL
On Response
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
On response is the frequency response of the on switch.
Insertion Loss
V
Insertion loss is the loss due to the on resistance of the switch.
I
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
AC Power Supply Rejection Ratio (ACPSRR)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the ability of
the part to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. 0 | Page ±6 of 20
ADG5412/ADG5413
TRENCH ISOLATION
NMOS
PMOS
In the ADG5412 and ADG5413, an insulating oxide layer
(trench) is placed between the NMOS and the PMOS transistors
of each CMOS switch. Parasitic junctions, which occur between
the transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed, and the result is a latch-
up proof switch.
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 33. Trench Isolation
Rev. 0 | Page ±7 of 20
ADG5412/ADG5413
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5412/ADG5413 high voltage switches
allow single-supply operation from 9 V to 40 V and dual-supply
operation from 9 V to 22 V. The ADG5412/ADG5413 (as
well as other select devices within the same family) achieve an
8 kV human body model ESD rating, which provides a robust
solution eliminating the need for separate protect circuitry
designs in some applications.
Rev. 0 | Page 18 of 20
ADG5412/ADG5413
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
1
0.65
BSC
12
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
5
9
8
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG54±2BRUZ
ADG54±2BRUZ-REEL7
ADG54±2BCPZ-REEL7
ADG54±3BRUZ
ADG54±3BRUZ-REEL7
ADG54±3BCPZ-REEL7
Temperature Range
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
Package Description
Package Option
RU-±6
RU-±6
CP-±6-±7
RU-±6
RU-±6
±6-Lead Thin Shrink Small Outline Package [TSSOP]
±6-Lead Thin Shrink Small Outline Package [TSSOP]
±6-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
±6-Lead Thin Shrink Small Outline Package [TSSOP]
±6-Lead Thin Shrink Small Outline Package [TSSOP]
±6-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-±6-±7
± Z = RoHS Compliant Part.
Rev. 0 | Page ±9 of 20
ADG5412/ADG5413
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09202-0-7/10(0)
Rev. 0 | Page 20 of 20
相关型号：
ADG5413BFBRUZ
Bidirectional Fault Protection and Detection, 10 Ω RON, Quad SPST Switches, 2 x NO, 2 x NC
ADI
©2020 ICPDF网 联系我们和版权申明