ADG5421FBCPZ-RL7 [ADI]
±60 V Fault Protection and Detection, 11 Ω RON, Dual SPST Switch;
| 型号： | ADG5421FBCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | ±60 V Fault Protection and Detection, 11 Ω RON, Dual SPST Switch |
| 文件： | 总31页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
60 V Fault Protection and Detection,
11 Ω RON, Dual SPST Switch
ADG5421F
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Overvoltage fault protection up to 60 V on S1 and S2 pins
Power-off protection up to 60 V on S1 and S2 pins
Known state without digital inputs present
Low on resistance of 11 Ω typical
ADG5421F
D1
D2
S1
S2
Ultraflat, on resistance
Latch-up immune under any circumstance
3.5 kV human body model (HBM) ESD rating
FAULT
DETECTION
AND SWITCH
DRIVER
FF
VSS to VDD −2 V signal range
IN1 IN2
Fully specified at 15 V, 20 V, +12 V, and +36 V
5 V to 22 V dual-supply operation
8 V to 44 V single-supply operation
Figure 1.
10-lead, 3 mm × 2 mm, LFCSP
APPLICATIONS
Analog input and output modules
Process control and distributed control systems
Data acquisition
COMPANION PRODUCTS
Precision 24-Bit ADC: AD7768-1
Precision 16-Bit, 2 MSPS SAR ADC: AD4000
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
GENERAL DESCRIPTION
The ADG5421F is a dual SPST, low on resistance switch that
features overvoltage protection, power-off protection, and
overvoltage detection on the source pins.
PRODUCT HIGHLIGHTS
1. Source pins are protected against voltages greater than the
supply rails, up to −60 V and +60 V in both powered and
unpowered state.
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. When
powered, if the analog input signal levels on either of the Sx pins
exceed VDD or VSS by the threshold voltage, VT, both switches
turn off together, and the open-drain fault flag (FF) pin pulls to a
logic low. Input signal levels up to +60 V or −60 V relative to
ground are blocked in both the powered and unpowered
condition.
2. Overvoltage detection with digital output indicates
operating state of switches.
3. Trench isolation guards against latch-up.
4. The ADG5421F can operate from a dual supply of 5 V up
to 22 V or a single power supply of +8 V up to +44 V.
5. Negative channel metal oxide semiconductor (NMOS)
only architecture requires 2 V headroom towards VDD and
provides low RON and low RON flatness across the signal
range of VSS to VDD − 2 V.
The switches turn on with a Logic 1 input and conduct equally
well in both directions. The digital input is compatible with
1.8 V logic inputs over the full operating supply range.
Rev. 0
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Technical Support
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ADG5421F
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Typical Performance Characteristics .......................................... 16
Test Circuits.................................................................................... 21
Terminology.................................................................................... 25
Theory of Operation ...................................................................... 26
Switch Architecture ................................................................... 26
Overvoltage Fault Protection ................................................... 27
Applications Information ............................................................. 28
Power Supply Rails..................................................................... 28
Power Supply Recommendations............................................ 28
Power Supply Sequencing Protection ..................................... 28
Signal Range................................................................................ 28
Intelligent Fault Detection........................................................ 28
Switch in a Known State............................................................ 28
High Voltage Surge Suppression ............................................. 29
Related Products......................................................................... 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Companion Products....................................................................... 1
Product Highlights........................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
15 V Dual Supply....................................................................... 3
20 V Dual Supply....................................................................... 5
12 V Single Supply ....................................................................... 8
36 V Single Supply ..................................................................... 11
Continuous Current per Channel, S or D............................... 13
Absolute Maximum Ratings ......................................................... 14
Thermal Resistance.................................................................... 14
Electrostatic Discharge (ESD) Ratings.................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions .......................... 15
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 31
Data Sheet
ADG5421F
SPECIFICATIONS
Table 1. Operating Supply Voltages
Parameter
SUPPLY VOLTAGE
Dual
Min
Typ
Max
Unit
±±
8
±22
44
V
V
Single
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter
+25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VDD = +13.± V, VSS = −13.± V
VSS to
VDD − 2
V
On Resistance, RON
11.±
Ω typ
Source voltage (VS) = VSS to 10 V,
source current (IS) = 10 mA, see
Figure 31
14
11
13.±
0.3
0.7
0.02
0.06
0.02
0.2
17.±
17
20.±
20
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 9 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VS = VSS to 10 V, IS = 10 mA
VDD = +16.± V, VSS = −16.± V
On-Resistance Flatness, RFLAT (ON)
On-Resistance Matching, RMATCH (ON)
0.8
0.9
0.1
0.1
0.3±
0.4±
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.0±
±0.2
nA typ
VS = ±10 V, drain voltage (VD) = 10 V,
see Figure 32
±2.±
±22
±8
nA max
nA max
VS = ±10 V, drain voltage (VD) = 10 V
VS = ±10 V, drain voltage (VD) = 10 V,
−40°C to +10±°C
Drain Off Leakage, ID (Off)
±0.0±
±0.2
nA typ
nA max
nA max
VS = ±10 V, VD = 10 V, see Figure 32
VS = ±10 V, VD = 10 V
±2.±
±3.±
±22
±8
VS = ±10 V, VD = 10 V,
−40°C to +10±°C
VS = ±10 V, VD = ±10 V, see Figure 33
Channel On Leakage, ID (On), IS (On)
±0.0±
±0.3
nA typ
±30
±14
nA max VS = ±10 V, VD = ±10 V
nA max VS = ±10 V, VD = ±10 V,
−40°C to +10±°C
FAULT
Threshold Voltage, VT
Source Leakage Current, IS
With Overvoltage
0.7
V
See Figure 2±
±30
µA typ
µA typ
V
DD = +16.± V, VSS = −16.± V,
GND = 0 V, VS = ±60 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
Power Supplies Grounded or
Floating
±±.±
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 3±
Rev. 0 | Page 3 of 31
ADG5421F
Data Sheet
Parameter
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to +85°C −40°C to +125°C Unit
nA typ
Test Conditions/Comments
±0.1
±0.2
±0.1
±0.2
V
DD = +16.± V, VSS = −16.± V,
GND = 0 V, VS = ±60 V, see Figure 34
DD = +16.± V, VSS = −16.± V,
GND = 0 V, VS = ±60 V
DD = 0 V, VSS = 0 V, GND = 0 V,
±2
±20
nA max
nA typ
nA max
µA typ
V
Power Supplies Grounded
Power Supplies Floating
V
VS = ±60 V, IN = 0 V, see Figure 3±
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
±2
±20
±0.1
VDD = floating, VSS = floating, GND =
0 V, VS = ±60 V, IN = 0 V, see Figure 3±
DIGITAL INPUTS AND OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
1.3
0.8
V min
V max
µA typ
µA max
pF typ
V max
Input Low or High Current, IINL or IINH
0.7
Input voltage (VIN) = 0 V or ± V
VIN = 0 V or ± V
1
Digital Input Capacitance, CIN
Output Voltage Low, VOL
DYNAMIC CHARACTERISTICS
On Time, tON
±
0.4
Fault flag current (IFF) = 2 mA
11.2
µs typ
Load resistance (RL) = 300 Ω,
load capacitance (CL) = 3± pF,
VS = 10 V, see Figure 4±
14.1
140
14.1
14.1
µs max
ns typ
RL = 300 Ω, CL = 3± pF, VS = 10 V
RL = 300 Ω, CL = 3± pF, VS = 10 V, see
Figure 4±
Off Time, tOFF
170
10
7.7
170
7.6
170
7.6
ns max
µs typ
µs min
RL = 300 Ω, CL = 3± pF, VS = 10 V
RL = 300 Ω, CL = 3± pF, VS = 10 V
RL = 300 Ω, CL = 3± pF, VS = 10 V
Break-Before-Make Time Delay, tD
Overvoltage Response Time, tRESPONSE
Positive
160
180
420
±10
9.8
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
RL = 1 kΩ, CL = ± pF, see Figure 40
RL = 1 kΩ, CL = ± pF
RL = 1 kΩ, CL = ± pF, see Figure 41
RL = 1 kΩ, CL = ± pF
RL = 1 kΩ, CL = ± pF, see Figure 42
RL = 1 kΩ, CL = ± pF
Pull-up resistor (RPULLUP) = 1 kΩ, CL =
12 pF, pull-up voltage (VPULL_UP) = ± V,
see Figure 43
190
±40
12.8
190
±70
12.8
Negative
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
12.8
110
130
1.8
140
2.6
140
2.6
ns max
µs typ
µs max
pC typ
dB typ
dB typ
% typ
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = ± V
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = ± V, see Figure 44
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = ± V
VS = 0 V, source resistor (RS) = 0 Ω,
CL = 1 nF, see Figure 46
RL = ±0 Ω, CL = ± pF,
frequency (f) = 1 MHz, see Figure 36
RL = ±0 Ω, CL = ± pF, f = 1 MHz, see
Figure 37
Interrupt Flag Recovery Time, tDIGREC
2.4
Charge Injection, QINJ
Off Isolation
−13±
−8±
−78
0.001
Channel to Channel Crosstalk
Total Harmonic Distortion Plus Noise,
THD + N
RL = 10 kΩ, VS = 10 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
Rev. 0 | Page 4 of 31
Data Sheet
ADG5421F
Parameter
−3 dB Bandwidth
Insertion Loss
+25°C
630
−0.9±
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
MHz typ RL = ±0 Ω, CL = ± pF, see Figure 38
dB typ
RL = ±0 Ω, CL = ± pF, f = 1 MHz, see
Figure 38
Source Off Capacitance, CS (Off)
Drain Off Capacitance, CD (Off)
Drain On Capacitance and Source On
Capacitance, CD (On) and CS (On)
7
±
11
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Drain On Capacitance and Source On
Capacitance Flatness, CDFLAT (On)
and CSFLAT (On)
Capacitance Matching, CMATCH (On)
POWER REQUIREMENTS
2.±
0.3
pF typ
pF typ
VS = VSS to VDD − 2 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VDD = +16.± V, VSS = −16.± V, GND = 0 V,
digital inputs = 0 V or +± V
Normal Mode
Positive Supply Current, IDD
130
20±
±±
90
7±
µA typ
µA max
µA typ
µA max
µA typ
µA max
20±
90
GND Current, IGND
Negative Supply Current, ISS
11±
11±
Fault Mode
IDD
VS = ±60 V
18±
270
1±±
210
±±
µA typ
µA max
µA typ
µA max
µA typ
µA max
270
210
90
IGND
ISS
90
20 V DUAL SUPPLY
VDD = 20 V 10%, VSS = −20 V 10%, and GND = 0 V, unless otherwise noted.
Table 3.
Parameter
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VDD = +18 V, VSS = −18 V
VSS to
VDD − 2
V
RON
11.±
Ω typ
VS = VSS to 1± V, IS = 10 mA,
see Figure 31
14
11
13.±
0.6
0.7
0.02
0.06
0.02
0.2
17.±
17
20.±
20
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to 1± V, IS = 10 mA
VS = VSS to 13.± V, IS = 10 mA
VS = VSS to 13.± V, IS = 10 mA
VS = VSS to 1± V, IS = 10 mA
VS = VSS to 1± V, IS = 10 mA
VS = VSS to 13.± V, IS = 10 mA
VS = VSS to 13.± V, IS = 10 mA
VS = VSS to 1± V, IS = 10 mA
VS = VSS to 1± V, IS = 10 mA
RFLAT (ON)
0.8
0.9
0.1
0.1
RMATCH (ON)
0.3±
0.4±
Rev. 0 | Page ± of 31
ADG5421F
Data Sheet
Parameter
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
LEAKAGE CURRENTS
IS (Off)
VDD = +22 V, VSS = −22 V
±0.0±
±0.2
nA typ
nA max
nA max
VS = ±1± V, VD = 1± V, see Figure 32
±2.±
±22
±8
VS = ±1± V, VD = 1± V
VS = ±1± V, VD = 1± V,
−40°C to +10±°C
ID (Off)
±0.0±
±0.2
nA typ
nA max
nA max
VS = ±1± V, VD = 1± V, see Figure 32
VS = ±1± V, VD = 1± V
±2.±
±3.±
±22
±8
VS = ±1± V, VD = 1± V,
−40°C to +10±°C
VS = ±1± V, VD = ±1± V, see Figure 33
VS = ±1± V, VD = ±1± V
VS = ±1± V, VD = ±1± V,
−40°C to +10±°C
ID (On), IS (On)
±0.0±
±0.3
nA typ
nA max
nA max
±30
±14
FAULT
VT
0.7
V typ
See Figure 2±
IS
With Overvoltage
±30
µA typ
µA typ
VDD = +22 V, VSS = −22 V,
GND = 0 V, VS = ±60 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 3±
Power Supplies Grounded or
Floating
±±.±
ID
With Overvoltage
±0.1
±0.2
±0.1
±0.2
nA typ
nA max
nA typ
nA max
µA typ
VDD = +22 V, VSS = −22 V,
GND = 0 V, VS = ±60 V, see Figure 34
VDD = +22 V, VSS = −22 V,
GND = 0 V, VS = ±60 V
VDD = 0 V, VSS = 0 V, GND = 0 V,
±2
±2
±20
Power Supplies Grounded
Power Supplies Floating
VS = ±60 V, IN = 0 V, see Figure 3±
±20
V
DD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V
DD = floating, VSS = floating, GND =
±0.1
V
0 V, VS = ±60 V, IN = 0 V, see Figure 3±
DIGITAL INPUTS AND OUTPUTS
VINH
VINL
IINL or IINH
1.3
0.8
V min
V max
µA typ
µA max
pF typ
V max
0.7
VIN = 0 V or ± V
VIN = 0 V or ± V
1
CIN
VOL
±
0.4
IFF = 2 mA
DYNAMIC CHARACTERISTICS
tON
12.6
µs typ
RL = 300 Ω, CL = 3± pF, VS = 10 V,
see Figure 4±
1±.9
140
1±.9
1±.9
µs max
ns typ
RL = 300 Ω, CL = 3± pF, VS = 10 V
RL = 300 Ω, CL = 3± pF, VS = 10 V,
see Figure 4±
tOFF
160
11.±
8.9
160
8.8
160
8.8
ns max
µs typ
µs min
RL = 300 Ω, CL = 3± pF, VS = 10 V
RL = 300 Ω, CL = 3± pF, VS = 10 V
RL = 300 Ω, CL = 3± pF, VS = 10 V
tD
Rev. 0 | Page 6 of 31
Data Sheet
ADG5421F
Parameter
tRESPONSE
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
Positive
160
190
360
440
11.7
14.8
120
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
RL = 1 kΩ, CL = ± pF, see Figure 40
RL = 1 kΩ, CL = ± pF
RL = 1 kΩ, CL = ± pF, see Figure 41
RL = 1 kΩ, CL = ± pF
RL = 1 kΩ, CL = ± pF, see Figure 42
RL = 1 kΩ, CL = ± pF
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = ± V, see Figure 43
190
460
14.8
190
490
14.9
Negative
tRECOVERY
tDIGRESP
140
2.2
140
3
140
3
ns max
µs typ
µs max
pC typ
dB typ
dB typ
% typ
RPULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = ± V
tDIGREC
R
PULLUP = 1 kΩ, CL = 12 pF,
VPULL_UP = ± V, see Figure 44
PULLUP = 1 kΩ, CL = 12 pF,
2.8
R
VPULL_UP = ± V
VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 46
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 36
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 37
QINJ
−1±0
−8±
−78
0.001
Off Isolation
Channel to Channel Crosstalk
THD + N
RL = 10 kΩ, VS = 10 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
−3 dB Bandwidth
Insertion Loss
630
−0.9±
MHz typ RL = ±0 Ω, CL = ± pF, see Figure 38
dB typ
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 38
CS (Off)
CD (Off)
CD (On), CS (On)
CDFLAT (On), CSFLAT (On)
CMATCH (On)
6
±
11
2.±
0.3
pF typ
pF typ
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
POWER REQUIREMENTS
VDD = +22 V, VSS = −22 V, GND = 0 V,
digital inputs = 0 V or +± V
Normal Mode
IDD
130
20±
±±
90
7±
µA typ
µA max
µA typ
µA max
µA typ
µA max
20±
90
IGND
ISS
11±
11±
Fault Mode
IDD
VS = ±60 V
18±
270
1±±
210
±±
µA typ
µA max
µA typ
µA max
µA typ
µA max
270
210
90
IGND
ISS
90
Rev. 0 | Page 7 of 31
ADG5421F
Data Sheet
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V 10%, and GND = 0 V, unless otherwise noted.
Table 4.
Parameter
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VDD = 10.8 V, VSS = 0 V
VSS to
VDD − 2
V
RON
11.±
Ω typ
VS = 0 V to 7.± V, IS = 10 mA,
see Figure 31
14.±
11
13.±
0.7
1.2±
0.01
0.04
0.02
0.2
18
21.±
20
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to 7.± V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 7.± V, IS = 10 mA
VS = 0 V to 7.± V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 6 V, IS = 10 mA
VS = 0 V to 7.± V, IS = 10 mA
VS = 0 V to 7.± V, IS = 10 mA
VDD = 13.2 V, VSS = 0 V
17
RFLAT (ON)
1.3
0.06
0.3±
1.3±
0.06
0.4±
RMATCH (ON)
LEAKAGE CURRENTS
IS (Off)
±0.0±
±0.2
nA typ
VS = 1 V to 10 V, VD = 10 V to 1 V,
see Figure 32
VS = 1 V to 10 V, VD = 10 V to 1 V
VS = 1 V to 10 V, VD = 10 V to 1 V,
−40°C to +10±°C
VS = 1 V to 10 V, VD = 10 V to 1 V,
see Figure 32
VS = 1 V to 10 V, VD = 10 V to 1 V
VS = 1 V to 10 V, VD = 10 V to 1 V,
−40°C to +10±°C
VS = 1 V to 10 V, VD = 10 V to 1 V,
see Figure 33
VS = 1 V to 10 V, VD = 10 V to 1 V
±2.±
±2.±
±3.±
±22
±8
nA max
nA max
ID (Off)
±0.0±
±0.2
nA typ
±22
±8
nA max
nA max
ID (On), IS (On)
±0.0±
±0.3
nA typ
±30
±14
nA max
nA max
VS = 1 V to 10 V, VD = 10 V to 1 V,
−40°C to +10±°C
FAULT
VT
0.7
V typ
See Figure 2±
IS
With Overvoltage
±30
µA typ
µA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 3±
Power Supplies Grounded or
Floating
±±.±
ID
With Overvoltage
±0.1
±0.2
±0.1
±0.2
nA typ
nA max
nA typ
nA max
µA typ
V
DD = +13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, see Figure 34
DD = +13.2 V, VSS = 0 V, GND = 0 V,
VS = ±60 V
DD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 3±
DD = 0 V, VSS = 0 V, GND = 0 V,
±2
±2
±20
V
Power Supplies Grounded
Power Supplies Floating
V
±20
V
VS = ±60 V, IN = 0 V
VDD = floating, VSS = floating, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 3±
±0.1
Rev. 0 | Page 8 of 31
Data Sheet
ADG5421F
Parameter
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
DIGITAL INPUTS AND OUTPUTS
VINH
VINL
IINL or IINH
1.3
0.8
V min
V max
µA typ
µA max
pF typ
V max
0.7
VIN = 0 V or ± V
VIN = 0 V or ± V
1
CIN
VOL
±
0.4
IFF = 2 mA
DYNAMIC CHARACTERISTICS
tON
±.3
µs typ
RL = 300 Ω, CL = 3± pF, VS = 8 V,
see Figure 4±
6.3
200
6.3
6.3
µs max
ns typ
RL = 300 Ω, CL = 3± pF, VS = 8 V
RL = 300 Ω, CL = 3± pF, VS = 8 V,
see Figure 4±
tOFF
240
4.±
3.±
240
3.4
240
3.4
ns max
µs typ
µs min
RL = 300 Ω, CL = 3± pF, VS = 8 V
RL = 300 Ω, CL = 3± pF, VS = 8 V
RL = 300 Ω, CL = 3± pF, VS = 8 V
tD
tRESPONSE
Positive
210
2±0
600
700
±.3
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
RL = 1 kΩ, CL = ± pF, see Figure 40
RL = 1 kΩ, CL = ± pF
RPULLUP = 1 kΩ, CL = ± pF, see Figure 41
RPULLUP = 1 kΩ, CL = ± pF
RL = 1 kΩ, CL = ± pF, see Figure 42
RL = 1 kΩ, CL = ± pF
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V,
2±0
700
6.±
2±0
700
6.6
Negative
tRECOVERY
6.2
110
tDIGRESP
see Figure 43
130
1.6
130
2.4
130
2.4
ns max
µs typ
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V,
see Figure 44
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V
VS = 6 V, RS = 0 Ω, CL = 1 nF,
see Figure 46
tDIGREC
2.1
−7±
µs max
pC typ
QINJ
Off Isolation
−69
dB typ
dB typ
% typ
RL = ±0 Ω, CL = ± pF, f = 1 MHz, see
Figure 36
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 37
Channel to Channel Crosstalk
THD + N
−78
0.0018
RL = 10 kΩ, VS = 6 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
−3 dB Bandwidth
Insertion Loss
±70
−0.9±
MHz typ RL = ±0 Ω, CL = ± pF, see Figure 38
dB typ
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 38
CS (Off)
CD (Off)
CD (On), CS (On)
CDFLAT (On), CSFLAT (On)
CMATCH (On)
8
7
11
2
0.4
pF typ
pF typ
pF typ
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
Rev. 0 | Page 9 of 31
ADG5421F
Data Sheet
Parameter
POWER REQUIREMENTS
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
DD = 13.2 V, VSS = 0 V, GND = 0 V,
digital inputs = 0 V or ± V
V
Normal Mode
IDD
12±
200
4±
80
80
µA typ
µA max
µA typ
µA max
µA typ
µA max
200
80
IGND
ISS
120
120
Fault Mode
IDD
VS = ±60 V
18±
270
1±±
210
±±
µA typ
µA max
µA typ
µA max
µA typ
µA max
270
210
90
IGND
ISS
90
Rev. 0 | Page 10 of 31
Data Sheet
ADG5421F
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V 10%, and GND = 0 V, unless otherwise noted.
Table 5.
Parameter
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VDD = 32.4 V, VSS = 0 V
VSS to
VDD − 2
V
RON
12
Ω typ
VS = 0 V to 29.± V, IS = 10 mA, see
Figure 31
14.±
11
13.±
1.1
1.2±
0.01
0.04
0.02
0.2
18
21.±
20
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to 29.± V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 29.± V, IS = 10 mA
VS = 0 V to 29.± V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 27 V, IS = 10 mA
VS = 0 V to 29.± V, IS = 10 mA
VS = 0 V to 29.± V, IS = 10 mA
VDD = 39.6 V, VSS = 0 V
17
RFLAT (ON)
1.3
0.06
0.3±
1.3±
0.06
0.4±
RMATCH (ON)
LEAKAGE CURRENTS
IS (Off)
±0.0±
±0.2
nA typ
VS = 1 V to 30 V, VD = 30 V to 1 V,
see Figure 32
VS = 1 V to 30 V, VD = 30 V to 1 V
VS = 1 V to 30 V, VD = 30 V to 1 V,
−40°C to +10±°C
VS = 1 V to 30 V, VD = 30 V to 1 V,
see Figure 32
VS = 1 V to 30 V, VD = 30 V to 1 V
VS = 1 V to 30 V, VD = 30 V to 1 V,
−40°C to +10±°C
VS = 1 V to 30 V, VD = 30 V to 1 V,
see Figure 33
VS = 1 V to 30 V, VD = 30 V to 1 V
±2.±
±2.±
±3.±
±22
±8
nA max
nA max
ID (Off)
±0.0±
±0.2
nA typ
±22
±8
nA max
nA max
ID (On), IS (On)
±0.0±
±0.3
nA typ
±30
±14
nA max
nA max
VS = 1 V to 30 V, VD = 30 V to 1 V,
−40°C to +10±°C
FAULT
VT
0.7
V typ
See Figure 2±
IS
With Overvoltage
±30
µA typ
µA typ
VDD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V, and VS = −40 V, see Figure 34
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, IN = 0 V or
floating, VS = ±60 V, see Figure 3±
Power Supplies Grounded or
Floating
±±.±
ID
With Overvoltage
±0.1
±0.2
±0.1
±0.2
nA typ
nA max
nA typ
nA max
µA typ
V
DD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V and VS = −40 V, see Figure 34
DD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = +60 V and VS = −40 V
DD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 3±
DD = 0 V, VSS = 0 V, GND = 0 V,
±2
±2
±20
V
Power Supplies Grounded
Power Supplies Floating
V
±20
V
VS = ±60 V, IN = 0 V
VDD = floating, VSS = floating, GND = 0 V,
VS = ±60 V, IN = 0 V, see Figure 3±
±0.1
Rev. 0 | Page 11 of 31
ADG5421F
Data Sheet
Parameter
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
DIGITAL INPUTS AND OUTPUTS
VINH
VINL
IINL or IINH
1.3
0.8
V min
V max
µA typ
µA max
pF typ
V max
0.7
VIN = 0 V or ± V
VIN = 0 V or ± V
1
CIN
VOL
±
0.4
IFF = 2 mA
DYNAMIC CHARACTERISTICS
tON
7.2
µs typ
RL = 300 Ω, CL = 3± pF, VS = 18 V,
see Figure 4±
8.7
200
8.7
8.7
µs max
ns typ
RL = 300 Ω, CL = 3± pF, VS = 18 V
RL = 300 Ω, CL = 3± pF, VS = 18 V,
see Figure 4±
tOFF
240
6
4.7
2±0
4.6
2±0
4.6
ns max
µs typ
µs min
RL = 300 Ω, CL = 3± pF, VS = 18 V
RL = 300 Ω, CL = 3± pF, VS = 18 V
RL = 300 Ω, CL = 3± pF, VS = 18 V
tD
tRESPONSE
Positive
240
290
600
700
6.6
ns typ
ns max
ns typ
ns max
µs typ
µs max
ns typ
RL = 1 kΩ, CL = ± pF, see Figure 40
RL = 1 kΩ, CL = ± pF
RPULLUP = 1 kΩ, CL = ± pF, see Figure 41
RPULLUP = 1 kΩ, CL = ± pF
RL = 1 kΩ, CL = ± pF, see Figure 42
RL = 1 kΩ, CL = ± pF
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V,
290
700
10.8
290
700
11.3
Negative
tRECOVERY
10.7
120
tDIGRESP
see Figure 43
1±0
4.1
1±0
8
1±0
8.±
ns max
µs typ
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V,
see Figure 44
RPULLUP = 1 kΩ, CL = 12 pF, VPULL_UP = ± V
VS = 18 V, RS = 0 Ω, CL = 1 nF,
see Figure 46
tDIGREC
7.8
−11±
µs max
pC typ
QINJ
Off Isolation
−70
dB typ
dB typ
% typ
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 36
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 37
Channel to Channel Crosstalk
THD + N
−78
0.0008
RL = 10 kΩ, VS = 18 V p-p,
f = 20 Hz to 20 kHz, see Figure 39
−3 dB Bandwidth
Insertion Loss
630
−0.9±
MHz typ RL = ±0 Ω, CL = ± pF, see Figure 38
dB typ
RL = ±0 Ω, CL = ± pF, f = 1 MHz,
see Figure 38
CS (Off)
CD (Off)
CD (On), CS (On)
CDFLAT (On), CSFLAT (On)
CMATCH (On)
6
±
10
3.3
0.3
pF typ
pF typ
pF typ
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
VS = VSS to VDD − 2 V, f = 1 MHz
Rev. 0 | Page 12 of 31
Data Sheet
ADG5421F
Parameter
POWER REQUIREMENTS
+25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
DD = 39.6 V, VSS = 0 V, GND = 0 V,
digital inputs = 0 V or ± V
V
Normal Mode
IDD
12±
200
4±
80
80
µA typ
µA max
µA typ
µA max
µA typ
µA max
200
80
IGND
ISS
120
120
Fault Mode
IDD
VS = +60 V and VS = −40 V
18±
270
1±±
210
±±
µA typ
µA max
µA typ
µA max
µA typ
µA max
270
210
90
IGND
ISS
90
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 6.
Parameter
25°C
85°C
125°C
Unit
Test Conditions/Comments
CONTINUOUS CURRENT, S OR D
θJA = 170°C/W
88
81
61
±7
41
39
mA max
mA max
VS = VSS to VDD − ± V
VS = VSS to VDD − 2 V
Rev. 0 | Page 13 of 31
ADG5421F
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 7.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Sx Pins
Value
60 V
−0.3 V to +48 V
−28 V to +0.3 V
−60 V to +60 V
80 V
θ
JA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
JC is the junction to case thermal resistance.
Sx to VDD
Sx to VSS
θ
80 V
VS to VD
80 V
Table 8. Thermal Resistance
Package Type1
CP-10-16
Dx Pins1
VSS − 0.7 V to VDD + 0.7 V or
30 mA, whichever occurs first
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
278 mA (pulsed at 1 ms,
10% duty cycle maximum)
θJA
170
θJC
±8.2
Unit
°C/W
Digital Inputs
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD-±1.
Peak Current, Sx or Dx Pins
Digital Output
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Temperature
Operating Range
Storage Range
Junction
Reflow Soldering Peak, Pb-Free
−40°C to +12±°C
−6±°C to +1±0°C
1±0°C
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADG5421F
As per JEDEC J-STD-020
Table 9. ADG5421F, 10-Lead LFCSP
ESD Model Withstand Threshold (kV)
HBM1
3.±
1 Overvoltages at the Dx pins are clamped by the internal diodes. Limit
current to the maximum ratings given.
Class
2
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
1 This is the HBM for the input and output port to supplies, the input and
output port to the input and output port, and for all other pins.
ESD CAUTION
Rev. 0 | Page 14 of 31
Data Sheet
ADG5421F
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADG5421F
TOP VIEW
(Not to Scale)
1
2
3
4
5
10
9
S1
S2
D1
D2
8
IN1
IN2
FF
7
GND
6
V
V
SS
DD
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
S1
S2
FF
Overvoltage Protected Source Terminal. S1 can be an input or an output.
Overvoltage Protected Source Terminal. S2 can be an input or an output.
Fault Flag Digital Output. The FF pin is an open-drain output that requires an external pull-up resistor. This digital
output pulls low when a fault condition occurs on either of the Sx inputs.
4
±
6
7
8
9
10
GND
VDD
VSS
IN2
IN1
D2
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Most Negative Power Supply Potential.
Logic Control Input.
Logic Control Input.
Drain Terminal. D1 can be an input or an output.
Drain Terminal. D2 can be an input or an output.
D1
Rev. 0 | Page 1± of 31
ADG5421F
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
12.0
20
V
V
= +15V
= –15V
T
= 25°C
DD
A
V
V
= +20V
= –20V
DD
SS
SS
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
18
16
14
+125°C
V
V
= +18V
= –18V
DD
SS
+105°C
+85°C
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +15V
= –15V
DD
12
10
SS
+25°C
V
V
= +13.5V
= –13.5V
DD
SS
8
6
V
V
= +22V
= –22V
DD
SS
–40°C
0
–15
–10
–5
5
10
V , V (V)
S
D
V , V (V)
S
D
Figure 3. On Resistance as a Function of VS, VD (Dual Supply)
Figure 6. On Resistance as a Function of VS, VD for Different Temperatures,
15 V Dual Supply
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
20
V
V
= +20V
= –20V
T
= 25°C
DD
A
SS
V
V
= 10.8V
= 0V
DD
SS
18
16
14
+125°C
+105°C
+85°C
V
V
= 12V
= 0V
DD
SS
12
10
+25°C
8
6
V
V
= 13.2V
= 0V
DD
SS
–40°C
0
0
1
2
3
4
5
6
7
8
9
10 11
–20
–15
–10
–5
5
10
15
V , V (V)
V , V (V)
S D
S
D
Figure 4. On Resistance as a Function of VS, VD (12 V Single Supply)
Figure 7. On Resistance as a Function of VS, VD for Different Temperatures,
20 V Dual Supply
12.0
20
V
V
= 12V
= 0V
T
= 25°C
DD
SS
A
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
18
16
14
+125°C
V
V
= 32.4V
= 0V
DD
SS
+105°C
+85°C
V
V
= 36V
= 0V
DD
SS
12
10
+25°C
8
6
V
V
= 39.6V
= 0V
DD
SS
–40°C
4
0
5
10
15
20
V , V (V)
25
30
35
0
1
2
3
5
6
7
8
V , V (V)
S
D
S
D
Figure 5. On Resistance as a Function of VS, VD (36 V Single Supply)
Figure 8. On Resistance as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Rev. 0 | Page 16 of 31
Data Sheet
ADG5421F
20
6
5
V
V
= 36V
= 0V
V
V
= 12V
= 0V
DD
SS
DD
SS
18
16
14
+125°C
I
(OFF) –+
I
I
(OFF) –+
(OFF) +–
S
D
D
4
I (OFF) +–
S
+105°C
+85°C
I , I (ON) ––
I , I (ON) ++
S
D
S D
3
2
12
10
+25°C
–40°C
1
0
8
6
–1
0
5
10
15
20
25
30
V , V (V)
S
D
TEMPERATURE (°C)
Figure 9. On Resistance as a Function of VS, VD for Different Temperatures,
36 V Single Supply
Figure 12. Leakage Current vs. Temperature, 12 V Single Supply
9
10
V
V
= +15V
= –15V
V
V
= 36V
= 0V
DD
SS
DD
SS
8
7
8
6
4
2
I
(OFF) –+
I
I
(OFF) –+
(OFF) +–
I
(OFF) –+
I
I
(OFF) –+
(OFF) +–
6
S
D
D
S
D
D
I (OFF) +–
I (OFF) +–
S
S
5
I , I (ON) ––
I , I (ON) ++
I , I (ON) ––
I , I (ON) ++
S
D
S
D
S
D
S D
4
3
2
1
0
0
–1
–2
–2
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Leakage Current vs. Temperature, 15 V Dual Supply
Figure 13. Leakage Current vs. Temperature, 36 V Single Supply
10
10
V
V
= +20V
= –20V
V
V
= +15V
= –15V
DD
SS
DD
SS
9
8
8
6
4
2
V
V
= –60V
= +60V
I
(OFF) –+
I
I
(OFF) –+
(OFF) +–
S
S
7
S
D
D
I (OFF) +–
S
6
I , I (ON) ––
I , I (ON) ++
S
D
S D
5
4
3
2
1
0
0
–2
–1
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Leakage Current vs. Temperature, 20 V Dual Supply
Figure 14. Dx Leakage Current vs. Temperature During Overvoltage,
15 V Dual Supply
Rev. 0 | Page 17 of 31
ADG5421F
Data Sheet
10
0
V
V
= +20V
= –20V
V
V
= +15V
= –15V
= 25°C
DD
SS
DD
9
8
SS
–20
–40
T
A
V
V
= –60V
= +60V
S
S
7
6
–60
5
–80
4
–100
–120
3
2
1
–140
–160
0
–1
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 15. Dx Leakage Current vs. Temperature During Overvoltage,
20 V Dual Supply
Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply
8
0
V
V
= 12V
= 0V
T
= 25°C
DD
SS
A
7
6
–20
–40
V
V
= 12V,
= 0V
DD
SS
V
V
= –60V
= +60V
S
S
5
–60
4
–80
V
V
= +15V,
= –15V
3
–100
–120
–140
–160
DD
SS
2
1
V
V
= 36V,
= 0V
DD
SS
0
V
V
= +20V,
= –20V
DD
SS
–1
–2
–180
–200
–40
–30
–20
–10
0
10
20
30
40
V
(V)
S
TEMPERATURE (°C)
Figure 16. Dx Leakage Current vs. Temperature During Overvoltage,
12 V Single Supply
Figure 19. QINJ vs. VS
6
0
V
V
= 36V
= 0V
V
V
= +15V
= –15V
= 25°C
DD
SS
DD
SS
5
–20
–40
T
A
4
3
V
S
= –60V
= +60V
V
S
–60
2
–80
1
–100
–120
0
–1
–2
–140
–160
–3
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 17. Dx Leakage Current vs. Temperature During Overvoltage,
36 V Single Supply
Figure 20. AC Power Supply Rejection Ratio (PSRR) vs. Frequency,
15 V Dual Supply
Rev. 0 | Page 18 of 31
Data Sheet
ADG5421F
0.0030
16
14
12
10
8
R
A
= 10kΩ
L
T
= 25°C
0.0025
0.0020
0.0015
0.0010
SINGLE SUPPLY = 12V
tON (±15V)
tOFF (±15V)
tON (±20V)
tOFF (±20V)
tON (+12V)
tOFF (+12V)
tON (+36V)
tOFF (+36V)
DUAL SUPPLY = ±15V
DUAL SUPPLY = ±20V
6
4
0.0005
0
SINGLE SUPPLY = 36V
2
0
0
4
8
12
16
20
–40
–20
0
20
40
60
80
100
120
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 21. THD + N vs. Frequency
Figure 24. tON, tOFF Times vs. Temperature for Various Supplies
0
0.90
V
V
= +15V
= –15V
DD
SS
–1
–2
–3
–4
–5
–6
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
V
= +15V
= –15V
= 25°C
DD
–7
–8
V
SS
T
A
100
1k
10k
100k
1M
10M
100M
1G
–40
0
15
85
125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 25. VT vs. Temperature, 15 V Dual Supply
Figure 22. Insertion Loss vs. Frequency,
15 V Dual Supply
20
18
16
14
12
10
8
0
–20
–40
OFF SOURCE
OFF DRAIN
ON SOURCE DRAIN
T
= 25°C
V
= +15V
= –15V
= 25°C
A
DD
V
SS
T
A
–60
–80
6
–100
–120
–140
4
2
0
–15
–10
–5
0
5
10
15
100
1k
10k
100k
1M
10M
100M
1G
V
(V)
FREQUENCY (Hz)
S
Figure 26. Pin Capacitance vs. VS
Figure 23. Crosstalk vs. Frequency, 15 V Dual Supply
Rev. 0 | Page 19 of 31
ADG5421F
Data Sheet
1.0
V
V
= +15V
= −15V
T
T
= 25°C
V
V
V
V
= +15V, V = –15V
SS
DD
SS
A
DD
DD
DD
DD
0.8
0.6
0.4
0.2
0
= +20V, V = –20V
SS
= 36V, V = 0V
SS
= 12V, V = 0V
SS
FF
Dx
2
–0.2
–0.4
–0.6
–0.8
–1.0
V
SS
Sx
A
–20
–10
0
10
20
30
CH1 10.0V CH2 10.0V
CH3 10.0V CH4 10.0V
1.00µs
T
CH1
–15.0V
–70.00000ns
V
(V)
S
Figure 27. Pin Capacitance Matching vs. VS
Figure 29. Drain Output Response to Negative Overvoltage
20
16
12
8
Sx
V
V
= +15V
= −15V
V
V
A
= +10V
T
DD
SS
DD
SS
= −10V
T
= 25°C
V
DD
FF
Dx
2
4
0
1
10
100
CH1 10.0V CH2 10.0V
CH3 10.0V CH4 10.0V
1.00µs
A
CH1
15.4V
T
0.000000s
FREQUENCY (MHz)
Figure 30. Large Voltage Signal Voltage vs. Frequency
Figure 28. Drain Output Response to Positive Overvoltage
Rev. 0 | Page 20 of 31
Data Sheet
ADG5421F
TEST CIRCUITS
V
I
I
D
S
Sx
Dx
Sx
Dx
A
A
R
10kΩ
I
L
DS
V
S
|V | > |V | OR |V
DD SS
|
S
R
= V/I
DS
ON
Figure 34. Switch Overvoltage Leakage
Figure 31. On Resistance (IDS Is the Drain to Source Current.)
V
= V = GND = 0V
SS
DD
I
I
D
I
(OFF)
A
I
(OFF)
A
S
S
D
Sx
Dx
Sx
Dx
A
A
R
10kΩ
L
V
V
D
S
V
S
Figure 32. Off Leakage
Figure 35. Switch Unpowered Leakage
I
(ON)
D
Sx
Dx
A
NC
V
D
NC = NO CONNECT
Figure 33. On Leakage
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
Sx
50Ω
INx
V
S
Dx
V
OUT
V
IN
R
L
50Ω
GND
V
OUT
OFF ISOLATION = 20 log
V
S
Figure 36. Off Isolation (VOUT Is the Output Voltage)
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
OUT
S1
R
L
50Ω
Dx
R
L
50Ω
S2
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 37. Channel to Channel Crosstalk
Rev. 0 | Page 21 of 31
ADG5421F
Data Sheet
V
V
SS
DD
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
Sx
50Ω
INx
V
S
Dx
V
OUT
V
IN
R
L
50Ω
GND
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 38. Bandwidth
V
V
SS
DD
0.1µF
0.1µF
AUDIO
PRECISION
V
V
DD
SS
R
S
Sx
V
INx
S
V p-p
Dx
V
OUT
V
R
IN
L
10kΩ
GND
Figure 39. THD + N
V
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
DD
SS
SOURCE
VOLTAGE
V
Sx
Dx
D
(+V
)
S
C *
L
5pF
R
L
V
S
1kΩ
0V
ADG5421F
+tRESPONSE
V
DD
V
× 0.5
DD
OUTPUT
(V
GND
)
D
0V
*INCLUDES TRACK CAPACITANCE
Figure 40. Positive Overvoltage Response Time, tRESPONSE
Rev. 0 | Page 22 of 31
Data Sheet
ADG5421F
V
V
V
V
DD
SS
0.1µF
0.1µF
SOURCE
VOLTAGE
5V
(V )
S
V
– 0.5V
SS
0V
R
1kΩ
PULLUP
DD
SS
V
Sx
Dx
D
C *
L
V
S
5pF
ADG5421F
tRESPONSE
5V
GND
OUTPUT
D
(V ) + 1V
*INCLUDES TRACK CAPACITANCE
Figure 41. Negative Overvoltage Response Time, Single-Supply, tRESPONSE
V
V
DD
DD
SS
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
V
SOURCE
VOLTAGE
V
Sx
Dx
D
(V
)
S
C *
L
5pF
R
L
1kΩ
V
S
0V
ADG5421F
tRECOVERY
OUTPUT
(V
GND
)
D
1V
0V
*INCLUDES TRACK CAPACITANCE
Figure 42. Overvoltage Recovery Time, tRECOVERY
V
V
V
DD
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
SS
SOURCE
VOLTAGE
Sx
Dx
(V
)
S
V
S
0V
5V
ADG5421F
R
PULLUP
tDIGRESP
1kΩ
OUTPUT
FF
C *
L
12pF
OUTPUT
(V
)
GND
FF
0.1V
OUT
0V
*INCLUDES TRACK CAPACITANCE
Figure 43. Interrupt Flag Response Time, tDIGRESP (VFF Is the Fault Flag Voltage)
Rev. 0 | Page 23 of 31
ADG5421F
Data Sheet
V
V
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
DD
SS
SOURCE
VOLTAGE
Sx
Dx
(V )
S
V
S
5V
0V
ADG5421F
R
1kΩ
PULLUP
tDIGREC
OUTPUT
FF
5V
C *
L
12pF
3V
OUTPUT
GND
(V
)
FF
0V
*INCLUDES TRACK CAPACITANCE
Figure 44. Interrupt Flag Recovery Time, tDIGREC
V
V
DD
SS
0.1µF
0.1µF
ADG5421F
V
50%
50%
IN
V
V
SS
DD
V
L
OUT
Sx
Dx
R
300Ω
C
L
V
S
35pF
INx
90%
V
OUT
10%
GND
tOFF
tON
Figure 45. Switching Times, tON and tOFF
V
V
V
DD
SS
0.1µF
0.1µF
ADG5421F
V
DD
SS
V
IN
V
R
OUT
S
Sx
Dx
OFF
ON
C
1nF
L
V
S
INx
V
OUT
ΔV
OUT
Q
= C × ΔV
L
OUT
INJ
GND
Figure 46. Charge Injection, QINJ
Rev. 0 | Page 24 of 31
Data Sheet
ADG5421F
TERMINOLOGY
IDD
tOFF
tOFF represents the delay between applying the digital control
I
DD represents the positive supply current.
input and the output switching off.
ISS
ISS represents the negative supply current.
tDIGRESP
t
DIGRESP is the time required for the FF pin to go low (0.3 V),
VD, VS
measured with respect to voltage on the Sx pin exceeding the
source voltage by 0.5 V.
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
tDIGREC
RON
tDIGREC is the time required for the FF pin to return high,
RON represents the ohmic resistance between the Dx pins and
measured with respect to voltage on the Sx pin falling below
the source voltage plus 0.5 V.
the Sx pins.
RFLAT (ON)
tRESPONSE
RFLAT (ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
IS (Off)
tRECOVERY
IS (Off) is the source leakage current with the switch off.
tRECOVERY represents the delay between an overvoltage on the
Sx pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
VINL
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
digital inputs.
On Response
On response is the frequency response of the on switch.
CD (Off)
CD (Off) represents the off switch Dx pin capacitance, which is
measured with reference to ground.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
CS (Off)
THD + N
CS (Off) represents the off switch Sx pin capacitance, which is
measured with reference to ground.
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. AC PSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pins to the output of the switch
(see Figure 20). The dc voltage on the device is modulated by a
sine wave of 0.62 V p-p.
CIN
CIN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
VT
input and the output switching on.
VT is the voltage threshold at which the overvoltage protection
circuitry engages.
Rev. 0 | Page 25 of 31
ADG5421F
Data Sheet
THEORY OF OPERATION
During overvoltage conditions, the leakage current into and out
of the Sx pins is limited to tens of microamperes and nanoamperes
only for the Dx pins. This limit protects the switches and
connected circuitry from overstresses and restricts the
current drawn from the signal source.
SWITCH ARCHITECTURE
The ADG5421F consists of two switch channels of N channel
diffused metal-oxide semiconductor (NDMOS) transistors.
This construction provides excellent performance in a small
area. The ADG5421F operates as a standard switch when input
signals with a voltage between VSS and VDD − 2 V are applied.
For example, the on resistance is 11 Ω typically, and the INx
pins controls when the switches open or close.
ESD Performance
The ADG5421F has an ESD rating of 3.5 kV for the HBM.
The Dx pins have ESD protection diodes to the rails, and the
voltage at these pins must not exceed the supply voltage. The
Sx pins have specialized ESD protection that allow the signal
voltage to reach 60 V regardless of the supply voltage level.
See Figure 47 for the switch channel overview.
Additional internal circuitry enables the switches to detect
overvoltage inputs by comparing the voltage on both the S1
and S2 pins with the VDD and VSS pins. A signal is considered
overvoltage when the signal exceeds the supply voltages by VT.
VT is typically 0.7 V but can range from 0.76 V at −40°C down
to 0.5 V at +125°C. See Figure 25 to see the change in VT with
the operating temperature.
V
DD
ESD
PROTECTION
ESD
DIODE
Sx
Dx
ESD
DIODE
When an overvoltage condition is detected on either the S1 or
S2 pins, both switches automatically open regardless of the
digital logic state (INx). The S1 to D1 and S2 to D2 become
high impedance and ensure that no current flows through
the switches. In Figure 28, the voltage on the Dx pin follows the
voltage on the Sx pins until the main channel switch turns off
completely, and the drain voltage discharges through the load.
The maximum voltage on the drain is limited by the internal
ESD diodes and the rate at which the output voltage discharges
is dependent on the load at the Dx pins.
FAULT
DETECTOR
SWITCH
DRIVER
V
SS
AND
INx
Figure 47. Switch Channel and Control Function
Trench Isolation
In the ADG5421F, an insulating oxide layer (trench) is placed
between the NDMOS and the P-channel DMOS (PDMOS)
transistors in the circuit. Parasitic junctions that occur between
the transistors in the junction isolated switches are eliminated,
and the result is a switch that is latch-up immune under all
circumstances. These devices pass the JESD78D latch-up test.
The maximum voltage that can be applied to any source input
is +60 V or −60 V. When the ADG5421F is powered using a
single supply of 25 V or greater, the maximum negative signal
level reduces to remain within the 80 V maximum rating. For
example, at VDD = +40 V, the maximum negative signal drops
from −60 V to −40 V. Construction of the process allows the
channel to withstand 80 V across either switch when the
switches are open. Note that these overvoltage limits apply
whether the power supplies are present or not.
NDMOS
PDMOS
P WELL
N WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 48. Trench Isolation
Rev. 0 | Page 26 of 31
Data Sheet
ADG5421F
The switches respond to a voltage on either of the Sx pins that
exceeds VDD or VSS by VT by turning off. The absolute input
voltage limits are −60 V and +60 V, while maintaining an
+80 V limit between the Sx pins and the supply rails. The
switches remain off until the voltage at the Sx pins return to
between VDD and VSS.
OVERVOLTAGE FAULT PROTECTION
When the voltage at the Sx inputs exceed VDD or VSS by VT, both
switches turn off, or, if the device is unpowered, the switches
remain off. Both switch inputs remain high impedance regardless
of the digital input state or the load resistance, and the output
acts as a virtual open circuit. Signal levels up to +60 V and −60 V
are blocked in both the powered and unpowered condition as
long as the +80 V absolute maximum rating limitation between
the Sx pins and VDD or VSS pins is met (see Figure 49). For example
with a +40 V single-supply, the overvoltage protection is +60 V
and −40 V.
When powered by the 15 V dual supply, the positive tRESPONSE
is typically 160 ns, and tRECOVERY is 9.8 µs. These values vary with
different supply voltage and output load conditions.
Exceeding 60 V on either Sx input may damage the ESD
protection circuitry on the ADG5421F.
V
DD
Power-Off Protection
When no power supplies are present, the switches remain in an
off state, and the switch inputs are high impedance. This state
ensures that no current flows and prevents damage to the
switches or downstream circuitry. The switch outputs are a
virtual open circuit.
80V
80V
ADG5421F
Dx
Sx
The switches remain off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to 60 V
are blocked when powered off.
V
SS
Figure 49. Sx to VDD or VSS Maximum Rating
Overvoltage Interrupt Flag
Power-On Protection
The voltages on the Sx inputs of the ADG5421F are
continuously monitored, and the active low digital output pin,
FF, indicates the fault state.
To activate the switches, the three following conditions must be
meet:
The voltage on the FF pin indicates if either of the Sx pins are
experiencing a fault condition. The FF pin is an open-drain
output that requires an external pull-up resistor. The output of
the FF pin is high when both the Sx pins are within the normal
operating range. If either of the Sx pin voltages exceeds the
supply voltage (VDD or VSS) by VT, the FF output provides a low
impedance path to GND.
•
•
•
The minimum supply operating conditions in Table 1.
The input signal must be between VSS − VT and VDD + VT.
The digital logic control input, INx, is on.
When the switches are on, signal levels from VSS up to VDD − 2 V
are passed.
Rev. 0 | Page 27 of 31
ADG5421F
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY SEQUENCING PROTECTION
The ADG5421F overvoltage protected switches provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments where overvoltage signals can be
present, and the system must remain operational both during
and after an overvoltage occurs.
When the ADG5421F is off, the switch channels remain open
and signals from −60 V to +60 V can be applied without
damaging the device. The switch channels only close when the
supplies are connected, a suitable digital control signal is placed
on the INx pins, and the signal is within the normal operating
range. Note that placing the ADG5421F between external
connectors and sensitive components offers protection in
systems where a signal is presented to the Sx pins before the
supply voltages are available.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required on both VDD and VSS to GND.
The ADG5421F can operate with bipolar supplies between 5 V
and 22 V. Note that the VDD and VSS supplies do not have to be
symmetrical, but the supply range must not exceed 44 V. The
ADG5421F can also operate with single supplies between 8 V
and 44 V with VSS connected to GND.
SIGNAL RANGE
The ADG5421F switches have overvoltage detection circuitry on
the S1 and S2 pins that compares the voltage levels with VDD
and VSS. To protect downstream circuitry from overvoltages,
supply the ADG5421F with voltages that match the intended
signal range. The NDMOS only architecture used in this switch
allows signals up to VDD − 2 V to be passed with little distortion.
A signal that exceeds the supply rail by VT is then blocked. This
signal block offers protection to both the device and any
downstream circuitry.
The ADG5421F is fully specified at the 15 V, 20 V, +12 V,
and +36 V supply ranges.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
INTELLIGENT FAULT DETECTION
An example of a bipolar power solution is shown in Figure 50.
The ADP5070 (dual switching regulator) generates a positive and
negative supply rail for the ADG5421F amplifier and/or a
precision converter in a typical signal chain. Also shown in
Figure 50 are two optional LDOs, ADP7118 and ADP7182,
positive and negative low dropout (LDOs) regulators, respectively,
that can be used to reduce the output ripple of the ADP5070 in
ultralow noise sensitive applications.
The ADG5421F digital output pin (FF) can interface with a
microprocessor or control system and be used as an interrupt
flag. This feature provides real-time diagnostic information on
the state of the device and the system to which the device
connects.
The control system can use the digital interrupt to start a
variety of actions, such as the following:
+16.5V
ADP7118
+15V
LDO
•
•
•
Initiating investigation into the source of the overvoltage fault
Shutting down critical systems in response to the overvoltage
Data recorders marking data during these events as
unreliable or out of specification
+5V
ADP5070
INPUT
–16.5V
ADP7182
–15V
LDO
Figure 50. Bipolar Power Solution
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5421F powers on and that all input voltages are within
the normal operating range before initiating operation.
Table 11. Recommended Power Management Devices
Product
Description
ADP±070 1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
The FF pin is an open drain that requires an external pull-up
resistor, which allows signals to be combined into a single
interrupt for larger modules that contain multiple devices.
ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7182 −28 V, −200 mA, low noise, LDO linear regulator
SWITCH IN A KNOWN STATE
If no digital inputs are present on the switch control lines, INx,
the switches remain in an off state to prevent any unwanted
signals passing through the switch.
Rev. 0 | Page 28 of 31
Data Sheet
ADG5421F
Table 12 details the results achieved by using the discrete
HIGH VOLTAGE SURGE SUPPRESSION
protection circuit shown in Figure 51. To replicate the harshest
environments, the surge test was performed by striking the
Sx pins directly through a 40 Ω resistor and a 0.5 µF capacitor
coupling network. The EFT test was performed by striking the
Sx pins directly without any capacitive coupling through cables.
To achieve protection from high voltage transients, such as
IEC 61000-4-2 ESD, IEC 61000-4-4 electrical fast transient
(EFT), and IEC 61000-4-5 surge, implement the circuit shown
in Figure 51 by using discrete resistor and a transient voltage
suppression (TVS) device.
Table 12. High Voltage Transient Protection
ADG5421F
82Ω
S1
S2
IEC 61000-4 Transient
Protection Level (kV)
D1
D2
V
IN
ESD (Contact)
EFT
Surge
±8
±4
±1
60V
TVS
FAULT
DETECTION
AND SWITCH
DRIVER
FF
IN1 IN2
Figure 51. High Voltage Transient Protection
Rev. 0 | Page 29 of 31
ADG5421F
Data Sheet
RELATED PRODUCTS
Table 13. Related Products to the ADG5421F
Device(s)
Configuration Fault Limit
Fault Indicator Package
Function
ADG±401F
SPST
Voltage rails
Voltage rails
Voltage rails
Voltage rails
Voltage rails
General flag
General flag
General flag
LFCSP
±60 V fault protection, 6 Ω RON,
SPST switch with 0.6 kΩ feedback
channel
ADG±412F/ADG±413F
Quad SPST
TSSOP/LFCSP ±±± V fault protection and
detection, 10 Ω RON, quad SPST
switches
TSSOP/LFCSP ±±± V bidirectional fault protection
and detection, 10 Ω RON, quad SPST
switches
TSSOP/LFCSP ±±± V fault protection and
detection, 10 Ω RON, 4-channel
multiplexer
TSSOP/LFCSP ±±± V fault protection and
detection, 10 Ω RON, dual SPDT
switch
ADG±412BF/ADG±413BF Quad SPST
ADG±404F
ADG±436F
ADG±462F
4:1 mux
General and
specific flags
Dual SPDT
General and
specific flags
Quad channel
protector
Secondary
supplies
General flag
TSSOP/LFCSP ±±± V fault protection and
detection, 10 Ω RON, quad channel
protector
Rev. 0 | Page 30 of 31
Data Sheet
ADG5421F
OUTLINE DIMENSIONS
3.10
3.00
2.90
0.30
0.25
0.20
0.50 BSC
6
10
2.10
2.00
1.90
0.45
0.40
0.35
PIN 1
CORNER
1
5
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
INDICATOR
0.80
0.75
0.70
0.55
BSC
0.050 MAX
0.035 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
Figure 52. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 2 mm Body and 0.75 mm Package Height
(CP-10-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADG±421FBCPZ-RL7
EVAL-ADG±421FEBZ
−40°C to +12±°C
10-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-10-16
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D25051-10/20(0)
Rev. 0 | Page 31 of 31
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