ADG663BRU-REEL [ADI]
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16, TSSOP-16, Multiplexer or Switch;
| 型号： | ADG663BRU-REEL |
| 厂家： | 
ADI |
| 描述： | IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16, TSSOP-16, Multiplexer or Switch 开关 |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
Precision 5 V Quad SPST Switches
ADG661/ADG662/ADG663
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
+5 V, ؎5 V Pow er Supplies
Ultralow Pow er Dissipation (<0.5 W)
Low Leakage (<100 pA)
Low On Resistance (<50 ⍀)
Fast Sw itching Tim es
Low Charge Injection
TTL/ CMOS Com patible
TSSOP Package
S1
S1
IN1
IN2
IN1
IN2
D1
S2
D1
S2
D2
S3
D2
S3
ADG662
ADG661
IN3
IN4
IN3
IN4
D3
S4
D3
S4
APPLICATIONS
Battery Pow ered Instrum ents
Single Supply System s
Rem ote Pow ered Equipm ent
+5 V Supply System s
Com puter Peripherals such as Disk Drives
Precision Instrum entation
Audio and Video Sw itching
Autom atic Test Equipm ent
Precision Data Acquisition
Sam ple Hold System s
D4
D4
S1
IN1
D1
S2
IN2
D2
S3
ADG663
IN3
IN4
D3
S4
Com m unication System s
D4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Each switch conducts equally well in both directions when ON
and has an input signal range that extends to the supplies. In the
OFF condition, signal levels up to the supplies are blocked. All
switches exhibit break-before-make switching action for use in
multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital
inputs.
GENERAL D ESCRIP TIO N
T he ADG661, ADG662 and ADG663 are monolithic CMOS
devices comprising four independently selectable switches.
T hese switches feature low, well-controlled on resistance and
wide analog signal range, making them ideal for precision analog
signal switching.
T hey are fabricated using Analog Devices' advanced linear
compatible CMOS (LC2MOS) process, which offers benefits of
low leakage currents, ultralow power dissipation and low capaci-
tance for fast switching speeds with minimum charge injection.
P RO D UCT H IGH LIGH TS
1. +5 V Single Supply Operation
T he ADG661, ADG662 and ADG663 offer high perfor-
mance, including low on resistance and wide signal range,
fully specified and guaranteed with ±5 V and +5 V supply
rails.
T he on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion making the parts ideally suited for portable and battery
powered instruments.
2. Ultralow Power Dissipation
CMOS construction ensures ultralow power dissipation.
3. Low RON
4. Break-Before-Make Switching
T he ADG661, ADG662 and ADG663 contain four indepen-
dent SPST switches. T he ADG661 and ADG662 differ only in
that the digital control logic is inverted. T he ADG661 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG662. T he ADG663
has two switches with digital control logic similar to that of the
ADG661, while the logic is inverted on the other two switches.
T his prevents channel shorting when the switches are config-
ured as a multiplexer.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
1
ADG661/ADG662/ADG663–SPECIFICATIONS
(V = +5 V ؎ 10%, V = –5 V ؎ 10%, GND = 0 V, unless otherwise noted)
Dual Supply
DD
SS
B Versions
–40؇C to +85؇C
P aram eter
+25؇C
Units
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
RON
VDD to VSS
50
V
30
38
Ω typ
Ω max
VD = –3.5 V to +3.5 V, IS = –10 mA;
VDD = +4.5 V, VSS = –4.5 V
LEAKAGE CURRENT S
Source OFF Leakage IS (OFF)
VDD = +5.5 V, VSS = –5.5 V
VD = ±4.5 V, VS = ±4.5 V;
T est Circuit 2
VD = ±4.5 V, VS = ±4.5 V;
T est Circuit 2
±0.025
±0.1
±0.025
±0.1
±0.05
±0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
±2.5
±2.5
±5
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
VD = VS = ±4.5 V;
T est Circuit 3
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
µA typ
VIN = VINL or VINH
±0.1
µA max
DYNAMIC CHARACT ERIST ICS2
tON
150
55
80
6
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF;
VS = ±3 V; T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = ±3 V; T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +3 V; T est Circuit 5
VS = 0 V, RS = 0 Ω, CL = 10 nF;
T est Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 8
275
120
tOFF
Break-Before-Make T ime Delay, tD
(ADG663 Only)
Charge Injection
pC typ
dB typ
dB typ
OFF Isolation
70
90
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
28
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENT S
+4.5/5.5
–4.5/5.5
V min/max
V min/max
µA typ
µA max
µA typ
VDD
IDD
0.0001
0.0001
VDD = +5.5 V, VSS = –5.5 V
Digital Inputs = 0 V or 5 V
1
1
ISS
µA max
NOT ES
1T emperature ranges are as follows: B Versions, –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG661/ADG662/ADG663
(V = +5 V ؎ 10%, V = 0 V, GND = 0 V, unless otherwise noted)
Single Supply
DD
SS
B Versions
–40؇C to +85؇C
P aram eter
+25؇C
Units
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
RON
0 V to VDD
75
V
45
68
Ω typ
Ω max
VD = 0 V to +3.5 V, IS = –10 mA;
VDD = +4.5 V
LEAKAGE CURRENT S
VDD = +5.5 V
Source OFF Leakage IS (OFF)
±0.025
±0.1
±0.025
±0.1
±0.05
±0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
T est Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
T est Circuit 2
VD = VS = +4.5 V/+1 V;
T est Circuit 3
±2.5
±2.5
±5
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
µA typ
VIN = VINL or VINH
±0.1
µA max
DYNAMIC CHARACT ERIST ICS2
tON
250
45
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF;
VS = +2 V; T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = +2 V; T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +2 V; T est Circuit 5
VS = 0 V, RS = 0 Ω, CL = 10 nF;
T est Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 8
400
100
tOFF
Break-Before-Make T ime Delay, tD
(ADG663 Only)
Charge Injection
140
12
pC typ
dB typ
dB typ
OFF Isolation
70
Channel-to-Channel Crosstalk
90
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
28
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENT S
VDD
IDD
+4.5/5.5
1
V min/max
µA typ
µA max
0.0001
VDD = +5.5 V
Digital Inputs = 0 V or 5 V
NOT ES
1T emperature ranges are as follows: B Versions, –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
ADG661/ADG662/ADG663
ABSO LUTE MAXIMUM RATINGS1
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
(T A = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
Analog, Digital Inputs2 . . . . . . . . . . . VSS –2 V to VDD +2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Operating T emperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
T SSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
θJC T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
ADG661BRU
ADG662BRU
ADG663BRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
16-Lead T SSOP
16-Lead T SSOP
16-Lead T SSOP
RU-16
RU-16
RU-16
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG661/ADG662/ADG663 features proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high energy electrostatic discharges. T here-
fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
ADG661/ADG662/ADG663
P IN CO NFIGURATIO N
TERMINO LO GY
VDD
VSS
Most positive power supply potential.
IN1
D1
S1
1
2
3
4
5
6
7
8
16
IN2
Most negative power supply potential in
dual supplies. In single supply applications,
it may be connected to GND.
15 D2
14 S2
ADG661
ADG662
ADG663
TOP VIEW
(Not to Scale)
V
13
12
V
DD
SS
GND
Ground (0 V) Reference.
NC
GND
S
Source T erminal. May be an input or output.
Drain T erminal. May be an input or output.
Logic Control Input.
11 S3
10 D3
S4
D4
D
IN
9
IN4
IN3
RON
Ohmic resistance between D and S.
Source leakage current with the switch “OFF.”
D rain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D, S.
“OFF” Switch Source Capacitance.
“OFF” Switch Drain Capacitance.
“ON” Switch Capacitance.
NC = NO CONNECT
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
CS (OFF)
Table I. Truth Table (AD G661/AD G662)
AD G661 In
AD G662 In
Switch Condition
C
D (OFF)
0
1
1
0
ON
OFF
CD, CS (ON)
tON
Delay between applying the digital control
input and the output switching on.
Table II. Truth Table (AD G663)
tOFF
tD
Delay between applying the digital control
input and the output switching off.
Logic
Switch 1, 4
Switch 2, 3
“OFF” time or “ON” time measured between
the 90% points of both switches, when
switching from one address state to another.
0
1
OFF
ON
ON
OFF
Crosstalk
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” switch.
Charge
Injection
A measure of the glitch impulse transferred
from the digital input to analog output during
switching.
REV. 0
–5–
ADG661/ADG662/ADG663
Typical Performance Characteristics
50
40
30
20
10
0
50
40
30
20
10
0
50
40
V
V
= +5V
= –5V
T
= +25؇C
DD
SS
A
T
= +25°C
A
V
V
= +5V
= 0V
DD
SS
30
20
+85؇C
+25؇C
V
V
= +5V
= –5V
DD
SS
10
0
–5 –4 –3 –2 –1
0
1
2
3
4
5
–4 –3 –2 –1
0
1
2
3
4
5
–5
0
1
2
3
4
5
V
OR V – DRAIN OR SOURCE VOLTAGE – V
V OR V – DRAIN OR SOURCE VOLTAGE – V
D S
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
S
D
Figure 1. On Resistance as a
Function of VD (VS) Dual Supplies
Figure 2. On Resistance as a
Function of VD (VS) for
Figure 3. On Resistance as a
Function of VD (VS) Single Supply
Different Tem peratures
10
120
10mA
V
V
= +5V
= –5V
DD
SS
V
V
= +5V
= –5V
V
V
V
V
= +5V
= –5V
DD
DD
SS
1mA
100A
10A
1A
SS
100
1
= ؎5V
= ؎5V
S
D
I
(OFF)
D
4 SW
0.1
80
60
40
1 SW
I
(ON)
D
0.01
I–, I+
100nA
10nA
I
(OFF)
S
0.001
100
1k
10k
100k
1M
10M
25 35 45
55 65 75
85
95 105
10
100
10k 100k 1M
1k
FREQUENCY – Hz
10M
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 5. Leakage Currents as a
Function of Tem perature
Figure 4. Supply Current vs. Input
Switching Frequency
Figure 6. Off Isolation vs.
Frequency
0.006
110
V
V
= +5V
= –5V
DD
SS
I
(ON)
V
V
= +5V
= –5V
= +25؇C
D
DD
0.004
0.002
SS
100
90
80
70
60
T
A
I
(OFF)
D
I (OFF)
S
0.000
–0.002
–0.004
–0.006
–5 –4 –3 –2 –1
0
1
2
3
4
5
100
1k
10k
100k
1M
10M
V
OR V – DRAIN OR SOURCE VOLTAGE
FREQUENCY – Hz
D
S
Figure 7. Leakage Currents as a
Function of VD (VS)
Figure 8. Crosstalk vs. Frequency
–6–
REV. 0
ADG661/ADG662/ADG663
Test Circuits
I
DS
I
(OFF)
A
I
(OFF)
A
I
(ON)
D
S
D
V1
S
D
S
D
A
S
D
V
V
V
V
D
S
D
S
V
S
R
= V1/I
DS
ON
3. On Leakage
1. On Resistance
2. Off Leakage
V
V
DD
0.1F
3V
DD
V
50%
50%
50%
50%
ADG661
IN
S
D
V
OUT
3V
ADG662
V
R
C
L
IN
L
V
S
35pF
300⍀
IN
90%
90%
V
V
OUT
GND
SS
0.1F
tON
tOFF
V
SS
4. Switching Tim es
V
V
DD
0.1F
3V
0V
V
IN
50%
50%
DD
S1
D1
D2
V
V
S1
OUT1
90%
90%
V
V
OUT1
R
C
L1
35pF
L1
V
OUT2
S2
0V
300⍀
V
S2
R
C
L2
IN1, IN2
L2
35pF
300⍀
90%
V
90%
GND
SS
V
OUT2
IN
0V
tD
tD
0.1F
V
SS
5. Break-Before-Make Tim e Delay
V
V
DD
3V
DD
V
R
IN
S
S
D
V
OUT
C
10nF
L
V
S
IN
V
OUT
⌬V
OUT
V
V
GND
SS
Q
= C
؋
⌬V L OUT
INJ
SS
6. Charge Injection
REV. 0
–7–
ADG661/ADG662/ADG663
Test Circuits (Continued)
AP P LICATIO N
Figure 9 illustrates a precise, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an OP07. During the track mode, SW1 is closed and
the output VOUT follows the input signal VIN. In the hold mode,
SW1 is opened and the signal is held by the hold capacitor CH.
V
DD
0.1F
V
DD
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. T he ADG661/ADG662/
ADG663 minimizes this droop due to its low leakage specifica-
tions. T he droop rate is further minimized by the use of a poly-
styrene hold capacitor. T he droop rate for the circuit shown is
typically 15 µV/µs.
S
D
V
OUT
R
50⍀
L
IN
V
V
S
IN
V
GND
SS
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp OP07 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. T his compensation network also re-
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the ±3 V input
range. T he acquisition time is 2.5 ms while the settling time is
1.85 µs.
0.1F
V
SS
7. Off Isolation
V
V
DD
DD
0.1F
50⍀
S
D
+5V
V
2200pF
IN1
V
S
V
IN2
+5V
SW1
D
S
+5V
V
S
S
D
D
OUT
NC
C
C
R
C
OP07
–5V
V
OUT
V
1000pF
V
IN
SW2
GND
SS
R
L
75⍀
AD845
–5V
50⍀
C
H
CHANNEL TO CHANNEL
CROSSTALK = 20
؋
LOG V /V 2200pF
0.1F
S
OUT
V
SS
ADG661
ADG662
ADG663
8. Channel-to-Channel Crosstalk
–5V
Figure 9. Accurate Sam ple-and-Hold
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-Lead TSSO P
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–8–
REV. 0
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