ADG709 [ADI]
CMOS, 3 ohm Low Voltage 4-/8-Channel Multiplexers; CMOS ， 3欧姆的低电压4- / 8通道多路复用器
| 型号： | ADG709 |
| 厂家： | 
ADI |
| 描述： | CMOS, 3 ohm Low Voltage 4-/8-Channel Multiplexers |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, 3 ⍀ Low Voltage
a
4-/8-Channel Multiplexers
ADG708/ADG709
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
1.8 V to 5.5 V Single Supply
؎3 V Dual Supply
ADG708
ADG709
3 ⍀ On-Resistance
S1
S1A
S4A
0.75 ⍀ On-Resistance Flatness
100 pA Leakage Currents
14 ns Switching Times
Single 8-to-1 Multiplexer ADG708
Differential 4-to-1 Multiplexer ADG709
16-Lead TSSOP Package
Low Power Consumption
TTL/CMOS-Compatible Inputs
DA
DB
D
S1B
S4B
S8
1 OF 4
1 OF 8
DECODER
DECODER
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
A2 EN
EN
A1
A0 A1
A0
Audio and Video Switching
Battery-Powered Systems
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG708 and ADG709 are low voltage, CMOS analog
multiplexers comprising eight single channels and four differential
channels respectively. The ADG708 switches one of eight inputs
(S1–S8) to a common output, D, as determined by the 3-bit
binary address lines A0, A1, and A2. The ADG709 switches one
of four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An EN
input on both devices is used to enable or disable the device. When
disabled, all channels are switched OFF.
1. Single/Dual Supply Operation. The ADG708 and ADG709
are fully specified and guaranteed with 3 V and 5 V single
supply and ±3 V dual supply rails.
2. Low RON (3 Ω Typical).
3. Low Power Consumption (<0.01 µW).
4. Guaranteed Break-Before-Make Switching Action.
5. Small 16-Lead TSSOP Package.
Low power consumption and operating supply range of 1.8 V to
5.5 V make the ADG708 and ADG709 ideal for battery-powered,
portable instruments. All channels exhibit break-before-make
switching action preventing momentary shorting when switch-
ing channels.
These switches are designed on an enhanced submicron process
that provides low power dissipation yet gives high switching
speed, very low on-resistance and leakage currents. On-resistance
is in the region of a few ohms and is closely matched between
switches and very flat over the full signal range. These parts can
operate equally well as either Multiplexers or Demultiplexers,
and have an input signal range that extends to the supplies.
The ADG708 and ADG709 are available in a 16-lead TSSOP
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADG708/ADG709–SPECIFICATIONS1
(VDD = 5 V ؎ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
B Version
–40؇C
C Version
–40؇C
Parameter
+25؇C to +85؇C
+25؇C to +85؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
0 V to VDD
V
On-Resistance (RON
)
3
4.5
3
4.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
5
0.4
0.8
5
0.4
0.8
On-Resistance Match Between
Channels (∆RON
)
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
On-Resistance Flatness (RFLAT(ON)
)
0.75
0.75
1.2
1.2
LEAKAGE CURRENTS
VDD = 5.5 V
Source OFF Leakage IS (OFF)
±0.01
±0.01
±0.01
±0.01
±0.1
±0.01
±0.1
±0.01
±0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
±20
±20
±20
±0.3
Drain OFF Leakage ID (OFF)
±0.75
±0.75
Channel ON Leakage ID, IS (ON)
VD = VS = 1 V, or 4.5 V, Test Circuit 4
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
I
INL or IINH
0.005
2
0.005
2
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
14
8
14
8
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5
VS1 = 3 V/0 V, VS8 = 0 V/3 V
25
1
25
1
Break-Before-Make Time Delay, tD
RL = 300 Ω, CL = 35 pF
VS = 3 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF
VS = 3 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS = 3 V, Test Circuit 7
VS = 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
t
t
ON(EN)
14
7
14
7
25
12
25
12
OFF(EN)
Charge Injection
Off Isolation
±3
±3
–60
–80
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
Channel-to-Channel Crosstalk
–60
–80
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
–3 dB Bandwidth
CS (OFF)
55
13
55
13
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 9
pF typ
C
D (OFF)
ADG708
ADG709
85
42
85
42
pF typ
pF typ
CD, CS (ON)
ADG708
ADG709
96
48
96
48
pF typ
pF typ
POWER REQUIREMENTS
IDD
V
DD = 5.5 V
0.001
0.001
µA typ
Digital Inputs = 0 V or 5.5 V
1.0
1.0
µA max
NOTES
1Temperature range is as follows: B and C Versions: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–2–
ADG708/ADG709
SPECIFICATIONS1 (VDD = 3 V ؎ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
B Version
–40؇C
C Version
–40؇C
Parameter
+25؇C to +85؇C
+25؇C to +85؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
0 V to VDD
V
On-Resistance (RON
)
8
11
8
11
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD , IDS = 10 mA
12
0.4
1.2
12
0.4
1.2
On-Resistance Match Between
Channels (∆RON
)
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 3
VS = VD = 1 V or 3 V, Test Circuit 4
±0.01
±0.01
±0.01
±0.1 ±0.3
±0.01
±0.1 ±0.75
±0.01
±0.1 ±0.75
nA typ
nA max
nA typ
nA max
nA typ
nA max
±20
±20
±20
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON) ±0.01
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.4
2.0
0.4
V min
V max
IINL or IINH
0.005
2
0.005
±0.1
2
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
18
8
18
30
8
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5
VS1 = 2 V/0 V, VS2 = 0 V/2 V
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 7
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
30
1
Break-Before-Make Time Delay, tD
tON(EN)
1
18
8
18
30
8
15
±3
30
15
tOFF(EN)
Charge Injection
Off Isolation
±3
–60
–80
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
Channel-to-Channel Crosstalk
–60
–80
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
–3 dB Bandwidth
CS (OFF)
55
13
55
13
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 9
pF typ
CD (OFF)
ADG708
ADG709
85
42
85
42
pF typ
pF typ
CD, CS (ON)
ADG708
ADG709
96
48
96
48
pF typ
pF typ
POWER REQUIREMENTS
IDD
V
DD = 3.3 V
0.001
0.001
1.0
µA typ
µA max
Digital Inputs = 0 V or 3.3 V
1.0
NOTES
1Temperature ranges are as follows: B and C Versions: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
ADG708/ADG709–SPECIFICATIONS1
DUAL SUPPLY (VDD = +3 V ؎ 10%, VSS = –3 V ؎ 10%, GND = 0 V)
B Version
–40؇C
+25؇C to +85؇C
C Version
–40؇C
+25؇C to +85؇C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS to VDD
2.5
VSS to VDD
2.5
V
On-Resistance (RON
)
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to VDD, IDS = 10 mA;
Test Circuit 1
4.5
5
0.4
0.8
4.5
5
0.4
0.8
On-Resistance Match Between
Channels (∆RON
)
VS = VSS to VDD, IDS = 10 mA
VS = VSS to VDD, IDS = 10 mA
On-Resistance Flatness (RFLAT(ON)
)
0.6
0.6
1.0
1.0
LEAKAGE CURRENTS
VDD = +3.3 V, VSS = –3.3 V
Source OFF Leakage IS (OFF)
±0.01
±0.01
±0.01
±0.01
±0.1
±0.01
±0.1
±0.01
±0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 2
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 3
±20
±20
±20
±0.3
Drain OFF Leakage ID (OFF)
±0.75
±0.75
Channel ON Leakage ID, IS (ON)
VS = VD = +2.25 V/–1.25 V, Test Circuit 4
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.4
2.0
0.4
V min
V max
IINL or IINH
0.005
2
0.005
2
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
14
8
14
8
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5
VS = 1.5 V/0 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF
VS = 1.5 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF
VS = 1.5 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS = 1.5 V, Test Circuit 7
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
25
1
25
1
Break-Before-Make Time Delay, tD
tON(EN)
14
8
14
8
25
15
25
15
tOFF(EN)
Charge Injection
Off Isolation
±3
±3
–60
–80
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
Channel-to-Channel Crosstalk
–60
–80
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
–3 dB Bandwidth
CS (OFF)
55
13
55
13
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 9
pF typ
CD (OFF)
ADG708
ADG709
85
42
85
42
pF typ
pF typ
CD, CS (ON)
ADG708
ADG709
96
48
96
48
`
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
0.001
0.001
0.001
0.001
µA typ
µA max
µA typ
µA max
1.0
1.0
1.0
1.0
ISS
VSS = –3.3 V
Digital Inputs = 0 V or 3.3 V
NOTES
1Temperature range is as follows: B and C Versions: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–4–
ADG708/ADG709
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 432 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W
Lead Temperature, Soldering
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
Digital Inputs2 . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
. . . . . . . . . . . . . . . . . (Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG708/ADG709 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Table I. ADG708 Truth Table
PIN CONFIGURATIONS
A2
A1
A0
EN
Switch Condition
TSSOP
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
A1
A2
1
2
16
15
14
13
12
11
A0
EN
V
3
4
5
6
7
8
GND
SS
S1
S2
S3
S4
D
ADG708
TOP VIEW
(Not to Scale)
V
DD
S5
S6
10 S7
9
S8
X = Don’t Care
Table II. ADG709 Truth Table
A1
A1
A0
EN
ON Switch Pair
1
2
16
15
14
A0
EN
GND
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
NONE
V
V
3
4
5
6
7
8
SS
S1A
S2A
S3A
S4A
DA
DD
1
2
3
4
ADG709
TOP VIEW
(Not to Scale)
13 S1B
12 S2B
11 S3B
10 S4B
X = Don’t Care.
9
DB
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
ADG708BRU
ADG709BRU
ADG708CRU
ADG709CRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
RU-16
RU-16
RU-16
RU-16
REV. 0
–5–
ADG708/ADG709
TERMINOLOGY
VDD
VSS
Most positive power supply potential.
Most negative power supply in a dual supply
application. In single supply applications, this
should be tied to ground at the device.
tON (EN)
Delay time between the 50% and 90% points
of the EN digital input and the switch “ON”
condition.
t
OFF (EN)
Delay time between the 50% and 90% points
of the EN digital input and the switch “OFF”
condition.
GND
Ground (0 V) Reference.
S
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
tOPEN
“OFF” time measured between the 80% points
of both switches when switching from one address
state to another.
D
IN
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
RON
Ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on-resistance
as measured over the specified analog signal range.
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
IS (OFF)
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D, S.
Charge
Injection
A measure of the glitch impulse transferred from
the digital input to the analog output during
switching.
I
D (OFF)
ID, IS (ON)
VD (VS)
Bandwidth
The frequency at which the output is attenuated
by 3 dBs.
CS (OFF)
“OFF” switch source capacitance. Measured
with reference to ground.
On Response The frequency response of the “ON” switch.
CD (OFF)
“OFF” switch drain capacitance. Measured
with reference to ground.
On Loss
VINL
The loss due to the ON resistance of the switch.
Maximum input voltage for Logic “0.”
Minimum input voltage for Logic “1.”
Input current of the digital input.
Positive Supply Current.
CD, CS (ON) “ON” switch capacitance. Measured with
reference to ground.
VINH
I
INL (IINH)
CIN
Digital Input Capacitance.
IDD
ISS
tTRANSITION
Delay time measured between the 50% and 90%
points of the digital inputs and the switch “ON”
condition when switching from one address state
to another.
Negative Supply Current.
REV. 0
–6–
Typical Performance Characteristics–
ADG708/ADG709
8
8
7
6
5
V
V
= 3V
= 0V
DD
SS
T
V
= 25؇C
A
= 0V
7
6
5
4
3
2
SS
V
= 2.7V
DD
+85؇C
V
= 3.3V
DD
4
3
2
1
0
V
= 4.5V
DD
–40؇C
V
= 5.5V
DD
+25؇C
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
V
, V , DRAIN OR SOURCE VOLTAGE – V
D
D
S
Figure 4. On Resistance as a Function of VD (VS) for Differ-
ent Temperatures, Single Supply
Figure 1. On Resistance as a Function of VD (VS) for Single
Supply
8
8
T
= 25؇C
A
V
V
= +3.0V
= –3.0V
DD
7
6
5
7
SS
6
5
4
3
4
3
2
1
0
V
V
= +2.25V
= –2.25V
DD
+25؇C
SS
+85؇C
–40؇C
2
1
V
V
= +3.0V
= –3.0V
V
V
= +2.75V
= –2.75V
DD
DD
SS
SS
0
–1.0
–3.0 –2.5 –2.0 –1.5
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
–1.5
–3.0 –2.5 –2.0 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
V
OR V – DRAIN OR SOURCE VOLTAGE – V
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
S
D
Figure 2. On Resistance as a Function of VD (VS) for Dual
Supply
Figure 5. On Resistance as a Function of VD (VS) for Differ-
ent Temperatures, Dual Supply
0.12
8
V
V
= 5V
= 0V
DD
SS
V
V
T
= 5V
= 0V
= 25؇C
DD
SS
7
6
0.08
A
I
(ON)
D
0.04
0.00
5
4
3
2
1
0
+25؇C
+85؇C
–40؇C
I
(OFF)
S
–0.04
–0.08
–0.12
I
(OFF)
D
0
1
2
3
4
5
0
1
2
3
4
5
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
V
(V – Volts
S)
D
D
Figure 3. On Resistance as a Function of VD (VS) for Differ-
ent Temperatures, Single Supply
Figure 6. Leakage Currents as a Function of VD (VS)
REV. 0
–7–
ADG708/ADG709
0.12
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
–0.05
V
V
T
= 3V
= 0V
= 25؇C
DD
V
V
= 3V
= 0V
DD
SS
SS
0.08
A
I
(ON)
D
0.04
0.00
–0.04
–0.08
I
(OFF)
S
I
(OFF)
D
I
(OFF)
D
I
(ON)
75
D
I
(OFF)
55
S
–0.12
0
0.5
1.0
1.5
(V – Volts
2.0
2.5
3.0
15
25
35
45
65
85
V
TEMPERATURE – ؇C
D
S)
Figure 7. Leakage Currents as a Function of VD (VS)
Figure 10. Leakage Currents as a Function of Temperature
10m
0.12
T
= 25؇C
V
V
= +3.0V
= –3.0V
A
DD
SS
1m
100
10
1
0.08
0.04
T
= 25؇C
A
V
V
= +3.0V
= –3.0V
DD
SS
I
(ON)
D
V
= +5V
DD
0.00
–0.04
–0.08
V
= +3V
DD
I
(OFF)
S
100n
10n
1n
I
(OFF)
D
–0.12
10
100
1k
10k
100k
1M
10M
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY – Hz
V
(V – Volts
D
S)
Figure 8. Leakage Currents as a Function of VD (VS)
Figure 11. Supply Current vs. Input Switching Frequency
0
0.35
V
V
= 5V
= 0V
AND
= +3V
= –3V
V
T
= 5V
= 25؇C
DD
DD
SS
A
0.30
0.25
0.20
0.15
0.10
0.05
0.00
–0.05
–20
–40
V
V
DD
SS
–60
I
(OFF)
D
–80
I
(ON)
75
D
–100
I
(OFF)
65
S
–120
15
25
35
45
55
85
30k
100k
1M
10M
100M
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 9. Leakage Currents as a Function of Temperature
Figure 12. Off Isolation vs. Frequency
REV. 0
–8–
ADG708/ADG709
0
0
–5
V
= 5V
= 25؇C
DD
T
A
V
= 5V
= 25؇C
DD
–20
T
A
–40
–60
–10
–15
–20
–80
–100
–120
30k
100k
1M
10M
100M
30k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Crosstalk vs. Frequency
Figure 14. On Response vs. Frequency
20
10
T
= 25؇C
A
V
V
= 5V
= 0V
DD
SS
0
V
V
= 3V
= 0V
DD
–10
SS
–20
–30
–40
V
V
= +3V
= –3V
DD
SS
2
–3
–2
–1
0
1
3
4
5
VOLTAGE – Volts
Figure 15. Charge Injection vs. Source Voltage
REV. 0
–9–
ADG708/ADG709
Test Circuits
I
DS
V
V
SS
DD
V1
V
V
DD
SS
S1
S2
I
(OFF)
A
D
S
D
D
S8
V
D
V
S
0.8V
EN
V
GND
S
R
= V /I
1 DS
ON
Test Circuit 3. ID (OFF)
Test Circuit 1. On Resistance
V
V
V
DD
SS
V
V
V
DD
SS
V
SS
DD
V
DD
SS
I (OFF)
S
I
(ON)
A
D
S1
S2
S8
S1
S8
A
D
D
V
S
V
D
2.4V
V
S
EN
0.8V
GND
EN
V
GND
D
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF)
V
V
V
DD
SS
3V
0V
V
DD
SS
ADDRESS
DRIVE (V
50%
50%
)
A2
A1
A0
IN
V
S1
S1
V
IN
50⍀
S2 THRU S7
S8
V
S8
ADG708*
V
S1
90%
V
D
OUT
2.4V
EN
V
C
35pF
OUT
R
300⍀
L
L
GND
90%
V
S8
t
t
TRANSITION
* SIMILAR CONNECTION FOR ADG709
TRANSITION
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
V
V
V
3V
DD
SS
ADDRESS
V
DD
SS
DRIVE (V )
IN
V
A2
A1
A0
S1
S
0V
V
IN
50⍀
S2 THRU S7
S8
ADG708*
V
D
OUT
80%
80%
2.4V
EN
V
OUT
C
35pF
R
300⍀
L
L
GND
t
OPEN
* SIMILAR CONNECTION FOR ADG709
Test Circuit 6. Break-Before-Make Delay, tOPEN
REV. 0
–10–
ADG708/ADG709
V
V
V
V
3V
DD
SS
ENABLE
50%
50%
DD
SS
DRIVE (V
)
IN
A2
A1
A0
V
S1
S
0V
S2 THRU S8
t
(EN)
OFF
V
0
ADG708*
D
0.9V
0.9V
0
0
V
OUTPUT
0V
EN
OUT
C
35pF
R
300⍀
GND
L
V
IN
L
50⍀
t
(EN)
ON
* SIMILAR CONNECTION FOR ADG709
Test Circuit 7. Enable Delay, tON (EN), tOFF (EN)
V
V
V
3V
DD
SS
LOGIC INPUT
(V
)
IN
V
DD
SS
A2
A1
A0
0V
ADG708*
R
S
D
S
V
V
⌬V
C
1nF
OUT
OUT
OUT
V
L
S
EN
Q
= C
؋
⌬V INJ
L
OUT
V
GND
IN
*SIMILAR CONNECTION FOR ADG709
Test Circuit 8. Charge Injection
V
V
V
DD
SS
V
DD
A2
A1
A0
DD
S1
S8
A2
A1
A0
EN
2.4V
*
ADG708
V
S
*
50⍀
ADG708
D
S1
V
OUT
R
50⍀
L
S2
S8
D
V
**
EN
OUT
V
S
V
R
50⍀
V
GND
SS
SS
GND
L
SS
V
V
SS
V
V
V
S
OUT
V
S
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG
OFF ISOLATION = 20LOG
10
10
*
SIMILAR CONNECTION FOR ADG709
V
WITH SWITCH
OUT
INSERTION LOSS = 20LOG
10
(
)
V
WITHOUT SWITCH
OUT
*
SIMILAR CONNECTION FOR ADG709
**
CONNECT TO 2.4V FOR BANDWIDTH MEASUREMENTS
Test Circuit 9. OFF Isolation and Bandwidth
Test Circuit 10. Channel-to-Channel Crosstalk
Power-Supply Sequencing
When using CMOS devices, care must be taken to ensure correct
power-supply sequencing. Incorrect power-supply sequencing
can result in the device being subjected to stresses beyond the
maximum ratings listed in the data sheet. Digital and analog
inputs should always be applied after power supplies and ground.
For single supply operation, VSS should be tied to GND as close
to the device as possible.
REV. 0
–11–
ADG708/ADG709
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
8
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–12–
REV. 0
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