ADG721BRMZ [ADI]
CMOS, Low Voltage, 4 Ω Dual SPST Switches in 3 mm à 2 mm LFCSP; CMOS ，低压， 4个I ©双SPST 3毫米的开关？ 2毫米LFCSP
| 型号： | ADG721BRMZ |
| 厂家： | 
ADI |
| 描述： | CMOS, Low Voltage, 4 Ω Dual SPST Switches in 3 mm à 2 mm LFCSP |
| 文件： | 总16页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, Low Voltage, 4 Ω Dual SPST
Switches in 3 mm × 2 mm LFCSP
Data Sheet
ADG721/ADG722/ADG723
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
1.8 V to 5.5 V single supply
4 Ω (max) on resistance
Low on resistance flatness
−3 dB bandwidth >200 MHz
Tiny package options
8-lead MSOP
ADG722
ADG721
S1
D1
S1
D1
IN1
IN1
D2
S2
D2
S2
IN2
IN2
3 mm × 2 mm LFCSP (A grade)
Fast switching times
Figure 1.
Figure 2.
t
t
ON, 20 ns
OFF, 10 ns
ADG723
Low power consumption (<0.1 μW)
TTL/CMOS compatible
S1
D1
IN1
APPLICATIONS
D2
S2
IN2
USB 1.1 signal switching circuits
Cell phones
PDAs
SWITCHES SHOWN FOR
A LOGIC "0" INPUT
Battery-powered systems
Communication systems
Sample hold systems
Audio signal routing
Video switching
Figure 3.
Mechanical reed relay replacement
GENERAL DESCRIPTION
and normally closed, respectively. In the ADG723, Switch 1 is
normally open and Switch 2 is normally closed.
The ADG721, ADG722, and ADG723 are monolithic CMOS
SPST switches. These switches are designed on an advanced
submicron process that provides low power dissipation yet gives
high switching speed, low on resistance, and low leakage
currents. The devices are packaged in both a tiny 3 mm × 2 mm
LFCSP and an MSOP, making them ideal for space-constrained
applications.
Each switch of the ADG721, ADG722, and ADG723 conducts
equally well in both directions when on. The ADG723 exhibits
break-before-make switching action.
PRODUCT HIGHLIGHTS
1. 1.8 V to 5.5 V single-supply operation.
2. Very low RON (4 Ω max at 5 V, 10 Ω max at 3 V).
3. Low on resistance flatness.
4. −3 dB bandwidth >200 MHz.
5. Low power dissipation. CMOS construction ensures low
power dissipation.
The ADG721, ADG722, and ADG723 are designed to operate
from a single 1.8 V to 5.5 V supply, making them ideal for use
in battery-powered instruments and with the new generation of
DACs and ADCs from Analog Devices, Inc.
The ADG721, ADG722, and ADG723 contain two independent
single-pole/single-throw (SPST) switches. The ADG721 and
ADG722 differ only in that both switches are normally open
6. 8-lead MSOP and 3 mm × 2 mm LFCSP.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004-2011 Analog Devices, Inc. All rights reserved.
ADG721/ADG722/ADG723
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology.......................................................................................7
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 10
Applications..................................................................................... 12
ADG721/ADG722/ADG723 Supply Voltages ....................... 12
On Response vs. Frequency ...................................................... 12
Off Isolation ................................................................................ 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Pin Descriptions....................................... 6
REVISION HISTORY
10/11—Rev. D to Rev. E
Changes to Ordering Guide ...............................................................
4/11—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 14
1/11—Rev. B to Rev. C
Changes to Table 4............................................................................ 6
Changes to Ordering Guide .......................................................... 14
2/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Specifications................................................................ 3
Changes to Absolute Maximum Ratings....................................... 5
Change to Figure 4 ........................................................................... 6
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
3/04—Rev. 0 to Rev. A
Additions to Applications................................................................ 1
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions....................................................... 10
Rev. E | Page 2 of 16
Data Sheet
ADG721/ADG722/ADG723
SPECIFICATIONS
VDD = 5 V 10%, GND = 0 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 1.
A, B Grade1
Parameter
+25°C
−40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 to VDD
5
V
2.5
4
0.3
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = −10 mA
See Figure 12
VS = 0 V to VDD, IS = −10 mA
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT(ON)
1.0
0.85
VS = 0 V to VDD, IS = −10 mA
1.5
LEAKAGE CURRENTS – A Grade
Source off Leakage, IS (OFF)
Drain off Leakage, ID (OFF)
Channel on Leakage, ID, IS (ON)
LEAKAGE CURRENTS – B Grade
Source off Leakage, IS (OFF)
VDD = 5.5 V
0.01
0.01
0.01
nA typ
nA typ
nA typ
VS = 4.5 V/1 V, VD = 1 V/4.5 V, see Figure 13
VS = 4.5 V/1 V, VD = 1 V/4.5 V, see Figure 13
VS = VD = 1 V or VS = VD = 4.5 V, see Figure 14
VDD = 5.5 V
VS = 4.5 V/1 V, VD = 1 V/4.5 V
Test Circuit 2
VS = 4.5 V/1 V, VD = 1 V/4.5 V
See Figure 13
VS = VD = 1 V or VS = VD = 4.5 V
See Figure 14
0.01
0.25
0.01
0.25
0.01
0.25
nA typ
nA max
nA typ
nA max
nA typ
nA max
0.35
0.35
0.35
Drain off Leakage, ID (OFF)
Channel on Leakage, ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
μA typ
VIN = VINL or VINH
0.1
μA max
DYNAMIC CHARACTERISTICS2
tON
14
6
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 15
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 15
20
10
1
tOFF
Break-Before-Make Time Delay, tD (ADG723 Only)
7
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V, see Figure 16
VS = 2 V, RS = 0 Ω, CL = 1 nF, see Figure 17
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 19
Charge Injection
Off Isolation
2
−60
−80
−77
−97
200
7
Channel-to-Channel Crosstalk
Bandwidth −3 dB
CS (OFF)
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 20
pF typ
CD (OFF)
7
pF typ
CD, CS (ON)
18
pF typ
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital inputs = 0 V or 5 V
0.001
μA typ
1.0
μA max
1 Temperature range: A, B grades, −40°C to +85°C. All specifications apply to both grades unless otherwise stated.
2 Guaranteed by design; not subject to production test.
Rev. E | Page 3 of 16
ADG721/ADG722/ADG723
Data Sheet
VDD = 3 V 10%, GND = 0 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2.
A, B Grades1
Parameter
+25°C
−40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 to VDD
10
V
6.5
0.3
3.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = −10 mA
See Figure 12
VS = 0 V to VDD, IS = −10 mA
On Resistance Match Between Channels, ∆RON
1.0
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS – A Grade
Source off Leakage, IS (OFF)
Drain off Leakage, ID (OFF)
Channel on Leakage, ID, IS (ON)
LEAKAGE CURRENTS – B Grade
Source off Leakage, IS (OFF)
VS = 0 V to VDD, IS = −10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V, see Figure 13
VS = 3 V/1 V, VD = 1 V/3 V, see Figure 13
VS = VD = 1 V or 3 V, Figure 14
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V
See Figure 13
VS = 3 V/1 V, VD = 1 V/3 V
See Figure 13
0.01
0.01
0.01
nA typ
nA typ
nA typ
0.01
0.25
0.01
0.25
0.01
0.25
nA typ
nA max
nA typ
nA max
nA typ
nA max
0.35
0.35
0.35
Drain off Leakage, ID (OFF)
Channel on Leakage, ID, IS (ON)
VS = VD = 1 V or 3 V
See Figure 14
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.4
V min
V max
IINL or IINH
0.005
μA typ
VIN = VINL or VINH
0.1
μA max
DYNAMIC CHARACTERISTICS2
tON
16
7
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 2 V, see Figure 15
RL = 300 Ω, CL = 35 pF
VS = 2 V, see Figure 15
24
11
1
tOFF
Break-Before-Make Time Delay, tD (ADG723 Only)
7
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 2 V, see Figure 16
VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 17
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 19
RL = 50 Ω, CL = 5 pF, see Figure 20
Charge Injection
Off Isolation
2
−60
−80
−77
−97
200
7
Channel-to-Channel Crosstalk
Bandwidth −3 dB
CS (OFF)
CD (OFF)
7
18
CD, CS (ON)
POWER REQUIREMENTS
IDD
VDD = 3.3 V
Digital inputs = 0 V or 3 V
0.001
μA typ
1.0
μA max
1 Temperature range: A, B Grades, −40°C to +85°C. All specifications apply to both grades unless otherwise stated.
2 Guaranteed by design; not subject to production test.
Rev. E | Page 4 of 16
Data Sheet
ADG721/ADG722/ADG723
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter
VDD to GND
Analog, Digital Inputs1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
Continuous Current, S or D
Operating Temperature Range
Industrial (A, B Grade)
Storage Temperature Range
Junction Temperature
8-Lead MSOP
30 mA
−40°C to +85°C
−65°C to +150°C
+150°C
ESD CAUTION
θJA Thermal Impedance
θJC Thermal Impedance
8-Lead LFCSP (4-Layer Board)
θJA Thermal Impedance1
Lead Temperature, Soldering
Vapor Phase (60 sec)
206°C/W
44°C/W
50.8°C/W
215°C
220°C
Infrared (15 sec)
Lead-Free Temperature,
Soldering
IR Reflow, Peak Temperature
Time at Peak Temperature
ESD
260°C (+0/−5°C)
10 sec to 40 sec
2 kV
1Assumes exposed paddle is tied to ground.
Rev. E | Page 5 of 16
ADG721/ADG722/ADG723
Data Sheet
PIN CONFIGURATION AND PIN DESCRIPTIONS
V
1
8
7
6
5
S1
DD
ADG721/
ADG722/
2
3
4
D1
IN1
D2
S2
ADG723
IN2
TOP VIEW
(Not to Scale)
GND
NOTES
1. EXPOSED PADDLE OF LFCSP
SHOULD BE TIED TO GROUND.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Descriptions
1
2
3
4
5
6
7
8
S1
D1
IN2
GND
S2
D2
IN1
VDD
Source Pin 1. May be an input or an output.
Drain Pin 1. May be an input or an output.
Logic Control Input for Switch S2D2.
Ground (0 V) Reference.
Source Pin 2. May be an input or an output.
Drain Pin 2. May be an input or an output.
Logic Control Input for Switch S1D1.
Positive Power Supply Input.
Table 5. Truth Table (ADG721/ADG722)
Table 6. Truth Table (ADG723)
ADG721 In
ADG722 In
Switch Condition
Logic
Switch 1
Switch 2
0
1
1
0
Off
On
0
1
Off
On
On
Off
Rev. E | Page 6 of 16
Data Sheet
ADG721/ADG722/ADG723
TERMINOLOGY
VDD
VD (VS)
Most positive power supply potential.
Analog voltage on the D and S terminals.
GND
CS (OFF)
Ground (0 V) reference.
Off switch source capacitance.
S
CD (OFF)
Source terminal. May be an input or output.
Off switch drain capacitance.
D
CD, CS (ON)
Drain terminal. May be an input or output.
On switch capacitance.
IN
tON
Logic control input.
Delay between applying the digital control input and the output
switching on.
RON
Ohmic resistance between D and S.
tOFF
Delay between applying the digital control input and the output
switching off.
∆RON
On resistance match between any two channels, that is,
R
ON max − RON min.
tD
Off time or on time measured between the 90% points of both
switches, when switching from one address state to another
(ADG723 only).
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
Crosstalk
A measure of unwanted signal that is the result of parasitic
capacitance.
IS (OFF)
Source leakage current with the switch off.
Off Isolation
ID (OFF)
A measure of unwanted signal coupling through an off switch.
Drain leakage current with the switch off.
Charge Injection
A measure of the glitch impulse transferred during switching.
ID, IS (ON)
Channel leakage current with the switch on.
Rev. E | Page 7 of 16
ADG721/ADG722/ADG723
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1m
6.0
T
= 25°C
A
V
= 5V
5.5
5.0
4.5
4.0
DD
V
= 2.7V
DD
100µ
10µ
1µ
V
= 4.5V
DD
V
= 3.0V
DD
3.5
3.0
2.5
2.0
V
= 5.0V
DD
100n
10n
1n
1.5
1.0
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 8. Supply Current vs. Input Switching Frequency
Figure 5. On Resistance as a Function of VD (VS), Single Supplies
–30
–40
–50
–60
–70
6
+85°C
V
= 3V
V
= 3V, 5V
DD
DD
5
4
3
2
+25°C
–40°C
–80
–90
1
0
–100
10k
100k
1M
10M
100M
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (Hz)
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 6. On Resistance as a Function of a VD (VS) for Different Temperatures,
DD = 3 V
Figure 9. Off Isolation vs. Frequency
V
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
–30
–40
V
DD
= 3V, 5V
V
= 5V
DD
–50
+25°C
+85°C
–40°C
–60
–70
–80
1.5
1.0
0.5
0
–90
–100
–110
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10k
100k
1M
10M
100M
FREQUENCY (Hz)
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
DD = 5 V
Figure 10. Crosstalk vs. Frequency
V
Rev. E | Page 8 of 16
Data Sheet
ADG721/ADG722/ADG723
–6
V
= 5V
DD
–7
–8
–9
–10
–11
–12
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 11. On Response vs. Frequency
Rev. E | Page 9 of 16
ADG721/ADG722/ADG723
TEST CIRCUITS
Data Sheet
I
DS
V1
I
(OFF)
A
I
(OFF)
A
I
(ON)
A
S
D
D
S
D
S
D
S
D
V
V
R
= V1/I
DS
V
V
D
V
D
S
S
ON
S
Figure 12. On Resistance
Figure 13. Off Leakage
Figure 14. On Leakage
V
DD
0.1µF
ADG721
ADG722
V
50%
50%
50%
50%
IN
V
DD
V
L
OUT
S
D
V
IN
R
C
L
V
S
300Ω
35pF
IN
90%
90%
V
OUT
GND
tON
tOFF
Figure 15. Switching Times
V
V
DD
0.1µF
V
50%
50%
IN
0V
0V
DD
S1
D1
V
V
V
OUT1
S1
90%
90%
V
V
R
C
OUT1
L1
300Ω
L1
35pF
V
OUT2
D2
R
S2
S2
C
IN1, IN2
L2
300Ω
L2
35pF
GND
V
90%
IN
90%
OUT2
0V
tD
tD
Figure 16. Break-Before-Make Time Delay, tD (ADG723 Only)
V
DD
SW ON
SW OFF
V
DD
V
R
IN
S
S
D
V
OUT
C
1nF
L
V
S
IN
V
OUT
ΔV
OUT
GND
Q
= C × ΔV
OUT
INJ
L
Figure 17. Charge Injection
Rev. E | Page 10 of 16
Data Sheet
ADG721/ADG722/ADG723
V
V
DD
DD
0.1µF
0.1µF
V
V
DD
DD
S
D
S
D
V
V
OUT
OUT
R
R
L
L
50Ω
50Ω
IN
IN
V
V
S
V
S
V
IN
IN
GND
GND
Figure 19. Channel-to-Channel Crosstalk
Figure 18. Off Isolation
V
DD
0.1µF
V
DD
50Ω
S
S
D
D
V
IN1
V
V
IN2
S
V
OUT
NC
GND
R
L
50Ω
CHANNEL-TO-CHANNEL
CROSSTALK
= 20 × log
|V
/V |
OUT
S
Figure 20. Bandwidth
Rev. E | Page 11 of 16
ADG721/ADG722/ADG723
APPLICATIONS
Data Sheet
The ADG721/ADG722/ADG723 belong to a new family of
Analog Devices CMOS switches. This series of general-purpose
switches has improved switching times, lower on resistance, higher
bandwidths, low power consumption, and low leakage currents.
The signal transfer characteristic is dependent on the switch
channel capacitance, CDS. This capacitance creates a frequency
zero in the numerator of the transfer function A(s). Because the
switch on resistance is small, this zero usually occurs at high
frequencies. The bandwidth is a function of the switch output
capacitance combined with CDS and the load capacitance. The
frequency pole corresponding to these capacitances appears in
the denominator of A(s).
ADG721/ADG722/ADG723 SUPPLY VOLTAGES
Functionality of the ADG721/ADG722/ADG723 extends from
a 1.8 V to a 5.5 V single supply, which makes it ideal for battery-
powered instruments, where important design parameters are
power efficiency and performance.
The dominant effect of the output capacitance, CD, causes the
pole breakpoint frequency to occur first. Therefore, in order to
maximize bandwidth, a switch must have a low input and
output capacitance and low on resistance (see Figure 11).
It is important to note that the supply voltage affects the input
signal range, the on resistance, and the switching times of the part.
The typical performance characteristics and the specifications
clearly show the effects of the power supplies.
OFF ISOLATION
Off isolation is a measure of the input signal coupled through
an off switch to the switch output. The capacitance, CDS, couples
the input signal to the output load, when the switch is off, as
shown in Figure 22.
For VDD = 1.8 V, on resistance is typically 40 Ω over the
temperature range.
ON RESPONSE VS. FREQUENCY
Figure 21 illustrates the parasitic components that affect the ac
performance of CMOS switches (the switch is shown surrounded
by a box). Additional external capacitances further degrade some
aspects of performance. These capacitances affect feedthrough,
crosstalk, and system bandwidth.
C
DS
S
D
V
OUT
C
V
C
R
LOAD
D
IN
LOAD
Figure 22. Off Isolation Is Affected by External Load
Resistance and Capacitance
C
DS
S
D
V
OUT
The larger the value of CDS, the larger the value of feedthrough
produced. Figure 9 illustrates the drop in off isolation as a
function of frequency. From dc to roughly 1 MHz, the switch
shows better than −80 dB isolation. Up to frequencies of 10
MHz, the off isolation remains better than −60 dB. As the
frequency increases, more and more of the input signal is
coupled through to the output. Off isolation can be maximized
by choosing a switch with the smallest CDS possible. The values
of load resistance and capacitance also affect off isolation
because they contribute to the coefficients of the poles and
zeros in the transfer function of the switch when open.
R
ON
C
R
V
D
C
LOAD
LOAD
IN
Figure 21. Switch Represented by Equivalent Parasitic Components
The transfer function that describes the equivalent diagram of
the switch (Figure 21) is of the form (A)s, as shown in the
following equation:
s
(
(
RON CDS
RON CT RT
)
+ 1
+ 1
A(s) = RT
s
)
where:
CT = CLOAD + CD + CDS
RT = RLOAD/(RLOAD + RON)
s
(
RLOAD CDS
)
A(s) =
s
(
RLOAD
)
(
CLOAD + CD + CDS
)
+ 1
Rev. E | Page 12 of 16
Data Sheet
ADG721/ADG722/ADG723
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 23. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
1.75
2.00 BSC
1.65
1.50
5
8
3.00 BSC
1.90
1.80
1.65
EXPOSED
PAD
0.20 MIN
4
1
PIN 1
INDICATOR
INDEX
AREA
0.50
0.40
0.30
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.15 REF
COPLANARITY
0.08
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.50
Figure 24. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 2 mm Body, Very Very Thin, Dual Lead
(CP-8-4)
Dimensions shown in millimeters
Rev. E | Page 13 of 16
ADG721/ADG722/ADG723
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
Package Description
8-Lead MSOP
Package Option
RM-8
Branding2
S6B
ADG721BRM
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
ADG721BRM-REEL
ADG721BRM-REEL7
ADG721BRMZ
ADG721BRMZ-REEL
ADG721BRMZ-REEL7
ADG721ACPZ-REEL
ADG721ACPZ-REEL7
ADG722BRM
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
RM-8
RM-8
RM-8
RM-8
S6B
S6B
#S6B
#S6B
#S6B
17
8-Lead MSOP
RM-8
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead LFCSP_WD
8-Lead LFCSP_WD
CP-8-4
CP-8-4
RM-8
RM-8
RM-8
RM-8
RM-8
CP-8-4
CP-8-4
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
CP-8-4
CP-8-4
17
S7B
S7B
#S7B
#S7B
#S7B
0U
ADG722BRM-REEL7
ADG722BRMZ
ADG722BRMZ-REEL
ADG722BRMZ-REEL7
ADG722ACPZ-REEL
ADG722ACPZ-REEL7
ADG723BRM
ADG723BRM-REEL
ADG723BRM-REEL7
ADG723BRMZ
ADG723BRMZ-REEL
ADG723BRMZ-REEL7
ADG723ACPZ-REEL
ADG723ACPZ-REEL7
0U
S8B
S8B
S8B
#S8B
#S8B
#S8B
S2N
S2N
1 Z = RoHS Compliant Part; # denotes lead-free product may be top or bottom marked.
2 Branding = due to package size limitations, these three characters represent the part number.
Rev. E | Page 14 of 16
Data Sheet
NOTES
ADG721/ADG722/ADG723
Rev. E | Page 15 of 16
ADG721/ADG722/ADG723
NOTES
Data Sheet
©2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00045-0-10/11(E)
Rev. E | Page 16 of 16
相关型号：
ADG721BRMZ-REEL
DUAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
ROCHESTER
ADG721BRMZ-REEL7
DUAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
ROCHESTER
ADG722ACPZ-REEL7
DUAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO8, 3 X 2 MM, ROHS COMPLIANT, LFCSP-8
ROCHESTER
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