ADG751ART-REEL [ADI]
1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO6, SOT-23, 6 PIN;
| 型号： | ADG751ART-REEL |
| 厂家： | 
ADI |
| 描述： | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO6, SOT-23, 6 PIN 光电二极管 输出元件 |
| 文件： | 总12页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, Low Voltage
a
RF/Video, SPST Switch
ADG751
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High Off Isolation –75 dB at 100 MHz
–3 dB Signal Bandwidth 300 MHz
+1.8 V to +5.5 V Single Supply
Low On-Resistance (15 ⍀)
Fast Switching Times
ADG751
S
D
t
ON Typically 9 ns
tOFF Typically 3 ns
Typical Power Consumption <0.01 W
TTL/CMOS Compatible
IN
APPLICATIONS
Audio and Video Switching
RF Switching
SWITCH SHOWN FOR A LOGIC "1" INPUT
Networking Applications
Battery Powered Systems
Communication Systems
Relay Replacement
Sample-and-Hold Systems
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. High Off Isolation –75 dB at 100 MHz.
The ADG751 is a low voltage SPST (single pole, single throw)
switch. It is constructed in a T-switch configuration, which
results in excellent Off Isolation while maintaining good fre-
quency response in the ON condition.
2. –3 dB Signal Bandwidth 300 MHz.
3. Low On-Resistance (15 Ω).
4. Low Power Consumption, typically <0.01 µW.
5. Tiny 6-lead SOT-23 and 8-lead µSOIC packages.
High off isolation and wide signal bandwidth make this part
suitable for switching RF and video signals. Low power con-
sumption and operating supply range of +1.8 V to +5.5 V make
it ideal for battery powered, portable instruments.
The ADG751 is designed on a submicron process that provides
low power dissipation yet gives high switching speed and low on
resistance. This part is a fully bidirectional switch and can handle
signals up to and including the supply rails.
The ADG751 is available in 6-lead SOT-23 and 8-lead µSOIC
packages.
REV.
A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
781/461-3113
2012
Fax:
© Analog Devices, Inc.,
ADG751* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• ADG751 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• Evaluation Board for 6 lead SOT23 Devices in the
Switches/Multiplexers Portfolio
• Evaluation Board for 8 lead MSOP Devices in the Switch/
Mux Portfolio
DISCUSSIONS
View all ADG751 EngineerZone Discussions.
DOCUMENTATION
Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
• ADG751: CMOS, Low Voltage, RF/Video, SPST Switch Data
Sheet
TECHNICAL SUPPORT
User Guides
Submit a technical question or find your regional support
number.
• UG-893: Evaluating the 8-Lead MSOP Devices in the
Switch/Mux Portfolio
• UG-948: Evaluation Board for 6-Lead SOT-23 Devices in
the Switches and Multiplexers Portfolio
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
REFERENCE MATERIALS
Product Selection Guide
• Switches and Multiplexers Product Selection Guide
Technical Articles
• CMOS Switches Offer High Performance in Low Power,
Wideband Applications
• Data-acquisition system uses fault protection
• Enhanced Multiplexing for MEMS Optical Cross Connects
• Temperature monitor measures three thermal zones
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
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(VDD = +5 V ؎ 10%, GND = 0 V, unless otherwise noted.)
ADG751–SPECIFICATIONS
B Grade
–40؇C to
A Grade
–40؇C to
+85؇C
Parameter
+25؇C
+85؇C
+25؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
0 V to VDD
V
On-Resistance (RON
)
28
35
3
15
18
2
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to 2.5 V, IDS = 10 mA
VDD = 4.5 V
40
5
20
3
On-Resistance Flatness (RFLAT(ON)
)
LEAKAGE CURRENTS
V
DD = +5.5 V
Source OFF Leakage IS (OFF)
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
nA typ
nA max Test Circuit 2
nA typ
nA max Test Circuit 2
nA typ
nA max Test Circuit 3
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
±3.0
±3.0
±3.0
±3.0
±3.0
±3.0
Drain OFF Leakage ID (OFF)
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Channel ON Leakage ID, IS (ON)
VD = VS = 1 V, or 4.5 V;
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
I
INL or IINH
0.001
2
0.001
2
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.5
±0.5
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
tON
9
9
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 4
VS = 1 V, RS = 0 Ω, CL = 1.0 nF;
Test Circuit 5
13
5
13
5
tOFF
3
3
Charge Injection
Off Isolation
1
1
–75
–65
dB typ
RL = 50 Ω, CL = 5 pF, f = 100 MHz;
Test Circuit 6
–3 dB Bandwidth
CS (OFF)
180
4
4
300
4
4
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 7
pF typ
pF typ
pF typ
CD (OFF)
CD, CS (ON)
26
15
POWER REQUIREMENTS
IDD
V
DD = +5.5 V
0.001
0.1
0.001
0.1
µA typ
µA max
Digital Inputs = 0 V or +5.5 V
0.5
0.5
NOTES
1Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV.
A
ADG751
(VDD = +3 V ؎ 10%, GND = 0 V, unless otherwise noted.)
SPECIFICATIONS
B Grade
–40؇C to
A Grade
–40؇C to
Parameter
+25؇C
+85؇C
+25؇C
+85؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
90
0 V to VDD
50
V
On-Resistance (RON
)
60
35
Ω typ
Ω max
VS = 0 V to VDD, IDS = –10 mA;
Test Circuit 1
LEAKAGE CURRENTS
VDD = +3.3 V
Source OFF Leakage IS (OFF)
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
nA typ
nA max Test Circuit 2
nA typ
nA max Test Circuit 2
nA typ
nA max Test Circuit 3
VD = 3 V/1 V, VS = 1 V/3 V;
±3.0
±3.0
±3.0
±3.0
±3.0
±3.0
Drain OFF Leakage ID (OFF)
VD = 1 V/3 V, VS = 3 V/1 V;
Channel ON Leakage ID, IS (ON)
VD = VS = 1 V, or 3 V;
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.4
2.0
0.4
V min
V max
I
INL or IINH
0.001
2
0.001
2
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.5
±0.5
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
tON
12
4
12
4
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 4
VS = 1 V, RS = 0 Ω, CL = 1.0 nF;
Test Circuit 5
19
6
19
6
tOFF
Charge Injection
Off Isolation
1
1
–75
–65
dB typ
RL = 50 Ω, CL = 5 pF, f = 100 MHz;
Test Circuit 6
–3 dB Bandwidth
CS (OFF)
180
4
4
280
4
4
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 7
pF typ
pF typ
pF typ
CD (OFF)
CD, CS (ON)
26
15
POWER REQUIREMENTS
IDD
V
DD = +3.3 V
0.001
0.1
0.001
0.1
µA typ
µA max
Digital Inputs = 0 V or +3.3 V
0.5
0.5
NOTES
1Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV.
–3–
A
ADG751
ABSOLUTE MAXIMUM RATINGS1
SOT-23 Package
(TA = +25°C unless otherwise noted)
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 229.6°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 91.99°C/W
θ
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Analog, Digital Inputs2 . . . . . . . . . . . –0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . .+150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . (TJ Max–TA)/θJA
µSOIC Package
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
θ
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG751 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV.
A
ADG751
TERMINOLOGY
PIN CONFIGURATIONS
8-Lead SOIC
(RM-8)
VDD
GND
S
Most positive power supply potential.
Ground (0 V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
NC
S
1
2
3
4
8
7
6
5
D
IN
RON
RFLAT(ON)
V
DD
ADG751
D
TOP VIEW
(Not to Scale)
NC
NC
GND
IN
Ohmic resistance between D and S.
Flatness is defined as the difference between
the maximum and minimum value of on resis-
tance as measured over the specified analog
signal range.
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D and S.
“OFF” switch source capacitance.
“OFF” switch drain capacitance.
“ON” switch capacitance.
Delay between applying the digital control
input and the output switching on. See Test
Circuit 4.
NC = NO CONNECT
6-Lead SOT-23
(RT-6)
IS (OFF)
I
D (OFF)
ID, IS (ON)
VD (VS)
CS (OFF)
CD (OFF)
CD, CS (ON)
tON
S
1
2
3
6
5
4
D
ADG751
V
GND
IN
DD
TOP VIEW
(Not to Scale)
NC
NC = NO CONNECT
tOFF
Delay between applying the digital control
input and the output switching off.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” switch.
Charge
Injection
A measure of the glitch impulse transferred from
the digital input to the analog output during
switching.
Bandwidth
The frequency at which the output is attenu-
ated by –3 dBs.
On Response
The frequency response of the “ON” switch.
Insertion Loss Loss due to the ON resistance of the switch.
VINL
Maximum input voltage for Logic “0.”
Minimum input voltage for Logic “1.”
Input current of the digital input.
Positive supply current.
VINH
IINL(IINH
IDD
)
Table I. Truth Table
ADG751 IN
Switch Condition
0
1
ON
OFF
REV.
A
–5–
–Typical Performance Characteristics
ADG751
65
35
30
25
20
15
10
T
= +25؇C
V
= +2.7V
A
DD
V
= +2.7V
60
55
50
45
40
35
DD
T
= +25؇C
A
V
= +3.3V
DD
V
= +3.3V
V
= +4.5V
DD
DD
30
25
V
= +4.5V
V
DD
= +5.5V
20
15
DD
V
= +5.5V
3
DD
5
0
0
1.0
2.0
3.0
4.0
5.0 5.4
1
D
2
4
5
V
OR V DRAIN SOURCE VOLTAGE – Volts
S
D
V
OR V DRAIN SOURCE VOLTAGE – Volts
S
Figure 4. On Resistance as a Function of VD (VS) Single
Supplies (B Grade)
Figure 1. On Resistance as a Function of VD (VS) Single
Supplies (A Grade)
65
35
V
= +3V
DD
V
= +3V
DD
60
55
50
45
40
35
+125؇C
30
25
+125؇C
+85؇C
+85؇C
20
15
10
5
+25؇C
–40؇C
+25؇C
–40؇C
30
25
20
15
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8 3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
OR V DRAIN SOURCE VOLTAGE – Volts
S
D
V
OR V DRAIN SOURCE VOLTAGE – Volts
S
D
Figure 5. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 3 V (B Grade)
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 3 V (A Grade)
35
65
V
= +5V
DD
V
= +5V
DD
60
55
50
45
40
35
30
30
25
20
15
10
5
+125؇C
+125؇C
+85؇C
+85؇C
25
20
15
10
5
–40؇C
+25؇C
+25؇C
–40؇C
0
0
0
0
1.0
2.0
3.0
4.0
5.0
1
2
3
4
5
V
OR V DRAIN SOURCE VOLTAGE – Volts
V
OR V DRAIN SOURCE VOLTAGE – Volts
S
D
S
D
Figure 6. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 5 V (B Grade)
Figure 3. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 5 V (A Grade)
–6–
REV.
A
ADG751
10m
0
V
= +5V
DD
T
= +25؇C
A
B GRADE
T
= +25؇C
1m
A
A GRADE
10
–5
1
100n
10n
0.1
–10
1k
10k
100k
100M
10M
100
1
10
300
FREQUENCY – MHz
FREQUENCY – Hz
Figure 10. Supply Current vs. Input Switching Frequency
Figure 7. On Response vs. Frequency (A Grade)
0
6
T
= +25؇C
A
4
2
0
T
= +25؇C
A
V
= +3V
DD
V
= +5V
DD
–2
–4
–5
–6
–8
–10
–10
0
1.0
3.0
SOURCE VOLTAGE – Volts
4.0
5.0
2.0
10
100
1
300
FREQUENCY – MHz
Figure 11. Charge Injection vs. Source/Drain Voltage
Figure 8. On Response vs. Frequency (B Grade)
0
T
= +25؇C
A
–25
–50
–75
A GRADE
B GRADE
–100
–125
1
10
100
300
FREQUENCY – MHz
Figure 9. Off Isolation vs. Frequency for Both Grades
REV.
A
–7–
ADG751
GENERAL DESCRIPTION
LAYOUT CONSIDERATIONS
The ADG751 is an SPST switch constructed using switches in a
T configuration to obtain high “OFF” isolation while maintain-
ing good frequency response in the “ON” condition.
Where accurate high frequency operation is important, careful
consideration should be given to the printed circuit board layout
and to grounding. Wire wrap boards, prototype boards and
sockets are not recommended because of their high parasitic
inductance and capacitance. The part should be soldered di-
rectly to a printed circuit board. A ground plane should cover all
unused areas of the component side of the board to provide a
low impedance path to ground. Removing the ground planes
from the area around the part reduces stray capacitance.
Figure 12 shows the T-switch configuration. While the switch is
in the OFF state, the shunt switch is closed and the two series
switches are open. The closed shunt switch provides a signal
path to ground for any of the unwanted signals that find their
way through the off capacitances of the series’ MOS devices.
This results in improved isolation between the input and output
than with an ordinary series switch. When the switch is in the
ON condition, the shunt switch is open and the signal path is
through the two series switches which are now closed.
Good decoupling is important in achieving optimum perfor-
mance. VDD should be decoupled with a 0.1 µF surface mount
capacitor to ground mounted as close as possible to the device
itself.
SERIES
D
S
SHUNT
IN
Figure 12. Basic T-Switch Configuration
–8–
REV.
A
ADG751
Test Circuits
V1
I
(OFF)
A
I
(OFF)
A
S
D
I
(ON)
A
S
D
D
S
D
S
D
NC
V
S
V
I
S
V
DS
D
V
D
R
= V1/I
DS
ON
NC = NO CONNECT
Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
V
DD
0.1F
V
50%
50%
IN
V
DD
S
D
V
OUT
R
300⍀
C
L
35pF
L
V
S
IN
V
S
90%
90%
V
GND
OUT
tOFF
tON
Test Circuit 4. Switching Times
V
DD
V
V
IN
DD
OFF
ON
R
S
S
D
V
OUT
C
L
V
S
1.0nF
IN
⌬V
V
OUT
OUT
Q
= C
؋
⌬V L OUT
INJ
GND
Test Circuit 5. Charge Injection
V
V
DD
DD
0.1F
0.1F
V
V
DD
DD
NETWORK
ANALYZER
NETWORK
ANALYZER
NETWORK
ANALYZER
NETWORK
ANALYZER
50⍀
50⍀
S
D
S
D
V
V
OUT
OUT
R
L
50⍀
R
L
50⍀
V
S
50⍀
IN
V
S
IN
GND
GND
V
IN
V
IN
V
OUT
OFF ISOLATION = 20 LOG
V
S
V
WITH SWITCH
OUT
INSERTION LOSS = 20 LOG
V
WITHOUT SWITCH
OUT
Test Circuit 6. Off Isolation
Test Circuit 7. Bandwidth
REV.
A
–9–
ADG751
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 12. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
2.90
2.80
6
1
5
2
4
3
3.00
2.80
2.60
1.70
1.60
1.50
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
4°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.30 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 13. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
–10–
REV. A
ADG751
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Brand2
SDB
SDB
SDB
SDB
SDA
SDA
SDA
SDA
SDA
Package Description
Package Option
ADG751BRMZ-REEL
ADG751BRT-REEL
ADG751BRT-REEL7
ADG751BRTZ-REEL7
ADG751ARMZ
ADG751ARMZ-REEL
ADG751ART-REEL
ADG751ART-REEL7
ADG751ARTZ-REEL7
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
RM-8
RJ-6
RJ-6
RJ-6
RM-8
RM-8
RJ-6
RJ-6
RJ-6
1 Z = RoHS Compliant Part.
2 Brand on these packages is limited to three characters due to space constraints.
REVISION HISTORY
8/12—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 11
4/99—Revision 0—Initial Version
©1999–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10943-0-8/12(A)
REV. A
–11–
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