ADG779BKSZ-REEL72 [ADI]
CMOS 1.8 V to 5.5 V, 2.5 Ω SPDT Switch/2:1 Mux in Tiny SC70 Package; CMOS 1.8 V至5.5 V , 2.5升©单刀双掷开关/ 2 : 1多路复用器,采用微型SC70封装型号: | ADG779BKSZ-REEL72 |
厂家: | ADI |
描述: | CMOS 1.8 V to 5.5 V, 2.5 Ω SPDT Switch/2:1 Mux in Tiny SC70 Package |
文件: | 总12页 (文件大小:285K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CMOS 1.8 V to 5.5 V, 2.5 Ω
SPDT Switch/2:1 Mux in Tiny SC70 Package
ADG779
FUNCTIONAL BLOCK DIAGRAM
FEATURES
1.8 V to 5.5 V single supply
2.5 Ω on resistance
ADG779
S2
D
0.75 Ω on-resistance flatness
−3 dB bandwidth >200 MHz
Rail-to-rail operation
6-lead SC70 package
Fast switching times
tON 20 ns
S1
IN
SWITCHES SHOWN FOR
A LOGIC 1 INPUT
Figure 1.
tOFF 6 ns
Typical power consumption (<0.01 μW)
TTL/CMOS compatible
APPLICATIONS
Battery-powered systems
Communication systems
Sample hold systems
Audio signal routing
Video switching
Mechanical reed relay replacements
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG779 is a monolithic CMOS SPDT (single-pole,
double-throw) switch. This switch is designed on a submicron
process that provides low power dissipation yet gives high
switching speed, low on resistance, and low leakage currents.
1. Tiny 6-Lead SC70 Package.
2. 1.8 V to 5.5 V Single-Supply Operation. The ADG779
offers high performance, including low on resistance and
fast switching times, and is fully specified and guaranteed
with 3 V and 5 V supply rails.
The ADG779 operates from a single supply range of 1.8 V to
5.5 V, making it ideal for use in battery-powered instruments
and with the new generation of DACs and ADCs from Analog
Devices, Inc.
3. Very Low RON (5 Ω max at 5 V, 10 Ω max at 3 V). At 1.8 V
operation, RON is typically 40 Ω over the temperature range.
Each switch of the ADG779 conducts equally well in both
directions when on. The ADG779 exhibits break-before-make
switching action.
4. On-Resistance Flatness (RFLAT (ON)) (0.75 Ω typ).
5. −3 dB Bandwidth > 200 MHz.
Because of the advanced submicron process, −3 dB bandwidth
of greater than 200 MHz can be achieved.
6. Low Power Dissipation. CMOS construction ensures low
power dissipation.
The ADG779 is available in a 6-lead SC70 package.
7. 14 ns Switching Times.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADG779
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................6
Terminology .......................................................................................7
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 10
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
REVISION HISTORY
10/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Terminology Section.................................................... 7
Changes to Ordering Guide .......................................................... 12
7/01—Revision 0: Initial Version
Rev. A | Page 2 of 12
ADG779
SPECIFICATIONS
VDD = 5 V 10ꢀ, GND = 0 V1
Table 1.
B Version
−40°C to
Parameter
25°C
+85°C
0 V to VDD
6
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
V
2.5
5
0.1
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = −10 mA, see Figure 12
VS = 0 V to VDD, IS = −10 mA
On-Resistance Match Between Channels (ΔRON)
0.8
On-Resistance Flatness (RFLAT (ON)
)
0.75
VS = 0 V to VDD, IS = −10 mA
1.2
LEAKAGE CURRENTS2
Source Off Leakage IS (Off)
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
VDD = 5.5 V
0.01
0.01
0.05
0.05
nA typ
nA typ
VS = 4.5 V/1 V, VD = 1 V/4.5 V, see Figure 13
VS = VD = 1 V, or VS = VD = 4.5 V, see Figure 14
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
μA typ
VIN = VINL or VINH
0.1
μA max
DYNAMIC CHARACTERISTICS2
tON
14
3
ns typ
ns max
ns typ
ns max
ns typ
ns min
dB typ
dB typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 15
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 15
20
6
tOFF
Break-Before-Make Time Delay, tD
Off Isolation
8
RL = 300 Ω, CL = 35 pF
1
VS1 = VS2 = 3 V, see Figure 16
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 17
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18
−67
−87
−62
−82
200
7
Channel-to-Channel Crosstalk
Bandwidth –3 dB
CS (Off)
CD, CS (On)
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 19
pF typ
pF typ
f = 1 MHz
f = 1 MHz
27
POWER REQUIREMENTS
VDD = 5.5 V
Digital Inputs = 0 V or 5 V
IDD
0.001
μA typ
1.0
μA max
1 Temperature range is B Version, −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. A | Page 3 of 12
ADG779
VDD = 3 V 10ꢀ, GND = 0 V1
Table 2.
B Version
−40°C to
Parameter
25°C
+85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
7
10
V
6
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = –10 mA, see Figure 12
VS = 0 V to VDD, IS = –10 mA
On-Resistance Match Between Channels (ΔRON)
0.1
2.5
0.8
On-Resistance Flatness (RFLAT (ON)
LEAKAGE CURRENTS2
Source Off Leakage IS (Off)
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
)
VS = 0 V to VDD, IS = –10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V, see Figure 13
VS = VD = 1 V, or VS = VD = 3 V, see Figure 14
0.01
0.01
0.05
0.05
nA typ
nA typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.005
μA typ
VIN = VINL or VINH
0.1
μA max
DYNAMIC CHARACTERISTICS2
tON
16
4
ns typ
ns max
ns typ
ns max
ns typ
ns min
dB typ
dB typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 2 V, see Figure 15
RL = 300 Ω, CL = 35 pF
VS = 2 V, see Figure 15
24
7
tOFF
Break-Before-Make Time Delay, tD
Off Isolation
8
RL = 300 Ω, CL = 35 pF
1
VS1 = VS2 = 2 V, see Figure 16
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 17
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18
–67
–87
–62
–82
200
7
Channel-to-Channel Crosstalk
Bandwidth −3 dB
CS (Off)
CD, CS (On)
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 19
pF typ
pF typ
f = 1 MHz
f = 1 MHz
27
POWER REQUIREMENTS
VDD = 3.3 V
Digital Inputs = 0 V or 3 V
IDD
0.001
μA typ
1.0
μA max
1 Temperature range is B Version, −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 12
ADG779
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to GND
Analog, Digital Inputs1
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
100 mA (pulsed at 1 ms,
10% duty cycle max)
30 mA
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
−40°C to +85°C
−65°C to +150°C
150°C
SC70 Package, Power Dissipation 315 mW
Table 4. Truth Table
ADG779 IN
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
332°C/W
120°C/W
Switch S1
On
Switch S2
Off
0
1
Off
On
215°C
220°C
Infrared (15 sec)
Reflow Soldering (Pb-free)
Peak Temperature
260 (+0/−5)°C
Time at Peak Temperature
10 sec to 40 sec
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 12
ADG779
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN
1
2
3
6
5
4
S2
D
ADG779
V
TOP VIEW
DD
(Not to Scale)
GND
S1
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
IN
Logic Control Input.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
VDD
GND
S1
D
S2
Rev. A | Page 6 of 12
ADG779
TERMINOLOGY
VDD
CD (Off)
Most positive power supply potential.
Off switch drain capacitance. Measured with reference to
ground.
IDD
Positive supply current.
CD, CS (On)
On switch capacitance. Measured with reference to ground.
GND
Ground (0 V) reference.
CIN
Digital input capacitance.
S
Source terminal. Can be an input or an output.
tON
Delay time between the 50ꢀ and 90ꢀ points of the digital input
and switch on condition.
D
Drain terminal. Can be an input or an output.
tOFF
IN
Delay time between the 50ꢀ and 90ꢀ points of the digital input
and switch off condition.
Logic control input.
VD (VS)
tBBM
Analog voltage on drain (D) and source (S) terminals.
On or off time measured between the 80ꢀ points of both
switches when switching from one to another.
RON
Ohmic resistance between the D and S.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during on/off switching.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ΔRON
On-resistance mismatch between any two channels.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another because of parasitic capacitance.
IS (Off)
Source leakage current with the switch off.
−3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
ID (Off)
Drain leakage current with the switch off.
On Response
The frequency response of the on switch.
ID, IS (On)
Channel leakage current with the switch on.
Insertion Loss
The loss due to the on resistance of the switch.
VINL
Maximum input voltage for Logic 0.
THD + N
VINH
The ratio of harmonic amplitudes plus noise of a signal to the
fundamental.
Minimum input voltage for Logic 1.
IINL (IINH
)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to
ground.
Rev. A | Page 7 of 12
ADG779
TYPICAL PERFORMANCE CHARACTERISTICS
0.15
0.10
0.05
0
6.0
V
V
V
= 5V
= 4.5V/1V
= 1V/4.5V
DD
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 2.7V
DD
T
= 25°C
D
S
A
V
= 4.5V
DD
V
= 3V
DD
I
, I (ON)
S
D
V
= 5V
DD
I
(OFF)
40
S
–0.05
0
10
20
30
50
60
70
80
90
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TEMPERATURE (°C)
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
S
D
Figure 3. On Resistance as a Function of VD (VS) Single Supplies
Figure 6. Leakage Currents as a Function of Temperature
6.0
0.15
0.10
0.05
0
V
V
V
= 3V
= 3V/1V
= 1V/3V
DD
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 3V
DD
D
S
+85°C
+25°C
–40°C
I
, I (ON)
S
D
I
(OFF)
40
S
–0.05
0
10
20
30
50
60
70
80
90
0
0.5
1.0
1.5
2.0
2.5
3.0
TEMPERATURE (°C)
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 4. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 3 V
Figure 7. Leakage Currents as a Function of Temperature
10m
1m
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
DD
V
= 5V
DD
100µ
10µ
1µ
+85°C
+25°C
–40°C
100n
10n
1n
1
10
100
1k
10k
100k
1M
10M
100M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (Hz)
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
Figure 5. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 5 V
Figure 8. Supply Current vs. Input Switching Frequency
Rev. A | Page 8 of 12
ADG779
–30
–40
–50
–60
–70
0
V
= 5V, 3V
DD
V
= 5V
DD
–2
–80
–90
–4
–6
–100
–110
–120
–130
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. Off Isolation vs. Frequency
Figure 11. On Response vs. Frequency
–30
–40
–50
–60
–70
V
= 5V, 3V
DD
–80
–90
–100
–110
–120
–130
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 10. Crosstalk vs. Frequency
Rev. A | Page 9 of 12
ADG779
TEST CIRCUITS
I
DS
V1
I
(OFF)
A
I
D
(OFF)
A
S
S
D
S
D
I
(ON)
D
S
D
A
V
D
V
S
V
V
D
S
V
R = V1/I
ON DS
S
Figure 13. Off Leakage
Figure 12. On Resistance
Figure 14. On Leakage
V
DD
0.1µF
S
V
50%
50%
IN
V
DD
D
90%
90%
V
V
OUT
OUT
C
L
R
V
S
L
35pF
300Ω
IN
tON
tOFF
GND
Figure 15. Switching Times
V
DD
0.1µF
V
50%
50%
IN
0V
0V
V
DD
S1
V
V
S1
S2
D2
D
V
OUT
50%
50%
V
S2
IN
C
L2
35pF
OUT
R
L2
300Ω
V
GND
IN
tD
tD
Figure 16. Break-Before-Make Time Delay, tD
Rev. A | Page 10 of 12
ADG779
V
V
DD
DD
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
DD
V
DD
S
50Ω
S
50Ω
IN
50Ω
IN
V
S
V
S
D
D
V
OUT
V
OUT
V
IN
R
50Ω
V
L
IN
R
50Ω
L
GND
GND
V
WITH SWITCH
OUT
V
OUT
INSERTION LOSS = 20 log
OFF ISOLATION = 20 log
V
WITHOUT SWITCH
OUT
V
S
Figure 19. Bandwidth
Figure 17. Off Isolation
V
DD
0.1µF
NETWORK
ANALYZER
V
DD
S1
S2
V
OUT
R
50Ω
L
D
R
50Ω
50Ω
IN
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 18. Channel-to-Channel Crosstalk
Rev. A | Page 11 of 12
ADG779
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.46
0.36
0.26
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 20. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model
Temperature Range
Package Description
Branding1
SKB
SKB
SKB
S0M
S0M
S0M
ADG779BKS-R2
ADG779BKS-REEL
ADG779BKS-REEL7
ADG779BKSZ-R22
ADG779BKSZ-REEL2
ADG779BKSZ-REEL72
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
1 Brand on these packages is limited to three characters due to space constraints.
2 Z = Pb-free part.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02491–0–10/05(A)
Rev. A | Page 12 of 12
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