ADG787BRMZ-500RL7 [ADI]
2.5 OHM CMOS Low Power Dual 2:1 Mux/Demux USB 1.1 Switch; 2.5欧姆CMOS低功耗双2 ： 1复用/解复用USB 1.1开关
| 型号： | ADG787BRMZ-500RL7 |
| 厂家： | 
ADI |
| 描述： | 2.5 OHM CMOS Low Power Dual 2:1 Mux/Demux USB 1.1 Switch |
| 文件： | 总16页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 Ω CMOS Low Power
Dual 2:1 Mux/Demux USB 1.1 Switch
ADG787
FUNCTIONAL BLOCK DIAGRAM
FEATURES
USB 1.1 signal switching compliant
−3 dB bandwidth, 150 MHz
Tiny 10-lead LFCSP and MSOP packages, 10-ball WLCSP
package
ADG787
S1A
D1
S1B
IN1
IN2
Single-supply 1.8 V to 5.5 V operation
Low on resistance
2.5 Ω typical
3.45 Ω maximum at 85°C
Typical power consumption: <0.1 μW
S2A
D2
S2B
SWITCHES SHOWN
FOR A LOGIC 0 INPUT
APPLICATIONS
USB 1.1 signal switching circuits
Cellular phones
Figure 1.
PDAs
MP3 players
Battery-powered systems
Headphone switching
Audio and video signal routing
Communications systems
GENERAL DESCRIPTION
The ADG787 is a low voltage, CMOS device that contains two
independently selectable single-pole, double-throw (SPDT)
switches. It is designed as a general analog-to-digital switch and
can also be used for routing USB 1.1 signals.
MASK: FS (12Mbps)
This device offers low on resistance of typically 2.5 Ω, making
the part an attractive solution for applications that require low
distortion through the switch.
The ADG787 comes in a 10-ball WLCSP, a tiny 10-lead LFCSP,
and a tiny 10-lead MSOP. These packages make the ADG787
the ideal solution for space-constrained applications.
1
20.0ns/DIV
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG787 exhibits break-before-make switching action.
V
= 3V p-p
IN
T
= 25°C
A
Figure 2. Eye Pattern; 12 Mbps, VDD = 4.2 V, PRBS 31
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG787
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions............................6
Truth Table .....................................................................................6
Typical Performance Characteristics ..............................................7
Test Circuits ................................................................................ 11
Terminology.................................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
REVISION HISTORY
5/06—Rev. 0 to Rev. A
Updated Formatting...........................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 3............................................................................ 5
Changes to Ordering Guide .......................................................... 15
1/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG787
SPECIFICATIONS
VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
+25°C
B Version1
0 to VDD
3.45
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
V
2.5
3
0.02
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VDD = 4.2 V, VS = 0 V to VDD, IS = 10 mA
See Figure 28
VDD = 4.2 V, VS = 3.5 V, IS = 10 mA
On Resistance Match Between Channels (ΔRON)
0.1
On Resistance Flatness (RFLAT (ON)
)
0.65
0.8
VDD = 4.2 V, VS = 0 V to VDD
IS = 10 mA
0.95
LEAKAGE CURRENTS
Source Off Leakage, IS (OFF)
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
VDD = 5.5 V
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 29
VS = VD = 1 V or 4.5 V; see Figure 30
0.05
0.05
nA typ
nA typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.005
2.5
μA typ
μA max
pF typ
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tON
13
19
3
5
0.06
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
RL = 50 Ω, CL = 35 pF
VS = 3 V; see Figure 31
RL = 50 Ω, CL = 35 pF
VS = 3 V; see Figure 31
CL = 50 pF; VS = 3 V
22
6
tOFF
Propagation Delay Skew, tSKEW
0.15
5
Break-Before-Make Time Delay (tBBM
)
10
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 3 V; see Figure 32
VD = 1 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
S1A to S2A/S1B to S2B; RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 37
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
14
−63
−110
−63
dB typ
S1A to S1B/S2A to S2B; RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 36
Total Harmonic Distortion (THD + N)
0.03
−0.2
145
16
%
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 36
Insertion Loss
−3 dB Bandwidth
CS (OFF)
dB typ
MHz typ
pF typ
pF typ
CD, CS (ON)
40
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
0.005
μA typ
1
μA max
1 Temperature ranges: B version: −40°C to +85°C for the MSOP and LFCSP packages, and −25°C to +85°C for the WLCSP package.
2 Guaranteed by design, not production tested.
Rev. A | Page 3 of 16
ADG787
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
+25°C B Version1
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
V
4
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VDD = 2.7 V, VS = 0 V to VDD
IS = 10 mA; see Figure 28
VDD = 2.7 V, VS = 1.5 V
IS = 10 mA
VDD = 2.7 V, VS = 0 V to VDD
IS = 10 mA
5.75
0.07
0.3
1.6
2.3
6
On Resistance Match Between Channels (ΔRON)
0.35
2.6
On Resistance Flatness (RFLAT (ON)
)
LEAKAGE CURRENTS
Source Off Leakage, IS (OFF)
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
VDD = 3.6 V
0.01
0.01
nA typ
nA typ
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 29
VS = VD = 0.6 V or 3.3 V; see Figure 30
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
1.3
0.8
V min
V max
IINL or IINH
0.005
2
μA typ
μA max
pF typ
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tON
18
30
4
6
0.04
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 31
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 31
CL = 50 pF; VS = 1.5 V
35
7
tOFF
Propagation Delay Skew, tSKEW
0.12
5
Break-Before-Make Time Delay (tBBM
)
15
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 32
VD = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
S1A to S2A/S1B to S2B; RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 37
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
10
−63
−110
−63
dB typ
S1A to S1B/S2A to S2B; RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 35
Total Harmonic Distortion (THD + N)
0.07
−0.24
145
16
%
dB typ
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 36
Insertion Loss
−3 dB Bandwidth
CS (OFF)
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36
pF typ
CD, CS (ON)
40
pF typ
POWER REQUIREMENTS
IDD
VDD = 3.6 V
Digital inputs = 0 V or 3.6 V
0.005
μA typ
1
μA max
1 Temperature range: B version: −40°C to +85°C for the MSOP and LFCSP packages, and −25°C to +85°C for the WLCSP package.
2 Guaranteed by design, not production tested.
Rev. A | Page 4 of 16
ADG787
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
Analog Inputs1, Digital Inputs
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V or
30 mA (whichever
occurs first)
Peak Current, S or D
5 V Operation
300 mA
3.3 V Operation
200 mA (pulsed at 1 ms,
10% duty cycle max)
Only one absolute maximum rating may be applied at any one
time.
Continuous Current, S or D
5 V Operation
3.3 V Operation
100 mA
80 mA
Operating Temperature Range
Extended Industrial (B Version)
MSOP and LFCSP packages
Industrial (B version)
−40°C to +85°C
WLCSP package
Storage Temperature Range
Junction Temperature
−25°C to +85°C
−65°C to +150°C
150°C
WLCSP Package (4-Layer Board)
θJA Thermal Impedance
LFCSP Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Lead-Free Temperature Soldering
IR Reflow, Peak Temperature
PeakTemperature
120°C/W
61°C/W
142°C/W
43.7°C/W
260(+0/−5)°C
Time at PeakTemperature
10 sec to 40 sec
1 Overvoltages at the IN, S, or D pins are clamped by internal diodes. Current
should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
ADG787
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
a
b
c
1
2
3
4
S1B GND S2B
V
1
2
3
4
5
10 S2A
DD
IN1
D1
IN2
D2
S1A
D1
9
8
7
6
D2
ADG787
TOP VIEW
(Not to Scale)
IN2
IN1
S1B
S2B
GND
S1A
V
S2A
DD
TOP VIEW
(BALLS AT THE BOTTOM)
Figure 3. 10-Lead LFCSP and 10-lead MSOP Pin Configuration
Figure 4. 10-Ball WLCSP Pin Configuration
Table 4. 10-Lead LFCSP/MSOP Pin Function Descriptions
Table 5. 10-Lead WLCSP Pin Function Descriptions
Pin
No.
Ball
Mnemonic
VDD
S1A
Description
Location Mnemonic Description
1
2
Most Positive Power Supply Potential.
Source Terminal. May be an input or
output.
Drain Terminal. May be an input or
output.
1a
S1B
Source Terminal. May be an input or
output.
Ground (0 V) Reference.
Source Terminal. May be an input or
output.
1b
1c
GND
S2B
3
D1
4
5
IN1
S1B
Logic Control Input.
Source Terminal. May be an input or
output.
Ground (0 V) Reference.
Source Terminal. May be an input or
output.
Logic Control Input.
Drain Terminal. May be an input or
output.
Source Terminal. May be an input or
output.
2a
IN1
Source Terminal. May be an input or
output.
Logic Control Input.
Drain Terminal. May be an input or
output.
Drain Terminal. May be an input or
output.
Logic Control Input.
Most Positive Power Supply Potential.
Source Terminal. May be an input or
output.
2c
3a
IN2
D1
6
7
GND
S2B
3c
D2
8
9
IN2
D2
4a
4b
4c
S1A
VDD
S2A
10
S2A
TRUTH TABLE
Table 6.
Logic (IN1/IN2)
Switch 1A/2A
Switch 1B/2B
0
1
Off
On
On
Off
Rev. A | Page 6 of 16
ADG787
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 4.2V
T
= 25°C
= 10mA
DD
I = 10mA
DS
A
V
= 4.5V
DD
I
DS
2.5
2.0
1.5
1.0
0.5
0
V
= 4.2V
DD
T
= +85°C
A
V
= 5V
DD
V
= 5.5V
T
T
= +25°C
= –40°C
DD
A
A
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SIGNAL RANGE
SIGNAL RANGE
Figure 5. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V
Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 4.2 V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
T
I
= 25°C
= 10mA
V
I
= 3V
A
DD
= 10mA
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
DS
DS
V
= 2.7V
DD
T
= +85°C
A
V
= 3V
DD
T
= +25°C
A
V
= 3.3V
T
= –40°C
DD
A
V
= 3.6V
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
SIGNAL RANGE
2.0
2.5
3.0
SIGNAL RANGE
Figure 6. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V
Figure 9. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3 V
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
V
= 5V
DD
= 10mA
I
DS
T
= +85°C
A
I , I (ON)
S
D
0.5
0
T
T
= +25°C
= –40°C
A
A
–0.5
–1.0
–1.5
–2.0
I
(OFF)
S
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
10
20
30
40
50
60
70
80
SIGNAL RANGE
TEMPERATURE (°C)
Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V
Figure 10. Leakage Current vs. Temperature, VDD = 5.5 V
Rev. A | Page 7 of 16
ADG787
2.0
30
25
20
15
10
5
T
= 25°C
A
1.5
1.0
I
(OFF)
S
V
= 3V
DD
0.5
T
T
ON
0
V
= 5V
DD
–0.5
–1.0
–1.5
I
, I (ON)
D
S
V
V
= 3V
= 5V
OFF
DD
DD
–2.0
0
0
–40
10
20
30
40
50
60
70
80
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Leakage Current vs. Temperature, VDD = 3.3 V
Figure 14. tON/tOFF Time vs. Temperature
2.0
0
–1
–2
–3
–4
–5
–6
–7
–8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
A
= 3V/4.2V/5V
DD
= 25°C
T
V
RISING
V
FALLING
IN
IN
1.5
2.0
2.5
3.0
3.5
4.0
DD
4.5
5.0
5.5
100
1k
10k
100k
1M
10M
100M
1G
SUPPLY VOLTAGE V (V)
FREQUENCY (Hz)
Figure 12. Threshold Voltage vs. Supply
Figure 15. Bandwidth
25
20
15
10
5
0
–20
V
A
= 3V/4.2V/5V
T
= 25°C
DD
A
V
= 5V
DD
T
= 25°C
–40
–60
V
= 3V
DD
–80
–100
0
–120
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
100
1k
10k
100k
1M
10M
100M
1G
V
FREQUENCY (Hz)
D
Figure 16. Off Isolation vs. Frequency
Figure 13. Charge Injection vs. Source Voltage
Rev. A | Page 8 of 16
ADG787
0
–20
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 3V/4.2V/5V
= 25°C
DD
INPUT RISE/FALL TIME = 15ns
= 25°C
T
A
T
A
–40
S1A TO S1B
–60
S1A TO S2A
–80
RISE DELAY
–100
–120
FALL DELAY
4.7
100
1k
10k
100k
1M
10M
100M
1G
2.7
3.2
3.7
4.2
5.2
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 17. Crosstalk vs. Frequency
Figure 20. Rise/Fall Time Delay vs. Supply Voltage
0
–20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
T
= 3V/4.2V/5V
INPUT RISE/FALL TIME = 15ns
DD
= 25°C
V
= 4.2V
A
DD
NO SUPPLY DECOUPLING
–40
–60
RISE DELAY
FALL DELAY
–80
–100
–120
100
1k
10k
100k
1M
10M
100M
1G
–40
–15
10
35
60
85
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 18. AC Power Supply Rejection Ratio (PSRR)
Figure 21. Rise/Fall Time Delay vs. Temperature
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
2.0
1.5
1.0
0.5
0
INPUT RISE/FALL TIME = 15ns
T
= 25°C
A
V
V
= 3V, V = 2V p-p
S
DD
= 5V, V = 2V p-p
S
DD
10
100
1k
10k
100k
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (Hz)
SUPPLY (V)
Figure 19. Total Harmonic Distortion + Noise
Figure 22. Rise-Time-to-Fall-Time Mismatch vs. Supply Voltage
Rev. A | Page 9 of 16
ADG787
1.2
INPUT RISE/FALL TIME = 15ns
= 4.2V
V
DD
MASK: FS (12Mbps)
1.0
0.8
0.6
0.4
0.2
0
1
20.0ns/DIV
–40
–15
10
35
60
85
2.5GS/s 400ps/pt
TEMPERATURE (°C)
Figure 26. Eye Pattern, 12 Mbps, VDD = 4.2 V, TA = 85°C, PRBS 31
Figure 23. Rise-Time-to-Fall-Time Mismatch vs. Temperature
300
INPUT RISE/FALL TIME = 15ns
T
= 25°C
A
MASK: FS (12Mbps)
250
200
150
100
50
1
0
2.5
20.0ns/DIV
2.5GS/s 400ps/pt
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY (V)
Figure 27. Eye Pattern, 12 Mbps, VDD = 4.2 V, TA = −40°C, PRBS 31
Figure 24. Propagation Delay Skew (tSKEW) vs. Supply Voltage
200
INPUT RISE/FALL TIME = 15ns
V
= 4.2V
180
160
140
120
100
80
DD
60
40
20
0
–40
–15
10
35
60
85
TEMPERATURE (°C)
Figure 25. Propagation Delay Skew (tSKEW) vs. Temperature
Rev. A | Page 10 of 16
ADG787
TEST CIRCUITS
I
I
(OFF)
A
I
D
(OFF)
A
DS
V1
S
S
D
V
V
D
S
S
D
Figure 29. Off Leakage
V
R
= V1/I
S
ON DS
I
(ON)
D
Figure 28. On Resistance
S
D
NC
A
V
D
Figure 30. On Leakage
V
V
DD
DD
0.1μF
S1B
S1A
V
S
V
L
50%
50%
OUT
D
V
IN
R
L
C
IN
35pF
50Ω
90%
90%
V
OUT
GND
tON
tOFF
Figure 31. Switching Times, tON, tOFF
V
V
DD
0.1μF
V
V
IN
50%
50%
0V
DD
S1B
S1A
V
S
V
L
OUT
D
80%
80%
OUT
R
C
L
IN
35pF
50Ω
tBBM
tBBM
GND
Figure 32. Break-Before-Make Time Delay, tBBM
V
DD
SW ON
SW OFF
V
V
IN
S1B
S1A
NC
D
V
S
V
OUT
1nF
IN
OUT
ΔV
OUT
GND
Q
= CL ⋅ ΔV
OUT
INJ
Figure 33. Charge Injection
Rev. A | Page 11 of 16
ADG787
V
V
V
V
DD
DD
DD
0.1μF
0.1μF
NETWORK
ANALYZER
NETWORK
ANALYZER
DD
50Ω
50Ω
S1B
S1A
S1B
S1A
50Ω
NC
V
S
V
S
D
D
V
V
OUT
OUT
R
R
L
L
50Ω
50Ω
GND
GND
V
V
WITH SWITCH
OUT
VS
OUT
OFF ISOLATION = 20 LOG
INSERTION LOSS = 20 LOG
V
WITHOUT SWITCH
OUT
Figure 34. Off Isolation
Figure 36. Bandwidth
V
V
DD
DD
NETWORK
ANALYZER
0.1μF
V
OUT
D2
D1
S2A
S2B
NC
50Ω
S1A
S1B
V
OUT
R
S1A
S1B
L
50Ω
50Ω
D
R
50Ω
50Ω
L
NC
V
S
50Ω
V
S
V
GND
OUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
Figure 37. Channel-to-Channel Crosstalk (S1A to S2A)
V
OUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
Figure 35. Channel-to-Channel Crosstalk (S1A to S1B)
Rev. A | Page 12 of 16
ADG787
TERMINOLOGY
IDD
tOFF
Positive supply current.
Delay time between the 50% and the 90% points of the digital
input and switch off condition.
VD (VS)
Analog voltage on Terminal D and Terminal S.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.
RON
Ohmic resistance between D and S.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during on-off switching.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
Off Isolation
ΔRON
A measure of unwanted signal coupling through an off switch.
On resistance match between any two channels.
Crosstalk
IS (OFF)
A measure of unwanted signal that is coupled from one channel
to another as a result of parasitic capacitance.
Source leakage current with the switch off.
ID (OFF)
−3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
Drain leakage current with the switch off.
ID, IS (ON)
On Response
The frequency response of the on switch.
Channel leakage current with the switch on.
VINL
Insertion Loss
The loss due to the on resistance of the switch.
Maximum input voltage for Logic 0.
VINH
THD + N
Minimum input voltage for Logic 1.
The ratio of the harmonic amplitudes plus noise of a signal, to
the fundamental.
IINL (IINH
)
Input current of the digital input.
TSKEW
The measure of the variation in propagation delay between each
channel.
CS (OFF)
Off switch source capacitance. Measured with reference to
ground.
Rise Time Delay
The rise time of a signal is a measure of the time for the signal
to rise from 10% of the ON level to 90% of the ON level. Rise
time delay is the difference between the rise time, measured at
the input, and the rise time, measured at the output.
CD (OFF)
Off switch drain capacitance. Measured with reference to
ground.
CD, CS (ON)
Fall Time Delay
On switch capacitance. Measured with reference to ground.
The fall time of a signal is a measure of the time for the signal to
fall from 90% of the ON level to 10% of the ON level. Fall time
delay is the difference between the fall time, measured at the
input, and the fall time, measured at the output.
CIN
Digital input capacitance.
tON
Rise-Time-to-Fall-Time Mismatch
This is the absolute value between the variation in the fall time
and the rise time, measured at the output.
Delay time between the 50% and the 90% points of the digital
input and switch on condition.
Rev. A | Page 13 of 16
ADG787
OUTLINE DIMENSIONS
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 38. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very, Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
8°
0°
0.15
0.05
0.60
0.40
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 39. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. A | Page 14 of 16
ADG787
0.63
0.57
0.51
1.56
1.50
1.44
SEATING
PLANE
C
B
A
1
2
3
4
0.36
0.32
0.28
BALL 1
IDENTIFIER
2.06
2.00
1.94
0.50 BSC
BALL PITCH
0.26
0.22
0.18
0.11
0.09
0.07
TOP VIEW
(BALL SIDE DOWN)
BOTTOM
VIEW
(BALL SIDE UP)
Figure 40. 10-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option Branding1
ADG787BRMZ2
–40°C to +85°C
10-Lead Mini Small Outline Package (MSOP)
10-Lead Mini Small Outline Package (MSOP)
10-Lead Mini Small Outline Package (MSOP)
10-Ball Wafer Level Chip Scale Package (WLCSP)
10-Ball Wafer Level Chip Scale Package (WLCSP)
RM-10
RM-10
RM-10
CB-10
CB-10
SM1
SM1
SM1
S04
ADG787BRMZ-500RL72 –40°C to +85°C
ADG787BRMZ-REEL2
ADG787BCBZ-500RL72 –25°C to +85°C
ADG787BCBZ-REEL2
–25°C to +85°C
ADG787BCPZ-500RL72 –40°C to +85°C
ADG787BCPZ-REEL2
–40°C to +85°C
–40°C to +85°C
S04
10-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-10-9
10-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-10-9
SM1
SM1
1 Due to space constraints, branding on this package is limited to three characters.
2 Z = Pb-free part.
Rev. A | Page 15 of 16
ADG787
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05250-0-5/06(A)
Rev. A | Page 16 of 16
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