ADG792ABCPZ-500RL7 [ADI]
IC-Compatible, Wide Bandwidth, Triple 4:1 Multiplexer; IC兼容，宽带宽，三重4 ： 1多路复用器
| 型号： | ADG792ABCPZ-500RL7 |
| 厂家： | 
ADI |
| 描述： | IC-Compatible, Wide Bandwidth, Triple 4:1 Multiplexer |
| 文件： | 总24页 (文件大小：582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
I2C-Compatible, Wide Bandwidth,
Triple 4:1 Multiplexer
ADG792A/ADG792G
FEATURES
Bandwidth: 190 MHz
FUNCTIONAL BLOCK DIAGRAMS
V
V
DD
DD
GND
GND
Low insertion loss and on resistance: 2.6 Ω typical
On resistance flatness: 0.3 Ω typical
Single 3 V/5 V supply operation
3.3 V analog signal range (5 V supply, 75 Ω load)
Low quiescent supply current: 1 nA typical
Fast switching times: tON 185 ns, tOFF 181 ns
I2C®-compatible interface
Compact, 24-lead, LFCSP package
Two I2C-controllable logic outputs
ESD protection
ADG792A
ADG792G
S1A
S1B
S1C
S1D
S1A
S1B
S1C
S1D
D1
D2
D3
D1
D2
S2A
S2B
S2C
S2D
S2A
S2B
S2C
S2D
S3A
S3B
S3C
S3D
S3A
S3B
S3C
S3D
D3
4 kV human body model
200 V machine model
1 kV field-induced charged device model
2
2
GPO1
GPO2
I C SERIAL
I C SERIAL
INTERFACE
INTERFACE
APPLICATIONS
A0 A1 A2 SDA SCL
A0 A1 A2 SDA SCL
RGB/YPbPr video switches
HDTV
Figure 1.
Projection TV
DVD-R/RW
AV receivers
GENERAL DESCRIPTION
arrays, the user can set the three I2C address pins allowing as
many as eight devices to connect to the same bus.
The ADG792A/ADG792G are monolithic CMOS devices, each
comprising three 4:1 multiplexer/demultiplexers that are con-
trollable through a standard I2C serial interface. The CMOS
process provides ultralow power dissipation yet delivers high
switching speed and low on resistance.
The ADG792A/ADG792G operate from a single 3 V or 5 V
supply voltage and is available in a compact 4 mm × 4 mm
body, 24-lead, Pb-free, LFCSP package.
The on resistance profile is very flat over the full analog input
range, and wide bandwidth ensures excellent linearity and low
distortion. These features, combined with a wide input signal
range, make the ADG792A/ADG792G the ideal switching
solution for a wide range of TV applications, including RGB
and YPbPr video switches.
PRODUCT HIGHLIGHTS
1. Wide bandwidth: 190 MHz.
2. Ultralow power dissipation.
3. Extended input signal range.
4. Integrated I2C serial interface.
When turned on, the switches conduct equally well in both
directions. In the off condition, signal levels, up to the supplies,
are blocked. The ADG792A/ADG792G switches exhibit break-
before-make switching action. The ADG792G also has two
general-purpose logic output pins controllable through the I2C
interface to control other non-I2C-compatible devices, such as
video filters. The integrated I2C interface provides a large degree
of flexibility in the system design. To build larger switching
5. Compact 4 mm × 4 mm, 24-lead, Pb-free LFCSP package.
6. ESD protection tested as per ESD Association Standards:
4 kV HBM (ANSI/ESD STM5.1-2001)
200 V MM (ANSI/ESD STM5.2-1999)
1 kV FICDM (ANSI/ESDSTM5.3.1-1999)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG792A/ADG792G
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology.................................................................................... 16
Theory of Operation ...................................................................... 17
I2C Serial Interface ..................................................................... 17
I2C Address.................................................................................. 17
Write Operation.......................................................................... 17
LDSW Bit..................................................................................... 19
Power On/Software Reset.......................................................... 19
Read Operation........................................................................... 19
Evaluation Board ............................................................................ 20
Using the ADG792G Evaluation Board .................................. 20
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I2C Timing Specifications............................................................ 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits..................................................................................... 14
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADG792A/ADG792G
SPECIFICATIONS
VDD = 5 V 10ꢀ, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ1
Max
Unit
ANALOG SWITCH
Analog Signal Range2
VS = VDD, RL = 1 MΩ
VS = VDD, RL = 75 Ω
VD = 0 V, IDS = −10 mA, see Figure 22
VD = 0 V to 1 V, IDS = −10 mA, see
Figure 22
0
0
4
V
V
Ω
Ω
3.3
3.5
4
On Resistance, RON
2.6
On Resistance Matching Between Channels, ∆RON VD = 0 V IDS = −10 mA
VD = 1 V IDS = −10 mA
0.15
0.3
0.5
0.6
0.55
Ω
Ω
Ω
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
VD = 0 V to 1 V, IDS = −10 mA
Source Off Leakage (IS(OFF)
)
VD = 4 V/1 V, VS = 1 V/4 V, see
Figure 23
VD = 4 V/1 V, VS = 1 V/4 V, see
Figure 23
0.25
0.25
0.25
nA
nA
nA
Drain Off Leakage (ID(OFF)
)
Channel On Leakage (ID(ON), IS(ON)
DYNAMIC CHARACTERISTICS3
tON, tENABLE
)
VD = VS = 4 V/1 V, see Figure 24
CL = 35 pF, RL = 50 Ω, VS = 2 V, see
Figure 28
CL = 35 pF, RL = 50 Ω, VS = 2 V, see
Figure 28
CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V,
see Figure 29
185
181
3
240
235
ns
ns
ns
tOFF, tDISABLE
Break-Before-Make Time Delay, tD
1
I2C to GPO Propagation Delay, tH, tL
Off Isolation
Channel-to-Channel Crosstalk
Same Multiplexer
Different Multiplexer
−3 dB Bandwidth
THD + N
ADG792G only
f = 10 MHz, RL = 50 Ω, see Figure 26
f = 10 MHz, RL = 50 Ω, see Figure 27
130
ns
dB
−60
−55
−75
190
0.14
5
dB
dB
MHz
%
pC
RL = 50 Ω, see Figure 25
RL = 100 Ω
CL = 1 nF, VS = 0 V, see Figure 30
Charge Injection
CS(OFF)
10
pF
CD(OFF)
26
pF
CD(ON), CS(ON)
37
pF
Power Supply Rejection Ratio, PSRR
Differential Gain Error
Differential Phase Error
LOGIC INPUTS (A0, A1, A2)3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Input Capacitance, CIN
LOGIC INPUTS (SCL, SDA)3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Hysteresis
f = 20 kHz
CCIR330 test signal
CCIR330 test signal
70
0.58
0.81
dB
%
Degrees
2.0
V
V
μA
pF
0.8
1
VIN = 0 V to VDD
0.005
3
0.7 × VDD
−0.3
VDD + 0.3
+0.3 × VDD
1
V
V
μA
V
pF
VIN = 0 V to VDD
+0.005
0.05 × VDD
3
Input Capacitance, CIN
Rev. 0 | Page 3 of 24
ADG792A/ADG792G
Parameter
LOGIC OUTPUTS3
Conditions
Min
Typ1
Max
Unit
SDA Pin
Output Low Voltage, VOL
ISINK = 3 mA
ISINK = 6 mA
0.4
0.6
±±
±0
V
V
μA
pF
Floating State Leakage Current
Floating State Output Capacitance
GPO± and GPO2 Pins
Output Low Voltage, VOL
Output High Voltage, VOH
POWER REQUIREMENTS
IDD
ILOAD = +2 mA
ILOAD = −2 mA
0.4
V
V
2.0
Digital inputs = 0 V or VDD, I2C interface
inactive
0.00±
±
μA
I2C interface active, fSCL = 400 kHz
I2C interface active, fSCL = 3.4 MHz
0.2
0.7
mA
mA
± All typical values are at TA = +25°C, unless otherwise stated.
2 Guaranteed by initial characterization, not subject to production test.
3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 24
ADG792A/ADG792G
VDD = 3 V ꢀ1%, GND = 1 V, TA = −41°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ1
Max
Units
ANALOG SWITCH
Analog Signal Range2
VS = VDD, RL = 1 MΩ
VS = VDD, RL = 75 Ω
VD = 0 V, IS = −10 mA, see Figure 22
VD = 0 V to 1 V, IS = −10 mA, see Figure 22
0
0
2.2
1.7
4
V
V
On Resistance, RON
3
Ω
Ω
Ω
Ω
Ω
6
On Resistance Matching Between Channels, ∆RON VD = 0 V IS = −10 mA
VD = 1 V IS = −10 mA
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
0.15
0.8
0.6
0.8
2.8
VD = 0 V to 1 V, IS = −10 mA
Source Off Leakage (IS(OFF)
)
VD = 2 V/1 V, VS = 1 V/2 V, see Figure 23
VD = 2 V/1 V, VS = 1 V/2 V, see Figure 23
VD = VS = 2 V/1 V, see Figure 24
0.25
0.25
0.25
nA
nA
nA
Drain Off Leakage (ID(OFF)
)
Channel On Leakage (ID(ON), IS(ON)
DYNAMIC CHARACTERISTICS3
tON, tENABLE
tOFF, tDISABLE
Break-Before-Make Time Delay, tD
)
CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28
CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28
CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V,
see Figure 29
200
197
3
260
255
ns
ns
ns
1
I2C to GPO propagation delay, tH, tL
Off Isolation
Channel-to-Channel Crosstalk
Same Multiplexer
Different Multiplexer
−3 dB Bandwidth
THD + N
ADG792G only
f = 10 MHz, RL = 50 Ω, see Figure 26
f = 10 MHz, RL = 50 Ω, see Figure 27
121
ns
dB
−60
−55
−75
180
0.14
3.5
dB
dB
MHz
%
pC
RL = 50 Ω, see Figure 25
RL = 100 Ω
CL = 1 nF, VS = 0 V, see Figure 30
Charge Injection
CS(OFF)
10
pF
CD(OFF)
26
pF
CD(ON), CS(ON)
37
pF
Power Supply Rejection Ratio, PSRR
Differential Gain Error
Differential Phase Error
LOGIC INPUTS (A0, A1, A2)3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Input Capacitance, CIN
LOGIC INPUTS (SCL, SDA)3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Hysteresis
f = 20 kHz
CCIR330 test signal
CCIR330 test signal
70
0.49
0.56
dB
%
Degrees
2.0
V
V
μA
pF
0.8
1
VIN = 0 V to VDD
+0.005
3
0.7 × VDD
−0.3
VDD + 0.3
+0.3 × VDD
1
V
V
μA
V
pF
VIN = 0 V to VDD
+0.005
0.05 × VDD
3
Input Capacitance, CIN
LOGIC OUTPUTS3
SDA Pin
Output Low Voltage, VOL
ISINK = 3 mA
ISINK = 6 mA
0.4
0.6
1
V
V
μA
pF
Floating State leakage Current
Floating State Output Capacitance
3
Rev. 0 | Page 5 of 24
ADG792A/ADG792G
Parameter
Conditions
Min
Typ1
Max
Units
GPO1 and GPO2 Pins
Output Low Voltage, VOL
Output High Voltage, VOH
POWER REQUIREMENTS
IDD
ILOAD = +2 mA
ILOAD = −2 mA
0.4
V
V
2.0
Digital inputs = 0 V or VDD,
I2C interface inactive
0.001
1
μA
I2C interface active, fSCL = 400 kHz
I2C interface active, fSCL = 3.4 MHz
0.1
0.2
mA
mA
1All typical values are at TA = +25°C, unless otherwise stated.
2 Guaranteed by initial characterization, not subject to production test.
3 Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 24
ADG792A/ADG792G
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; GND = 0 V; TA = −40°C to +85°C, unless otherwise noted. See Figure 2 for timing diagram.
Table 3.
Parameter1 Conditions
Min
Max
100
400
Unit Description
fSCL
Standard mode
Fast mode
kHz
kHz
Serial clock frequency
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
3.4
1.7
MHz
MHz
μs
t1
4
0.6
tHIGH, SCL high time
tLOW, SCL low time
μs
60
ns
ns
μs
μs
120
4.7
1.3
t2
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
160
320
250
100
10
ns
ns
ns
ns
ns
μs
μs
t3
tSU;DAT, data setup time
tHD;DAT, data hold time
2
t4
0
0
3.45
0.9
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
0
0
703
150
ns
ns
μs
μs
ns
μs
μs
ns
μs
μs
μs
μs
ns
t5
t6
4.7
0.6
160
4
0.6
160
4.7
1.3
4
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
High speed mode
Standard mode
Fast mode
t7
t8
tBUF, bus free time between a stop and a start condition
tSU;STO, setup time for stop condition
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
0.6
160
t9
1000 ns
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
20 + 0.1 CB 300
ns
10
20
80
160
300
ns
ns
ns
ns
t10
20 + 0.1 CB 300
10
20
80
160
ns
ns
t11
1000 ns
20 + 0.1 CB 300
ns
High speed mode
CB = 100 pF max
CB = 400 pF max
10
20
40
80
ns
ns
Rev. 0 | Page 7 of 24
ADG792A/ADG792G
Parameter1 Conditions
Min
Max
Unit Description
t11A
Standard mode
Fast mode
1000 ns
tRCL1, rise time of SCL signal after a repeated start condition and after
an acknowledge bit
20 + 0.1 CB 300
ns
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
10
20
80
160
300
ns
ns
ns
ns
t12
tFCL, fall time of SCL signal
20 + 0.1 CB 300
High speed mode
CB = 100 pF max
CB = 400 pF max
Fast mode
10
20
0
40
80
50
10
ns
ns
ns
ns
tSP
Pulse width of suppressed spike
High speed mode
0
1
Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD
2 A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
.
Timing Diagram
t11
t12
t6
t2
t6
SCL
t1
t3
t5
t10
t8
t4
t9
SDA
t7
P
S
S
P
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. 0 | Page 8 of 24
ADG792A/ADG792G
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +6 V
Analog, Digital Inputs
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
Continuous Current, S or D Pins 100 mA
Peak Current, S or D Pins
300 mA (pulsed at 1 ms, 10%
duty cycle max)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
24-Lead LFCSP
Only one absolute maximum rating can be applied at any
one time.
−40°C to +85°C
−65°C to +150°C
150°C
30°C/W
300°C
Lead Temperature, Soldering
(10 sec)
IR Reflow, Peak Temperature
(<20 sec)
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 24
ADG792A/ADG792G
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
PIN 1
INDICATOR
INDICATOR
S1A 1
S1B 2
D1 3
S1D 4
S1C 5
GPO2 6
18 A2
S1A
S1B
D1
S1D
S1C
NC
1
2
3
4
5
6
18 A2
17 S3C
16 S3D
15 D3
14 S3B
13 S3A
17 S3C
16 S3D
15 D3
14 S3B
13 S3A
ADG792G
ADG792A
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
NOTES
NOTES
1. THE EXPOSED PAD
MUST BE TIED TO GND.
1. NC = NO CONNECT.
2. THE EXPOSED PAD
MUST BE TIED TO GND.
Figure 4. ADG792G Pin Configuration
Figure 3. ADG792A Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
1
2
3
Mnemonic
ADG792A/ADG792G Function
S1A
S1B
D1
A Side Source Terminal for Mux 1. Can be an input or output.
B Side Source Terminal for Mux 1. Can be an input or output.
Drain Terminal for Mux 1. Can be an input or output.
4
5
6
7
8
9
S1D
S1C
NC/GPO2
S2A
S2B
D2
D Side Source Terminal for Mux 1. Can be an input or output.
C Side Source Terminal for Mux 1. Can be an input or output.
Not internally connected for ADG792A/General-Purpose Logic Output 2 for ADG792G.
A Side Source Terminal for Mux 2. Can be an input or output.
B Side Source Terminal for Mux 2. Can be an input or output.
Drain Terminal for Mux 2. Can be an input or output.
10
11
12
13
14
15
16
17
18
19
20
21
S2D
S2C
NC/GPO1
S3A
S3B
D3
S3D
S3C
A2
D Side Source Terminal for Mux 2. Can be an input or output.
C Side Source Terminal for Mux 2. Can be an input or output.
Not internally connected for ADG792A/General-Purpose Logic Output 1 for ADG792G.
A Side Source Terminal for Mux 3. Can be an input or output.
B Side Source Terminal for Mux 3. Can be an input or output.
Drain Terminal for Mux 3. Can be an input or output.
D Side Source Terminal for Mux 3. Can be an input or output.
C Side Source Terminal for Mux 3. Can be an input or output.
Logic Input. Sets Bit A2 from the least significant bits of the 7-bit slave address.
Logic Input. Sets Bit A1 from the least significant bits of the 7-bit slave address.
Logic Input. Sets Bit A0 from the least significant bits of the 7-bit slave address.
A1
A0
SCL
Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into the
device. External pull-up resistor required.
22
23
24
SDA
VDD
GND
Digital Input/Output. Bidirectional open-drain data line. External pull-up resistor required.
Positive Power Supply Input.
Ground (0 V) Reference.
Rev. 0 | Page 10 of 24
ADG792A/ADG792G
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
V
= 3.3V, R = 1MΩ
L
T
= 25°C
A
DD
A
V
= 5.0V
= 5.5V
DD
1 CHANNEL
1 CHANNEL
V
= 3V, R = 1MΩ
L
V
= 4.5V
DD
DD
2.5
2.0
1.5
1.0
0.5
0
V
V
= 2.7V, R = 1MΩ
DD
DD
L
V
= 3.3V, R = 75Ω
DD
L
V
= 3V, R = 75Ω
L
DD
V
= 2.7V, R = 75Ω
DD
L
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
(V ) (V)
2.0
2.5
3.0
INPUT SIGNAL (V)
V
D
S
Figure 5. Analog Signal Range (3 V Supply)
Figure 8. On Resistance vs. VD (VS) with 5 V Supply
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
7
6
5
4
3
2
1
0
T
= 25°C
V
= 5.5V, R = 1MΩ
L
A
V
= 5V, R = 1MΩ
DD
DD
L
1 CHANNEL
= 3V
V
= 5.5V, R = 75Ω
DD
L
V
DD
V
= 4.5V, R = 1MΩ
L
DD
T
= +85°C
A
V
= 5V, R = 75Ω
L
DD
V
= 4.5V, R = 75Ω
DD
L
T
= –40°C
A
T
= +25°C
A
T
= 25°C
A
1 CHANNEL
0
1
2
3
4
5
6
0
0.2
0.4
0.6
0.8
(V ) (V)
1.0
1.2
1.4
1.6
INPUT SIGNAL (V)
V
D
S
Figure 6. Analog Signal Range (5 V Supply)
Figure 9. On Resistance vs. VD (VS) for Various Temperatures
with 3 V Supply
6
5
4
3
2
1
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
T
= +25°C
A
T
= +85°C
A
A
1 CHANNEL
1 CHANNEL
= 5V
V
= 3.0V
DD
V
DD
T
T
= +25°C
= –40°C
A
V
= 2.7V
DD
A
V
= 3.3V
DD
0
0.2
0.4
0.6
0.8
1.0
(V ) (V)
1.2
1.4
1.6
1.8
0
0.5
1.0
1.5
2.0
2.5
3.0
V
D
V
(V ) (V)
S
S
D
Figure 7. On Resistance vs. VD (VS) with 3 V Supply
Figure 10. On Resistance vs. VD (VS) for Various Temperatures
with 5 V Supply
Rev. 0 | Page 11 of 24
ADG792A/ADG792G
0
–20
0
T = 25°C
A
T
= 25°C
A
V
= 3V/5V
DD
–1
–2
–3
–4
–5
–6
–40
SAME
MULTIPLEXER
V
= 3V
V
= 5V
DD
DD
–60
DIFFERENT
MULTIPLEXER
–80
–100
–120
0.01
0.1
1
10
100
1000
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
SOURCE VOLTAGE (V)
Figure 11. Charge Injection vs. Source Voltage
Figure 14. Crosstalk vs. Frequency
220
210
200
190
180
170
160
0
–2
–4
tON (3V)
–6
tOFF (3V)
–8
–10
–12
–14
–16
–18
–20
tON (5V)
tOFF (5V)
T
V
= 25°C
A
= 5V
DD
–40
–20
0
20
40
60
80
0.01
0.1
1
10
100
1000
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 12. tON/tOFF vs. Temperature
Figure 15. Bandwidth
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–20
T
= 25°C
T
V
= 25°C
A
A
1 CHANNEL
= 3V/5V
= 3V/5V
DD
V
DD
NO DECOUPLING CAPACITORS USED
–40
–60
–80
–100
–120
0.0001
0.001
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. PSRR vs. Frequency
Figure 13. Off Isolation vs. Frequency
Rev. 0 | Page 12 of 24
ADG792A/ADG792G
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
6
5
4
3
2
1
0
T
= 25°C
T = 25°C
A
A
V
= 5V
DD
V
= 5V
DD
V
= 3V
DD
V
= 3V
DD
0.1
0.6
1.1
1.6
2.1
2.6
3.1
–20 –18 –16 –14 –12 –10
–8
–6
–4
–2
0
LOAD CURRENT (mA)
fCLK FREQUENCY (MHz)
Figure 20. GPO VOH vs. Load Current
Figure 17. IDD vs. fCLK Frequency
2.5
2.0
1.5
1.0
0.5
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C
T
= 25°C
A
A
V
= 3V
V
= 5V
DD
DD
V
= 5V
DD
V
= 3V
DD
–0.2
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
LOAD CURRENT (mA)
2
I C LOGIC INPUT VOLTAGE (V)
Figure 18. IDD vs.I2C Logic Input Voltage (SDA, SCL)
Figure 21. GPO VOL vs. Load Current
120
115
110
105
100
95
tPHL (5V)
tPHL (3V)
tPLH (5V)
tPLH (3V)
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 19. I2C to GPO Propagation Delay vs. Temperature
Rev. 0 | Page 13 of 24
ADG792A/ADG792G
TEST CIRCUITS
V
DD
I
0.1µF
DS
NETWORK
ANALYZER
V1
S
D
50Ω
50Ω
SA
SB
50Ω
V
S
V
S
R
= V1/I
ON
DS
D
V
OUT
50Ω
GND
Figure 22. On Resistance
Figure 25. Bandwidth
V
DD
0.1µF
I
(OFF)
A
I
(OFF)
A
S
D
NETWORK
ANALYZER
S
D
50Ω
50Ω
S
V
V
D
S
50Ω
50Ω
V
S
D
V
OUT
50Ω
GND
Figure 26. Off Isolation
Figure 23. Off Leakage
V
DD
0.1µF
NETWORK
ANALYZER
I
(ON)
A
D
S
D
50Ω
NC
50Ω
SX
V
D
V
S
NC = NO CONNECT
50Ω
SY
V
OUT
R
L
50Ω
DY
DX
GND
50Ω 50Ω
Figure 24. On Leakage
Figure 27. Channel-to-Channel Crosstalk
Rev. 0 | Page 14 of 24
ADG792A/ADG792G
5V
CLOCK PULSES
CORRESPONDING
TO THE LDSW BITS
CLOCK PULSES
CORRESPONDING
TO THE LDSW BITS
0.1µF
V
DD
V
OUT
S
D
SCL
SCL
50%
50%
50%
50%
R
50Ω
C
L
35pF
L
V
S
2
I C
INTERFACE
90%
90%
V
V
GPO
OUT
10%
10%
tOFF
tON
tH
tL
SDA
SCL
GND
Figure 28. Switching Times
5V
CLOCK PULSE CORRESPONDING
TO THE LDSW BIT
0.1µF
V
DD
SCL
SA
SB
V
OUT
D
V
V
S
80%
OUT
R
50Ω
C
L
35pF
L
V
S
2
I C
INTERFACE
tD
SDA
SCL
GND
Figure 29. Break-Before-Make Time Delay
5V
V
DD
SWITCH ON
R
ΔV
S
SWITCH OFF
OUT
S
D
V
OUT
Q
= C × ΔV
OUT
C
1nF
INJ
L
L
V
S
GND
Figure 30. Charge Injection
Rev. 0 | Page 15 of 24
ADG792A/ADG792G
TERMINOLOGY
On Resistance (RON)
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitudes plus noise of a signal to
the fundamental.
The series on-channel resistance measured between the
S and D pins.
On Resistance Match (ΔRON)
−3 dB Bandwidth
The channel-to-channel matching of on resistance when
channels are operated under identical conditions.
The frequency at which the output is attenuated by 3 dB.
Off Isolation
On Resistance Flatness (RFLAT(ON)
)
The measure of unwanted signal coupling through an off switch.
The variation of on resistance over the specified range produced
by the specified analog input voltage change with a constant
load current.
Crosstalk
The measure of an unwanted signal that is coupled through
from one channel to another as a result of parasitic capacitance.
Channel Off Leakage (IOFF
The sum of leakage currents into or out of an off channel input.
)
Charge Injection
The measure of the glitch impulse transferred from the digital
input to the analog output during on/off switching.
Channel On Leakage (ION)
The current loss/gain through an on-channel resistance,
creating a voltage offset across the device.
Differential Gain Error
The measure of how much color saturation shift occurs when
the luminance level changes. Both attenuation and amplification
can occur; therefore, the largest amplitude change between any
two levels is specified and expressed in ꢀ.
Input Leakage Current (IIN, IINL, IINH
)
The current flowing into a digital input when a specified low
level or high level voltage is applied to that input.
Input/Output Off Capacitance (COFF
The capacitance between an analog input and ground when the
switch channel is off.
)
Differential Phase Error
The measure of how much hue shift occurs when the luminance
level changes. It can be a negative or positive value and is
expressed in degrees of subcarrier phase.
Input/Output On Capacitance (CON)
The capacitance between the inputs or outputs and ground
when the switch channel is on.
Input High Voltage (VINH
The minimum input voltage for Logic 1.
)
Digital Input Capacitance (CIN)
The capacitance between a digital input and ground.
Input Low Voltage (VINL
The maximum input voltage for Logic 0.
)
Output On Switching Time (tON)
Output High Voltage (VOH
The minimum output voltage for Logic 1.
)
The time required for the switch channel to close. The time is
measured from 50ꢀ of the falling edge of the LDSW bit to the
time the output reaches 90ꢀ of the final value.
Output Low Voltage (VOL)
The maximum output voltage for Logic 0.
Output Off Switching Time (tOFF
)
The time required for the switch to open. The time is measured
from 50ꢀ of the falling edge of the LDSW bit to the time the
output reaches 10ꢀ of the final value.
IDD
Positive supply current.
I2C to GPO Propagation Delay (tH, tl)
The time required for the logic value at the GPO pin to settle
after loading a GPO command. The time is measured from 50ꢀ
of the falling edge of the LDSW bit to the time the output
reaches 90ꢀ of the final value for high and 10ꢀ for low.
Rev. 0 | Page 16 of 24
ADG792A/ADG792G
THEORY OF OPERATION
The transitions on the SDA line must occur during the low
period of the clock signal, SCL, and remain stable during
the high period of SCL, because a low-to-high transition
when the clock signal is high can be interpreted as a stop
event which ends the communication between the master
and the addressed slave device.
The ADG792A/ADG792G are monolithic CMOS devices, each
comprising three 4:1 multiplexer/demultiplexers controllable
via a standard I2C serial interface. The CMOS process provides
ultralow power dissipation yet it delivers high switching speed
and low on resistance.
The on resistance profile is very flat over the full analog input
range and the wide bandwidth ensures excellent linearity and
low distortion. These features, combined with a wide input
signal range, make the ADG792A/ADG792G the ideal switching
solution for a wide range of TV applications.
4. After transferring all data bytes, the master establishes a
stop condition, defined as a low to high transition on the
SDA line while SCL is high. In write mode, the master
pulls the SDA line high during the tenth clock pulse to
establish a stop condition. In read mode, the master issues
a no acknowledge for the ninth clock pulse (the SDA line
remains high). The master then brings the SDA line low
before the tenth clock pulse, and then high during the
tenth clock pulse to establish a stop condition.
The switches conduct equally well in both directions when on.
In the off condition, signal levels up to the supplies are blocked.
The integrated serial I2C interface controls the operation of the
multiplexers and general-purpose logic pins.
I2C ADDRESS
The ADG792A/ADG792G have many attractive features, such
as the ability to individually control each multiplexer, the option
of reading back the status of any switch, and two general-purpose
logic output pins controllable through the I2C interface (available
with the ADG792G only). The following sections describe these
features in more detail.
The ADG792A/ADG792G has a seven-bit I2C address. The four
most significant bits are internally hardwired and the last three
bits (A0, A1, and A2) are user-adjustable. This allows the user
to connect up to eight ADG792A/ADG792Gs to the same bus.
The I2C bit map shows the configuration of the seven-bit
address.
I2C SERIAL INTERFACE
Seven-Bit I2C Address Bit Configuration
The ADG792A/ADG792G are controlled via an I2C-compatible
serial bus interface (refer to the I2C-Bus Specification available
from Philips Semiconductor) that allows the part to operate as
a slave device (no clock is generated by either the ADG792A or
the ADG792G). The communication protocol between the I2C
master and the device operates as follows:
MSB
LSB
1
0
1
0
A2
A1
A0
WRITE OPERATION
When writing to the ADG792A/ADG792G, the user must
1. The master initiates data transfer by establishing a start
condition defined as a high to low transition on the SDA
line while SCL is high. This indicates that an address/data
stream follows. All slave devices connected to the bus
respond to the start condition and shift in the next eight
bits, consisting of a seven bit address (MSB first) plus an
W
begin with an address byte and R/ bit, after which time
the switch acknowledges that it is prepared to receive data
by pulling SDA low. Data is loaded into the device as a 16-bit
word under the control of a serial clock input, SCL. Figure 31
illustrates the entire write sequence for the ADG792A/ADG792G.
The first data byte (AX7 to AX0) controls the status of the
switches and the LDSW and RESETB bits from the second byte
control the operation mode of the device. Table 6 shows a list of
all commands supported by the ADG792A/ADG792G with the
corresponding byte that needs to be loaded during a write
operation.
W
R/ bit. This bit determines the direction of the data flow
during the communication between the master and the
addressed slave device.
2. The slave device whose address corresponds to the
transmitted address responds by pulling the SDA line
low during the ninth clock pulse (this is termed the
acknowledge bit).
To achieve the desired configuration, one or more commands
can be loaded into the device. Any combination of the commands
listed in Table 6 can be used with the following restrictions:
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
•
Only one switch from a given multiplexer can be on at any
given time.
W
from, its serial register. If the R/ bit is set high, the master
W
reads from the slave device. However, if the R/ bit is set
low, the master writes to the slave device.
•
When a sequence of successive commands affect the same
element (that is, the switch or GPO pin), only the last
command is executed.
3. Data transmits over the serial bus in sequences of nine clock
pulses (eight data bits followed by an acknowledge bit).
Rev. 0 | Page 17 of 24
ADG792A/ADG792G
SCL
A2
A1
A0 R/W
AX7 AX6 AX5 AX4 AX3 AX2 AX1 AX0
X
X
X
X
X
X
SDA
STOP
CONDITION
BY MASTER
START
CONDITION
BY MASTER
ADDRESS BYTE
RESETB
LDSW
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
Figure 31. Write Operation
Table 6. ADG792A/ADG792G Command List
AX7
AX6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
AX3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
AX2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
AX1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
AX0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Addressed Switch/GPO Pin
S1A/D1, S2A/D2, S3A/D3 off
S1A/D1, S2A/D2, S3A/D3 on
S1B/D1,S2B/D2, S3B/D3 off
S1B/D1,S2B/D2, S3B/D3 on
S1C/D1, S2C/D2, S3C/D3 off
S1C/D1, S2C/D2, S3C/D3 on
S1D/D1, S2D/D2, S3D/D3 off
S1D/D1, S2D/D2, S3D/D3 on
S1A/D1 off
0
1
0
1
0
1
0
1
0
1
S1A/D1 on
0
S1B/D1 off
1
S1B/D1 on
0
S1C/D1 off
1
S1C/D1 on
0
S1D/D1 off
1
S1D/D1 on
0
S2A/D2 off
1
S2A/D2 on
0
S2B/D2 off
1
S2B/D2 on
0
S2C/D2 off
1
S2C/D2 on
0
S2D/D2 off
1
S2D/D2 on
0
S3A/D3 off
1
S3A/D3 on
0
S3B/D3 off
1
S3B/D3 on
0
S3C/D3 off
1
S3C/D3 on
0
S3D/D3 off
1
S3D/D3 on
X1
X1
X1
0
Mux1 disabled (all switches connected to D1 are off)
Mux2 disabled (all switches connected to D2 are off)
Mux3 disabled (all switches connected to D3 are off)
Reserved for ADG792A/ GPO1 low for ADG792G
Reserved for ADG792A/ GPO1 high for ADG792G
Reserved for ADG792A/ GPO2 low for ADG792G
Reserved for ADG792A/ GPO2 high for ADG792G
1
0
1
0
Reserved for ADG792A/ GPO1, GPO2 low for ADG792G
Reserved for ADG792A/GPO1, GPO2 high for ADG792G
All muxes disabled (all switches are off)
Reserved
1
0
1
1 X = logic state does not matter.
Rev. 0 | Page 18 of 24
ADG792A/ADG792G
operation of the multiplexers and GPO pins, this bit should be
set high. When RESETB = low, or after power-up, the switches
from all multiplexers are turned off (open) and the GPO pins
are set to low.
LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during the write operations.
The ADG792A/ADG792G execute all the commands loaded
between two successive write operations that have set the
LDSW bit high.
READ OPERATION
When reading data back from the ADG792A/ADG792G, the
W
user must begin with an address byte and R/ bit. The switch
Setting the LDSW high for every write cycle ensures that the
device executes the command immediately after the LDSW bit
is loaded into the device. This setting is used when the desired
configuration can be achieved by sending a single command, or
when the switches and/or GPO pin are not required to be updated
at the same time. When the desired configuration requires
multiple commands with a simultaneous update, the LDSW bit
should be set low while loading the commands, except for the
last one when the LDSW bit should be set high. Once the last
command with LDSW = high is loaded, the device simultaneously
executes all commands received since the last update.
then acknowledges that it is prepared to transmit data by pulling
SDA low. Following this acknowledgement, the ADG792A/
ADG792G transmit two bytes on the next clock edges. These
bytes contain the status of the switches, and each byte is followed
by an acknowledge bit. A logic high bit represents a switch in
the on (close) state, and a low represents a switch in the off
(open) state. For the GPO pin (ADG792G only), the bit repre-
sents the logic value of the pin. Figure 32 illustrates the entire
read sequence.
The bit maps accompanying Figure 32 show the relationship
between the elements of the ADG792A and ADG792G (that is,
the switches and GPO pins) and the bits that represent their
status after a completed read operation.
POWER ON/SOFTWARE RESET
The ADG792A/ADG792G have a software reset function
implemented by the RESETB bit from the second data byte
loaded into the device during a write operation. For normal
Bit Map ADG792A
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1 RB0
RB1 RB0
S1A/D1 S1B/D1 S1C/D1 S1D/D1 S2A/D2 S2B/D2 S2C/D2 S2D/D2 S3A/D3 S3B/D3 S3C/D3 S3D/D3
Bit Map ADG792G
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
S1A/D1 S1B/D1 S1C/D1 S1D/D1 S2A/D2 S2B/D2 S2C/D2 S2D/D2 S3A/D3 S3B/D3 S3C/D3 S3D/D3 GPO1 GPO2
SCL
A2
A1
A0 R/W
RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
SDA
STOP
CONDITION
START
ADDRESS BYTE
BY MASTER
CONDITION
BY MASTER
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
Figure 32. Read Operation
Rev. 0 | Page 19 of 24
ADG792A/ADG792G
EVALUATION BOARD
1200 × 768. See Figure 33 and Figure 34 for schematics of the
evaluation board.
The ADG792G evaluation kit allows designers to evaluate the
high performance of the devices with a minimum of effort.
USING THE ADG792G EVALUATION BOARD
The evaluation kit includes a printed circuit board populated
with the ADG792G. The evaluation board can be used to
evaluate the performance of both the ADG792A and
ADG792G. It interfaces to the USB port of a PC, or it can be
used as a standalone evaluation board.
The ADG792G evaluation kit is a test system designed to
simplify the evaluation of the device. Each input/output of the
part comes with a socket specifically chosen for easy audio/video
evaluation. An evaluation board data sheet is also available with
the evaluation board and provides full instructions for operating
the evaluation board.
Software is available with the evaluation board that allows the
user to easily program the ADG792G through the USB port. The
software runs on any PC that has Microsoft® Windows® 2000 or
Windows XP installed with a minimum screen resolution of
Rev. 0 | Page 20 of 24
ADG792A/ADG792G
4 0 1 9 - 0 2 0 6
D
D
D
D
D
D
D
G N
G N
G N
G N
G N
G N
G N
5 6
5 3
4 1
2 8
2 6
1 2
1 0
C
C
C
C
C
C
C
V C
V C
V C
V C
V C
V C
V C
5 5
4 3
3 2
2 7
1 7
1 1
7
C C A V
3
Figure 33. Eval-ADG792GEB Schematic, USB Controller Section
Rev. 0 | Page 21 of 24
ADG792A/ADG792G
4 0 2 9 - 0 2 0 6
Ω
Ω
Ω
1 0 k
R 8
J 8
J 7
J 3
1 0 k
R 4
1 0 k
R 3
R 1 8
K 1
D
G N
M O T T B O
C A S
1
2
E
E
4
5
P
T O
3
C A S
L A U D O _ O H N P
R 3 0
R 2 9
R 2 8
R 1 7
R 1 6
Ω 0
R 3 5
L A U D O _ O H N P
E S C A
5
K 2
Ω 0
R 3 4
T O P
E S C A
3
4
D
G N
M O T T B O
C A S
M O T T B O
1 8
1 7
1 6
1 5
1 4
1 3
1
1
2
D
G N
2
2
3
4
5
6
1
E
E
4
5
P
T O
K 9
3
C A S
R 1 5
R 1 4
L A U D O _ O H N P
L A U D O _ O H N P
E S C A
5
T O P
E S C A
3
2
4
M O T T B O
K 3
R 2 7
R 2 6
D
G N
1
D
G N
M O T T B O
C A S
K 8
1
2
E
E
4
5
P
T O
3
C A S
L A U D O _ O H N P
E S C A
L A U D O _ O H N P
R 1 3
5
T O P
E S C A
M O T T B O
3
4
R 2 5
2
D
G N
1
K 7
Figure 34. Eval-ADG792GEB Schematic, Chip Section
Rev. 0 | Page 22 of 24
ADG792A/ADG792G
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
*
2.45
2.30 SQ
2.15
TOP
3.75
EXPOSED
VIEW
BSC SQ
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
12
7
0.23 MIN
2.50 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 35. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
I2C Speed
Package Description
Package Option
CP-24-2
CP-24-2
CP-24-2
CP-24-2
ADG792ABCPZ-REEL1
ADG792ABCPZ-500RL71
ADG792ACCPZ-REEL1
ADG792ACCPZ-500RL71
ADG792GBCPZ-REEL1
ADG792GBCPZ-500RL71
ADG792GCCPZ-REEL1
ADG792GCCPZ-500RL71
EVAL-ADG792GEB2
100 kHz, 400 kHz
100 kHz, 400 kHz
100 kHz, 400 kHz, 3.4MHz
100 kHz, 400 kHz, 3.4MHz
100 kHz, 400 kHz
100 kHz, 400 kHz
100 kHz, 400 kHz, 3.4MHz
100 kHz, 400 kHz, 3.4MHz
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
CP-24-2
CP-24-2
CP-24-2
CP-24-2
1 Z = Pb-free part.
2 The evaluation board is RoHS compliant.
Rev. 0 | Page 23 of 24
ADG792A/ADG792G
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06029-0-7/06(0)
Rev. 0 | Page 24 of 24
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