ADGS5414BCPZ [ADI]
SPI Interface, Octal SPST Switches, 13.5 Ω RON, ±20 V/36 V, Mux;
| 型号： | ADGS5414BCPZ |
| 厂家： | 
ADI |
| 描述： | SPI Interface, Octal SPST Switches, 13.5 Ω RON, ±20 V/36 V, Mux |
| 文件： | 总30页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPI Interface, Octal SPST Switches,
13.5 Ω RON, ± ±2 ꢀV/3ꢁ ꢀ, ꢂMu
Data Sheet
ADGS5414
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SPI interface with error detection
ADGS5414
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst and daisy-chain mode
Industry-standard SPI Mode 0 and Mode 3 interface-
compatible
S1
S2
S3
S4
S5
S6
S7
S8
D1
D2
D3
D4
D5
D6
D7
D8
Guaranteed break-before-make switching, allowing external
wiring of switches to deliver multiplexer configurations
V
SS to VDD analog signal range
Fully specified at 1ꢀ V, 20 V, +12 V, and +36 V
SPI
INTERFACE
SDO
9 V to 40 V single-supply operation (VDD
9 V to 22 V dual-supply operation (VDD/VSS
)
SCLK SDI CS RESET/V
)
L
8 kV HBM ESD rating
Figure 1.
Low on resistance
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
APPLICATIONS
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
The ADGS5414 contains eight independent single-pole/single-
throw (SPST) switches. An SPI interface controls the switches
and has robust error detection features, including cyclic
redundancy check (CRC) error detection, invalid read/write
address error detection, and SCLK count error detection.
PRODUCT HIGHLIGHTS
1. The SPI interface removes the need for parallel conversion,
logic traces, and reduces the general-purpose input/output
(GPIO) channel count.
2. Daisy-chain mode removes the need for additional logic
traces when using multiple devices.
3. CRC error detection, invalid read/write address error
detenction, and SCLK count error detection ensures a
robust digital interface.
It is possible to daisy-chain multiple ADGS5414 devices together.
This enables the configuration of multiple devices with a minimal
amount of digital lines. The ADGS5414 can also operate in burst
mode to decrease the time between SPI commands.
4. CRC and error detection capabilities allow the use of the
ADGS5414 in safety critical systems.
Each switch conducts equally well in both directions when on, and
each switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
5. Break-before-make switching allows external wiring of the
switches to deliver multiplexer configurations.
6. The trench isolation analog switch section guards against
latch-up. A dielectric trench separates the positive and
negative channel transistors, preventing latch-up even under
severe overvoltage conditions.
The on-resistance profile is flat over the full analog input range,
ensuring ideal linearity and low distortion when switching
audio signals. The ADGS5414 exhibits break-before-make
switching action, allowing the use of the device in multiplexer
applications with external wiring.
Rev. 0
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ADGS5414
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Error Detection Features........................................................... 22
Clearing the Error Flags Register............................................. 23
Burst Mode.................................................................................. 23
Software Reset............................................................................. 23
Daisy-Chain Mode..................................................................... 23
Power-On Reset.......................................................................... 24
Break-Before-Make Switching.................................................. 25
Trench Isolation.......................................................................... 25
Applications Information.............................................................. 26
Power Supply Rails..................................................................... 26
Power Supply Recommendations............................................. 26
Register Summary .......................................................................... 27
Register Details ............................................................................... 28
Switch Data Register .................................................................. 28
Error Configuration Register.................................................... 28
Error Flags Register.................................................................... 29
Burst Enable Register................................................................. 29
Software Reset Register ............................................................. 29
Outline Dimensions....................................................................... 3ꢁ
Ordering Guide .......................................................................... 3ꢁ
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 1
Specifications..................................................................................... 3
15 ꢀ Dual Supply ....................................................................... 3
2ꢁ ꢀ Dual Supply ....................................................................... 5
12 ꢀ Single Supply........................................................................ 7
36 ꢀ Single Supply........................................................................ 9
Continuous Current per Channel, Sx or Dx Pins .................. 11
Timing Characteristics .............................................................. 11
Absolute Maximum Ratings.......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 15
Test Circuits..................................................................................... 19
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
Address Mode ............................................................................. 22
REVISION HISTORY
10/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 30
Data Sheet
ADGS5414
SPECIFICATIONS
1ꢀ V DUAL SUPPLY
Digital logic voltage (ꢀDD) = +15 ꢀ 1ꢁ0, negative supply voltage (ꢀSS) = −15 ꢀ 1ꢁ0, positive supply voltage (ꢀL) = 2.7 ꢀ to 5.5 ꢀ,
GND = ꢁ ꢀ, unless otherwise noted.
Table 1.
Parameter
+2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
13.5
Ω typ
Source voltage (VS) = ±10 V,
IS = −10 mA; see Figure 29
15
0.3
18
22
Ω max
Ω typ
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, source current
(IS) = −10 mA
On-Resistance Match Between Channels,
∆RON
0.8
1.8
2.2
1.3
2.6
1.4
3
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = ±10 V, IS = −10 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
±0.1
nA typ
VS = ±10 V, VD = ±10 V;
see Figure 32
±0.25
±0.1
±1
±±
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = ±10 V, VD = ±10 V;
see Figure 32
±0.25
±0.15
±0.4
±1
±2
±±
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = ±10 V; see Figure 28
±14
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.4
0.2
V max
V max
μA typ
Sink current (ISINK) = 5 mA
ISINK = 1 mA
Output voltage (VOUT) =
Output Current, Low (IOL) or High (IOH
)
0.001
4
ground voltage (VGND)or VL
±0.1
μA max
pF typ
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, Low (IINL) or High (IINH
)
0.001
4
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
tON
410
ns typ
Load resistance (RL) = 300 Ω,
load capacitance (CL) = 35 pF
420
135
140
260
250
125
515
185
515
195
210
ns max
ns typ
ns max
ns typ
ns min
pC typ
VS = 10 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 36
tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
Rev. 0 | Page 3 of 30
ADGS5414
Data Sheet
Parameter
+2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
Off Isolation
−60
dB typ
RL = 50 Ω, CL = 5 pF,
frequency (f) = 1 MHz; see
Figure 32
Channel to Channel Crosstalk
−±5
0.01
200
−0.9
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f =
1 MHz; see Figure 30
RL = 1 kΩ, 15 V p-p, f = 20
Hz to 20 kHz; see Figure 33
RL = 50 Ω, CL = 5 pF; see
Figure 34
RL = 50 Ω, CL = 5 pF, f =
1 MHz; see Figure 34
Total Harmonic Distortion + Noise
(THD + N)
−3 dB Bandwidth
MHz typ
dB typ
Insertion Loss
Source Capacitance (CS) (Off)
Drain Capacitance(CD) (Off)
CD (On), CS (On)
11
11
30
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
Positive Supply Current (IDD
VDD = +16.5 V, VSS = −16.5 V
All switches open
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 5.5 V
All switches closed, VL = 2.± V
All switches closed, VL = 2.± V
)
45
μA typ
μA max
μA typ
μA max
μA typ
μA max
±0
45
±0
310
430
IL
Inactive
6.3
14
μA typ
μA max
μA typ
Digital inputs = 0 V or VL
8.0
SCLK = 1 MHz
SCLK = 50 MHz
SDI = 1 MHz
CS and SDI = 0 V or VL, VL = 5
V
CS and SDI = 0 V or VL, VL =
3 V
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS and SCLK = 0 V or VL, VL
= 5 V
CS and SCLK = 0 V or VL, VL
= 3 V
CS and SCLK = 0 V or VL, VL
= 5 V
CS and SCLK = 0 V or VL, VL
= 3 V
Digital inputs toggle
between 0 V and VL, VL =
5.5 V
±
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
390
210
15
±.5
230
120
1.8
SDI = 25 MHz
Active at 50 MHz
2
2.1
1.0
mA max
mA typ
0.±
Digital inputs toggle
between 0 V and VL, VL = 2.± V
mA max
μA typ
μA max
V min
Negative Supply Current (ISS)
0.05
Digital inputs = 0 V or VL
1.0
±9
Dual-Supply Operation (VDD/VSS)
GND = 0 V
GND = 0 V
±22
V max
Rev. 0 | Page 4 of 30
Data Sheet
ADGS5414
20 V DUAL SUPPLY
ꢀDD = +2ꢁ ꢀ 1ꢁ0, ꢀSS = −2ꢁ ꢀ 1ꢁ0, ꢀL = 2.7 ꢀ to 5.5 ꢀ, GND = ꢁ ꢀ, unless otherwise noted.
Table 2.
Parameter
+2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
12.5
Ω typ
VS = ±15 V, IS = −10 mA;
see Figure 29
14
0.3
1±
21
Ω max
Ω typ
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −10 mA
On-Resistance Match Between
Channels, ∆RON
0.8
2.3
2.±
1.3
3.1
1.4
3.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = ±15 V, IS = −10 mA
VDD = +22 V, VSS = −22 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.1
nA typ
VS = ±15 V, VD = ±15 V;
see Figure 32
±0.25
±0.1
±1
±±
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = ±15 V, VD = ±15 V;
see Figure 32
±0.25
±0.15
±0.4
±1
±2
±±
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = ±15 V; see Figure 28
±14
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.4
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
Output Current, IOL or IOH
0.001
4
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, IINL or IINH
0.001
4
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
tON
410
418
135
144
255
245
160
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 36
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 34
485
185
495
195
205
tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
−60
dB typ
dB typ
% typ
Channel to Channel Crosstalk
(THD + N)
−±5
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 1 kΩ, 20 V p-p, f = 20 Hz to
20 kHz; see Figure 33
0.012
Rev. 0 | Page 5 of 30
ADGS5414
Data Sheet
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
−3 dB Bandwidth
Insertion Loss
200
−0.8
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 34
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
11
11
30
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
All switches open
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
All switches closed, VL = 2.7 V
50
μA typ
μA max
μA typ
μA max
μA typ
μA max
110
110
450
50
320
IL
Inactive
6.3
μA typ
μA max
μA typ
μA typ
μA typ
Digital inputs = 0 V or VL
8.0
SCLK = 1 MHz
SCLK = 50 MHz
14
7
CS and SDI = 0 V or VL, VL = 5 V
CS and SDI = 0 V or VL, VL = 3 V
390
CS = VL and SDI = 0 V or VL,
VL = 5 V
210
μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
SDI = 1 MHz
SDI = 25 MHz
15
μA typ
μA typ
μA typ
μA typ
mA typ
CS and SCLK = 0 V or VL, VL = 5 V
7.5
230
120
1.8
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz
Digital inputs toggle between
0 V and VL, VL = 5.5 V
2
2.1
1.0
mA max
mA typ
0.7
Digital inputs toggle between
0 V and VL, VL = 2.7 V
mA max
μA typ
μA max
V min
ISS
0.05
Digital inputs = 0 V or VL
1.0
9
Dual-Supply Operation (VDD/VSS)
GND = 0 V
GND = 0 V
22
V max
Rev. 0 | Page 6 of 30
Data Sheet
ADGS5414
12 V SINGLE SUPPLY
ꢀDD = 12 ꢀ 1ꢁ0, ꢀSS = ꢁ ꢀ, ꢀL = 2.7 ꢀ to 5.5 ꢀ, GND = ꢁ ꢀ, unless otherwise noted.
Table 3.
Parameter
+2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
42
V
26
Ω typ
VS = 0 V to 10 V, IS = −10 mA;
see Figure 29
VDD = 10.8 V, VSS = 0 V
30
0.3
36
Ω max
Ω typ
On-Resistance Match Between Channels,
∆RON
VS = 0 V to 10 V, IS = −10 mA
1
5.5
6.5
1.5
8
1.6
12
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.1
nA typ
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 32
±0.25
±0.1
±1
±1
±2
±±
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 32
±0.25
±0.15
±±
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V; see
Figure 28
±0.4
±14
nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.4
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
Output Current, IOL or IOH
0.001
4
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, IINL or IINH
0.001
4
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
tON
450
455
135
141
285
2±5
55
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 36
VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
555
195
5±5
205
225
tOFF
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
−60
−±5
dB typ
dB typ
Channel to Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
Rev. 0 | Page ± of 30
ADGS5414
Data Sheet
Parameter
+2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
THD +N
0.1
% typ
RL = 1 kΩ, 6 V p-p, f = 20 Hz
to 20 kHz; see Figure 33
−3 dB Bandwidth
Insertion Loss
220
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF; see
Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 34
−1.55
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
12
12
30
pF typ
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
All switches open
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 5.5 V
All switches closed, VL = 2.± V
All switches closed, VL = 2.± V
40
μA typ
μA max
μA typ
μA max
μA typ
μA max
65
40
65
300
420
IL
Inactive
6.3
μA typ
μA max
μA typ
μA typ
μA typ
Digital inputs = 0 V or VL
8.0
SCLK = 1 MHz
SCLK = 50 MHz
14
±
CS and SDI = 0 V or VL, VL = 5 V
CS and SDI = 0 V or VL, VL = 3 V
390
CS = VL and SDI = 0 V or VL,
VL = 5 V
210
15
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS and SCLK = 0 V or VL, VL =
5 V
CS and SCLK = 0 V or VL, VL =
3 V
CS and SCLK = 0 V or VL, VL =
5 V
CS and SCLK = 0 V or VL, VL =
3 V
Digital inputs toggle
between 0 V and VL, VL =
5.5 V
SDI = 1 MHz
SDI = 25 MHz
±.5
230
120
1.8
Active at 50 MHz
2
2.1
mA max
mA typ
0.±
Digital inputs toggle
between 0 V and VL, VL =
2.± V
1.0
9
40
mA max
V min
V max
Single-Supply Operation (VDD
)
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Rev. 0 | Page 8 of 30
Data Sheet
ADGS5414
36 V SINGLE SUPPLY
ꢀDD = 36 ꢀ 1ꢁ0, ꢀSS = ꢁ ꢀ, ꢀL = 2.7 ꢀ to 5.5 ꢀ, GND = ꢁ ꢀ, unless otherwise noted.
Table 4.
Parameter
+2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
23
V
14.5
Ω typ
VS = 0 V to 30 V, IS = −10 mA;
see Figure 29
VDD = 32.4 V, VSS = 0 V
16
0.3
19
Ω max
Ω typ
On-Resistance Match Between Channels,
∆RON
VS = 0 V to 30 V, IS = −10 mA
0.8
3.5
4.3
1.3
5.5
1.4
6.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 0 V to 30 V, IS = −10 mA
VDD = 39.6 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.1
nA typ
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 32
±0.25
±0.1
±1
±1
±2
±±
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 32
±0.25
±0.15
±±
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/30 V; see
Figure 28
±0.4
±14
nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.4
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
Output Current, IOL or IOH
0.001
4
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.± V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, IINL or IINH
0.001
4
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
tON
425
435
145
151
260
245
ns typ
ns max
ns typ
ns max
ns typ
ns min
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 3±
RL = 300 Ω, CL = 35 pF
515
195
515
195
205
tOFF
Break-Before-Make Time Delay, tD
VS1 = VS2 = 18 V; see Figure
36
Charge Injection, QINJ
Off Isolation
145
−60
−±5
pC typ
dB typ
dB typ
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1
MHz; Figure 30
Channel to Channel Crosstalk
Rev. 0 | Page 9 of 30
ADGS5414
Data Sheet
Parameter
+2ꢀ°C −40°C to +8ꢀ°C −40°C to +12ꢀ°C Unit
Test Conditions/Comments
THD + N
0.04
% typ
RL = 1 kΩ, 18 V p-p, f = 20 Hz
to 20 kHz; see Figure 33
−3 dB Bandwidth
Insertion Loss
200
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF; see
Figure 34
RL = 50 Ω, CL = 5 pF, f = 1
MHz;
−0.85
see Figure 34
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
11
11
26
pF typ
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
All switches open
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 5.5 V
All switches closed, VL = 2.± V
All switches closed, VL = 2.± V
80
μA typ
μA max
μA typ
μA max
μA typ
μA max
130
130
490
80
330
IL
Inactive
6.3
14
μA typ
μA max
μA typ
Digital inputs = 0 V or VL
8.0
SCLK = 1 MHz
SCLK = 50 MHz
SDI = 1 MHz
CS and SDI = 0 V or VL, VL = 5
V
CS and SDI = 0 V or VL, VL = 3
V
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS and SCLK = 0 V or VL, VL =
5 V
CS and SCLK = 0 V or VL, VL =
3 V
CS and SCLK = 0 V or VL, VL =
5 V
CS and SCLK = 0 V or VL, VL =
3 V
Digital inputs toggle
±
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
390
210
15
±.5
230
120
1.8
SDI = 25 MHz
Active at 50 MHz
between 0 V and VL, VL = 5.5 V
2
2.1
mA max
mA typ
0.±
Digital inputs toggle
between 0 V and VL, VL = 2.± V
1.0
9
40
mA max
V min
V max
Single-Supply Operation (VDD
)
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Rev. 0 | Page 10 of 30
Data Sheet
ADGS5414
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Pins
Table 5. Eight Channels On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx PINS
VDD = +15 V, VSS = −15 V (θJA = 50°C/W)
VDD = +20 V, VSS = −20 V (θJA = 50°C/W)
VDD = 12 V, VSS = 0 V (θJA = 50°C/W)
VDD = 36 V, VSS = 0 V (θJA = 50°C/W)
82
86
63
85
61
63
47
62
38
41
29
40
mA maximum
mA maximum
mA maximum
mA maximum
Table 6. One Channel On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx PINS
VDD = +15 V, VSS = −15 V (θJA = 50°C/W)
VDD = +20 V, VSS = −20 V (θJA = 50°C/W)
VDD = 12 V, VSS = 0 V (θJA = 50°C/W)
VDD = 36 V, VSS = 0 V (θJA = 50°C/W)
199
210
157
206
124
129
104
127
75
77
68
76
mA maximum
mA maximum
mA maximum
mA maximum
TIMING SPECIFICATIONS
VL = 2.7 V to 5.5 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
Limit
Unit
Test Conditions/Comments
TIMING CHARACTRISTICS
t1
t2
t3
t4
t5
t6
t7
t8
20
8
8
10
6
8
10
20
20
20
20
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
SCLK period
SCLK high pulse width
SCLK low pulse width
CS falling edge to SCLK active edge
Data setup time
Data hold time
SCLK active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
CS falling edge to SCLK becomes stable
CS rising edge to SCLK becomes stable
1
t9
t10
t11
t12
t13
8
1 Measured with the 1 kΩ pull-up resistor to VL and a 20 pF load. t9 determines the maximum SCLK frequency when using SDO.
Rev. 0 | Page 11 of 30
ADGS5414
Data Sheet
Timing Diagrams
t1
SCLK
CS
t2
t7
t4
t3
t6
t5
SDI
R/W
A6
A5
1
D2
D2
D1
D1
D0
D0
t10
t9
SDO
0
0
t8
Figure 2. Addressable Mode Timing Diagram
t1
SCLK
CS
t2
t3
t4
t7
t6
t5
SDI
D7
D6
D0
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N + 1
INPUT BYTE FOR DEVICE N
t9
t10
SDO
0
0
0
D7
D6
D1
D0
ZERO BYTE
INPUT BYTE FOR DEVICE N
t8
Figure 3. Daisy Chain Timing Diagram
t11
CS
SCLK
t13
t12
CS
Figure 4. SCLK/ Timing Diagram
Rev. 0 | Page 12 of 30
Data Sheet
ADGS5414
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 8.
Parameter
Rating
VDD to VSS
48 V
VDD to GND
VSS to GND
VL to GND
−0.3 V to +48 V
+0.3 V to −48 V
−0.3 V to +5.75 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
−0.3 V to +5.75 V
422 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data (see Table 5 and Table 6) +
15%
Analog Inputs1
Only one absolute maximum rating can be applied at any
one time.
Digital Inputs1
Peak Current, Sx or Dx Pins
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Continuous Current, Sx or Dx
Pins2
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak
Temperature, Pb Free
−40°C to +125°C
−65°C to +150°C
150°C
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
260(+0 or −5)°C
Table 9. Thermal Resistance
Package Type
Human Body Model (HBM)
Electrostatic Discharge (ESD)
8 kV
2
θJA
θJC
Unit
CP-24-171
50
3.28
°C/W
1 Overvoltages at the Sx and Dx pins are clamped by internal diodes. Limit
current to the maximum ratings given.
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51.
2 See Table 5 and Table 6.
2 θJCB is the junction to the bottom of the case value.
ESD CAUTION
Rev. 0 | Page 13 of 30
ADGS5414
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
18 V
SS
V
DD
S1 2
3
17
16
S8
D
8
D1
S2
D2
S3
ADGS5414
TOP VIEW
15 S7
4
5
6
(Not to Scale)
14
13
D7
S6
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE EXPOSED PAD BE
SOLDERED TO THE SUBSTRATE, V
.
SS
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
VDD
S1
Description
1
2
Most Positive Power Supply Potential.
Source Terminal 1. This pin can be an input or output.
Drain Terminal 1. This pin can be an input or output.
Source Terminal 2. This pin can be an input or output.
Drain Terminal 2. This pin can be an input or output.
Source Terminal 3. This pin can be an input or output.
Drain Terminal 3. This pin can be an input or output.
Source Terminal 4. This pin can be an input or output.
Drain Terminal 4. This pin can be an input or output.
Drain Terminal 5. This pin can be an input or output.
Source Terminal 5. This pin can be an input or output.
Drain Terminal 6. This pin can be an input or output.
Source Terminal 6. This pin can be an input or output.
Drain Terminal ±. This pin can be an input or output.
Source Terminal ±. This pin can be an input or output.
Drain Terminal 8. This pin can be an input or output.
Source Terminal 8. This pin can be an input or output.
3
4
5
6
±
8
9
10
11
12
13
14
15
16
1±
18
19
D1
S2
D2
S3
D3
S4
D4
D5
S5
D6
S6
D±
S±
D8
S8
VSS
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
SDO
Serial Data Output. This pin can daisy-chain a numeral ADGS5414 devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the
falling edge of SCLK. Pull this open-drain output to VL with an external resistor.
20
21
22
RESET/VL
CS
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.± V
to 5.5 V supply. Pull the pin low to complete a hardware reset. All switches are opened, and the
appropriate registers are set to their default.
Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes
low, it powers on the SCLK buffers and enables the input shift register. Data is transferred in on the
falling edges of the following clocks. Taking CS high updates the switch condition.
SCLK
Serial Clock Input. Data is captured on the positive edge of SCLK . Data can be transferred at rates
of up to 50 MHz.
23
24
GND
SDI
Ground (0 V) Reference.
Serial Data Input. Data is captured on the positive edge of the serial clock input.
Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Rev. 0 | Page 14 of 30
Data Sheet
ADGS5414
TYPICAL PERFORꢂANCE CHARACTERISTICS
25
16
14
12
10
8
T
= 25°C
T
= 25°C
A
A
V
V
= +10V
= –10V
V
V
= +9V
= –9V
DD
SS
DD
SS
20
15
10
5
V
V
= +11V
= –11V
DD
SS
V
V
= 32.4V
= 0V
DD
SS
V
V
= 39.6V
DD
= 0V
SS
V
V
= 36V
= 0V
DD
SS
V
V
= +13.5V
= –13.5V
DD
SS
6
V
V
= +15V
= –15V
DD
SS
V
V
= +16.5V
= –16.5V
DD
SS
4
2
0
0
–18
–14
–10
–6
–2
2
6
10
14
18
0
5
10
15
20
25
30
35
40
45
V , V (V)
V , V (V)
S
D
S
D
Figure 6. RON as a Function of VS and VD (Dual Supply)
Figure 9. RON as a Function of VS and VD (Single Supply)
16
14
12
10
8
25
20
15
10
5
T
= 25°C
A
V
V
= +18V
= –18V
DD
SS
T
= +125°C
= +85°C
A
T
A
A
A
V
V
= +20V
= –20V
V
V
= +22V
= –22V
DD
SS
DD
T
T
= +25°C
= –40°C
SS
6
4
2
V
V
= +15V
= –15V
DD
SS
0
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
–15
–10
–5
0
5
10
15
V , V (V)
V , V (V)
S
D
S
D
Figure 10. RON as a Function of VS and VD for Different Temperatures, 15 V Dual
Supply
Figure 7. RON as a Function of VS and VD (Dual Supply)
25
–35
–30
–25
–20
–15
–10
–5
V
V
= +20V
= –20V
T
= 25°C
DD
SS
A
V
V
= 10V
= 0V
DD
SS
V
V
= 10.8V
= 0V
DD
SS
V
V
= 9V
= 0V
20
15
10
5
DD
SS
T
= +125°C
= +85°C
A
T
A
A
A
V
V
= 11V
= 0V
DD
SS
V
V
= 12V
= 0V
DD
SS
T
T
= +25°C
= –40°C
V
V
= 13.2V
= 0V
DD
SS
0
0
–20
–15
–10
–5
0
5
10
15
20
0
–2
–4
–6
–8
V , V (V)
–10
–12
–14
S
D
V , V (V)
S
D
Figure 8. RON as a Function of VS and VD (Single Supply)
Figure 11. RON as a Function of VS and VD for Different Temperatures, 20 V Dual
Supply
Rev. 0 | Page 15 of 30
ADGS5414
Data Sheet
40
35
30
25
20
15
10
5
0.20
0.15
0.10
0.05
0
I
I
(OFF) +, –
(OFF) –, +
I
(OFF) +, –
I (OFF) –, +
S
S
D
D
I , I (ON) +, +
I , I (ON) –, –
S
D
S D
T
= +125°C
= +85°C
A
T
A
T
T
= +25°C
= –40°C
A
–0.05
–0.10
–0.15
–0.20
A
V
V
V
= +20V
= –20V
DD
SS
V
V
= 12V
= 0V
DD
SS
= +10V, –10V
BIAS
0
0
2
4
6
8
10
12
0
20
40
60
80
100
120
TEMPERATURE (°C)
V
, V (V)
D
S
Figure 15. Leakage Currents vs. Temperature, 20 V Dual Supply
Figure 12. RON as a Function of VS and VD for Different Temperatures, 12 V Single
Supply
0.20
25
I
I
(OFF) +, –
(OFF) –, +
I
(OFF) +, –
I (OFF) –, +
S
V
V
= 36V
= 0V
S
D
D
DD
SS
I , I (ON) +, +
I , I (ON) –, –
S
D
S D
0.15
0.10
0.05
0
20
15
10
5
T
= +125°C
= +85°C
A
T
A
A
A
T
T
= +25°C
= –40°C
–0.05
–0.10
–0.15
–0.20
V
V
V
= +12V
= 0V
DD
SS
= +1V, –1V
BIAS
0
0
5
10
15
20
, V (V)
25
30
35
40
0
20
40
60
80
100
120
TEMPERATURE (°C)
V
S
D
Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply
Figure 13. RON as a Function of VS and VD for Different Temperatures, 36 V Single
Supply
0.3
0.20
I
I
(OFF) +, –
(OFF) –, +
I
(OFF) +, –
I (OFF) –, +
S
S
D
D
I
I
(OFF) +, –
(OFF) –, +
I
(OFF) +, –
I (OFF) –, +
S
S
D
D
I , I (ON) +, +
I , I (ON) –, –
S
D
S D
I , I (ON) +, +
I , I (ON) –, –
S
D
S D
0.15
0.10
0.05
0
0.2
0.1
0
–0.05
–0.10
–0.15
–0.20
–0.1
–0.2
–0.3
V
V
V
= 36V
= 0V
V
V
V
= +15V
= –15V
DD
SS
DD
SS
= 1V, 30V
= +10V, –10V
BIAS
BIAS
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply
Figure 14. Leakage Currents vs. Temperature, 15 V Dual Supply
Rev. 0 | Page 16 of 30
Data Sheet
ADGS5414
0
10
–10
T
V
V
= 25°C
= +15V
T
V
V
= 25°C
= +15V
DD
100nF DECOUPLING CAP
10µF + 100nF DECOUPLIG CAP
NO DECOUPLING
A
A
DD
= –15V
= –15V
–20
–40
SS
SS
–30
–60
–50
–80
–70
–100
–120
–140
–90
–110
–130
100
1k
10k
100k
1M
10M
100M
1G
10G
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply
Figure 21. ACPSRR vs. Frequency, 15 V Dual Supply
0.12
0.10
0.08
0.06
0.04
0.02
0
0
–20
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
V
= 12V, V = 0V, V = 6V p-p
SS S
DD
LOAD = 1kΩ
= 25°C
T
–40
A
–60
V
= 36V, V = 0V, V = 18V p-p
SS S
–80
DD
–100
–120
–140
V
= 15V, V = 15V, V = 15V p-p
SS S
DD
V
= 20V, V = 20V, V = 20V p-p
SS S
DD
0
5
10
FREQUENCY (kHz)
15
20
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 22. THD + N vs. Frequency, Dual Supply
Figure 19. Crosstalk vs. Frequency, 15 V Dual Supply
0
300
250
200
150
100
50
T
V
V
= 25°C
A
T
= 25°C
V
V
V
V
= +20V, V = –20V
SS
A
DD
DD
DD
DD
= +15V
= –15V
= +15V, V = –15V
DD
SS
SS
= +12V, V = 0V
SS
= +36V, V = 0V
SS
–1
–2
–3
–4
–5
0
–20
–10
0
10
(V)
20
30
40
10k
100k
1M
10M
100M
1G
V
FREQUENCY (Hz)
S
Figure 23. Bandwidth vs. Frequency
Figure 20. Charge Injection vs. VS
Rev. 0 | Page 1± of 30
ADGS5414
Data Sheet
500
450
400
350
300
250
200
150
100
50
0.5
0.4
SCLK = 2.5MHz
SCLK IDLE
15V DS, tON
15V DS, tOFF
20V DS, tON
20V DS, tOFF
12V SS, tON
12V SS, tOFF
36V SS, tON
36V SS, tOFF
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0
–40
–20
0
20
40
60
80
100
120
0
2
4
6
8
TEMPERATURE (°C)
TIME (µs)
Figure 24. tON and tOFF Times vs. Temperature
Figure 26. Digital Feedthrough
120
100
80
60
40
20
0
450
T
= 25°C
V
L
A
T
= 25°C
A
I
WITH ONE SWITCH CLOSED
+12V
±15V
±20V
+36V
DD
400
350
300
250
200
150
100
50
V
V
= 5V
= 3V
L
L
0
2.7
3.0
3.5
4.0
V
4.5
5.0
5.5
0
10
20
30
40
50
(V)
SCLK FREQUENCY (MHz)
L
Figure 25. IDD vs. VL
CS
Figure 27. IL vs. SCLK Frequency when is High
Rev. 0 | Page 18 of 30
Data Sheet
ADGS5414
TEST CIRCUITS
I
(ON)
A
I
(ON)
A
D
D
Sx
Dx
Sx
Dx
V
S
V
V
S
V
D
D
Figure 28. On Leakage
Figure 32. Off Leakage
V
V
DD
SS
0.1µF
0.1µF
I
DS
AUDIO PRECISION
V
V
DD
SS
V1
R
S
Sx
Sx
Dx
V
S
V p-p
V
S
Dx
R
= V /I
1 DS
ON
V
OUT
R
L
GND
1kΩ
Figure 29. On Resistance
Figure 33. THD + Noise
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
V
0.1µF
DD
0.1µF
SS
V
NC
OUT
S1
D1
R
L
50Ω
NETWORK
ANALYZER
V
V
DD
SS
S2
D2
R
L
50Ω
Sx
50Ω
V
S
GND
V
S
Dx
V
OUT
R
L
GND
50Ω
V
OUT
CHANNEL TO CHANNEL CROSSTALK = 20 log
V
S
V
WITH SWITCH
OUT
Figure 30. Channel to Channel Crosstalk
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
S
Figure 34. Bandwidth
V
V
DD
SS
0.1µF
0.1µF
V
SS
NETWORK
ANALYZER
V
V
NETWORK
ANALYZER
DD
SS
Sx
50Ω
INTERNAL
BIAS
50Ω
V
V
DD
SS
R
50ꢀ
L
V
S
Dx
V
S
V
OUT
R
L
GND
50Ω
V
NC
OUT
S1
D1
R
50ꢀ
L
GND
V
OUT
OFF ISOLATION = 20 log
V
S
V
V
OUT
ACPSRR = 20 log
S
Figure 31. Off Isolation
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE ACPSRR MEASUREMENT.
Figure 35. ACPSRR
Rev. 0 | Page 19 of 30
ADGS5414
Data Sheet
V
V
V
V
DD
SS
0.1µF
0.1µF
SCLK
50%
50%
0V
0V
DD
SS
80%
80%
V
V
OUT1
OUT2
S1
D1
V
V
S1
V
OUT1
R
300ꢀ
C
L1
35pF
L1
S2
D2
S2
V
OUT2
R
300ꢀ
C
L2
35pF
L2
80%
80%
INPUT LOGIC
GND
0V
tD
tD
Figure 36. Break-Before-Make Time Delay, tD
V
V
V
DD
SS
0.1µF
0.1µF
V
DD
SS
SCLK
V
OUT
50%
50%
Sx
Dx
R
300ꢀ
C
L
35pF
L
90%
V
S
V
INPUT LOGIC
GND
OUT
10%
tON
tOFF
Figure 37. Switching Times
V
V
DD
SS
SS
3V
V
V
DD
SCLK
R
V
S
Sx
Dx
V
OUT
C
1nF
L
S
Q
= C × ∆V
L OUT
INJ
INPUT LOGIC
GND
V
OUT
∆V
OUT
SWITCH OFF
SWITCH ON
Figure 38. Charge Injection
Rev. 0 | Page 20 of 30
Data Sheet
ADGS5414
TERꢂINOLOGY
IDD
CIN
I
DD is the positive supply current.
CIN is the digital input capacitance.
ISS
tON
I
SS is the negative supply current.
tON is the delay between applying the digital control input and
the output switching on.
VD, VS
ꢀD and ꢀS are the analog voltages on Terminal D and Terminal
tOFF
S, respectively.
tOFF is the delay between applying the digital control input and
the output switching off.
RON
RON represents the ohmic resistance between Terminal D and
tD
Terminal S.
tD is the off time measured between the 8ꢁ0 point of both
switches when switching from one address state to another.
ΔRON
ΔRON is the difference between the RON of any two channels.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
RFLAT(ON)
RFLAT(ON) is defined as the difference between the maximum and
minimum value of on resistance measured over the specified
analog signal range.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) are the channel leakage currents with the
switch on.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINL
On Response
ꢀINL is the maximum input voltage for Logic ꢁ.
On response is the frequency response of the on switch.
VINH
Insertion Loss
ꢀINH is the minimum input voltage for Logic 1.
Insertion loss is the loss due to the on resistance of the switch.
IINL, IINH
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
I
INL and IINH are the low and high input currents of the digital
inputs.
CD (Off)
AC Power Supply Rejection Ratio (ACPSRR)
CD (Off) is the off switch drain capacitance, which is measured
with reference to GND.
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. ACPSRR is a measure of the ability of
the device to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of ꢁ.62 ꢀ p-p.
CS (Off)
CS (Off) is the off switch source capacitance, which is measured
with reference to GND.
CD (On), CS (On)
CD (On) and CS (On) are the on switch capacitances, which are
measured with reference to GND.
Rev. 0 | Page 21 of 30
ADGS5414
Data Sheet
THEORY OF OPERATION
A register write occurs on the 16th SCLK rising edge during SPI
writes.
The ADGS5414 is a set of SPI controlled, octal SPST switches with
error detection features. SPI Mode 0 and Mode 3 can be used
with the device, and it operates with SCLK frequencies up to 50
MHz. The default mode for the ADGS5414 is address mode in
which the registers of the device are accessed by a 16-bit SPI
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
CS
command that is bounded by . The SPI command becomes
ERROR DETECTION FEATURES
24 bits long if the user enables CRC error detection. Other error
detection features include SCLK count error detection and invalid
read/write error detection. If any of these SPI interface errors occur,
they are detectable by reading the error flags register. The
ADGS5414 can also operate in two other modes: burst mode
and daisy-chain mode.
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors: incorrect SCLK error
detection, invalid read and write address error detection, and
CRC error detection. Each of these errors has a corresponding
enable bit in the error configuration register. In addition, there
is an error flag bit for each of these errors in the error flags
register.
CS
The interface pins of the ADGS5414 are , SCLK, SDI, and SDO.
CS
Hold
low when using the SPI interface. Data is captured on
CRC Error Detection
SDI on the rising edge of SCLK, and data is propagated out on SDO
on the falling edge of SCLK. SDO has an open-drain output;
thus, connect a pull-up to this output. When not pulled low by
the ADGS5414, SDO is in a high impedance state.
The CRC error detection feature extends a valid SPI frame by
eight SCLK cycles. These eight extra cycles send the CRC byte for
that SPI frame. The CRC byte is calculated by the SPI block using
W
the 16-bit payload: the R/ bit, a selected register address,
ADDRESS MODE
Bits[6:0], and selected Register Data Bits[7:0]. The CRC
polynomial used in the SPI block is x8 + x2 + x1 + 1 with a seed
value of 0. For a timing diagram with CRC enabled, see Figure 40.
Register writes occur at the 24th SCLK rising edge with CRC
error checking enabled.
Address mode is the default mode for the ADGS5414 upon
power-up. A single SPI frame in address mode is bounded by
CS
CS
a
falling edge and the succeeding rising edge. The SPI frame
is comprised of 16 SCLK cycles. The timing diagram for address
mode is shown in Figure 39. The first SDI bit indicates if the SPI
command is a read or write command. When the first bit is set
to 0, a write command is issued, and if the first bit is set to 1, a
read command is issued. The next seven bits determine the target
register address. The remaining eight bits provide the data to the
addressed register. The last eight bits are ignored during a read
command, because, during these clock cycles, SDO propagates
out the data contained in the addressed register.
During an SPI write, the microcontroller or computer processing
unit (CPU) provides the CRC byte through SDI. The SPI block
checks the CRC byte just before the 24th SCLK rising edge. On this
same edge, the register write is prevented if an incorrect CRC byte
is received by the SPI interface. The CRC error flag is asserted
in the error flags register in the case of the incorrect CRC byte
being detected.
During an SPI read, the CRC byte is provided to the
microcontroller through SDO.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the ninth to the 16th SCLK falling edge during SPI
reads.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
SDI
R/W A6
0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Figure 39. Address Mode Timing Diagram
Rev. 0 | Page 22 of 30
Data Sheet
ADGS5414
1
2
8
9
10
16
17
18
19
20
21
22
23
24
CS
SCLK
SDI
R/W A6
0
A0
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
SDO
0
1
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
Figure 40. Timing Diagram with CRC Enabled
SCLK Count Error Detection
BURST MODE
SCLK count error detection allows the user to detect if an incorrect
number of SCLK cycles are sent by the microcontroller or CPU.
When in address mode, with CRC disabled, 16 SCLK cycles are
expected. If 16 SCLK cycles are not detected, the SCLK count
error flag asserts in the error flags register. When less than 16 SCLK
cycles are received by the device, a write to the register map does
not occur. When the ADGS5414 receives more than 16 SCLK
cycles, a write to the memory map still occurs at the 16th SCLK
rising edge, and the flag asserts in the error flags register. With
CRC enabled, the expected number of SCLK cycles becomes 24.
SCLK count error detection is enabled by default and can be
configured by the user through the error configuration register.
The SPI interface can accept consecutive SPI commands
CS
without the need to deassert the
line, which is called burst
mode. Burst mode is enabled through the burst enable register
(Address 0x05). This mode uses the same 16-bit command to
communicate with the device. In addition, the response of
the device at SDO is still aligned with the corresponding SPI
command. Figure 41 shows an example of SDI and SDO during
burst mode.
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
Invalid Read/Write Address Error
CS
within a given
frame is counted, and if the total is not a
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error occurs.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register does not
occur when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be disabled
by the user through the error configuration register.
multiple of 16, or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
CS
SDI
COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0]
SDO
RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0]
Figure 41. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset.
To do so, write two consecutive SPI commands, namely 0xA3
followed by 0x05, to Register 0x0B. After a software reset, all
register values are set to default.
CLEARING THE ERROR FLAGS REGISTER
To clear the error flags register, write the 16-bit SPI frame (not
included in the register map), 0x6CA9, to the device. This SPI
DAISY-CHAIN MODE
W
command does not trigger the invalid R/ address error. When
The connection of several ADGS5414 devices in a daisy-chain
configuration is possible, and Figure 42 shows this setup. All
CRC is enabled, the user must send the correct CRC byte for a
successful error clear command. At the 16th or 24th SCLK rising
edge, the error flags register resets to zero.
CS
devices share the same and SCLK line, whereas the SDO of a
device forms a connection to the SDI of the next device, creating a
shift register. In daisy-chain mode, SDO is an eight cycle delayed
version of SDI. When in daisy-chain mode, all commands target
the switch data register (SW_DATA). Therefore, it is not
possible to make configuration changes while in daisy-chain mode.
Rev. 0 | Page 23 of 30
ADGS5414
Data Sheet
ADGS5414
DEVICE 1
ADGS5414
DEVICE 2
S1
S2
S3
S4
S5
S6
S7
S8
D1
D2
D3
D4
D5
D6
D7
D8
S1
S2
S3
S4
S5
S6
S7
S8
D1
D2
D3
D4
D5
D6
D7
D8
V
L
SDO
SPI
INTERFACE
SPI
INTERFACE
SDO
SDI
SCLK
CS
V
L
Figure 42. Two SPI Controlled Switches Connected in a Daisy-Chain Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
CS
SCLK
SDI
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Figure 43. SPI Command to Enter Daisy-Chain Mode
CS
SDI
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0]
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
SDO
8’h00
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0]
SDO2
SDO3
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0]
8’h00 COMMAND3[7:0]
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 44. Example of an SPI Frame when Four ADGS5414 Devices are Connected in Daisy-Chain Mode
The ADGS5414 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, 0x2500
(see Figure 43). When the ADGS5414 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
An SCLK rising edge reads in data on SDI while data is
propagated out on SDO on an SCLK falling edge. The expected
CS
goes high. If this is not the case, the SPI interface sends the last
eight bits received to the switch data register.
number of SCLK cycles must be a multiple of eight before
POWER-ON RESET
The digital section of the ADGS5414 goes through an initialization
phase during VL power-up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
a minimum of 120 μs from the time of power-up or reset before
any SPI command is issued. Ensure VL does not drop out during
the 120 μs initialization phase because it can result in the
incorrect operation of the ADGS5414.
For the timing diagram of a typical daisy-chain SPI frame, see
CS
Figure 44. For example, when
goes high, Device 1 writes
Command 0, SW_DATA, Bits[7:0] to its switch data register,
Device 2 writes Command 1, SW_DATA, Bits[7:0] to its
switches. The SPI block uses the last eight bits it receives
through SDI to update the switches. After entering daisy-chain
mode, the first eight bits sent out by SDO on each device in the
CS
chain are 0x00. When
goes high, the internal shift register
value does not reset back to zero.
Rev. 0 | Page 24 of 30
Data Sheet
ADGS5414
In junction isolation, the P-well and N-well of the PMOS and
BREAK-BEFORE-MAKE SWITCHING
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed, and the result is a latch-
up proof switch.
The ADGS5414 exhibits break-before-make switching action,
which allows the use of the device in multiplexer applications. A
multiplexer function can be achieved by externally hardwiring the
device in the required mux configuration, as shown in Figure 45.
4:1 MUX
4 × SPST
S1
The Analog Devices, Inc., high voltage latch-up proof family of
switches and multiplexers provides a robust olution for
instrumentation, industrial, aerospace, and other harsh
environments that are prone to latch-up, which is an
undesirable high current state that can lead to device failure and
persists until the power supply is turned off. The ADGS5414
high voltage switches allow single-supply operation from 9 V to
40 V and dual-supply operation from 9 V to 22 V.
S2
Dx
S3
S4
SPI
INTERFACE
NMOS
PMOS
SCLK SDI CS RESET/V
L
Figure 45. An SPI Controlled Switch Configured in a 4:1 Mux
TRENCH ISOLATION
In the analog switch section of the ADGS5414, an insulating oxide
layer (trench) is placed between the N-type metal-oxide semi-
conductor (NMOS) and the P-type metal-oxide semiconductor
(PMOS) transistors of each complementary metal-oxide semi-
conductor CMOS switch. Parasitic junctions, which occur between
the transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 46. Trench Isolation
Rev. 0 | Page 25 of 30
ADGS5414
Data Sheet
APPLICATIONS INFORMATION
Figure 47 also shows two optional low dropout regulators
POWER SUPPLY RAILS
(LDOs), ADP7118 and ADP7182, positive and negative LDOs
respectively, that can reduce the output ripple of the ADP5070
in ultralow noise sensitive applications.
To guarantee correct operation of the ADGS5414, 0.1 μF
decoupling capacitors are required.
The ADGS5414 can operate with bipolar supplies between 9 V
and 22 V. The supplies on VDD and VSS do not need to be
symmetrical; however, the VDD to VSS range must not exceed 44 V.
The ADGS5414 can also operate with single supplies between
9 V and 40 V with VSS connected to GND.
The ADM7160 can be used to generate the VL voltage that is
required to power the digital circuitry within the ADGS5414.
ADM7160
+3.3V
LDO
+16.5V
–16.5V
ADP7118
LDO
+15V
–15V
+5V
INPUT
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
ADP5070
ADP7182
LDO
The device is fully specified at 15 V, 20 V, +12 V, and +36 V,
analog supply voltage ranges.
Figure 47. Bipolar Power Solution
POWER SUPPLY RECOMMENDATIONS
Table 10. Recommended Power Management Devices
Product Description
Analog Devices has a wide range of power management
products that meet the requirements of most high performance
signal chains.
ADP5070 1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator
ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7182 −28 V, −200 mA, low noise, LDO linear regulator
An example of a bipolar power solution is shown in Figure 47.
The ADP5070 dual switching regulator generates a positive and
negative supply rail for the ADGS5414, an amplifier, and/or a
precision converter in a typical signal chain.
Rev. 0 | Page 26 of 30
Data Sheet
ADGS5414
REGISTER SUMMARY
Table 11. Register Summary
Reg. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default RW
0x01 SW_DATA
0x02 ERR_CONFIG
0x03 ERR_FLAGS
0x05 BURST_EN
0x0B SOFT_RESETB
SW8_EN SW7_EN SW6_EN SW5_EN SW4_EN SW3_EN
SW2_EN
SW1_EN
0x00
0x06
R/W
R/W
R
Reserved
Reserved
RW_ERR_EN SCLK_ERR_EN CRC_ERR_EN
RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG 0x00
BURST_MODE_EN 0x00
Reserved
R/W
R/W
SOFT_RESETB
0x00
Rev. 0 | Page 27 of 30
ADGS5414
Data Sheet
REGISTER DETAILS
SWITCH DATA REGISTER
SW_DATA, Address 0x01, Reset: 0x00
The switch data register controls the status of the eight switches of the ADGS5414.
Table 12. Bit Descriptions for SW_DATA
Bit
Bit Name
Setting
Description
Default Access
7
SW8_EN
Enable bit for Switch 8.
Switch 8 open.
Switch 8 closed.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
6
5
4
3
2
1
0
SW7_EN
SW6_EN
SW5_EN
SW4_EN
SW3_EN
SW2_EN
SW1_EN
Enable bit for Switch 7.
Switch 7 open.
Switch 7 closed.
0
1
Enable bit for Switch 6.
Switch 6 open.
Switch 6 closed.
0
1
Enable bit for Switch 5.
Switch 5 open.
Switch 5 closed.
0
1
Enable bit for Switch 4.
Switch 4 open.
Switch 4 closed.
0
1
Enable bit for Switch 3.
Switch 3 open.
Switch 3 closed.
0
1
Enable bit for Switch 2.
Switch 2 open.
Switch 2 closed.
0
1
Enable bit for Switch 1.
Switch 1 open.
Switch 1 closed.
0
1
ERROR CONFIGURATION REGISTER
ERR_CONFIG, Address 0x02, Reset: 0x06
The error configuration register allows the user to enable or disable the relevant error features as required.
Table 13. Bit Descriptions for ERR_CONFIG
Bit
[7:3]
2
Bit Name
Setting
Description
Default Access
Reserved
These bits are reserved; set these bits to 0.
0x0
0x1
R
RW_ERR_EN
Enable bit for detecting an invalid read/write address.
R/W
0
1
Disabled.
Enabled.
1
0
SCLK_ERR_EN
CRC_ERR_EN
Enable bit for detecting the correct number of SCLK cycles in an SPI frame. 0x1
16 SCLK cycles are expected when CRC is disabled and burst mode is
disabled. 24 SCLK cycles are expected when CRC is enabled and burst
mode is disabled. A multiple of 16 SCLK cycles is expected when CRC is
disabled and burst mode is enabled. A multiple of 24 SCLK cycles is
expected when CRC is enabled and burst mode is enabled.
R/W
R/W
0
1
Disabled.
Enabled.
Enable bit for CRC error detection. SPI frames must be 24 bits wide when
enabled.
0x0
0
1
Disabled.
Enabled.
Rev. 0 | Page 28 of 30
Data Sheet
ADGS5414
ERROR FLAGS REGISTER
ERR_FLAGS, Address 0x03, Reset: 0x00,
The error flags register allows the user to determine if an error occurs. To clear the error flags register, write the special 16-bit SPI
command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user
must include the correct CRC byte during the SPI write for the clear Error Flags Register command to be successful.
Table 14. Bit Descriptions for ERR_FLAGS
Bit
[7:3]
2
Bit Name
Setting
Description
Default Access
RESERVED
These bits are reserved and are set to 0.
0x0
0x0
R
R
RW_ERR_FLAG
Error flag for invalid read/write address. The error flag asserts during an
SPI read if the target address does not exist. The error flag also asserts
when the target address of a SPI write is does not exist or is read only.
0
1
No Error.
Error.
1
0
SCLK_ERR_FLAG
CRC_ERR_FLAG
Error flag for the detection of the correct number of SCLK cycles in an SPI
frame.
No Error.
0x0
0x0
R
R
0
1
Error.
Error Flag that determines if a CRC error occurs during a register write.
0
1
No Error.
Error.
BURST ENABLE REGISTER
BURST_EN, Address 0x05, Reset: 0x00
The burst enable register allows the user to enable/disable the burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting
.
CS
Table 15. Bit Descriptions for BURST_EN
Bits
[7:1]
0
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved; set these bits to 0.
0x0
0x0
R
BURST_MODE_EN
Burst mode enable bit.
Disabled.
Enabled.
R/W
0
1
SOFTWARE RESET REGISTER
SOFT_RESETB, Address 0x0B, Reset: 0x00
This register performs a software reset. Consecutively, write 0xA3 and 0x05 to this register and to reset the device registers to their default
state.
Table 15. Bit Descriptions for SOFT_RESETB
Bits
Bit Name
Settings
Description
Default Access
0x0
[7:0]
SOFT_RESETB
To Perform a Software Reset, consecutively write 0xA3 followed by 0x05
to this register.
R
Rev. 0 | Page 29 of 30
ADGS5414
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN
1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
1.00
0.95
0.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.
Figure 48. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.95 mm Package Height
(CP-24-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADGS5414BCPZ
ADGS5414BCPZ-RL7
EVAL-ADGS5414SDZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-24-17
CP-24-17
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15902-0-10/17(0)
Rev. 0 | Page 30 of 30
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