ADIS16486BMLZ-P [ADI]
Six Degrees of Freedom Inertial Sensor;
| 型号： | ADIS16486BMLZ-P |
| 厂家： | 
ADI |
| 描述： | Six Degrees of Freedom Inertial Sensor |
| 文件： | 总38页 (文件大小：1048K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Six Degrees of Freedom Inertial Sensor
Data Sheet
ADIS16486
FEATURES
GENERAL DESCRIPTION
Triaxial digital gyroscope, 450°/sec dynamic range
(minimum)
The ADIS16486 is a complete inertial system that includes a triaxis
gyroscope and a triaxis accelerometer. Each inertial sensor in the
ADIS16486 combines industry leading iMEMS® technology with
signal conditioning that optimizes dynamic performance. The
factory calibration characterizes each sensor for sensitivity, bias,
alignment, and linear acceleration (gyroscope bias). Therefore,
each sensor has dynamic compensation formulas that provide
accurate sensor measurements.
0.018° axis to axis misalignment error (typical)
5.3°/hr in-run bias stability (typical)
0.25°/√hr angular random walk (typical)
0.01% FS nonlinearity
Triaxial digital accelerometer, 18 g dynamic range
(minimum)
Triaxial, delta angle, and delta velocity outputs
The ADIS16486 provides a simple, cost effective method for
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +85°C
SPI compatible
Programmable operation and control
Automatic and manual bias correction controls
4 FIR filter banks, 120 configurable taps
Digital input and output: data ready alarm indicator,
external clock
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, which reduces system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation
systems. The serial peripheral interface (SPI) and register structure
provide a simple interface for data collection and configuration
control. Parylene coating of all internal circuitry provides a
protective barrier against moisture exposure.
Alarms for condition monitoring
Power-down and sleep mode for power management
Optional external sync input clock: 2.4 kHz (maximum)
Continuous self test of inertial sensors
On demand self test of inertial sensors
Continuous CRC-based memory testing
Single VDD power supply operation: 3.0 V to 3.6 V
2000 g mechanical shock survivability
Operating temperature range: −40°C to +105°C
The ADIS16486 uses the same footprint and connector system as
the ADIS16480, ADIS16485, ADIS16487, and ADIS16488A, which
greatly simplifies the upgrade process. The ADIS16486 is packaged
in a module that is approximately 47 mm × 44 mm × 14 mm with
a 24-lead standard connector interface.
APPLICATIONS
Attitude and heading reference systems
Platform stabilization and control
Unmanned vehicle navigation
Robotics and instrumentation
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 DIO3 DIO4 RST
VDD
POWER
MANAGEMENT
GND
SELF TEST
I/O
ALARMS
TRIAXIAL
OUTPUT
DATA
CS
GYROSCOPE
REGISTERS
SCLK
DIN
TRIAXIAL
ACCELEROMETER
CALIBRATION
AND
FILTERS
SPI
CONTROLLER
USER
CONTROL
REGISTERS
TEMPERATURE
VDD
DOUT
CLOCK
ADIS16486
VDDRTC
Figure 1.
Rev. 0
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Technical Support
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ADIS16486
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
User Register Memory Map.......................................................... 12
User Register Definitions .............................................................. 15
Gyroscope Data .......................................................................... 16
Acceleration Data....................................................................... 17
Delta Angles................................................................................ 18
Delta Velocity ............................................................................. 20
Real-Time Clock (RTC) ............................................................ 21
Calibration .................................................................................. 23
FIR Filters.................................................................................... 34
Applications Information ............................................................. 36
Mounting Best Practices ........................................................... 36
Evaluation Tools......................................................................... 37
Power Supply Considerations .................................................. 37
X-Ray Sensitivity ........................................................................ 37
Packaging and Ordering Information......................................... 38
Outline Dimensions................................................................... 38
Ordering Guide .......................................................................... 38
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings....................................................... 7
Thermal Resistance...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
Typical Performance Characteristics............................................. 9
Theory of Operation ...................................................................... 10
Introduction................................................................................ 10
Register Structure....................................................................... 10
SPI Communication .................................................................. 11
Device Configuration ................................................................ 11
Reading Sensor Data.................................................................. 11
REVISION HISTORY
1/2021—Revision 0: Initial Version
Rev. 0 | Page 2 of 38
Data Sheet
ADIS16486
SPECIFICATIONS
TC = 25°C, VDD = 3.3 V, angular rate = 0°/sec, and dynamic range = 450°/sec 1 g, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
450
Typ
Max
480
1
Unit
GYROSCOPES
Dynamic Range
Sensitivity
°/sec
°/sec/LSB
%
32-bit data format (see Table 41)
−40°C ≤ TC ≤ +85°C
3.052 × 10−7
Repeatability1
Sensitivity Temperature Coefficient −40°C ≤ TC ≤ +85°C, 1 σ
25
0.018
1.0
ppm/°C
Degrees
Degrees
% FS
Misalignment Error
Axis to axis
Axis to frame (package)
Nonlinearity
Best fit straight line, full scale (FS) = 450°/sec
0.01
Bias
Repeatability1, 2
−40°C ≤ TC ≤ +85°C, 1 σ
1 σ
1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
−15°C ≤ TC ≤ +65°C, 10°C range
Any axis, 1 σ (CONFIG, Bit 7 = 1)
Any axis, 1 σ (CONFIG, Bit 7 = 0)
0.2
5.3
0.25
0.0025
0.0611
0.009
0.015
°/sec
°/hr
°/√hr
°/sec/°C
°/sec
In-Run Bias Stability
Angular Random Walk
Temperature Coefficient
Error over Temperature
Linear Acceleration Effect
°/sec/g
°/sec/g
Noise
Output Noise
No filtering
Frequency (f) = 10 Hz to 40 Hz, no filtering
0.16
0.0068
330
°/sec rms
°/sec/√Hz rms
Hz
Rate Noise Density
3 dB Bandwidth
Sensor Resonant Frequency
ACCELEROMETERS3
Dynamic Range
Sensitivity
18
kHz
Each axis
18
g
32-bit data format (see Table 55)
−40°C ≤ TC ≤ +85°C
1.221 × 10−8
g/LSB
%
Repeatability1
0.5
Sensitivity Temperature Coefficient −40°C ≤ TC ≤ +85°C, 1 σ
25
0.035
1.0
10
90
ppm/°C
Degrees
Degrees
mg
Misalignment
Nonlinearity
Axis to axis
Axis to frame (package)
Best fit straight line, 10 g
Best fit straight line, 18 g
mg
Bias
Repeatability1, 2, 4
In-Run Bias Stability
Velocity Random Walk
Temperature Coefficient
Noise
−40°C ≤ TC ≤ +85°C, 1 σ
1 σ
1 σ
16
70
0.029
0.1
mg
μg
m/sec/√hr
mg/°C
−40°C ≤ TC ≤ +85°C, 1 σ
Output Noise
Noise Density
3 dB Bandwidth
Sensor Resonant Frequency
TEMPERATURE SENSOR
Scale Factor
No filtering
f = 10 Hz to 40 Hz, no filtering
1.29
0.063
330
mg rms
mg/√Hz rms
Hz
5.5
kHz
Output = 0x0000 at 25°C ( 5°C)
0.00565
°C/LSB
LOGIC INPUTS5
Input Voltage
High (VIH)
2.0
V
Low (VIL)
0.8
V
RST Pulse Width
CS Wake-Up Pulse Width
1
µs
µs
20
Rev. 0 | Page 3 of 38
ADIS16486
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
10
Unit
Input Current
Logic 1, High (IIH)
Logic 0, Low (IIL)
All Pins Except RST
RST Pin
VIH = 3.3 V
VIL = 0 V
µA
10
µA
mA
pF
0.33
10
Input Capacitance (CIN)
DIGITAL OUTPUTS
Output Voltage
High (VOH
)
Source current (ISOURCE) = 0.5 mA
Sink current (ISINK) = 2.0 mA
Endurance6
2.4
V
V
Low (VOL
)
0.4
FLASH MEMORY
Data Retention7
100,000
20
Cycles
Years
TJ = 85°C
FUNCTIONAL TIMES8
Power-On Start-Up Time
Backup
Reset Recovery Time9
Sleep Mode Recovery Time
Flash Memory
Time until data is available
600
1500
600
ms
ms
ms
µs
1370
390
730
1000
Update Time10
Test Time
1.05
50
6.8
sec
ms
On Demand Self Test (ODST) Time
CONVERSION RATE
Initial Clock Accuracy
Temperature Coefficient
Sync Input Clock
Using internal clock (2460 Hz)
12
ms
2.46
0.02
40
kSPS
%
ppm/°C
kHz
0.711
3.0
2.4
3.6
POWER SUPPLY
VDD
Operating voltage range
Normal mode, µ + 1 σ
Sleep mode
Power-down mode
Operating voltage range
Normal mode, VDDRTC = 3.3 V
V
Power Supply Current12
186
12.2
37
3.3
13
mA
mA
µA
V
VDDRTC13
Real-Time Clock (RTC) Supply
Current
3.0
3.6
µA
1 The repeatability specifications represent analytical projections based on the following drift contributions and conditions: temperature hysteresis (−40°C to +85°C),
electronics drift (high temperature operating life test: +110°C, 500 hours), drift from temperature cycling (JESD22, Method A104-C, Method N, 500 cycles, −55°C to +85°C), rate
random walk (10-year projection), and broadband noise.
2 Bias repeatability describes a long-term behavior over a variety of conditions. Short-term repeatability relates to the in-run bias stability and noise density specifications.
3 All specifications associated with the accelerometers relate to the full-scale range of 18 g.
4 X-ray exposure can degrade this performance metric.
5 The digital input and output signals use a 3.3 V system.
6 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.
7 The data retention specification assumes a TJ of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
8 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.
9
RST
The
line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.
10 Monitoring the data ready signal (see Table 143 for the FNCTIO_CTRL register configuration) for the return of regular pulsing can help minimize system wait times.
11 The device functions at clock rates below 0.7 kHz, but at reduced performance levels.
12 Supply current transients can reach 600 mA during initial startup or reset recovery.
13 Connecting the VDDRTC supply is a requirement, even if the application does not use the RTC function.
Rev. 0 | Page 4 of 38
Data Sheet
ADIS16486
TIMING SPECIFICATIONS
TC = 25°C and VDD = 3.3 V, unless otherwise noted. See Figure 2 to Figure 4 for the timing diagrams.
Table 2.
Parameter Description
Min1
0.01
2
Typ
Max1
Unit
MHz
µs
fSCLK
tSTALL
tCLS
SCLK frequency
Stall period between data
SCLK low period
15
2
31
ns
tCHS
tCS
SCLK high period
CS to SCLK edge
31
32
ns
ns
tDAV
tDSU
tDHD
tDR, tDF
tDSOE
tHD
DOUT valid after SCLK edge
10
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
DOUT rise and fall times, ≤100 pF loading
CS assertion to DOUT active
2
2
3
8
11
0
SCLK falling edge to DOUT invalid
Last SCLK rising edge to CS deassertion
CS deassertion to DOUT high impedance
Data ready pulse width
Input sync pulse width
Input sync to data invalid
0
32
0
tSFS
tDSHI
9
11
15
t1
t2
t3
5
560
570
Input sync period
417
1 Guaranteed by design and characterization, but not tested in production.
2 See Table 3 for exceptions to the stall time rating.
Register Write Processing Times
Table 3.
Parameter
Description
Min1
Typ
Max
Unit
STALL TIME
FNCTIO_CTRL, Bits[7:4]
Enabling input sync mode
Disabling input sync mode
Configure data ready
Enable and/or select finite impulse response (FIR)
filter banks
75
147
3
µs
µs
µs
µs
FNCTIO_CTRL, Bits[3:0]
FILTR_BNK_0
101
FILTR_BNK_1
NULL_CNFG
Enable and/or select FIR filter banks
Configure autonull bias function
101
116
µs
µs
1 Monitor the data ready signal (see Table 143 for the FNCTIO_CTRL register configuration) for the return of regular pulsing to help minimize system wait times.
Rev. 0 | Page 5 of 38
ADIS16486
Data Sheet
Timing Diagrams
CS
tCHS
tCLS
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
DOUT
tDSOE
tDAV
tHD
tDR
tDSHI
MSB
DB14
tDSU
DB13
DB12
DB11
DB10
DB2
DB1
tDF
LSB
LSB
tDHD
DIN
R/W
A6
A5
A4
A3
A2
D2
D1
Figure 2. SPI Timing and Sequence
tSTALL
CS
SCLK
Figure 3. Stall Time and Data Rate
t2
t3
t1
DIO4
(SYNC CLOCK)
DATA
READY
OUTPUT
REGISTERS
DATA VALID
DATA VALID
Figure 4. Input Clock Timing Diagram, FNCTIO_CTRL, Bits[7:4] = 0xFD
Rev. 0 | Page 6 of 38
Data Sheet
ADIS16486
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
the PCB thermal design is required.
Parameter
Rating
Mechanical Shock Survivability
Any Axis, Unpowered
Any Axis, Powered
VDD to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Temperature Range
Calibration
2000 g
2000 g
−0.3 V to +3.6 V
−0.3 V to VDD + 0.2 V
−0.3 V to VDD + 0.2 V
θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJC is the junction
to case thermal resistance.
Table 5. Package Characteristics
Package Type
θJA
θJC
Device Weight
−40°C to +85°C
−40°C to +105°C
−65°C to +150°C
Operating
Storage1
ML-24-6
22.8°C/W
10.1°C/W
48 g
ESD CAUTION
1 Extended exposure to temperatures that are lower than −55°C or higher
than +105°C can adversely affect the accuracy of the factory calibration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. 0 | Page 7 of 38
ADIS16486
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16486
TOP VIEW
(Not to Scale)
24 22 20 18 16 14 12 10
8
7
6
5
4
3
2
1
PIN 23
PIN 1
23 21 19 17 15 13 11
9
NOTES
1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT
FOR THE MATING SOCKET CONNECTOR.
2. THE ACTUAL CONNECTOR PINS ARE NOT VISIBLE FROM
THE TOP VIEW.
3. MATING CONNECTOR: SAMTEC CLM-112-02 OR EQUIVALENT.
4. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
PIN 1 PIN 2
Figure 5. Pin Configuration
Figure 6. Axial Orientation (Top Side Facing Up)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
DIO3
DIO4
SCLK
DOUT
DIN
Type
Description
1
2
3
4
5
6
Input and output
Input and output
Input
Output
Input
Configurable Digital Input and Output 3.
Configurable Digital Input and Output 4.
SPI Serial Clock.
SPI Data Output. Clocks output on the SCLK falling edge.
SPI Data Input. Clocks input on the SCLK rising edge.
SPI Chip Select.
CS
Input
7
8
DIO1
RST
Input and output
Input
Configurable Digital Input and Output 1.
Reset.
9
DIO2
VDD
GND
DNC
VDDRTC
Input and output
Supply
Supply
Not applicable
Supply
Configurable Digital Input and Output 2.
Power Supply.
Power Ground.
Do Not Connect. Do not connect to these pins.
RTC Power Supply. The VDDRTC power supply must be connected even if
the RTC feature is not used.
10, 11, 12
13, 14, 15
16 to 22, 24
23
Rev. 0 | Page 8 of 38
Data Sheet
ADIS16486
TYPICAL PERFORMANCE CHARACTERISTICS
100
0.001
AVERAGE
AVERAGE
+1σ
+1σ
10
0.0001
–1σ
–1σ
1
0.01
0.00001
0.1
1
10
100
1000
10000
0.01
0.1
1
10
100
1000
10000
INTEGRATION PERIOD (Seconds)
INTEGRATION PERIOD (Seconds)
Figure 7. Gyroscope Allan Variance, 25°C
Figure 8. Accelerometer Allan Variance, 25°C
Rev. 0 | Page 9 of 38
ADIS16486
Data Sheet
THEORY OF OPERATION
sensor data, an RTC, error flags, alarm flags, and identification
data. The control registers include sample rate, filtering, input
and output, alarms, calibration, and diagnostic configuration
options. All communication between the ADIS16486 and an
external processor involves either reading or writing to one of
the user registers.
INTRODUCTION
The ADIS16486 is an autonomous sensor system that starts up
on its own when it has a valid power supply. After completing its
initialization process, the ADIS16486 begins sampling, processing,
and loading calibrated sensor data into the output registers, which
are accessible using the SPI port. The SPI port typically connects to
a compatible port on an embedded processor (see Figure 9). See
Table 7 for a list of the master processor pin names and functions.
The four SPI signals facilitate synchronous serial data
communication. The factory default configuration provides users
with a data ready signal on the DIO2 pin to trigger consistent
data acquisition (see Figure 28).
TRIAXIAL
GYROSCOPE
OUTPUT
REGISTERS
ADC
DSP
TRIAXIAL
ACCELEROMETER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
CONTROLLER
I/O LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
+3.3V
Figure 10. Basic Operation
VDD
The register structure uses a paged addressing scheme that
contains 13 pages, with each page containing 64 register locations.
Each register is 16 bits wide, and each byte has a unique address
within the memory map of that page. The SPI port accesses one
page at a time using the bit sequence in Figure 11. The user
selects the desired page by writing the corresponding page ID to
the PAGE_ID register. Read the PAGE_ID register to
determine which page is currently active. Table 9 displays the
PAGE_ID register contents for each page along with their basic
functions. The PAGE_ID register is located at Address 0x00 on
every page.
10
11
12
23
SYSTEM
PROCESSOR
SPI MASTER
ADIS16486
6
3
SS
CS
SCLK
DIN
SCLK
MOSI
5
4
9
MISO
IRQ
DOUT
DIO2
13
14
15
Figure 9. Electrical Connection Diagram
Table 7. Generic Master Processor Pin Names and Functions
Table 9. User Accessible Page Register Assignments
Page PAGE_ID Value Function
Mnemonic
Function
SS
Slave select
0
1
2
3
0x00
0x01
0x02
0x03
Output data, clock, identification
Reserved
Calibration
Control: sample rate, filtering, input
and output, alarms
SCLK
MOSI
MISO
IRQ
Serial clock
Master output, slave input
Master input, slave output
Interrupt request
4
5
0x04
0x05
Serial number
FIR Filter Bank A, Coefficient 0 to
Coefficient 59
FIR Filter Bank A, Coefficient 60 to
Coefficient 119
FIR Filter Bank B, Coefficient 0 to
Coefficient 59
FIR Filter Bank B, Coefficient 60 to
Coefficient 119
FIR Filter Bank C, Coefficient 0 to
Coefficient 59
FIR Filter Bank C, Coefficient 60 to
Coefficient 119
FIR Filter Bank D, Coefficient 0 to
Coefficient 59
Table 8 provides a list of settings that describe the SPI protocol of
the ADIS16486. The initialization routine of the master processor
typically establishes these settings using firmware commands to
write them into its serial control registers.
6
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
7
Table 8. Generic Master Processor SPI Settings
Processor Setting Description
8
Master
The ADIS16486 operates as a slave
Maximum serial clock rate
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence
SCLK ≤ 15 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
9
10
11
12
Shift register and data length
REGISTER STRUCTURE
The register structure and SPI port support a simple connection
between the ADIS16486 and an embedded processor platform.
The register structure contains both output data registers and
control registers. The output data registers include the latest
FIR Filter Bank D, Coefficient 60 to
Coefficient 119
Rev. 0 | Page 10 of 38
Data Sheet
ADIS16486
CS
SCLK
DIN
R/W A6
A5
R/W A6
A5
A4
A3
A2
A1
D9
A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
D15 D14 D13 D12 D11 D10
D15 D14 D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 11. SPI Communication Bit Sequence
boot stream. When in operation, the ADIS16486 continually
monitors critical portions of the SRAM using CRC verification and
reports the errors in SYS_E_FLAG, Bit 2.
SPI COMMUNICATION
Each SPI command and response is 16 bits long and uses the
digital coding shown in Figure 11.
MANUAL
FLASH
BACKUP
DEVICE CONFIGURATION
Each register contains 16 bits (two bytes). Bits[7:0] contain the
low byte and Bits[15:8] contain the high byte of each register.
Each byte has its own unique address in the user register map
(see Table 10). Update the contents of a register by writing to
its low byte first and its high byte second. There are three parts
to coding an SPI command (see Figure 11) to write a new byte of
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
SPI ACCESS
(NO SPI ACCESS)
START-UP
RESET
R
data to a register: the write bit ( /W = 1), the address of the byte,
Figure 13. SRAM and Flash Memory Diagram
[A6:A0], and the new data for that location, [DC7:DC0]. Figure 12
provides a coding example for writing 0xFEDC to the
XG_BIAS_LOW register (see Table 105), assuming the
PAGE_ID register already equals 0x0002.
READING SENSOR DATA
The 16-bit command code (see Figure 11) for a read request on
the SPI has three parts: the read bit ( /W = 0), the address of
R
the register, [A6:A0], and eight don’t care bits, [DC7:DC0]. A
read command produces the contents of the desired register on
the DOUT pin during the following 16-bit communication
cycle. Figure 14 provides an example that includes two register
reads in succession. This example starts with DIN = 0x1A00 to
request the contents of the Z_GYRO_OUT register and follows
with 0x1800 to request the contents of the Z_GYRO_LOW register
(assuming the PROD_ID register already equals 0x0000).
Figure 14 shows an example of a full duplex mode of operation
in which the ADIS16486 receives a new request while
CS
SCLK
DIN
0x90DC
0x91FE
Figure 12. SPI Sequence for Writing 0xFEDC to XG_BIAS_LOW
See Table 11 for a list of the processing times for each register
write. The processing time represents the time between the
completion of the write command and the time that the command
takes full effect on the operation of the ADIS16486.
transmitting the data response from the prior request.
Dual Memory Structure
NEXT
The ADIS16486 uses a dual memory structure (see Figure 13)
in which the static random access memory (SRAM) supports
real-time operation and the flash memory provides nonvolatile
storage. During the start-up process, the operating code,
calibration coefficients, and user register settings load from the
flash memory into the SRAM to support normal operation. The
manual flash update command, GLOB_CMD, Bit 3 (see
Table 141), provides a simple method for saving user register
values to the flash memory. Registers with the flash backup feature
are indicated by a yes in the flash backup column of Table 10.
This flash backup preserves these settings for automatic recall
during the next power-on or reset recovery process. The flash
memory has two independent banks that operate in a ping pong
manner, alternating with each manual flash update. During startup
or reset recovery, the ADIS16486 performs a cyclic redundancy
check (CRC) on the boot stream data in the flash memory. If an
error is found, the ADIS16486 sets the error flag, SYS_E_FLAG,
Bit 1, and restarts the boot process using the backup copy of the
DIN
0x1A00
0x1800
ADDRESS
DOUT
Z_GYRO_OUT
Z_GYRO_LOW
Figure 14. SPI Read Example
Figure 15 provides an example of the four SPI signals when reading
the PROD_ID register (see Table 91) in a repeating pattern. This
pattern can be helpful when troubleshooting the SPI setup and
communications because this pattern provides a clear expectation
for all signals (the PROD_ID register contents never change).
CS
SCLK
DIN
DIN = 0111 1110 0000 0000 = 0x7E00
DOUT HIGH-Z
HIGH-Z
DOUT = 0100 0000 0110 0110 = 0x4066 = 16,486 (PROD_ID)
Figure 15. SPI Read Example, Second 16-Bit Sequence
Rev. 0 | Page 11 of 38
ADIS16486
Data Sheet
USER REGISTER MEMORY MAP
Table 10. User Register Memory Map (N/A Means Not Applicable)
Name
R/W Flash Backup Page ID Address
Default Register Description
PAGE_ID
Reserved
DATA_CNT
SENS_PWR
SYS_E_FLAG
DIAG_STS
ALM_STS
R/W No
N/A N/A
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x20, 0x21
0x22, 0x23
0x24, 0x25
0x26, 0x27
0x0000
N/A
N/A
Page identifier
Reserved
Data and sample counter
Internal power supply monitor
Output, status and error flag indicators
Output, self test error flags
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
N/A
0x0000
0x0000
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Output, alarm error flags
Output, internal temperature
TEMP_OUT
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
Reserved
X_DELTANG_LOW
X_DELTANG_OUT
Y_DELTANG_LOW
Y_DELTANG_OUT
Z_DELTANG_LOW
Z_DELTANG_OUT
X_DELTVEL_LOW
X_DELTVEL_OUT
Y_DELTVEL_LOW
Y_DELTVEL_OUT
Z_DELTVEL_LOW
Z_DELTVEL_OUT
Reserved
Output, x-axis gyroscope, low word
Output, x-axis gyroscope, high word
Output, y-axis gyroscope, low word
Output, y-axis gyroscope, high word
Output, z-axis gyroscope, low word
Output, z-axis gyroscope, high word
Output, x-axis accelerometer, low word
Output, x-axis accelerometer, high word
Output, y-axis accelerometer, low word
Output, y-axis accelerometer, high word
Output, z-axis accelerometer, low word
Output, z-axis accelerometer, high word
Reserved
Output, x-axis delta angle, low word
Output, x-axis delta angle, high word
Output, y-axis delta angle, low word
Output, y-axis delta angle, high word
Output, z-axis delta angle, low word
Output, z-axis delta angle, high word
Output, x-axis delta velocity, low word
Output, x-axis delta velocity, high word
Output, y-axis delta velocity, low word
Output, y-axis delta velocity, high word
Output, z-axis delta velocity, low word
Output, z-axis delta velocity, high word
Reserved
N/A N/A
0x28 to 0x3F N/A
R
R
R
R
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
No
No
No
0x40, 0x41
0x42, 0x43
0x44, 0x45
0x46, 0x47
0x48, 0x49
0x4A, 0x4B
0x4C, 0x4D
0x4E, 0x4F
0x50, 0x51
0x52, 0x53
0x54, 0x55
0x56, 0x57
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A N/A
R/W No
R/W No
R/W No
0x58 to 0x77 N/A
TIME_MS_OUT
TIME_DH_OUT
TIME_YM_OUT
PROD_ID
Reserved
PAGE_ID
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 0x7F
N/A
N/A
N/A
0x4066
RTC: minutes and seconds
RTC: day and hour
RTC: year and month
Output, product identification (16,486)
Reserved
R
Yes
N/A N/A
R/W No
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
0x00 to 0x7F N/A
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x0000
N/A
Page identifier
Reserved
Reserved
X_GYRO_SCALE
Y_GYRO_SCALE
Z_GYRO_SCALE
X_ACCL_SCALE
Y_ACCL_SCALE
Z_ACCL_SCALE
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Calibration, gyroscope scale, x-axis
Calibration, gyroscope scale, y-axis
Calibration, gyroscope scale, z-axis
Calibration, accelerometer scale, x-axis
Calibration, accelerometer scale, y-axis
Calibration, accelerometer scale, z-axis
Rev. 0 | Page 12 of 38
Data Sheet
ADIS16486
Name
R/W Flash Backup Page ID Address
Default Register Description
XG_BIAS_LOW
XG_BIAS_HIGH
YG_BIAS_LOW
YG_BIAS_HIGH
ZG_BIAS_LOW
ZG_BIAS_HIGH
XA_BIAS_LOW
XA_BIAS_HIGH
YA_BIAS_LOW
YA_BIAS_HIGH
ZA_BIAS_LOW
ZA_BIAS_HIGH
Reserved
USER_SCR_1
USER_SCR_2
USER_SCR_3
USER_SCR_4
FLSHCNT_LOW
FLSHCNT_HIGH
PAGE_ID
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W No
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x10, 0x11
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x20, 0x21
0x22, 0x23
0x24, 0x25
0x26, 0x27
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Calibration, offset, gyroscope bias, x-axis, low word
Calibration, offset, gyroscope bias, x-axis, high word
Calibration, offset, gyroscope bias, y-axis, low word
Calibration, offset, gyroscope bias, y-axis, high word
Calibration, offset, gyroscope bias, z-axis, low word
Calibration, offset, gyroscope bias, z-axis, high word
Calibration, offset, accelerometer bias, x-axis, low word
Calibration, offset, accelerometer bias, x-axis, high word
Calibration, offset, accelerometer bias, y-axis, low word
Calibration, offset, accelerometer bias, y-axis, high word
Calibration, offset, accelerometer bias, z-axis, low word
Calibration, offset, accelerometer bias, z-axis, high word
Reserved
User Scratch Register 1
User Scratch Register 2
User Scratch Register 3
User Scratch Register 4
Diagnostic, flash memory endurance counter, low word
Diagnostic, flash memory endurance counter, high word
Page identifier
Control, global commands
Reserved
0x28 to 0x73 0x0000
0x74, 0x75
0x76, 0x77
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 07F
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x0000
0x0000
0x0000
0x0000
N/A
N/A
0x0000
0x0000
N/A
GLOB_CMD
Reserved
FNCTIO_CTRL
GPIO_CTRL
CONFIG
DEC_RATE
NULL_CNFG
SLP_CNT
W
No
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W Yes
N/A N/A
R/W Yes
R/W Yes
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
N/A N/A
0x000D Auxiliary input and output line configuration
0x00X01 General-purpose input and output control
0x00C0
0x0000
0x070A Control, continuous bias estimation
N/A
Control, clock, miscellaneous configuration
Control, output, decimation filter
Control, power management
Reserved
FIR filter control
FIR filter control
Reserved
Alarm configuration
Alarm configuration
Reserved
Alarm configuration, x-axis gyroscope alarm
Alarm configuration, y-axis gyroscope alarm
Alarm configuration, z-axis gyroscope alarm
Alarm configuration, x-axis accelerometer alarm
Alarm configuration, y-axis accelerometer alarm
Alarm configuration, z-axis accelerometer alarm
Reserved
Firmware revision
Firmware revision day and month
Firmware revision year
Boot revision number
Page identifier
Reserved
Signature CRC, calibration values, low word
Signature CRC, calibration values, high word
Derived CRC, calibration values, low word
Derived CRC, calibration values, high word
Signature CRC, program code, low word
Reserved
0x12 to 0x15 N/A
0x16, 0x17
0x18, 0x19
0x1A to 0x1F N/A
0x20, 0x21
0x22, 0x23
FILTR_BNK_0
FILTR_BNK_1
Reserved
ALM_CNFG_0
ALM_CNFG_1
Reserved
XG_ALM_MAGN
YG_ALM_MAGN
ZG_ALM_MAGN
XA_ALM_MAGN
YA_ALM_MAGN
ZA_ALM_MAGN
Reserved
FIRM_REV
FIRM_DM
FIRM_Y
BOOT_REV
PAGE_ID
Reserved
0x0000
0x0000
0x0000
0x0000
0x24 to 0x27 N/A
0x28, 0x29
0x2A, 0x2B
0x2C, 0x2D
0x2E, 0x2F
0x30, 0x31
0x32, 0x33
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x34 to 0x77 N/A
R
R
R
R
Yes
Yes
Yes
Yes
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 0x7F
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
N/A
N/A
N/A
N/A
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
R/W No
N/A N/A
CAL_SIGTR_LWR
CAL_SIGTR_UPR
CAL_DRVTN_LWR
CAL_DRVTN_UPR
CODE_SIGTR_LWR
R
R
R
R
R
Yes
Yes
No
No
Yes
Rev. 0 | Page 13 of 38
ADIS16486
Data Sheet
Name
R/W Flash Backup Page ID Address
Default Register Description
CODE_SIGTR_UPR
CODE_DRVTN_LWR
CODE_DRVTN_UPR
Reserved
SERIAL_NUM
Reserved
PAGE_ID
Reserved
FIR_COEF_Axxx
PAGE_ID
Reserved
FIR_COEF_Axxx
PAGE_ID
Reserved
FIR_COEF_Bxxx
PAGE_ID
Reserved
FIR_COEF_Bxxx
PAGE_ID
Reserved
FIR_COEF_Cxxx
PAGE_ID
Reserved
R
R
R
Yes
No
No
0x04
0x04
0x04
0x04
0x04
0x04
0x05
0x05
0x05
0x06
0x06
0x06
0x07
0x07
0x07
0x08
0x08
0x08
0x09
0x09
0x09
0x0A
0x0A
0x0A
0x0B
0x0B
0x0B
0x0C
0x0C
0x0C
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x1C to 0x1F N/A
0x20, 0x21 N/A
0x22 to 0x7F N/A
0x00, 0x01
0x02 to 0x07 N/A
0x08 to 0x7F N/A
N/A
N/A
N/A
Signature CRC, program code, high word
Derived CRC, program code, low word
Derived CRC, program code, high word
Reserved
Lot specific serial number
Reserved
Page identifier
Reserved
FIR Filter Bank A, Coefficient 0 through Coefficient 59
Page identifier
Reserved
FIR Filter Bank A, Coefficient 60 through Coefficient 119
Page identifier
Reserved
FIR Filter Bank B, Coefficient 0 through Coefficient 59
Page identifier
Reserved
FIR Filter Bank B, Coefficient 60 through Coefficient 119
Page identifier
Reserved
FIR Filter Bank C, Coefficient 0 through Coefficient 59
Page identifier
Reserved
FIR Filter Bank C, Coefficient 60 through Coefficient 119
Page identifier
Reserved
N/A N/A
Yes
R
N/A N/A
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
0x0000
0x00
0x0000
0x02 to 0x07 N/A
0x08 to 0x7F N/A
0x00
0x02 to 0x07 N/A
0x02 to 0x7E N/A
0x00
0x02 to 0x07 N/A
0x08 to 0x7F N/A
0x00
0x02 to 0x07 N/A
0x08 to 0x7F N/A
0x00
0x02 to 0x07 N/A
0x08 to 0x7F N/A
0x00
0x02 to 0x07 N/A
0x08 to 0x7F N/A
0x00
0x0000
0x0000
0x0000
0x0000
FIR_COEF_Cxxx
PAGE_ID
Reserved
FIR_COEF_Dxxx
PAGE_ID
Reserved
0x0000
FIR Filter Bank D, Coefficient 0 through Coefficient 59
Page identifier
Reserved
0x0000
0x02 to 0x07 N/A
0x08 to 0x7F N/A
FIR_COEF_Dxxx
FIR Filter Bank D, Coefficient 60 through Coefficient 119
1 GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx pins and do not have a default setting.
Table 11. Processing Times for Register Writes
Registers
Processing Time (µs)
821
TIME_MS_OUT, TIME_DH_OUT, TIME_YM_OUT
X_GYRO_SCALE, Y_GYRO_SCALE, Z_GYRO_SCALE, X_ACCL_SCALE, Y_ACCL_SCALE, Z_ACCL_SCALE
XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_HIGH
XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW, YA_BIAS_HIGH, ZA_BIAS_LOW, ZA_BIAS_HIGH
XG_ALM_MAGN, YG_ALM_MAGN, ZG_ALM_MAGN, XA_ALM_MAGN, YA_ALM_MAGN, ZA_ALM_MAGN
USER_SCR_1, USER_SCR_2, USER_SCR_3, USER_SCR_4
GLOB_CMD
406.5
406.5
406.5
406.5
0
822
GPIO_CTRL, DEC_RATE, CONFIG, ALM_CNFG_0, ALM_CNFG_1, SLP_CNT
82
FNCTIO_CTRL
NULL_CNFG
FILTR_BNK_0, FILTR_BNK_1
FIR_COEF_xxxx
147
116
101
03
1 The processing time for the TIME_xx_xxxx registers does not include the time it takes for these values to synchronize (≤1 sec).
2 The processing time for the GLOB_CMD register does not include the time it takes to execute each command in this register.
3 The processing time for the FIR_COEF_xxxx registers does not include the time it takes for the FIR filters to settle.
Rev. 0 | Page 14 of 38
Data Sheet
ADIS16486
USER REGISTER DEFINITIONS
Page Number (PAGE_ID)
Status and Error Flag Indicators (SYS_E_FLAG)
The contents in the PAGE_ID register (see Table 12 and Table 13)
contain the current page setting and provide a control for selecting
another page for SPI access. For example, set DIN = 0x8002 to
select Page 2 for SPI-based user access. See Table 10 for the page
assignments associated with each user accessible register.
The SYS_E_FLAG register (see Table 19 and Table 20) provides
various error flags. Reading this register causes its bits to return
to 0, except for Bit 7. If an error condition persists, the flag (bit)
automatically returns an alarm value of 1.
Table 19. SYS_E_FLAG Register Definition
Table 12. PAGE_ID Register Definition
Page ID
Addresses
Default
Access
Flash Backup
Page ID
Addresses
Default
Access
Flash Backup
0x00
0x08, 0x09
0x0000
R
No
0x00
0x00, 0x01
0x0000
R/W
No
Table 20. SYS_E_FLAG Bit Definitions
Table 13. PAGE_ID Bit Definition
Bits
Description (Default = 0x0000)
Bits
Description (Default = 0x0000)
15
Watch dog timer flag. A 1 indicates that the ADIS16486
automatically resets itself to clear an issue.
[15:0]
Page number, binary numerical format
[14:9] Not used.
Data and Sample Counter (DATA_CNT)
8
Internal power supply monitor. A 1 indicates an issue
The DATA_CNT register (see Table 14 and Table 15) is a
continuous, real-time, sample counter. The counter starts at
0x0000, increments every time that the sensor output data
registers update, and wraps around from 0xFFFF to 0x0000.
with the power supply for the sensors. Initiate a reset to
recover. Replace the ADIS16486 if this error persists.
7
Processing overrun. A 1 indicates the occurrence of a
processing overrun. Initiate a reset to recover. Replace
the ADIS16486 if this error persists. One potential source
of this error is not providing power to the VDDRTC pin.
Table 14. DATA_CNT Register Definition
Page ID Addresses Default
Access Flash Backup
6
5
Flash memory update failure. A 1 indicates that the
most recent flash memory update (GLOB_CMD, Bit 3, see
Table 141) failed. Repeat the test and replace the
ADIS16486 if this error persists.
0x00 0x04, 0x05 Not applicable
R
No
Table 15. DATA_CNT Bit Definition
Bits Description (No Default)
[15:0] Data counter, binary format
Sensor failure. A 1 indicates the failure of at least one of
the self test processes: continuous or on demand. Run
the ODST (GLOB_CMD, Bit 1, see Table 141) when the
unit is in not in motion. Replace the ADIS16486 if the
error persists.
Internal Power Supply Monitor (SENS_PWR)
The SENS_PWR register (see Table 16 and Table 17) is a read
only register that provides a measurement of the internal power
supply. Table 18 provides some examples of the data format.
4
3
Overrange. A 1 indicates that the digital magnitude of at
least one sensor has reached 99% of its maximum value.
Initiate a reset to recover and replace the ADIS16486 if
this error persists.
Table 16. SENS_PWR Register Definition
Page ID Addresses Default
SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer multiple
of 16. Repeat the previous communication sequence to
recover. Persistence in this error can indicate a weakness in
the SPI service from the master processor.
Access Flash Backup
0x00 0x06, 0x07 Not applicable
R
No
Table 17. SENS_PWR Bit Definition
Bits Description (No Default)
2
1
SRAM error condition. A 1 indicates a failure in the CRC
(period = 20 ms) between the SRAM and flash memory.
Initiate a reset to recover. Replace the ADIS16486 if this
error persists.
[15:0] Relative power supply measurement, twos complement
(see Equation 1)
2.5 V
Supply
Boot memory failure. A 1 indicates that the CRC on the
primary flash memory bank did not match the reference
CRC value, and that the device automatically rebooted
using the backup memory bank in flash. Replace the
ADIS16486 if this error persists.
SENS _ PWRLSB
=
×216 − 215
(1)
Table 18. SENS_PWR Data Format Examples
Supply Level (V) Decimal Hex Binary
0x029D 0000 0010 1001 1101
0
Alarm status flag. A 1 indicates that one of the user-
programmable alarms is active. See the ALM_STS
register for an indication of which alarm is active.
4.90
4.95
5
+669
+331
0
0x014B
0x0000
0xFEBC
0000 0001 0100 1011
0000 0000 0000 0000
1111 1110 1011 1100
5.05
5.10
−324
−643
0xFD7D 1111 1101 0111 1101
Rev. 0 | Page 15 of 38
ADIS16486
Data Sheet
Table 25. TEMP_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x0E, 0x0F Not applicable No
Self Test Error Flags (DIAG_STS)
SYS_E_FLAG, Bit 5 (see Table 20) contains the pass and fail result
(0 = pass) for both CST and ODST operations, whereas the
DIAG_STS register (see Table 21 and Table 22) contains pass
and fail flags (0 = pass) for each inertial sensor. Reading the
DIAG_STS register clears all bits to 0. The bits in the DIAG_STS
register return to 1 if the error conditions persist. The CST
leverages a proprietary method for detecting abnormal behavior
during normal operation, whereas the ODST artificially forces
each inertial sensor to simulate their response to actual motion.
R
Table 26. TEMP_OUT Bit Definition
Bits
Description (No Default)
[15:0]
Temperature data, twos complement, 0.00565°C per LSB,
25°C = 0x0000
Table 27. TEMP_OUT Data Format Examples
Temperature (°C) Decimal Hex Binary
+85
+10,619
+2
+1
0
−1
−2
−11,504
0x297B
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0010 1001 0111 1011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
Table 21. DIAG_STS Register Definition
+25 + 0.0113
+25 + 0.00565
+25
+25 − 0.00565
+25 − 0.0113
−40
Page ID
Addresses
Default
Access
Flash Backup
0x00
0x0A, 0x0B
0x0000
R
No
Table 22. DIAG_STS Bit Definitions
Bits Description (Default = 0x0000)
[15:6] Not used
0xD310 1101 0011 0001 0000
5
4
3
2
1
0
ODST failure, z-axis accelerometer (1 = failure)
ODST failure, y-axis accelerometer (1 = failure)
ODST failure, x-axis accelerometer (1 = failure)
ODST failure, z-axis gyroscope (1 = failure)
ODST failure, y-axis gyroscope (1 = failure)
GYROSCOPE DATA
The gyroscopes in the ADIS16486 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 16
shows the orientation of each gyroscope axis, as well as the
direction of rotation that produces a positive response in each
of their measurements.
ODST failure, x-axis gyroscope (1 = failure) or
continuous self test (CST) failure, all gyroscope and
accelerometers (1 = failure)
Z-AXIS
Alarm Error Flags (ALM_STS)
ω
Z
The ALM_STS register (see Table 23 and Table 24) contains the
error flags for the alarm settings in the ALM_CNFG_0 (see
Table 159) and ALM_CNFG_1 (see Table 161) registers. Reading
the ALM_STS register clears all bits to 0. If the alarm condition
is persistent, the corresponding bit returns to 1 in the next
sample cycle.
X-AXIS
Y-AXIS
ω
X
ω
Y
PIN 23
PIN 1
Table 23. ALM_STS Register Definition
Figure 16. Gyroscope Axis and Polarity Assignments
Page ID
Addresses
Default
Access
Flash Backup
Each gyroscope has two output data registers. Figure 17 shows
how the X_GYRO_LOW and X_GYRO_OUT registers
combine to support a 32-bit, twos complement data format for
the x-axis gyroscope measurements. This format also applies to
the y- and x-axes.
0x00
0x0C, 0x0D
0x0000
R
No
Table 24. ALM_STS Bit Definitions
Bits
Description (Default = 0x0000)
[15:6]
Not used
5
4
3
2
1
0
Z-axis accelerometer alarm flag (1 = alarm is active)
Y-axis accelerometer alarm flag (1 = alarm is active)
X-axis accelerometer alarm flag (1 = alarm is active)
Z-axis gyroscope alarm flag (1 = alarm is active)
Y-axis gyroscope alarm flag (1 = alarm is active)
X-axis gyroscope alarm flag (1 = alarm is active)
X_GYRO_OUT
X_GYRO_LOW
15
0 15
0
X-AXIS GYROSCOPE DATA
Figure 17. Gyroscope Output Data Structure
X-Axis Gyroscope (X_GYRO_LOW, X_GYRO_OUT)
The X_GYRO_LOW (see Table 28 and Table 29) and X_GYRO
_OUT (see Table 30 and Table 31) registers contain the gyroscope
data for the x-axis.
Internal Temperature (TEMP_OUT)
The TEMP_OUT register (see Table 25 and Table 26) provides
a coarse measurement of the temperature inside of the ADIS16486.
This data is most useful for monitoring relative changes in the
thermal environment.
Table 28. X_GYRO_LOW Register Definition
Page ID Addresses Default
Access Flash Backup
0x00 0x10, 0x11 Not applicable
R
No
Rev. 0 | Page 16 of 38
Data Sheet
ADIS16486
Table 29. X_GYRO_LOW Bit Definition
Gyroscope Resolution
Bits
Description (No Default)
Table 40 and Table 41 offer various numerical examples that
demonstrate the format of the angular rate (gyroscopes) data in
both 16-bit and 32-bit formats.
[15:0]
X-axis gyroscope data, low word
Table 30. X_GYRO_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x12, 0x13 Not applicable No
Table 40. 16-Bit Gyroscope Data Format Examples
Rotation Rate
R
(°/sec)
Decimal
+22,500
+2
+1
0
−1
−2
−22,500
Hex
Binary
Table 31. X_GYRO_OUT Bit Definition
+450
0x57E4
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0101 0111 1110 0100
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
Bits
Description (No Default)
+0.04
+0.02
0
−0.02
−0.04
−450
[15:0]
X-axis gyroscope data, high word, twos complement,
450°/sec range, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
Y-Axis Gyroscope (Y_GYRO_LOW, Y_GYRO_OUT)
The Y_GYRO_LOW (see Table 32 and Table 33) and Y_GYRO
_OUT (see Table 34 and Table 35) registers contain the gyroscope
data for the y-axis.
0xA81C 1010 1000 0001 1100
Table 41. 32-Bit Gyroscope Data Format Examples
Rotation Rate (°/sec)
Decimal
Hex
Table 32. Y_GYRO_LOW Register Definition
+450
+1,474,560,000 0x57E40000
Page ID Addresses Default
Access Flash Backup
+0.02/215
+0.02/216
0
+2
+1
0
−1
−2
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x00 0x14, 0x15 Not applicable
R
No
Table 33. Y_GYRO_LOW Bit Definition
−0.02/216
−0.02/215
−450
Bits
Description (No Default)
[15:0]
Y-axis gyroscope data, low word
−1,474,560,000 0x73600000
Table 34. Y_GYRO_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x16, 0x17 Not applicable No
ACCELERATION DATA
R
The accelerometers in the ADIS16486 measure both dynamic
and static (response to gravity) acceleration along three orthogonal
axes (x, y, and z). Figure 18 shows the orientation of each
accelerometer axis, along with the direction of acceleration that
produces a positive response in each of their measurements.
Z-AXIS
Table 35. Y_GYRO_OUT Bit Definition
Bits
Description (No Default)
[15:0]
Y-axis gyroscope data, high word, twos complement,
450°/sec range, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
Z-Axis Gyroscope (Z_GYRO_LOW, Z_GYRO_OUT)
aZ
The Z_GYRO_LOW (see Table 36 and Table 37) and Z_GYRO
_OUT (see Table 38 and Table 39) registers contain the gyroscope
data for the z-axis.
X-AXIS
Table 36. Z_GYRO_LOW Register Definition
Y-AXIS
Page ID Addresses Default
Access Flash Backup
aX
aY
0x00 0x18, 0x19 Not applicable
R
No
PIN 23
PIN 1
Table 37. Z_GYRO_LOW Bit Definition
Figure 18. Accelerometer Axis and Polarity Assignments
Bits
Description (No Default)
[15:0]
Z-axis gyroscope data, low word, additional resolution
bits
Each accelerometer has two output data registers. Figure 19
shows how the X_ACCL_LOW and X_ACCL_OUT registers
combine to support a 32-bit, twos complement data format for
the x-axis accelerometer measurements. This format also applies
to the y- and x-axes.
Table 38. Z_GYRO_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x1A, 0x1B Not applicable No
R
X_ACCL_OUT
X_ACCL_LOW
Table 39. Z_GYRO_OUT Bit Definition
15
0 15
0
Bits
Description (No Default)
X-AXIS ACCELEROMETER DATA
[15:0]
Z-axis gyroscope data, high word, twos complement,
450°/sec range, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
Figure 19. Accelerometer Output Data Structure
Rev. 0 | Page 17 of 38
ADIS16486
Data Sheet
Table 52. Z_ACCL_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x26, 0x27 Not applicable No
X-Axis Accelerometer (X_ACCL_LOW, X_ACCL_OUT)
The X_ACCL_LOW (see Table 42 and Table 43) and X_ACCL
_OUT (see Table 44 and Table 45) registers contain the
accelerometer data for the x-axis.
R
Table 53. Z_ACCL_OUT Bit Definition
Bits
Description (No Default)
Table 42. X_ACCL_LOW Register Definition
[15:0]
Z-axis accelerometer data, high word, twos complement,
18 g range, 0 g = 0x0000, 1 LSB = 0.8 mg
Page ID Addresses Default
Access Flash Backup
0x00 0x1C, 0x1D Not applicable
R
No
Accelerometer Resolution
Table 43. X_ACCL_LOW Bit Definition
Bits Description (No Default)
Table 54 and Table 55 offer various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
[15:0] X-axis accelerometer data, low word
Table 44. X_ACCL_OUT Register Definition
Table 54. 16-Bit Accelerometer Data Format Examples
Page ID Addresses Default
Access Flash Backup
Acceleration
Decimal
+20,000
+2
Hex
Binary
0x00 0x1E, 0x1F Not applicable
R
No
+18 g
0x4E20
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xB1E0
0100 1110 0010 0000
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1011 0001 1110 0000
+1.6 mg
+0.8 mg
0 mg
Table 45. X_ACCL_OUT Bit Definition
+1
0
Bits
Description (No Default)
[15:0]
X-axis accelerometer data, high word, twos complement,
−0.8 mg
−1.6 mg
−18 g
−1
−2
−20,000
18 g range, 0 g = 0x0000, 1 LSB = 0.8 mg
Y-Axis Accelerometer (Y_ACCL_LOW, Y_ACCL_OUT)
The Y_ACCL_LOW (see Table 46 and Table 47) and Y_ACCL
_OUT (see Table 48 and Table 49) registers contain the
accelerometer data for the y-axis.
Table 55. 32-Bit Accelerometer Data Format Examples
Acceleration (g)
Decimal
Hex
+18
+1,310,720,000
+2
+1
0
−1
−2
0x4E200000
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0xB1E00000
Table 46. Y_ACCL_LOW Register Definition
+0.0008/215
+0.0008/216
0
Page ID Addresses Default
Access Flash Backup
0x00 0x20, 0x21 Not applicable
R
No
−0.0008/216
−0.0008/215
−18
Table 47. Y_ACCL_LOW Bit Definition
Bits Description (No Default)
−1,310,720,000
[15:0] Y-axis accelerometer data, low word
DELTA ANGLES
Table 48. Y_ACCL_OUT Register Definition
In addition to the angular rate of rotation (gyroscope)
measurements around each axis (x, y, and z), the ADIS16486
provides delta angle measurements that represent a computation
of angular displacement between each sample update.
Z-AXIS
Page ID Addresses Default
Access Flash Backup
0x00 0x22, 0x23 Not applicable
R
No
Table 49. Y_ACCL_OUT Bit Definition
Bits
Description (No Default)
[15:0]
Y-axis accelerometer data, twos complement, 18 g
range, 0 g = 0x0000, 1 LSB = 0.8 mg
ΔΘ
Z
Z-Axis Accelerometer (Z_ACCL_LOW, Z_ACCL_OUT)
The Z_ACCL_LOW (see Table 50 and Table 51) and Z_ACCL
_OUT (see Table 52 and Table 53) registers contain the
accelerometer data for the z-axis.
X-AXIS
Y-AXIS
ΔΘ
X
Table 50. Z_ACCL_LOW Register Definition
ΔΘ
Y
PIN 23
Page ID Addresses Default
Access Flash Backup
PIN 1
0x00 0x24, 0x25 Not applicable
R
No
Figure 20. Delta Angle Axis and Polarity Assignments
Table 51. Z_ACCL_LOW Bit Definition
Bits Description (No Default)
[15:0] Z-axis accelerometer data, low word
Rev. 0 | Page 18 of 38
Data Sheet
ADIS16486
The delta angle outputs represent an integration of the gyroscope
measurements and use the following formula for all three axes (the
x-axis is shown as follows):
Table 60. Y_DELTANG_LOW Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x44, 0x45 Not applicable No
R
D − 1
1
2 fS
Table 61. Y_DELTANG_LOW Bit Definition
∆θx,nD
=
×
ω
+ωx,nD +d −1
x,nD +d
∑
(
)
d =0
Bits
Description (No Default)
[15:0]
Y-axis delta angle data, low word
where:
D is the decimation rate = DEC_RATE + 1 (see Table 149).
fs is the sample rate.
d is the incremental variable in the summation formula.
ωx is the x-axis rate of rotation (gyroscope).
n is the sample time, prior to the decimation filter.
Table 62. Y_DELTANG_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x46, 0x47 Not applicable No
R
Table 63. Y_DELTANG_OUT Bit Definition
Bits Description (No Default)
When using the internal sample clock, fS is equal to 2460 SPS.
When using the external clock option, fS is equal to the frequency
of the external clock. Ensure that the external clock frequency is
at least 700 Hz to prevent overflow in the delta angle data
registers at high rotation rates.
[15:0] Y-axis delta angle data, twos complement, 720° range,
0° = 0x0000, 1 LSB = 720°/215 = ~0.022°
Z-Axis Delta Angle (Z_DELTANG_LOW, Z_DELTANG_OUT)
The Z_DELTANG_LOW (see Table 64 and Table 65) and
Z_DELTANG_OUT (see Table 66 and Table 67) registers
contain the delta angle data for the z-axis.
Each axis of the delta angle measurements has two output data
registers. Figure 21 shows how the X_DELTANG_LOW and
X_DELTANG_OUT registers combine to support a 32-bit, twos
complement data format for the x-axis delta angle measurements.
This format also applies to the y- and x-axes.
Table 64. Z_DELTANG_LOW Register Definition
Page ID Addresses Default
Access Flash Backup
0x00 0x48, 0x49 Not applicable
R
No
X_DELTANG_OUT
X_DELTANG_LOW
15
0 15
0
Table 65. Z_DELTANG_LOW Bit Definition
X-AXIS DELTA ANGLE DATA
Bits
Description (No Default)
[15:0]
Z-axis delta angle data, low word
Figure 21. Delta Angle Output Data Structure
X-Axis Delta Angle (X_DELTANG_LOW, X_DELTANG_OUT)
Table 66. Z_DELTANG_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x4A, 0x4B Not applicable No
The X_DELTANG_LOW (see Table 56 and Table 57) and
X_DELTANG_OUT (see Table 58 and Table 59) registers
contain the delta angle data for the x-axis.
R
Table 67. Z_DELTANG_OUT Bit Definition
Bits Description (No Default)
Table 56. X_DELTANG_LOW Register Definition
Page ID Addresses Default
Access Flash Backup
[15:0] Z-axis delta angle data, twos complement, 720° range,
0° = 0x0000, 1 LSB = 720°/215 = ~0.022°
0x00 0x40, 0x41 Not applicable
R
No
Delta Angle Resolution
Table 57. X_DELTANG_LOW Bit Definition
Table 68 and Table 69 offer various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Bits
Description (No Default)
[15:0]
X-axis delta angle data, low word
Table 58. X_DELTANG_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x42, 0x43 Not applicable No
Table 68. 16-Bit Delta Angle Data Format Examples
Delta Angle (°)
Decimal Hex
Binary
R
+720 × (215 − 1)/215 +32,767
0x7FFF 0111 1111 1110 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+720/214
+720/215
0
+2
+1
0
Table 59. X_DELTANG_OUT Bit Definition
Bits Description (No Default)
[15:0] X-axis delta angle data, twos complement, 720° range,
0° = 0x0000, 1 LSB = 720°/215 = ~0.022°
−720/215
−720/214
−720
−1
−2
−32,768
Y-Axis Delta Angle (Y_DELTANG_LOW, Y_DELTANG_OUT)
The Y_DELTANG_LOW (see Table 60 and Table 61) and
Y_DELTANG_OUT (see Table 62 and Table 63) registers
contain the delta angle data for the y-axis.
Rev. 0 | Page 19 of 38
ADIS16486
Data Sheet
X-Axis Delta Velocity (X_DELTVEL_LOW, X_DELTVEL_OUT)
Table 69. 32-Bit Delta Angle Data Format Examples
The X_DELTVEL_LOW (see Table 70 and Table 71) and
X_DELTVEL_OUT (see Table 72 and Table 73) registers
contain the delta velocity data for the x-axis.
Delta Angle (°)
+720 × (223 − 1)/223
+720/222
+720/223
0
−720/223
−720/223
−720
Decimal
Hex
+2,147,483,647 0x7FFFFFFF
+2
+1
0
−1
−2
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
Table 70. X_DELTVEL_LOW Register Definition
Page ID Addresses Default
Access Flash Backup
0x00 0x4C, 0x4D Not applicable
R
No
Table 71. X_DELTVEL_LOW Bit Definition
−2,147,483,648 0x80000000
Bits
Description (No Default)
DELTA VELOCITY
[15:0]
X-axis delta velocity data, low word
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16486 provides delta velocity
measurements that represent a computation of linear velocity
change between each sample update.
Table 72. X_DELTVEL_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x4E, 0x4F Not applicable No
R
Z-AXIS
Table 73. X_DELTVEL_OUT Bit Definition
Bits
Description (No Default)
ΔV
Z
[15:0]
X-axis delta velocity data, high word, twos complement,
200 m/sec range, 0 m/sec = 0x0000, 1 LSB = 200 m/sec ÷
215 = ~6.104 mm/sec
X-AXIS
Y-AXIS
Y-Axis Delta Velocity (Y_DELTVEL_LOW, Y_DELTVEL_OUT)
ΔV
X
The Y_DELTVEL_LOW (see Table 74 and Table 75) and
Y_DELTVEL_OUT (see Table 76 and Table 77) registers
contain the delta velocity data for the y-axis.
ΔV
Y
PIN 23
PIN 1
Figure 22. Delta Velocity Axis and Polarity Assignments
Table 74. Y_DELTVEL_LOW Register Definition
The delta velocity outputs represent an integration of the
Page ID Addresses Default
Access Flash Backup
acceleration measurements and use the following formula for
all three axes (the x-axis is shown as follows):
0x00 0x50, 0x51 Not applicable
R
No
Table 75. Y_DELTVEL_LOW Bit Definition
D−1
1
2 fS
Bits
Description (No Default)
∆Vx,nD
=
×
ax,nD+d +ax,nD +d −1
∑
(
)
d =0
[15:0]
Y-axis delta velocity data, low word
where:
Table 76. Y_DELTVEL_OUT Register Definition
Page ID Addresses Default Access Flash Backup
0x00 0x52, 0x53 Not applicable No
D is the decimation rate = DEC_RATE + 1 (see Table 149).
fs is the sample rate.
d is the incremental variable in the summation formula.
ax is the x-axis acceleration (accelerometer).
n is the sample time, prior to the decimation filter.
R
Table 77. Y_DELTVEL_OUT Bit Definition
Bits Description (No Default)
When using the internal sample clock, fS is equal to 2460 SPS.
When using the external clock option, fS is equal to the frequency
of the external clock. Ensure that the frequency of the external
clock is at least 700 Hz to prevent overflow in the delta velocity
data registers at high acceleration levels.
[15:0] Y-axis delta velocity data, high word, twos complement,
200 m/sec range, 0 m/sec = 0x0000, 1 LSB = 200 m/sec ÷
215 = ~6.104 mm/sec
Z-Axis Delta Velocity (Z_DELTVEL_LOW, Z_DELTVEL_OUT)
The Z_DELTVEL_LOW (see Table 78 and Table 79) and
Z_DELTVEL_OUT (see Table 80 and Table 81) registers
contain the delta velocity data for the z-axis.
Each axis of the delta velocity measurements has two output
data registers. Figure 23 shows how the X_DELTVEL_LOW
and X_DELTVEL_OUT registers combine to support a 32-bit,
twos complement data format for the x-axis delta velocity
measurements. This format also applies to the y- and x-axes.
Table 78. Z_DELTVEL_LOW Register Definition
Page ID Addresses Default
Access Flash Backup
0x00 0x54, 0x55 Not applicable
R
No
X_ DELTVEL_OUT
X_ DELTVEL_LOW
15
0 15
0
Table 79. Z_DELTVEL_LOW Bit Definition
X-AXIS DELTA VELOCITY DATA
Bits
Description (No Default)
[15:0]
Z-axis delta velocity data, low word
Figure 23. Delta Velocity Output Data Structure
Rev. 0 | Page 20 of 38
Data Sheet
ADIS16486
Table 80. Z_DELTVEL_OUT Register Definition
The updates to the timer become active only after a write to
TIME_YM_OUT, Bits[14:8] byte completes.
Page ID Addresses Default
Access Flash Backup
0x00 0x56, 0x57 Not applicable
R
No
The RTC registers reflect the newly updated values only after the
next seconds tick of the clock that follows the write to TIME_YM_
OUT, Bits[14:8] (year(s)). Writing to TIME_YM_OUT, Bits[14:8]
activates all of the timing values. Therefore, always write to this
location last when updating the timer, even if the year information
does not require updating.
Table 81. Z_DELTVEL_OUT Bit Definition
Bits Description (No Default)
[15:0] Z-axis delta velocity data, high word, twos complement,
200 m/sec range, 0 m/sec = 0x0000, 1 LSB = 200 m/sec ÷
215 = ~6.104 mm/sec
Write the current time to each time data register after setting
CONFIG, Bit 0 = 1 (DIN = 0x8003, DIN = 0x8AC1, DIN =
0x8B00). This sequence preserves the factory default for other
bits in the CONFIG register. After configuring the CONFIG
register, set GLOB_CMD, Bit 3 = 1 (DIN = 0x8003, DIN =
0x8204, DIN = 0x8300) to back up these settings in flash. Even
though only VDDRTC must have power for time tracking,
access to the time data in the TIME_xx_OUT registers requires
normal operation (VDD = 3.3 V and full startup). Even when
not using the RTC function, the supply voltage on VDDRTC
must meet the conditions in Table 1.
Delta Velocity Resolution
Table 82 and Table 83 illustrate delta angle data in both 16-bit
and 32-bit formats.
Table 82. 16-Bit Delta Velocity Data Format Examples
Velocity (m/sec)
Decimal Hex
Binary
+200 × (215 − 1)/215 +32,767
0x7FFF 0111 1111 1110 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+200/214
+200/215
0
+2
+1
0
−200/215
−200/214
−200
−1
−2
−32,768
RTC: Minutes and Seconds, TIME_MS_OUT
Table 84. TIME_MS_OUT Register Definition
Table 83. 32-Bit Delta Velocity Data Format Examples
Page ID Addresses Default
Access Flash Backup
Velocity (m/sec)
+200 × (231 − 1)/231
+200/230
+200/231
0
−200/231
−200/230
−200
Decimal
Hex
0x00
0x78, 0x79 Not applicable R/W
No
+2,147,483,647
+2
+1
0
−1
−2
0x7FFFFFFF
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x80000000
Table 85. TIME_MS_OUT Bit Definitions
Bits
Description (No Default)
[15:14]
[13:8]
[7:6]
Not used
Minute(s), binary data, range = 0 to 59
Not used
[5:0]
Second(s), binary data, range = 0 to 59
−2,147,483,648
RTC: Day and Hour, TIME_DH_OUT
REAL-TIME CLOCK (RTC)
The VDDRTC power supply pin (see Table 6, Pin 23) provides a
separate supply for the RTC function. Connecting the VDDRTC
pin to its own 3.3 V supply enables the RTC to keep track of time,
even when the main supply (VDD) is off. Note that the VDDRTC
power supply must always be connected, even when this
function is not used.
Table 86. TIME_DH_OUT Register Definition
Page ID Addresses Default
Access Flash Backup
0x00
0x7A, 0x7B Not applicable R/W No
Table 87. TIME_DH_OUT Bit Definitions
Bits
Description (No Default)
[15:13]
[12:8]
[7:6]
Not used
Configure the RTC function by selecting one of two modes in
Bit 0 of the CONFIG register (see Table 147). The RTC data is
available in the TIME_MS_OUT (see Table 85), TIME_DH_OUT
(see Table 87), and TIME_YM_OUT (see Table 89) registers.
When using the elapsed timer mode, the time data registers start
at 0x0000 when the device starts up (or resets) and begin keeping
time in a similar manner to a stopwatch.
Day(s), binary data, range = 1 to 31
Not used
[5:0]
Hour(s), binary data, range = 0 to 23
RTC: Year and Month, TIME_YM_OUT
Table 88. TIME_YM_OUT Register Definition
Page ID Addresses Default
Access Flash Backup
When using the clock and calendar mode, write the current time
to the real-time registers in the following sequence: second(s)
(TIME_MS_OUT, Bits[5:0]), minute(s) (TIME_ MS_OUT,
Bits[13:8]), hour(s) (TIME_DH_OUT, Bits[5:0]), day(s)
(TIME_DH_OUT, Bits[12:8]), month(s) (TIME_YM_OUT,
Bits[3:0]), and year(s) (TIME_YM_OUT, Bits[14:8]).
0x00
0x7C, 0x7D Not applicable R/W
No
Rev. 0 | Page 21 of 38
ADIS16486
Data Sheet
See Figure 15 for an example of how to use a looping read of
this register to validate the integrity of the communication.
Table 89. TIME_YM_OUT Bit Definitions
Bits
Description (No Default)
Table 90. PROD_ID Register Definition
[15]
Not used
Page ID Addresses
Default Access Flash Backup
[14:8] Year(s), binary data, range = 0 to 99, relative to 2000 AD
0x00 0x7E, 0x7F
0x4066 Yes
R
[7:4]
[3:0]
Not used
Month(s), binary data, range = 1 to 12
Table 91. PROD_ID Bit Definition
Product Identification, PROD_ID
Bits
Description (Default = 0x4066)
The PROD_ID register (see Table 90 and Table 91) contains
the numerical portion of the device number (16,486).
[15:0]
Product identification = 0x4066
fs
4
D
FIR
FILTER
BANK
÷D
1
4
1
D
MEMS
SENSOR
ADC
330Hz
÷4
GYROSCOPE
INTERNAL
CLOCK
2-POLE: 404Hz, 757Hz
4×
SELECTABLE AVERAGE/DECIMATION FILTER
9.84kHz
AVERAGE
DECIMATION
FILTER
FIR FILTER BANK
FILTR_BNK_0
FILTR_BNK_1
D = DEC_RATE, BITS[10:0] + 1
ACCELEROMETER
1-POLE: 330Hz
fs
DIOx
OPTIONAL INPUT CLOCK
FNCTIO_CTRL, BIT 7 = 1
fs < 2400Hz
NOTES
1. WHEN FNCTIO_CTRL, BIT 7 = 1, fs IS THE EXTERNAL INPUT CLOCK, AND EACH CLOCK PULSE ON THE DESIGNATED DIOx LINE
(FNCTIO_CTRL, BITS[5:4]) STARTS A 4-SAMPLE BURST, AT A SAMPLE RATE OF 9.84 kHz. THESE FOUR SAMPLES FEED INTO THE
4× AVERAGE/DECIMATION FILTER, WHICH PRODUCES A DATA RATE THAT IS EQUAL TO THE INPUT CLOCK FREQUENCY.
2. WHEN FNCTIO_CTRL, BIT 7 = 0, fs IS THE INTERNALLY GENERATED 2.46 kHz SAMPLE CLOCK.
Figure 24. Sampling and Frequency Response Signal Flow
Rev. 0 | Page 22 of 38
Data Sheet
ADIS16486
Table 96. Z_GYRO_SCALE Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x08, 0x09 0x0000 R/W Yes
CALIBRATION
The signal chain of each inertial sensor (accelerometers and
gyroscopes) includes the application of unique correction
formulas, which come from extensive characterization of bias,
sensitivity, alignment, and response to linear acceleration
(gyroscopes) over a temperature range of −40°C to +85°C for
every ADIS16486. These correction formulas are not accessible,
but users can adjust bias and scale factor for each sensor
individually through user accessible registers. These correction
factors follow immediately after the factory derived correction
formulas in the signal chain.
Table 97. Z_GYRO_SCALE Bit Definition
Bits Description (Default = 0x0000)
[15:0] Z-axis gyroscope scale correction, twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Calibration, Accelerometer Scale, X_ACCL_SCALE
The X_ACCL_SCALE register (see Table 98 and Table 99)
allows users to adjust the scale factor for the x-axis accelerometers.
See Figure 26 for an illustration of how this scale factor influences
the x-axis accelerometer data.
Calibration, Gyroscope Scale, X_GYRO_SCALE
The X_GYRO_SCALE register (see Table 92 and Table 93)
allows users to adjust the scale factor for the x-axis gyroscopes.
See Figure 25 for an illustration of how this scale factor
influences the x-axis gyroscope data.
Table 98. X_ACCL_SCALE Register Definition
Page ID Addresses
Default Access Flash Backup
0x02 0x0A, 0x0B
0x0000 R/W Yes
Table 92. X_GYRO_SCALE Register Definition
Table 99. X_ACCL_SCALE Bit Definition
Bits Description (Default = 0x0000)
Page ID Addresses
Default Access Flash Backup
0x02 0x04, 0x05
0x0000 R/W Yes
[15:0] X-axis accelerometer scale correction, twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Table 93. X_GYRO_SCALE Bit Definition
Bits Description (Default = 0x0000)
1 + X_ACCL_SCALE
FACTORY
[15:0] X-axis gyroscope scale correction, twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
X-AXIS
ACCL
CALIBRATION
AND
X_ACCL_OUT X_ACCL_LOW
FILTERING
1 + X_GYRO_SCALE
XA_BIAS_HIGH
XA_BIAS_LOW
FACTORY
X-AXIS
GYRO
CALIBRATION
AND
Figure 26. User Calibration Signal Path, Accelerometers
X_GYRO_OUT X_GYRO_LOW
FILTERING
Calibration, Accelerometer Scale, Y_ACCL_SCALE
XG_BIAS_HIGH XG_BIAS_LOW
The Y_ACCL_SCALE register (see Table 100 and Table 101)
allows users to adjust the scale factor for the y-axis accelerometers.
This register influences the y-axis accelerometer measurements
in the same manner that the X_ACCL_SCALE register influences
the x-axis accelerometer measurements (see Figure 26).
Figure 25. User Calibration Signal Path, Gyroscopes
Calibration, Gyroscope Scale, Y_GYRO_SCALE
The Y_GYRO_SCALE register (see Table 94 and Table 95)
allows users to adjust the scale factor for the y-axis gyroscopes.
This register influences the y-axis gyroscope measurements in
the same manner that the X_GYRO_SCALE register influences
the x-axis gyroscope measurements (see Figure 25).
Table 100. Y_ACCL_SCALE Register Definition
Page ID Addresses
Default Access Flash Backup
0x02
0x0C, 0x0D 0x0000 R/W
Yes
Table 94. Y_GYRO_SCALE Register Definition
Table 101. Y_ACCL_SCALE Bit Definition
Bits Description (Default = 0x0000)
Page ID Addresses
Default Access Flash Backup
0x02 0x06, 0x07
0x0000 R/W Yes
[15:0] Y-axis accelerometer scale correction, twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Table 95. Y_GYRO_SCALE Bit Definition
Bits Description (Default = 0x0000)
[15:0] Y-axis gyroscope scale correction, twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Calibration, Accelerometer Scale, Z_ACCL_SCALE
The Z_ACCL_SCALE register (see Table 102 and Table 103)
allows users to adjust the scale factor for the z-axis accelerometers.
This register influences the z-axis accelerometer measurements
in the same manner that the X_ACCL_SCALE register influences
the x-axis accelerometer measurements (see Figure 26).
Calibration, Gyroscope Scale, Z_GYRO_SCALE
The Z_GYRO_SCALE register (see Table 96 and Table 97)
allows users to adjust the scale factor for the z-axis gyroscopes.
This register influences the z-axis gyroscope measurements in the
same manner that the X_GYRO_SCALE register influences the
x-axis gyroscope measurements (see Figure 25).
Table 102. Z_ACCL_SCALE Register Definition
Page ID Addresses
Default Access Flash Backup
0x02 0x0E, 0x0F
0x0000 R/W Yes
Rev. 0 | Page 23 of 38
ADIS16486
Data Sheet
Table 103. Z_ACCL_SCALE Bit Definition
Table 110. YG_BIAS_HIGH Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x16, 0x17 0x0000 R/W Yes
Bits
Description (Default = 0x0000)
[15:0] Z-axis accelerometer scale correction, twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Table 111. YG_BIAS_HIGH Bit Definition
Bits Description (Default = 0x0000)
Calibration, Gyroscope Bias, XG_BIAS_LOW,
XG_BIAS_HIGH
[15:0] Y-axis gyroscope offset correction, high word, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
The XG_BIAS_LOW (see Table 104 and Table 105) and XG_
BIAS_HIGH (see Table 106 and Table 107) registers combine
to allow users to adjust the bias of the x-axis gyroscopes. The
digital format examples in Table 40 also apply to the XG_BIAS_
HIGH register, and the digital format examples in Table 41 apply
to the 32-bit number that comes from combining the XG_BIAS_
LOW and XG_BIAS_HIGH registers. See Figure 25 for an
illustration of how these two registers combine and influence
the x-axis gyroscope measurements.
Calibration, Gyroscope Bias, ZG_BIAS_LOW,
ZG_BIAS_HIGH
The ZG_BIAS_LOW (see Table 112 and Table 113) and ZG_
BIAS_HIGH (see Table 114 and Table 115) registers combine
to allow users to adjust the bias of the z-axis gyroscopes. The
digital format examples in Table 40 also apply to the ZG_BIAS_
HIGH register, and the digital format examples in Table 41 apply
to the 32-bit number that comes from combining the ZG_BIAS_
LOW and ZG_BIAS_HIGH registers. These registers influence
the z-axis gyroscope measurements in the same manner that the
XG_BIAS_LOW and XG_BIAS_HIGH registers influence the
x-axis gyroscope measurements (see Figure 25).
Table 104. XG_BIAS_LOW Register Definition
Page ID Addresses
Default Access Flash Backup
0x02 0x10, 0x11
0x0000 R/W Yes
Table 105. XG_BIAS_LOW Bit Definition
Table 112. ZG_BIAS_LOW Register Definition
Bits
Description (Default = 0x0000)
Page ID Addresses
Default Access Flash Backup
[15:0]
X-axis gyroscope offset correction, low word, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec ÷ 216
~0.000000305°/sec
=
0x02 0x18, 0x19
0x0000 R/W Yes
Table 113. ZG_BIAS_LOW Bit Definition
Bits Description (Default = 0x0000)
Table 106. XG_BIAS_HIGH Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x12, 0x13 0x0000 R/W Yes
[15:0] Z-axis gyroscope offset correction, low word, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec ÷ 216
~0.000000305°/sec
=
Table 107. XG_BIAS_HIGH Bit Definition
Bits Description (Default = 0x0000)
Table 114. ZG_BIAS_HIGH Register Definition
Page ID Addresses
Default Access Flash Backup
[15:0] X-axis gyroscope offset correction, high word, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
0x02 0x1A, 0x1B
0x0000 R/W Yes
Calibration, Gyroscope Bias, YG_BIAS_LOW,
YG_BIAS_HIGH
Table 115. ZG_BIAS_HIGH Bit Definition
Bits Description (Default = 0x0000)
The YG_BIAS_LOW (see Table 108 and Table 109) and YG_
BIAS_HIGH (see Table 110 and Table 111) registers combine
to allow users to adjust the bias of the y-axis gyroscopes. The
digital format examples in Table 40 also apply to the YG_BIAS_
HIGH register, and the digital format examples in Table 41 apply
to the 32-bit number that comes from combining the YG_BIAS_
LOW and YG_BIAS_HIGH registers. These registers influence
the y-axis gyroscope measurements in the same manner that
the XG_BIAS_LOW and XG_BIAS_HIGH registers influence
the x-axis gyroscope measurements (see Figure 25).
[15:0] Z-axis gyroscope offset correction, high word, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
Calibration, Accelerometer Bias, XA_BIAS_LOW,
XA_BIAS_HIGH
The XA_BIAS_LOW (see Table 116 and Table 117) and XA_
BIAS_HIGH (see Table 118 and Table 119) registers combine
to allow users to adjust the bias of the x-axis accelerometers. The
digital format examples in Table 54 also apply to the XA_BIAS_
HIGH register, and the digital format examples in Table 55 apply
to the 32-bit number that comes from combining the XA_BIAS_
LOW and XA_BIAS_HIGH registers. See Figure 26 for an
illustration of how these two registers combine and influence
the x-axis accelerometer measurements.
Table 108. YG_BIAS_LOW Register Definition
Page ID Addresses
Default Access Flash Backup
0x02 0x14, 0x15
0x0000 R/W Yes
Table 109. YG_BIAS_LOW Bit Definition
Bits Description (Default = 0x0000)
Table 116. XA_BIAS_LOW Register Definition
Page ID Addresses
Default Access Flash Backup
[15:0] Y-axis gyroscope offset correction, low word, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec ÷ 216
~0.000000305°/sec
0x02
0x1C, 0x1D 0x0000 R/W
Yes
=
Rev. 0 | Page 24 of 38
Data Sheet
ADIS16486
Table 117. XA_BIAS_LOW Bit Definition
manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers
influence the x-axis accelerometer measurements (see Figure 26).
Bits
Description (Default = 0x0000)
[15:0]
X-axis accelerometer offset correction, low word, twos
Table 124. ZA_BIAS_LOW Register Definition
complement, 0 g = 0x0000, 1 LSB = 0.8 mg ÷ 216
~0.01221 µg
=
Page ID Addresses
Default Access Flash Backup
0x02 0x24, 0x25
0x0000 R/W Yes
Table 118. XA_BIAS_HIGH Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x1E, 0x1F 0x0000 R/W Yes
Table 125. ZA_BIAS_LOW Bit Definition
Bits Description (Default = 0x0000)
[15:0] Z-axis accelerometer offset correction, low word, twos
complement, 0 g = 0x0000, 1 LSB = 0.8 mg ÷ 216
~0.01221 µg
=
Table 119. XA_BIAS_HIGH Bit Definition
Bits Description (Default = 0x0000)
[15:0] X-axis accelerometer offset correction, high word, twos
Table 126. ZA_BIAS_HIGH Register Definition
complement, 0 g = 0x0000, 1 LSB = 0.8 mg
Page ID Addresses
Default Access Flash Backup
Calibration, Accelerometer Bias, YA_BIAS_LOW,
YA_BIAS_HIGH
0x02 0x26, 0x27
0x0000 R/W Yes
Table 127. ZA_BIAS_HIGH Bit Definition
Bits Description (Default = 0x0000)
The YA_BIAS_LOW (see Table 120 and Table 121) and YA_
BIAS_HIGH (see Table 122 and Table 123) registers combine
to allow users to adjust the bias of the y-axis accelerometers. The
digital format examples in Table 54 also apply to the YA_BIAS_
HIGH register, and the digital format examples in Table 55 apply
to the 32-bit number that comes from combining the YA_BIAS_
LOW and YA_BIAS_HIGH registers. These registers influence
the y-axis accelerometer measurements in the same manner
that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence
the x-axis accelerometer measurements (see Figure 26).
[15:0] Z-axis accelerometer offset correction, high word, twos
complement, 0 g = 0x0000, 1 LSB = 0.8 mg
Scratch Registers, USER_SCR_x
The USER_SCR_1 (see Table 128 and Table 129), USER_SCR_2
(see Table 130 and Table 131), USER_SCR_3 (see Table 132
and Table 133), and USER_SCR_4 (see Table 134 and Table 135)
registers provide four locations for users to store information.
Table 128. USER_SCR_1 Register Definition
Table 120. YA_BIAS_LOW Register Definition
Page ID Addresses
Default Access Flash Backup
Page ID Addresses
Default Access Flash Backup
0x02 0x74, 0x75
0x0000 R/W Yes
0x02 0x20, 0x21
0x0000 R/W Yes
Table 129. USER_SCR_1 Bit Definition
Bits Description (Default = 0x0000)
[15:0] User defined
Table 121. YA_BIAS_LOW Bit Definition
Bits
Description (Default = 0x0000)
[15:0]
Y-axis accelerometer offset correction, low word, twos
Table 130. USER_SCR_2 Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x76, 0x77 0x0000 R/W Yes
complement, 0 g = 0x0000, 1 LSB = 0.8 mg ÷ 216
~0.01221 µg
=
Table 122. YA_BIAS_HIGH Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x22, 0x23 0x0000 R/W Yes
Table 131. USER_SCR_2 Bit Definition
Bits Description (Default = 0x0000)
[15:0] User defined
Table 123. YA_BIAS_HIGH Bit Definition
Bits Description (Default = 0x0000)
Table 132. USER_SCR_3 Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x78, 0x79 0x0000 R/W Yes
[15:0] Y-axis accelerometer offset correction, high word, twos
complement, 0 g = 0x0000, 1 LSB = 0.8 mg
Table 133. USER_SCR_3 Bit Definition
Bits Description (Default = 0x0000)
[15:0] User defined
Calibration, Accelerometer Bias, ZA_BIAS_LOW,
ZA_BIAS_HIGH
The ZA_BIAS_LOW (see Table 124 and Table 125) and ZA_
BIAS_HIGH (see Table 126 and Table 127) registers combine
to allow users to adjust the bias of the z-axis accelerometers.
The digital format examples in Table 54 also apply to the ZA_
BIAS_HIGH register, and the digital format examples in Table 55
apply to the 32-bit number that comes from combining the
ZA_BIAS_LOW and ZA_BIAS_HIGH registers. These registers
influence the z-axis accelerometer measurements in the same
Table 134. USER_SCR_4 Register Definition
Page ID Addresses Default Access Flash Backup
0x02 0x7A, 0x7B 0x0000 R/W Yes
Table 135. USER_SCR_4 Bit Definition
Bits Description (Default = 0x0000)
[15:0] User defined
Rev. 0 | Page 25 of 38
ADIS16486
Data Sheet
Flash Memory Endurance Counter, FLSHCNT_LOW,
FLSHCNT_HIGH
Table 141. GLOB_CMD Bit Definitions
Bits
Description (Default = 0x0000)
The FLSHCNT_LOW (see Table 136 and Table 137) and
FLSHCNT_HIGH (see Table 138 and Table 139) registers
combine to create a 32-bit binary counter that tracks the number
of flash memory write cycles. In addition to the number of
write cycles, the flash memory has a finite service lifetime,
which depends on the junction temperature. Figure 27 provides
guidance for estimating the retention life for the flash memory
at specific junction temperatures. The junction temperature is
approximately 7°C above the case temperature.
[15:8]
Not used
7
Software reset
Factory calibration restore
Not used
6
[5:4]
3
Flash memory update
Not used
2
1
Self test
0
Bias correction update
Software Reset
Table 136. FLSHCNT_LOW Register Definition
Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 7 = 1
(DIN = 0x8280, then DIN = 0x8300) to initiate a reset of the
ADIS16486. This reset removes all data, initializes all of the
registers from their flash settings, and restarts data sampling
and processing. This function provides a firmware alternative
Page ID Addresses Default
Access Flash Backup
0x02
0x7C, 0x7D Not applicable R/W
Yes
Table 137. FLSHCNT_LOW Bit Definition
Bits Description (No Default)
RST
to providing a low pulse on the
pin (see Table 6).
[15:0] Flash memory write counter, low word
Factory Calibration Restore
Table 138. FLSHCNT_HIGH Register Definition
Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 6 = 1
(DIN = 0x8240, then DIN = 0x8300) to restore the factory
calibration. This restoration writes 0x0000 to the following
registers: X_GYRO_SCALE, Y_GYRO_SCALE,
Z_GYRO_SCALE, X_ACCL_SCALE, Y_ACCL_SCALE,
Z_ACCL_SCALE, XG_BIAS_LOW, XG_BIAS_HIGH,
YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW,
ZG_BIAS_HIGH, XA_BIAS_LOW, XA_BIAS_HIGH,
YA_BIAS_LOW, YA_BIAS_HIGH, ZA_BIAS_LOW, and
ZA_BIAS_HIGH.
Page ID Addresses Default
Access Flash Backup
0x02
0x7E, 0x7F Not applicable R/W Yes
Table 139. FLSHCNT_HIGH Bit Definition
Bits
Description (No Default)
[15:0] Flash memory write counter, high word
600
450
300
Flash Memory Update
Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 3 = 1
(DIN = 0x8208, then DIN = 0x8300) to initiate a manual flash
update. SYS_E_FLAG, Bit 6 (see Table 20) identifies success (0)
or failure (1) in completing this process.
150
0
ODST
Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 1 = 1
(DIN = 0x8202, then DIN = 0x8300) to run the ODST routine,
which executes the following steps:
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
Figure 27. Flash Memory Retention
1. Measure the output on each sensor.
2. Activate an internal force on the mechanical elements of
each sensor, which simulates the force associated with
actual inertial motion.
3. Measure the output response on each sensor.
4. Deactivate the internal force on each sensor.
5. Calculate the difference between the force on and normal
operating conditions (force off).
Global Commands, GLOB_CMD
The GLOB_CMD register (see Table 140 and Table 141) provides
trigger bits for several operations. Write a 1 to the appropriate
bit in the GLOB_CMD register to start a desired function.
Table 140. GLOB_CMD Register Definition
Page ID Addresses
Default Access Flash Backup
6. Compare the difference with internal pass and fail criteria.
7. Report the pass and fail results for each sensor in DIAG_
STS (see Table 22) and the overall pass and fail flag in SYS_
E_FLAG, Bit 5 (see Table 20).
0x03 0x02, 0x03
0x0000 No
W
Rev. 0 | Page 26 of 38
Data Sheet
ADIS16486
When using an external clock, the self test execution times may
vary from the 12 ms listed in Table 1. In addition, false positive
results are possible when executing the ODST while the device
is in motion.
data collection and minimize latency. The factory default assigns
the DIO2 pin as a positive polarity, data ready signal. This
means that the data in the output registers is valid when the
DIO2 line is high (see Figure 28). This configuration is intended
when the DIO2 pin drives an interrupt service pin that activates
on a low to high pulse.
Bias Correction Update
Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 0 = 1
(DIN = 0x8201, then DIN = 0x8300) to update the user offset
registers with the correction factors of the continuous bias
estimator (CBE). Ensure that the inertial platform is stable during
the entire average time for optimal bias estimates.
DIO2
INACTIVE
ACTIVE
Figure 28. Data Ready, when FNCTIO_CTRL, Bits[3:0] = 1101 (Default)
Use the following sequence to change this assignment to the
DIO1 pin with a negative polarity:
Auxiliary Input and Output Line Configuration,
FNCTIO_CTRL
1. Select Page 3 (DIN = 0x8003).
2. Set FNCTIO_CTRL, Bits[3:0] = 1000 (DIN = 0x8608, then
DIN = 0x8700).
The FNCTIO_CTRL register (see Table 142 and Table 143)
provides configuration control for each input and output pin
(DIO1, DIO2, DIO3, and DIO4). Each DIOx pin supports only
one function at a time. In cases where a single pin has two
assignments, the enable bit for the lower priority function
automatically resets to zero (disabling the lower priority function).
The order of priority is as follows, from highest priority to lowest
priority: data ready, sync clock input, alarm indicator, and
general-purpose. Changing the FNCTIO_CTRL, Bits[5:4] bit
settings requires an execution time of 75 ms, whereas changing
the settings of the remaining bits in the FNCTIO_CTRL register
only takes 3 ms. During this execution time (75 ms or 3 ms),
the operational state and the contents of the register remain
unchanged. However, the SPI interface supports normal
The period of the data ready signal can vary by up to 2%.
Input Sync and Clock Control
FNCTIO_CTRL, Bits[7:4] provide configuration options for
using one of the DIOx pins as an input synchronization signal for
sampling inertial sensor data. For example, use the following
sequence to establish the DIO4 pin as a positive polarity, input
clock pin, and to keep the factory default setting for the data ready
function:
1. Select Page 3 (DIN = 0x8003).
2. Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86FD).
3. Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8700).
communication (for accessing other registers).
Note that this command also disables the internal sampling
clock. Therefore, data sampling does not occur if an input clock
signal is not present. Use an input clock frequency of 2400 Hz
for the best performance.
Table 142. FNCTIO_CTRL Register Definition
Page ID Addresses
Default Access Flash Backup
0x03 0x06, 0x07
0x000D R/W Yes
Alarm Indicator
Table 143. FNCTIO_CTRL Bit Definitions
FNCTIO_CTRL, Bits[11:8] provide three configuration options
for using one of the DIOx pins as an alarm indicator: on and off,
polarity, and the DIOx pin. The primary purpose of this signal
is to provide an output signal that activates when a bit in the
SYS_E_FLAG register = 1 (see Table 20). For example, use the
following sequence to establish the DIO3 pin as a negative-polarity,
alarm indicator, while preserving the factory default setting for the
data ready function:
Bits
[15:12]
11
Description (Default = 0x000D)
Not used
Alarm indicator: 1 = enabled, 0 = disabled
Alarm indicator polarity: 1 = positive, 0 = negative
Alarm indicator line selection:
00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4
Sync clock input enable: 1 = enabled, 0 = disabled
Sync clock input polarity:
10
[9:8]
7
6
1. Select Page 3 (DIN = 0x8003).
1 = rising edge, 0 = falling edge
2. Set FNCTIO_CTRL, Bits[7:0] = 0x0D (DIN = 0x860D).
3. Set FNCTIO_CTRL, Bits[15:8] = 0x0A (DIN = 0x870A).
[5:4]
Sync clock input line selection:
00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4
Data ready enable: 1 = enabled, 0 = disabled
Data ready polarity: 1 = positive, 0 = negative
Data ready line selection:
3
General-Purpose Input and Output Control, GPIO_CTRL
2
Table 144. GPIO_CTRL Register Definition1
[1:0]
Page ID Addresses
Default Access Flash Backup
00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4
0x03 0x08, 0x09
0x00X0 R/W Yes
Data Ready Indicator
1 GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx pins and do not have
a default setting.
FNCTIO_CTRL, Bits[3:0] provide three configuration options for
the data ready function: on and off, polarity, and which DIOx
pin is used. The primary purpose of this signal is to drive the
interrupt control line of an embedded processor to synchronize
Rev. 0 | Page 27 of 38
ADIS16486
Data Sheet
Table 145. GPIO_CTRL Bit Definitions1
Bits
Description (Default = 0x00X0)
[15:8]
Don’t care
7
6
5
4
3
2
1
0
General-Purpose Input and Output Line 4 (DIO4) data level
General-Purpose Input and Output Line 3 (DIO3) data level
General-Purpose Input and Output Line 2 (DIO2) data level
General-Purpose Input and Output Line 1 (DIO1) data level
DIO4 direction control (1 = output, 0 = input)
DIO3 direction control (1 = output, 0 = input)
DIO2 direction control (1 = output, 0 = input)
DIO1 direction control (1 = output, 0 = input)
PIN 23
PIN 1
POINT OF PERCUSSION
ALIGNMENT REFERENCE POINT.
SEE CONFIG, BIT 6.
Figure 29. Point of Percussion Reference Point
Linear Acceleration Effect on Gyroscope Bias
The ADIS16486 includes first-order compensation for the
linear g effect in the gyroscopes, which uses the following
model:
1 GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx pins and do not have
a default setting.
When the FNCTIO_CTRL register does not configure a DIOx pin,
the GPIO_CTRL register provides register controls for general-
purpose use of the pin. GPIO_CTRL, Bits[3:0] provide input and
output assignment controls for each line. When the DIOx pins
are inputs, monitor their level by reading GPIO_CTRL, Bits[7:4].
When the DIOx pins are used as outputs, set their level by writing
to GPIO_CTRL, Bits[7:4]. For example, use the following
sequence to set the DIO1 and DIO3 pins as high and low
output lines, respectively, and set the DIO2 and DIO4 pins as
input lines:
XC
XPC
LG11 LG12 LG13
A
ω
ω
ω
ω
ω
ω
X
= LG
LG22 LG23 × AY
+
21
YC
YPC
LG31 LG32 LG33
AZ
ZC
ZPC
The linear g correction factors, LGXY, apply correction for linear
acceleration in all three directions to the data path of each
gyroscope (ωXPC, ωYPC, and ωZPC) at the rate of the data samples
(2460 SPS when using the internal clock). CONFIG, Bit 7
provides an on and off control for this compensation. The
factory default value for this bit activates this compensation. To
turn the compensation off, select Page 3 (DIN = 0x8003) and
set CONFIG, Bit 7 = 0 (DIN = 0x8A40, then DIN = 0x8B00).
This command sequence also preserves the default setting for
the point of percussion alignment function (on).
1. Select Page 3 (DIN = 0x8003).
2. Set GPIO_CTRL, Bits[7:0] = 0x15 (DIN = 0x8815, then
DIN = 0x8900).
Miscellaneous Configuration, CONFIG
The CONFIG register (see Table 146 and Table 147) provides
configuration options for the linear g compensation in the
gyroscopes (on and off), point of percussion alignment for the
accelerometers (on and off), and the RTC function.
Decimation Filter, DEC_RATE
The DEC_RATE register (see Table 148 and Table 149) provides
user control for the final filter stage (see Figure 24), which
averages and decimates the accelerometer and gyroscope data,
while also extending the time that the delta angle and delta
velocity track between each update. The output sample rate is
equal to 2460/(DEC_RATE + 1). When using the external clock
option (FNCTIO_CTRL, Bits[7:4], see Figure 24), replace 2460 in
this relationship with the input clock frequency. For example,
select Page 3 (DIN = 0x8003), and set DEC_RATE = 0x18 (DIN
= 0x8C18, then DIN = 0x8D00) to reduce the output sample rate
to 98.4 SPS (2460 ÷ 25).
Table 146. CONFIG Register Definition
Page ID Addresses
Default Access Flash Backup
0x03 0x0A, 0x0B
0x00C0 R/W Yes
Table 147. CONFIG Bit Definitions
Bits Description (Default = 0x00C0)
[15:8] Not used
7
Linear g compensation for gyroscopes (1 = enabled)
Point of percussion alignment (1 = enabled)
Not used
6
Table 148. DEC_RATE Register Definition
[5:2]
1
Page ID Addresses
Default Access Flash Backup
RTC, daylight savings time (1: enabled, 0: disabled)
0x03
0x0C, 0x0D 0x0000 R/W
Yes
0
RTC control (1: relative and elapsed timer mode,
0: calendar mode)
Table 149. DEC_RATE Bit Definitions
Point of Percussion
Bits
Description (Default = 0x0000)
CONFIG, Bit 6 offers a point of percussion alignment function
that maps the accelerometer sensors to the corner of the package
identified in Figure 29. To activate this feature, select Page 3
(DIN = 0x8003) and set CONFIG, Bit 6 = 1 (DIN = 0x8A40,
DIN = 0x8B00).
[15:11]
[10:0]
Don’t care
Decimation rate, binary format, maximum = 2047, see
Figure 24 for the impact on sample rate
Rev. 0 | Page 28 of 38
Data Sheet
ADIS16486
Continuous Bias Estimation, NULL_CNFG
Table 152. SLP_CNT Register Definition
Page ID Addresses Default
Access Flash Backup
The NULL_CNFG register (see Table 150 and Table 151) provides
the configuration controls for the CBE, which is associated with
the bias correction update command in GLOB_CMD, Bit 0 (see
Table 141). NULL_CNFG, Bits[3:0] establishes the total average
time (tA) for the bias estimates, and NULL_CNFG, Bits[13:8]
provides on and off controls for each sensor. The factory
default configuration for the NULL_CNFG register enables the
bias null command for the gyroscopes, disables the bias null
command for the accelerometers, and sets the average time to
~26.64 sec. This calculation assumes that the internal sample
clock (fS = 2460 SPS) is used. If the user supplies an external
clock by setting Bit 7 to 1 of the FNCTIO_CRTL register (see
Table 142 and Table 143), fS is the inertial measurement unit
(IMU) sample rate before decimation.
0x03
0x10, 0x11 Not applicable R/W
No
Table 153. SLP_CNT Bit Definitions
Bits
Description (No Default)
[15:10] Not used
9
Power-down mode
Normal sleep mode
Programmable time bits, 1 sec/LSB, 0x00 = indefinite
8
[7:0]
To initiate sleep mode for a specific period, select Page 3 (DIN =
0x8003), write the amount of sleep time to SLP_CNT, Bits[7:0],
and set SLP_CNT, Bit 8 = 1 (DIN = 0x9101). Sleep mode begins
CS
when the
line goes high after setting SLP_CNT, Bit 8 = 1. Use
the following sequence to place the ADIS16486 into sleep mode
for 100 sec:
Table 150. NULL_CNFG Register Definition
1. Select Page 3 (DIN = 0x8003).
Page ID Addresses
Default Access Flash Backup
2. Set SLP_CNT, Bits[7:0] = 0x64 (DIN = 0x9064), 100 sec
0x03 0x0E, 0x0F
0x070A R/W Yes
sleep time.
Table 151. NULL_CNFG Bit Definitions
Bits Description (Default = 0x070A)
[15:14] Not used.
3. Set SLP_CNT, Bit 8 = 1 (DIN = 0x9101), start sleep mode.
To initiate an indefinite sleep mode, set SLP_CNT, Bits[7:0] = 0x00
(DIN = 0x9000), and then set SLP_CNT, Bit 8 = 1 (DIN = 0x9101).
To initiate a power-down period of 100 sec, use the sequence
for placing the ADIS16486 into sleep mode for 100 sec with one
exception: set SLP_CNT, Bit 9 = 1 (DIN = 0x9102) instead of
setting SLP_CNT, Bit 8 = 1 (DIN = 0x9101). To initiate an
indefinite power-down, set SLP_CNT, Bits[7:0] = 0x00 first,
and then set SLP_CNT, Bit 9 = 1 (DIN = 0x9102).
13
12
11
10
9
Z-axis acceleration bias correction enable (1 = enabled).
Y-axis acceleration bias correction enable (1 = enabled).
X-axis acceleration bias correction enable (1 = enabled).
Z-axis gyroscope bias correction enable (1 = enabled).
Y-axis gyroscope bias correction enable (1 = enabled).
X-axis gyroscope bias correction enable (1 = enabled).
Not used.
8
[7:4]
[3:0]
To wake the device from sleep or power-down mode, use one of
the following options to restore normal operation:
Time base control (TBC), range is 0 to 13 (default = 10),
and time base (tB) = 2TBC/fS, where fS is the IMU sample
rate before decimation and is 2460 SPS if the factory
default internal clock is used. The tA required for
autonull = 64 × tB.
CS
•
•
•
Assert
RST
from high to low.
Pulse
low, and then high again.
Cycle the power.
When a sensor bit in the NULL_CNFG register is active (equal
to 1), setting GLOB_CMD, Bit 0 = 1 (DIN sequence: 0x8003,
0x8201, 0x8300) causes the corresponding bias correction register
to automatically update with a value that corrects for its present
bias error (from the CBE). For example, setting NULL_CNFG,
Bit 8 = 1 causes an update in the XG_BIAS_LOW (see Table 105)
and XG_BIAS_HIGH (see Table 107) registers.
If the sleep mode and power-down mode bits are both set to
high, the normal sleep mode bit (SLP_CNT, Bit 8) takes
precedence.
FIR Filter Control, FILTR_BNK_0, FILTR_BNK_1
The FILTR_BNK_0 (see Table 154 and Table 155) and FILTR_
BNK_1 (see Table 156 and Table 157) registers provide the
configuration controls for the FIR filter bank in the signal chain
of each sensor (see Figure 24). These registers provide on and
off control for the FIR bank for each inertial sensor, along with
the FIR bank (A, B, C, D) that each sensor uses.
Power Management, SLP_CNT
The SLP_CNT register (see Table 152 and Table 153) provides
controls for both power-down mode and sleep mode. The trade-
off between power-down mode and sleep mode is idle power
and recovery time. Power-down mode offers the best power
consumption but requires the most time to recover. In addition, all
volatile settings are lost during power-down, whereas sleep
mode preserves these settings.
Write commands to the FILTR_BNK_0 and FILTR_BNK_1
registers, which enable or configure the FIR filters and take up
to 101 µs to fully process. During this execution time, the SPI
interface supports normal operation, and the register values
update at the conclusion of the update process.
Rev. 0 | Page 29 of 38
ADIS16486
Data Sheet
7
7
Table 154. FILTR_BNK_0 Register Definition
1
8
(3)
(4)
(5)
ΔZ_GYRO_OUT =
Z
Y
(
n
)
)
−
−
Z
Y
(
n −104
)
∑
∑
G
G
Page ID Addresses
Default Access Flash Backup
n = 0
n = 0
0x03 0x16, 0x17
0x0000 R/W Yes
where ZG = Z_GYRO_OUT.
Table 155. FILTR_BNK_0 Bit Definitions
7
7
1
8
Bits
Description (Default = 0x0000)
ΔY_GYRO_OUT =
(
n
(
n −104
)
∑
∑
G
G
n = 0
n = 0
15
Don’t care
14
Y-axis accelerometer filter enable (1 = enabled)
Y-axis accelerometer filter bank selection:
00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D
X-axis accelerometer filter enable (1 = enabled)
X-axis accelerometer filter bank selection:
00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D
Z-axis gyroscope filter enable (1 = enabled)
Z-axis gyroscope filter bank selection:
where YG = Y_GYRO_OUT.
[13:12]
7
7
1
8
ΔX_GYRO_OUT =
X
(
n
)
−
X
(
n −104
)
∑
∑
G
G
11
n = 0
n = 0
[10:9]
where XG = X_GYRO_OUT.
Solving for ΔZ_ACCL_OUT and ΔY_ACCL_OUT
8
[7:6]
Use Equation 6 and Equation 7 to solve for ΔZ_ACCL_OUT
and ΔY_ACCL_OUT in Bits[5:4] and Bits[1:0] in Table 161.
00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D
Y-axis gyroscope filter enable (1 = enabled)
Y-axis gyroscope filter bank selection:
5
7
7
1
8
[4:3]
ΔZ_ACCL_OUT =
Z
n −
A ( )
Z
n −104
(6)
(7)
(
)
∑
∑
A
n = 0
00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D
X-axis gyroscope filter enable (1 = enabled)
X-axis gyroscope filter bank selection:
n = 0
2
where ZA = Z_ACCL_OUT.
[1:0]
7
7
1
8
00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D
ΔY_ACCL_OUT =
Y
n −
A ( )
Y n −104
( )
A
∑
∑
n = 0
n = 0
Table 156. FILTR_BNK_1 Register Definition
Page ID Addresses Default Access Flash Backup
0x03 0x18, 0x19 0x0000 R/W Yes
where YA = Y_ACCL_OUT.
Table 159. ALM_CNFG_0 Bit Definitions
Bits
15
Description (Default = 0x0000)
Table 157. FILTR_BNK_1 Bit Definitions
X-axis accelerometer. 0: alarm is off, and 1: alarm is on.
Not used.
Bits
[15:3]
2
Description (Default = 0x0000)
14
Don’t care
[13:12] X-axis accelerometer polarity and mode settings.
Select one of the four options for the condition that
triggers the alarm (ALM_STS, Bit 3 = 1, see Table 24).
Z-axis accelerometer filter enable (1 = enabled)
Z-axis accelerometer filter bank selection:
[1:0]
00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D
00: X_ACCL_OUT < XA_ALM_MAGN.
Alarm Configuration, ALM_CNFG_0, ALM_CNFG_1
01: ΔX_ACCL_OUT < XA_ALM_MAGN (see Equation 2).
10: X_ACCL_OUT > XA_ALM_MAGN.
11: ΔX_ACCL_OUT > XA_ALM_MAGN (see Equation 2).
The ALM_CNFG_0 (see Table 158 and Table 159) and ALM_
CNFG_1 (see Table 160 and Table 161) registers provide three
configuration control options for the alarm functions of each
inertial sensor: on and off, polarity, and mode of operation
(static and dynamic).
11
Z-axis gyroscope. 0: alarm is off, and 1: alarm is on.
Not used.
10
[9:8]
Z-axis gyroscope polarity and mode settings. Select
one of the four options for the condition that triggers
the alarm (ALM_STS, Bit 2 = 1, see Table 24).
Table 158. ALM_CNFG_0 Register Definition
Page ID Addresses
Default Access Flash Backup
00: Z_GYRO_OUT < ZG_ALM_MAGN.
01: ΔZ_GYRO_OUT < ZG_ALM_MAGN (see Equation 3).
10: Z_GYRO_OUT > ZG_ALM_MAGN.
11: ΔZ_GYRO_OUT > ZG_ALM_MAGN (see Equation 3).
Y-axis gyroscope. 0: alarm is off, and 1: alarm is on.
Not used.
0x03 0x20, 0x21
0x0000 R/W Yes
Solving for ΔX_ACCL_OUT, ΔZ_GYRO_OUT,
ΔY_GYRO_OUT, and ΔX_GYRO_OUT
7
Use Equation 2 to Equation 5 to solve for ΔX_ACCL_OUT,
ΔZ_GYRO_OUT, ΔY_GYRO_OUT, and ΔX_GYRO_OUT in
Bits[13:12], Bits[9:8], Bits[5:4], and Bits[1:0] in Table 159.
6
[5:4]
Y-axis gyroscope polarity and mode settings. Select
one of the four options for the condition that triggers
the alarm (ALM_STS, Bit 1 = 1, see Table 24).
00: Y_GYRO_OUT < YG_ALM_MAGN.
01: ΔY_GYRO_OUT < YG_ALM_MAGN (see Equation 4).
10: Y_GYRO_OUT > YG_ALM_MAGN.
7
7
1
8
ΔX_ACCL_OUT =
X
n −
A ( )
X
n −104
(2)
(
)
∑
∑
A
n = 0
n = 0
where XA = X_ACCL_OUT.
11: ΔY_GYRO_OUT > YG_ALM_MAGN (see Equation 4).
Rev. 0 | Page 30 of 38
Data Sheet
ADIS16486
Alarm Example
Bits
3
Description (Default = 0x0000)
X-axis gyroscope. 0: alarm is off, and 1: alarm is on.
Not used.
Use the following sequence to configure the x-axis gyroscopes
alarm to be active (ALM_STS, Bit 0 = 1) when the rate of
rotation around the x-axis exceeds 100°/sec:
2
1:0
X-axis gyroscope polarity and mode settings. Select
one of the four options for the condition that triggers
the alarm flag (ALM_STS, Bit 0 = 1, see Table 24).
00: X_GYRO_OUT < XG_ALM_MAGN.
01: ΔX_GYRO_OUT < XG_ALM_MAGN (see Equation 5).
10: X_GYRO_OUT > XG_ALM_MAGN.
1. Select Page 3 (DIN = 0x8003).
2. Set XG_ALM_MAGN, Bits[7:0] = 0x88 (DIN = 0xA888).
3. Set XG_ALM_MAGN, Bits[15:8] = 0x13 (DIN = 0xA913).
4. Set ALM_CNFG_1, Bits[7:0] = 0x0C (DIN = 0xA00C).
5. Set ALM_CNFG_1, Bits[15:8] = 0x00 (DIN = 0xA100).
11: ΔX_GYRO_OUT > XG_ALM_MAGN (see Equation 5).
The value for the XG_ALM_MAGN register is 0x1388, as
shown in the equation
Table 160. ALM_CNFG_1 Register Definition
Page ID Addresses Default Access Flash Backup
0x03 0x22, 0x23 0x0000 R/W Yes
100°/sec ÷ 0.02°/sec/LSB = 5000 LSB = 0x1388
Y-Axis Gyroscope Alarm, YG_ALM_MAGN
Table 161. ALM_CNFG_1 Bit Definitions
Bits Description (Default = 0x0000)
[15:8] Not used.
The YG_ALM_MAGN register (see Table 164 and Table 165)
contains the alarm threshold for the y-axis gyroscope when
ALM_CNFG_0, Bit 7 = 1 (see Table 159). This alarm is associated
with the alarm flag in ALM_STS, Bit 1 (see Table 24).
7
Z-axis accelerometer. 0: alarm is off, and 1: alarm is on.
Not used.
6
[5:4]
Z-axis accelerometer polarity and mode settings. Select
one of the four options for the condition that triggers
the alarm (ALM_STS, Bit 5 = 1, see Table 24).
Table 164. YG_ALM_MAGN Register Definition
Page ID
Addresses
Default
Access
Flash Backup
0x03
0x2A, 0x2B
0x0000
R/W
Yes
00: Z_ACCL_OUT < ZA_ALM_MAGN.
01: ΔZ_ACCL_OUT < ZA_ALM_MAGN (see Equation 6).
10: Z_ACCL_OUT > ZA_ALM_MAGN.
Table 165. YG_ALM_MAGN Bit Definition
Bits Description (Default = 0x0000)
11: ΔZ_ACCL_OUT > ZA_ALM_MAGN (see Equation 6).
Z-axis accelerometer mode. 0: static, and 1: dynamic.
Y-axis accelerometer. 0: alarm is off, and 1: alarm is on.
Not used.
[15:0] Y-axis gyroscope alarm threshold settings, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
4
3
Z-Axis Gyroscope Alarm, ZG_ALM_MAGN
2
The ZG_ALM_MAGN register (see Table 166 and Table 167)
contains the alarm threshold for the z-axis gyroscope when
ALM_CNFG_0, Bit 11 = 1 (see Table 159). This alarm is associated
with the alarm flag in ALM_STS, Bit 2 (see Table 24).
[1:0]
Y-axis accelerometer polarity and mode settings. Select
one of the four options for the condition that triggers
the alarm (ALM_STS, Bit 4 = 1, see Table 24).
00: Y_ACCL_OUT < YA_ALM_MAGN.
01: ΔY_ACCL_OUT < YA_ALM_MAGN (see Equation 7).
10: Y_ACCL_OUT > YA_ALM_MAGN.
11: ΔY_ACCL_OUT > YA_ALM_MAGN (see Equation 7).
Table 166. ZG_ALM_MAGN Register Definition
Page ID
Addresses
Default
Access
Flash Backup
0x03
0x2C, 0x2D
0x0000
R/W
Yes
X-Axis Gyroscope Alarm, XG_ALM_MAGN
Table 167. ZG_ALM_MAGN Bit Definition
Bits Description (Default = 0x0000)
The XG_ALM_MAGN register (see Table 162 and Table 163)
contains the alarm threshold for the x-axis gyroscope when
ALM_CNFG_0, Bit 3 = 1 (see Table 159). This alarm is associated
with the alarm flag in ALM_STS, Bit 0 (see Table 24).
[15:0] Z-axis gyroscope alarm threshold settings, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
X-Axis Accelerometer Alarm, XA_ALM_MAGN
Table 162. XG_ALM_MAGN Register Definition
The XA_ALM_MAGN register (see Table 168 and Table 169)
contains the alarm threshold for the x-axis accelerometer when
ALM_CNFG_0, Bit 15 = 1 (see Table 159). This alarm is associated
with the alarm flag in ALM_STS, Bit 3 (see Table 24).
Page ID
Addresses
Default
Access
Flash Backup
0x03
0x28, 0x29
0x0000
R/W
Yes
Table 163. XG_ALM_MAGN Bit Definition
Bits Description (Default = 0x0000)
[15:0] X-axis gyroscope alarm threshold settings, twos
complement, 0°/sec = 0x0000, 1 LSB = 0.02°/sec
Table 168. XA_ALM_MAGN Register Definition
Page ID
Addresses
Default
Access
Flash Backup
0x03
0x2E, 0x2F
0x0000
R/W
Yes
Table 169. XA_ALM_MAGN Bit Definition
Bits
Description (Default = 0x0000)
[15:0]
X-axis accelerometer alarm threshold settings, twos
complement, 0 g = 0x0000, 1 LSB = 0.8 mg
Rev. 0 | Page 31 of 38
ADIS16486
Data Sheet
by FIRM_DM, Bits[15:8] = 0x11. FIRM_DM, Bits[7:4] and
Y-Axis Accelerometer Alarm, YA_ALM_MAGN
FIRM_DM, Bits[3:0] contain digits that represent the day of
factory configuration in a BCD format. For example, the 27th day
of the month is represented by FIRM_DM, Bits[7:0] = 0x27.
The YA_ALM_MAGN register (see Table 170 and Table 171)
contains the alarm threshold for the y-axis accelerometer when
ALM_CNFG_1, Bit 3 = 1 (see Table 161). This alarm is associated
with the alarm flag in ALM_STS, Bit 4 (see Table 24).
Table 176. FIRM_DM Register Definition
Page ID Addresses Default
Access Flash Backup
Table 170. YA_ALM_MAGN Register Definition
0x03 0x7A, 0x7B Not applicable
R
Yes
Page ID
Addresses
Default
Access
Flash Backup
0x03
0x30, 0x31
0x0000
R/W
Yes
Table 177. FIRM_DM Bit Definitions
Bits
Description (No Default)
Table 171. YA_ALM_MAGN Bit Definition
[15:12]
Factory configuration month BCD code, tens digit,
numerical format = 4-bit binary, range = 0 to 2
Bits
Description (Default = 0x0000)
[15:0]
Y-axis accelerometer alarm threshold settings, twos
[11:8]
[7:4]
[3:0]
Factory configuration month BCD code, ones digit,
numerical format = 4-bit binary, range = 0 to 9
complement, 0 g = 0x0000, 1 LSB = 0.8 mg
Z-Axis Accelerometer Alarm, ZA_ALM_MAGN
Factory configuration day BCD code, tens digit,
numerical format = 4-bit binary, range = 0 to 3
The ZA_ALM_MAGN register (see Table 172 and Table 173)
contains the alarm threshold for the z-axis accelerometer when
ALM_CNFG_1, Bit 7 = 1 (see Table 161). This alarm is associated
with the alarm flag in ALM_STS, Bit 5 (see Table 24).
Factory configuration day BCD code, ones digit,
numerical format = 4-bit binary, range = 0 to 9
Firmware Revision Year, FIRM_Y
The FIRM_Y register (see Table 178 and Table 179) contains
the year of the factory configuration date. For example, the
year, 2013, is represented by FIRM_Y = 0x2013.
Table 172. ZA_ALM_MAGN Register Definition
Page ID
Addresses
Default
Access
Flash Backup
0x03
0x32, 0x33
0x0000
R/W
Yes
Table 178. FIRM_Y Register Definition
Page ID Addresses Default
Table 173. ZA_ALM_MAGN Bit Definition
Access Flash Backup
Bits
Description (Default = 0x0000)
0x03 0x7C, 0x7D Not applicable
R
Yes
[15:0]
Z-axis accelerometer alarm threshold settings, twos
complement, 0 g = 0x0000, 1 LSB = 0.8 mg
Table 179. FIRM_Y Bit Definitions
Firmware Revision, FIRM_REV
Bits
Description (No Default)
The FIRM_REV register (see Table 174 and Table 175) provides
the firmware revision for the internal firmware. This register
uses a binary coded decimal (BCD) format, where each nibble
represents a digit. For example, if FIRM_REV = 0x1234, the
firmware revision is 12.34.
[15:12]
Factory configuration year BCD code, thousands digit,
numerical format = 4-bit binary, range = 0 to 9
[11:8]
[7:4]
[3:0]
Factory configuration year BCD code, hundreds digit,
numerical format = 4-bit binary, range = 0 to 9
Factory configuration year BCD code, tens digit,
numerical format = 4-bit binary, range = 0 to 3
Table 174. FIRM_REV Register Definition
Factory configuration year BCD code, ones digit,
numerical format = 4-bit binary, range = 0 to 9
Page ID Addresses Default
Access Flash Backup
0x03 0x78, 0x79 Not applicable
R
Yes
Boot Revision Number, BOOT_REV
Table 180. BOOT_REV Register Definition
Table 175. FIRM_REV Bit Definitions
Bits Description (No Default)
Page ID Addresses Default
Access Flash Backup
0x03 0x7E, 0x7F Not applicable
R
Yes
[15:12] Firmware revision BCD code, tens digit, numerical
format = 4-bit binary, range = 0 to 9
Table 181. BOOT_REV Bit Definitions
[11:8]
[7:4]
[3:0]
Firmware revision BCD code, ones digit, numerical
format = 4-bit binary, range = 0 to 9
Bits
Description (No Default)
[15:8]
[7:0]
Binary, major revision number
Binary, minor revision number
Firmware revision BCD code, tenths digit, numerical
format = 4-bit binary, range = 0 to 9
Firmware revision BCD code, hundredths digit,
numerical format = 4-bit binary, range = 0 to 9
Continuous SRAM Testing
This device employs a CRC function on the SRAM memory blocks
that contain the program code (CODE_SIGTR_xxx) and the
calibration coefficients (CAL_DRVTN_xxx). This process operates
in the background and generates real-time 32-bit CRC values for
the program code and calibration coefficients, respectively. At
the conclusion of each cycle, the processor writes these calculated
Firmware Revision Day and Month, FIRM_DM
The FIRM_DM register (see Table 176 and Table 177) contains the
month and day of the factory configuration date. FIRM_DM,
Bits[15:12] and FIRM_DM, Bits[11:8] contain digits that represent
the month of the factory configuration in a BCD format. For
example, November is the 11th month in a year and is represented
Rev. 0 | Page 32 of 38
Data Sheet
ADIS16486
values in the CAL_SIGTR_xxx and CODE_DRVTN_xxx registers
(see Table 187, Table 189, Table 195, and Table 197) and compares
them with the signature values, which reflect the state of these
memory locations at the time of factory configuration. When the
calculation results do not match the signature values, SYS_E_
FLAG, Bit 2 increases to a 1. The respective signature values are
available for user access through the CAL_SIGTR_xxx and
CODE_DRVTN_xxx registers (see Table 183, Table 185, Table
191, and Table 193). The following conditions must be met for
SYS_E_FLAG, Bit 2 to remain at 0:
Signature CRC, Program Code, CODE_SIGTR_LWR
Table 190. CODE_SIGTR_LWR Register Definition
Page ID Addresses Default Access Flash Backup
0x04 0x0C, 0x0D Not applicable Yes
R
Table 191. CODE_SIGTR_LWR Bit Definition
Bits Description (No Default)
[15:0] Factory programmed CRC value for the calibration
coefficients, low word
Signature CRC, Program Code, CODE_SIGTR_UPR
•
•
•
•
CAL_SIGTR_LWR = CAL_DRVTN_LWR
CAL_SIGTR_UPR = CAL_DRVTN_UPR
CODE_SIGTR_LWR = CODE_DRVTN_LWR
CODE_SIGTR_UPR = CODE_DRVTN_UPR
Table 192. CODE_SIGTR_UPR Register Definition
Page ID Addresses Default
Access Flash Backup
0x04 0x0E, 0x0F Not applicable
R
Yes
Signature CRC, Calibration Values, CAL_SIGTR_LWR
Table 193. CODE_SIGTR_UPR Bit Definition
Bits Description (No Default)
[15:0] Factory programmed CRC value for the calibration
coefficients, high word
Table 182. CAL_SIGTR_LWR Register Definition
Page ID Addresses Default
Access Flash Backup
0x04 0x04, 0x05 Not applicable
R
Yes
Derived CRC, Program Code, CODE_DRVTN_LWR
Table 183. CAL_SIGTR_LWR Bit Definition
Bits Description (No Default)
Table 194. CODE_DRVTN_LWR Register Definition
Page ID Addresses Default
Access Flash Backup
[15:0] Factory programmed CRC value for the program code,
low word
0x04 0x10, 0x11 Not applicable
R
No
Signature CRC, Calibration Values, CAL_SIGTR_UPR
Table 195. CODE_DRVTN_LWR Bit Definition
Bits Description (No Default)
Table 184. CAL_SIGTR_UPR Register Definition
[15:0] Calculated CRC value for the calibration coefficients, low
word
Page ID Addresses Default
Access Flash Backup
0x04 0x06, 0x07 Not applicable
R
Yes
Derived CRC, Program Code, CODE_DRVTN_UPR
Table 185. CAL_SIGTR_UPR Bit Definition
Bits Description (No Default)
Table 196. CODE_DRVTN_UPR Register Definition
Page ID Addresses Default
Access Flash Backup
[15:0] Factory programmed CRC value for the program code,
high word
0x04 0x12, 0x13 Not applicable
R
No
Derived CRC, Calibration Values, CAL_DRVTN_LWR
Table 197. CODE_DRVTN_UPR Bit Definition
Bits Description (No Default)
Table 186. CAL_DRVTN_LWR Register Definition
[15:0] Calculated CRC value for the calibration coefficients,
high word
Page ID Addresses Default
Access Flash Backup
0x04 0x08, 0x09 Not applicable
R
No
Lot Specific Serial Number, SERIAL_NUM
Table 187. CAL_DRVTN_LWR Bit Definition
Bits Description (No Default)
Table 198. SERIAL_NUM Register Definition
Page ID Addresses Default
Access Flash Backup
[15:0] Calculated CRC value for the program code, low word
Derived CRC, Calibration Values, CAL_DRVTN_UPR
Table 188. CAL_DRVTN_UPR Register Definition
0x04 0x20, 0x21 Not applicable
R
Yes
Table 199. SERIAL_NUM Bit Definition
Bits
Description (No Default)
Page ID Addresses Default
Access Flash Backup
[15:0]
Lot specific serial number
0x04 0x0A, 0x0B Not applicable
R
No
Table 189. CAL_DRVTN_UPR Bit Definition
Bits Description (No Default)
[15:0] Calculated CRC value for the program code, high word
Rev. 0 | Page 33 of 38
ADIS16486
Data Sheet
Use the following sequence to set the FIR_COEF_A071 register
to a decimal value of −169 (0xFF57):
FIR FILTERS
The ADIS16486 has four user configurable FIR filter banks. The
sample rate of the FIR filter banks is identical to the IMU
sample rate. Because decimation occurs after the FIR filters, the
FIR sample rate is independent of the decimation rate and not
affected by the setting of the DEC_RATE register. If the user
selects the internally generated sample clock (which is the
default setting), the nominal IMU sample rate (and FIR sample
rate) is 2460 SPS. If the user supplies an external clock by setting
Bit 7 to 1 of the FNCTIO_CRTL register (see Table 142 and
Table 143), the FIR sample rate is the same frequency as the
input synchronization clock provided to the ADIS16486.
1. Select Page 6 (DIN = 0x8006).
2. Set FIR_COEF_A071, Bits[7:0] = 0x57 (DIN = 0x9E57).
3. Set FIR_COEF_A071, Bits[15:8] = 0xFF (DIN = 0x9FFF).
FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119
Table 203. Filter Bank B Memory Map
Page
Page ID
Address
Register
PAGE_ID
Not used
7
7
0x07
0x07
0x00
0x02 to
0x07
7
7
7
0x07
0x07
0x07
0x08
0x0A
0x0C to
0x7C
FIR_COEF_B000
FIR_COEF_B001
FIR_COEF_B002 to
FIR_COEF_B058
The user can individually configure and select one of the four FIR
filter banks for each individual inertial sensor using the FILTR_
BNK_0 (see Table 155) and FILTR_BNK_1 (see Table 157)
registers (see Figure 24). Each FIR filter bank (A, B, C, D) has
120 taps that consume two pages of memory. The coefficient
associated with each tap in each filter bank has its own
dedicated register that uses a 16-bit, twos complement format.
The FIR filter has unity gain when the sum of all of the coefficients
is equal to 32,768. For filter designs that require fewer than 120
taps, write 0x0000 to all unused registers to eliminate the
latency associated with that particular tap.
7
8
8
0x07
0x08
0x08
0x7E
0x00
0x02 to
0x07
FIR_COEF_B059
PAGE_ID
Not used
8
8
8
0x08
0x08
0x08
0x08
0x0A
0x0C to
0x7C
FIR_COEF_B060
FIR_COEF_B061
FIR_COEF_B062 to
FIR_COEF_B118
8
0x08
0x7E
FIR_COEF_B119
FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119
FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119
Table 201 and Table 202 offer detailed register and bit definitions
for FIR_COEF_A071, one of the FIR coefficient registers in
Bank A (see Table 200).
Table 204. Filter Bank C Memory Map
Page
Page ID
Address
Register
PAGE_ID
Not used
9
9
0x09
0x09
0x00
0x02 to
0x07
Table 200. FIR Filter Bank A Memory Map
Page Page ID
Address
Register
5
5
5
5
5
0x05
0x05
0x05
0x05
0x05
0x00
0x02 to 0x07
0x08
0x0A
0x0C to 0x7C
PAGE_ID
Not used
FIR_COEF_A000
FIR_COEF_A001
FIR_COEF_A002 to
FIR_COEF_A058
9
9
9
0x09
0x09
0x09
0x08
0x0A
0x0C to
0x7C
FIR_COEF_C000
FIR_COEF_C001
FIR_COEF_C002 to
FIR_COEF_C058
9
10
10
0x09
0x0A
0x0A
0x7E
0x00
0x02 to
0x07
FIR_COEF_C059
PAGE_ID
Not used
5
6
6
6
6
6
0x05
0x06
0x06
0x06
0x06
0x06
0x7E
0x00
0x02 to 0x07
0x08
0x0A
FIR_COEF_A059
PAGE_ID
Not used
FIR_COEF_A060
FIR_COEF_A061
FIR_COEF_A062 to
FIR_COEF_A118
10
10
10
0x0A
0x0A
0x0A
0x08
0x0A
0x0C to
0x7C
FIR_COEF_C060
FIR_COEF_C061
FIR_COEF_C062 to
FIR_COEF_C118
0x0C to 0x7C
10
0x0A
0x7E
FIR_COEF_C119
6
0x06
0x7E
FIR_COEF_A119
Table 201. FIR_COEF_A071 Register Definition
Page ID Addresses Default Access Flash Backup
0x1E, 0x1F Not applicable R/W Yes
0x06
Table 202. FIR_COEF_A071 Bit Definition
Bits
Description (No Default)
[15:0]
FIR Bank A, Coefficient 71, twos complement
Rev. 0 | Page 34 of 38
Data Sheet
ADIS16486
FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119
Table 206. FIR Filter Descriptions, Default Configuration
FIR Filter Bank
Taps
120
120
32
−3 dB Frequency (Hz)
Table 205. Filter Bank D Memory Map
A
B
C
D
310
55
275
63
Page
Page ID
Address
Register
PAGE_ID
Not used
11
0x0B
0x00
11
0x0B
0x02 to
0x07
32
11
11
11
0x0B
0x0B
0x0B
0x08
0x0A
0x0C to
0x7C
FIR_COEF_D000
FIR_COEF_D001
FIR_COEF_D002 to
FIR_COEF_D058
0
–10
NO FIR
FILTERING
–20
B
D
A
C
–30
–40
–50
–60
–70
–80
–90
11
12
12
0x0B
0x0C
0x0C
0x7E
0x00
0x02 to
0x07
0x08
0x0A
0x0C to
0x7C
FIR_COEF_D059
PAGE_ID
Not used
12
12
12
0x0C
0x0C
0x0C
FIR_COEF_D060
FIR_COEF_D061
FIR_COEF_D062 to
FIR_COEF_D118
–100
0
12
0x0C
0x7E
FIR_COEF_D119
200
400
600
800
1000
1200
FREQUENCY (Hz)
Default Filter Performance
Figure 30. FIR Filter Frequency Response Curves
The FIR filter banks have factory programmed filter designs. They
are all low-pass filters that have unity dc gain. Table 206 provides a
summary of each filter design, and Figure 30 shows the frequency
response characteristics. The phase delay is equal to ½ of the total
number of taps.
Rev. 0 | Page 35 of 38
ADIS16486
Data Sheet
APPLICATIONS INFORMATION
39.600 BSC
19.800 BSC
MOUNTING BEST PRACTICES
For the best performance, follow these rules when installing the
ADIS16486 into a system:
PASSTHROUGH HOLE
FOR MOUNTING SCREWS
DIAMETER OF THE HOLE
MUST ACCOMODATE
DIMENSIONAL TOLERANCE
BETWEEN THE CONNECTOR
AND HOLES.
•
•
•
Eliminate the opportunity for translational force (x-axis
and y-axis direction, per Figure 18) application on the
electrical connector.
Isolate the mounting force to the four corners on the
portion of the package surface that surrounds the
mounting holes.
DEVICE
OUTLINE
0.560 BSC 2×
ALIGNMENT HOLES
FOR MATING SOCKET
Use uniform mounting forces on all four corners. The
suggested torque setting is 40 inch ounces (0.285 Nm).
These three rules help prevent irregular force profiles that can
warp the package and introduce bias errors in the sensors.
Figure 33 provides an example that leverages washers to set the
package off the mounting surface and uses 2.85 mm passthrough
holes and backside washers and nuts for attachment. Figure 31
and Figure 32 provide details for mounting hole and connector
alignment pin drill locations.
5 BSC
5 BSC
NOTES
1. ALL DIMENSIONS IN mm UNITS.
2. IN THIS CONFIGURATION, THE CONNECTOR IS FACING DOWN AND
ITS PINS ARE NOT VISIBLE.
Figure 31. Suggested PCB Layout Pattern, Connector Down
0.4334 [11.0]
0.019685
For more information on mounting the ADIS16486, see the
AN-1295 Application Note.
[0.5000]
(TYP)
0.0240 [0.610]
0.054 [1.37]
0.1800
[4.57]
0.0394 [1.00]
0.0394 [1.00]
0.022±
DIA (TYP)
NONPLATED
THRU HOLE 2×
0.022 DIA THRU HOLE (TYP)
NONPLATED THRU HOLE
Figure 32. Suggested Layout and Mechanical Design When Using
Samtec CLM-112-02-G-D-A for the Mating Connector
MOUNTING SCREWS
M2 × 0.4mm, 4×
WASHERS (OPTIONAL)
M2, 4×
ADIS16486
SPACERS/WASHERS
SUGGESTED, 4×
PCB
MATING CONNECTOR
CLM-112-02
PASS-THROUGH HOLES
DIAMETER ≥ 2.85mm
WASHERS (OPTIONAL)
M2, 4×
NUTS
M2 × 0.4mm, 4×
Figure 33. Mounting Example
Rev. 0 | Page 36 of 38
Data Sheet
ADIS16486
T
EVALUATION TOOLS
VDD
Breakout Board, ADIS16IMU1/PCBZ
1
The ADIS16IMU1/PCBZ (sold separately) provides a breakout
board function for the ADIS16486, providing access to the
ADIS16486 through larger connectors that support standard
1 mm ribbon cabling. This breakout board also provides four
mounting holes for attaching the ADIS16486 to the breakout
board. See the Ordering Guide for ordering details.
CURRENT
PC-Based Evaluation, EVAL-ADIS2
4
The EVAL-ADIS2 provides the system support PC-based
evaluation of the ADIS16486.
CH1 2.00V
100ms/DIV
CH4 100mA Ω
POWER SUPPLY CONSIDERATIONS
Figure 34. Transient Current Demand, Startup
The VDD power supply must charge 24 µF of capacitance (inside
of the ADIS16486, across the VDD pins and GND pins) during
the initial ramp and settling process of the power supply. When
VDD reaches 2.85 V, the ADIS16486 begins its internal start-up
process, which generates additional transient current demand.
See Figure 34 for a typical current profile during the start-up
process. The first peak in Figure 34 relates to charging the 24 µF
capacitor bank, whereas the second peak (~360 ms after the first
peak) relates to the initialization process of the ADIS16486. See
Figure 35 for a close view of the current profile associated with
the second peak in Figure 34.
T
CURRENT
4
CH4 100mA Ω
1ms/DIV
Figure 35. Transient Current Demand, Peak Demand
X-RAY SENSITIVITY
Exposure to high dose rate X-rays, such as those in production
systems that inspect solder joints in electronic assemblies, can
affect accelerometer bias errors. For optimal performance,
avoid exposing the ADIS16486 to this type of inspection.
Rev. 0 | Page 37 of 38
ADIS16486
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
44.254
44.000
39.854
39.600
39.346
43.746
2.20 BSC
(8 PLACES)
20.10
19.80
19.50
Ø 2.40 BSC
(4 PLACES)
DETAIL A
15.00
BSC
1.942
1.642
1.342
PIN 1
8.25
BSC
42.854
42.600
42.346
1.00 BSC
47.254
47.000
46.746
DETAIL A
BOTTOM VIEW
FRONT VIEW
14.254
14.000
13.746
DETAIL B
6.50 BSC
3.454
3.200
2.946
5.50
BSC
5.50
BSC
2.84 BSC
1.00 BSC
PITCH
0.30 SQ BSC
DETAIL B
Figure 36. 24-Lead Module with Connector Interface [MODULE]
(ML-24-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADIS16486BMLZ-P
ADIS16IMU1/PCBZ
EVAL-ADIS2Z
−40°C to +105°C
24-Lead Module with Connector Interface [MODULE]
Breakout Board
EVAL-ADIS2 Evaluation System
ML-24-6
1 Z = RoHS Compliant Part.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23373-1/21(0)
www.analog.com/ADIS16486 (Rev. 0)
Rev. 0 | Page 38 of 38
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