ADIS16505-3 [ADI]
Precision, Miniature MEMS IMU;型号: | ADIS16505-3 |
厂家: | ADI |
描述: | Precision, Miniature MEMS IMU |
文件: | 总41页 (文件大小:801K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Precision, Miniature MEMS IMU
Data Sheet
ADIS16505
FEATURES
GENERAL DESCRIPTION
Triaxial, digital gyroscope
The ADIS16505 is a precision, miniature microelectromechanical
system (MEMS) inertial measurement unit (IMU) that includes
a triaxial gyroscope and a triaxial accelerometer. Each inertial
sensor in the ADIS16505 combines with signal conditioning
that optimizes dynamic performance. The factory calibration
characterizes each sensor for sensitivity, bias, alignment,
linear acceleration (gyroscope bias), and point of percussion
(accelerometer location). As a result, each sensor has dynamic
compensation formulas that provide accurate sensor
12ꢀ°/sec, ꢀ00°/sec, 2000°/sec dynamic range models
2.3°/hr in-run bias stability (ADIS16ꢀ0ꢀ-1)
0.13°/√hr angular random walk, x-axis and y-axis, 1 σ
(ADIS16ꢀ0ꢀ-1)
0.2ꢀ° axis to axis misalignment error
Triaxial, digital accelerometer, 78.4 m/secꢁ dynamic range
26.ꢀ μm/secꢁ in-run bias stability (x-axis and y-axis)
Triaxial, delta angle and delta velocity outputs
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +8ꢀ°C
SPI compatible data communications
measurements over a broad set of conditions.
The ADIS16505 provides a simplified, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation
systems. The serial peripheral interface (SPI) and register
structure provide a simple interface for data collection and
configuration control.
Programmable operation and control
Automatic and manual bias correction controls
Data ready indicator for synchronous data acquisition
External sync modes: direct, scaled, and output
On demand self-test of inertial sensors
On demand self-test of flash memory
Single-supply operation (VDD): 3.0 V to 3.6 V
14,700 m/sec2 mechanical shock survivability
Operating temperature range: −40°C to +10ꢀ°C
The ADIS16505 is available in a 100-ball, ball grid array (BGA)
package that is approximately 15 mm × 15 mm × 5 mm.
APPLICATIONS
Navigation, stabilization, and instrumentation
Unmanned and autonomous vehicles
Smart agriculture and construction machinery
Factory/industrial automation, robotics
Virtual/augmented reality
Internet of Moving Things
FUNCTIONAL BLOCK DIAGRAM
DR
RST
VDD
POWER
MANAGEMENT
GND
SELF TEST
INPUT/OUTPUT
OUTPUT
DATA
CS
TRIAXIAL
GYROSCOPE
REGISTERS
SCLK
DIN
CALIBRATION
TRIAXIAL
ACCELEROMETER
SPI
CONTROLLER
AND
FILTERS
USER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
DOUT
CLOCK
ADIS16505
SYNC
Figure 1.
Rev. B
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Tel: 781.329.4700 ©2019–2020 Analog Devices, Inc. All rights reserved.
Technical Support
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ADIS16505
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
SPI ................................................................................................ 17
Data Ready (DR) ........................................................................ 17
Reading Sensor Data.................................................................. 18
Burst Read Function.................................................................. 19
Latency......................................................................................... 21
Device Configuration ................................................................ 21
Memory Structure...................................................................... 21
User Register Memory Map.......................................................... 22
User Register Defintions ............................................................... 24
Gyroscope Data .......................................................................... 24
Delta Angles................................................................................ 28
Delta Velocity ............................................................................. 29
Calibration .................................................................................. 31
Applications Information ............................................................. 38
Assembly and Handling Tips ................................................... 38
Power Supply Considerations .................................................. 39
Evaluation Tools......................................................................... 39
Packaging and Ordering Information......................................... 41
Outline Dimensions................................................................... 41
Ordering Guide .......................................................................... 41
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Specifications .................................................................. 6
Absolute Maximum Ratings....................................................... 7
Thermal Resistance...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
Typical Performance Characteristics........................................... 11
Gyroscopes .................................................................................. 11
Accelerometers ........................................................................... 14
Theory of Operation ...................................................................... 15
Introduction................................................................................ 15
Clock Control ............................................................................. 15
Bartlett Window Filter............................................................... 16
Calibration................................................................................... 16
Decimation Filter ....................................................................... 16
Register Structure....................................................................... 16
REVISION HISTORY
7/2020—Rev. A to Rev. B
Deleted Table 111 and Table 112; Renumbered Sequentially........34
Deleted Bias Correction Update Section.........................................35
Changes to Table 113, Table 115, Table 117, Table 119, and
Table 121...................................................................................................36
Changes to Table 129 and Table 131........................................... 37
Changes to Figure 65 ..................................................................... 40
Changes to Table 1 ........................................................................... 3
Changes to Table 3 and Table 4...................................................... 7
Changes to Clock Control Section............................................... 15
Changes to Figure 44 and Figure 45 ............................................ 20
Changes to Table 9 ......................................................................... 23
Changes to Table 11....................................................................... 24
Changes to Table 102 and Table 106........................................... 33
Changes to Table 108 and Table 110........................................... 34
10/2019—Revision A: Initial Version
Rev. B | Page 2 of 41
Data Sheet
ADIS16505
SPECIFICATIONS
Case temperature (TC) = 25°C, VDD = 3.3 V, angular rate = 0°/sec, and dynamic range = 2000°/sec 1 g, unless otherwise noted. 1 g is
the acceleration due to gravity and assumed to be 9.8 m/sec2.
Table 1.
Parameter
Test Conditions/Comments
Min
125
500
2000
Typ
Max Unit
GYROSCOPES
Dynamic Range
ADIS16505-1
ADIS16505-2
ADIS16505-3
°/sec
°/sec
°/sec
Sensitivity
ADIS16505-1, 16-bit data format
ADIS16505-2, 16-bit data format
ADIS16505-3, 16-bit data format
ADIS16505-1, 32-bit data format
ADIS16505-2, 32-bit data format
ADIS16505-3, 32-bit data format
ADIS16505-1, −40°C ≤ TC ≤ +85°C, 1σ
ADIS16505-2, −40°C ≤ TC ≤ +85°C, 1σ
ADIS16505-3, −40°C ≤ TC ≤ +85°C, 1σ
Axis to axis, −40°C ≤ TC ≤ +85°C, 1 σ
ADIS16505-1, full scale (FS) = 125°/sec
ADIS16505-2, FS = 500°/sec
ADIS16505-3, FS = 2000°/sec
160
40
10
10,485,760
2,621,440
655,360
0.5
0.5
0.3
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
%
Error over Temperature
%
%
Misalignment Error1
Nonlinearity2
0.25
0.2
0.2
Degrees
%FS
%FS
0.2
%FS
Bias
Repeatability3
−40°C ≤ TC ≤ +85°C, 1 σ, x-axis and z-axis
−40°C ≤ TC ≤ +85°C, 1 σ, y-axis
ADIS16505-1, 1 σ, x-axis
ADIS16505-1, 1 σ, y-axis
ADIS16505-1, 1 σ, z-axis
ADIS16505-2, 1 σ, x-axis
ADIS16505-2, 1 σ, y-axis
ADIS16505-2, 1 σ, z-axis
ADIS16505-3, 1 σ, x-axis
ADIS16505-3, 1 σ, y-axis
ADIS16505-3, 1 σ, z-axis
ADIS16505-1, x-axis and y-axis, 1 σ
ADIS16505-1, z-axis, 1 σ
ADIS16505-2, x-axis and y-axis, 1 σ
ADIS16505-2, z-axis, 1 σ
ADIS16505-3, x-axis and y-axis, 1 σ
ADIS16505-3, z-axis, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ, x-axis and z-axis
−40°C ≤ TC ≤ +85°C, 1 σ, y-axis
X-axis, 1 σ
0.14
1.4
1.5
2.3
1.7
2.2
2.7
1.6
7.5
8.1
4.9
0.13
0.19
0.15
0.2
0.29
0.32
0.3
0.7
0.572 × 10−3
1.02 × 10−3
0.408 × 10−3
3.1 × 10−6
°/sec
°/sec
°/hr
°/hr
°/hr
°/hr
°/hr
°/hr
°/hr
°/hr
°/hr
°/√hr
°/√hr
°/√hr
°/√hr
°/√hr
°/√hr
°/sec
°/sec
(°/sec)/(m/sec2)
(°/sec)/(m/sec2)
(°/sec)/(m/sec2)
(°/sec)/(m/sec2)2
In-Run Bias Stability
Angular Random Walk
Error over Temperature
Linear Acceleration Effect
Y-axis, 1 σ
Z-axis, 1 σ
Vibration Rectified Error (VRE)
X-axis, random vibration, 19.6 m/sec2 rms,
50 Hz to 2 kHz
Y-axis, random vibration, 19.6 m/sec2 rms,
50 Hz to 2 kHz
Z-axis, random vibration, 19.6 m/sec2 rms,
50 Hz to 2 kHz
5.6 × 10−6
0.3 × 10−6
(°/sec)/(m/sec2)2
(°/sec)/(m/sec2)2
Rev. B | Page 3 of 41
ADIS16505
Data Sheet
Parameter
Test Conditions/Comments
No filtering, 1 σ, 25°C
Min
Typ
Max Unit
Output Noise
ADIS16505-1, x-axis, y-axis
ADIS16505-1, z-axis
ADIS16505-2, x-axis, y-axis
ADIS16505-2, z-axis
68 × 10−3
104 × 10−3
82 × 10−3
116 × 10−3
152 × 10−3
181 × 10−3
°/sec rms
°/sec rms
°/sec rms
°/sec rms
°/sec rms
ADIS16505-3, all axes
Rate Noise Density
Frequency = 10 Hz to 40 Hz
ADIS16505-1, x-axis and y-axis
ADIS16505-1, z-axis
ADIS16505-2, x-axis and y-axis
ADIS16505-2, z-axis
ADIS16505-3, x-axis and y-axis
ADIS16505-3, z axis
ADIS16505-1, ADIS16505-2, x-axis and y-axis
ADIS16505-1, ADIS16505-2, z-axis
ADIS16505-3, x-axis and y-axis
ADIS16505-3, z-axis
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
Hz
Hz
Hz
Hz
3.0 × 10−3
4.3 × 10−3
3.4 × 10−3
4.6 × 10−3
6.1 × 10−3
480
590
573
639
3 dB Bandwidth
Sensor Resonant Frequency
X-axis, y-axis
66
kHz
Z-axis
78
kHz
ACCELEROMETERS4
Dynamic Range
Sensitivity
Each axis
78.4
m/sec2
LSB/(m/sec2)
%
32-bit data format
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
26,756,268
0.07
0.1
Error over Temperature
Repeatability3
%
Misalignment Error
Nonlinearity
Axis to axis, −40°C ≤ TC ≤ +85°C, 1 σ
Best fit straight line, 19.6 m/sec2
Best fit straight line, 78.4 m/sec2, x-axis
0.05
0.25
0.5
Degrees
%FS
%FS
Best fit straight line, 78.4 m/sec2,
y-axis and z-axis
1.5
%FS
Bias
Repeatability3
In-Run Bias Stability
X-Axis and Y-Axis
Z-Axis
−40°C ≤ TC ≤ +85°C, 1 σ
1 σ
19.6 × 10−3
m/sec2
26.5 × 10−6
43.1 × 10−6
m/sec2
m/sec2
Velocity Random Walk
X-Axis and Y-Axis
Z-Axis
Error over Temperature
Output Noise
X-Axis and Y-Axis
Z-Axis
1 σ
0.009
0.012
9.8 × 10−3
m/sec/√hr
m/sec/√hr
m/sec2
−40°C ≤ TC ≤ +85°C, 1 σ
No filtering
4.8 × 10−3
6.07 × 10−3
m/sec2 rms
m/sec2 rms
Noise Density
X-Axis and Y-Axis
Z-Axis
3 dB Bandwidth
Sensor Resonant Frequency
f = 10 Hz to 40 Hz, no filtering
167 × 10−6
243 × 10−6
750
2.4
2.2
m/sec2/√Hz rms
m/sec2/√Hz rms
Hz
kHz
kHz
X-axis and y-axis
Z-axis
TEMPERATURE SENSOR
Scale Factor
Output = 0x0000 at 0°C ( 5°C)
0.1
°C/LSB
Rev. B | Page 4 of 41
Data Sheet
ADIS16505
Parameter
LOGIC INPUTS5
Input Voltage
High, VIH
Test Conditions/Comments
Min
Typ
Max Unit
2.0
1
V
Low, VIL
0.8
V
RST Pulse Width
Input Current
Logic 1, IIH
Logic 0, IIL
All Pins Except RST
μs
VIH = 3.3 V
VIL = 0 V
10
10
μA
μA
mA
pF
RST Pin
0.33
10
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Voltage
High, VOH
Low, VOL
Source current (ISOURCE) = 0.5 mA
Sink current (ISINK) = 2.0 mA
Endurance6
2.4
V
V
0.4
FLASH MEMORY
Data Retention7
10,000
20
Cycles
Years
TJ = 85°C
FUNCTIONAL TIMES8
Power-On Start-Up Time
Reset Recovery Time9
Factory Calibration Restore
Flash Memory Backup
Flash Memory Test Time
Self Test Time10
Time until data is available
310
255
136
70
30
24
ms
ms
ms
ms
ms
ms
SPS
%
GLOB_CMD, Bit 7 = 1 (see Table 112)
GLOB_CMD, Bit 1 = 1 (see Table 112)
GLOB_CMD, Bit 3 = 1 (see Table 112)
GLOB_CMD, Bit 4 = 1 (see Table 112)
GLOB_CMD, Bit 2 = 1 (see Table 112)
CONVERSION RATE
Initial Clock Accuracy
Sync Input Clock
2000
3
1.9
3.0
2.1
3.6
55
kHz
V
mA
POWER SUPPLY, VDD
Power Supply Current11
Operating voltage range
Normal mode, VDD = 3.3 V
44
1 Cross-axis sensitivity is the sine of this number.
2 This measurement is based on the deviation from a best fit linear model.
3 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of high temperature operating life (HTOL) at 105°C.
4 All specifications associated with the accelerometers relate to the full-scale range of 8 g, unless otherwise noted.
5 The digital input/output signals use a 3.3 V system.
6 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.
7 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
8 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.
9
RST
The
line must be in a low state for at least 10 ꢀs to ensure a proper reset initiation and recovery.
10 The self test time can extend when using external clock rates lower than 2000 Hz.
11 Power supply current transients can reach 100 mA during initial startup or reset recovery.
Rev. B | Page 5 of 41
ADIS16505
Data Sheet
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Burst Read Mode
Parameter
fSCLK
tSTALL
tREADRATE
tCS
Description
Min
0.1
16
24
200
Typ
Max
Min
Typ
Max
Unit
MHz
μs
μs
ns
Serial clock
Stall period between data
Read rate
2.1
0.1
N/A1
1.1
Chip select to SCLK edge
200
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times
DOUT rise/fall times
CS high after SCLK edge
25
25
ns
ns
ns
ns
ns
ns
μs
25
50
25
50
5
5
12.5
12.5
5
5
12.5
12.5
0
5
0
5
t1
Input sync positive pulse width; direct sync mode,
MSC_CTRL[3:2] = 01 (binary, see Table 106)
tSTDR
Input sync to data ready valid transition, no SPI traffic,
direct sync mode, MSC_CTRL[3:2] = 01 (binary, see Table 106)
Input sync to data ready valid transition, full SPI traffic2,
direct sync mode, MSC_CTRL[3:2] = 01 (binary, see Table 106)
Data invalid time
Input sync period
305
405
23
305
405
23
μs
μs
tNV
t2
μs
μs
500
500
1 N/A means not applicable.
2 Full SPI traffic is defined as a transfer of 64 16-bit registers using an SCLK frequency of 2 MHz. Reading the sensor values from the previous data sample proportionally
increases the tSTDR on the current cycle.
Timing Diagrams
CS
tSCLKR
tSCLKF
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
DOUT
tDAV
tDR
MSB
R/W
DB14
tDSU
DB13
A5
DB12
DB11
A3
DB10
tDF
DB2
DB1
LSB
LSB
tDHD
DIN
A6
A4
A2
D2
D1
Figure 2. SPI Timing and Sequence Diagram
tREADRATE
tSTALL
CS
SCLK
Figure 3. Stall Time and Data Rate Timing Diagram
t2
tSTDR
t1
SYNC
DR
tNV
Figure 4. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL[3:2] = 01 (Binary)
Rev. B | Page 6 of 41
Data Sheet
ADIS16505
THERMAL RESISTANCE
ABSOLUTE MAXIMUM RATINGS
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 3.
Parameter
Rating
Mechanical Shock Survivability
Any Axis, Unpowered, 0.5 ms ,
½ Sine.
The ADIS16505 is a multichip module that includes many
active components. The values in Table 4 identify the thermal
response of the hottest component inside of the ADIS16505,
with respect to the overall power dissipation of the module.
This approach enables a simple method for predicting the
temperature of the hottest junction, based on either ambient
or case temperature.
14,700 m/sec2
VDD to GND
−0.3 V to +3.6 V
−0.3 V to VDD + 0.2 V
−0.3 V to VDD + 0.2 V
Digital Input Voltage to GND
Digital Output Voltage to GND
Temperature Range
Calibration
Operating
Storage1
−40°C to +85°C
−40°C to +105°C
−65°C to +150°C
2 bar
For example, when the ambient temperature is 70°C, the hottest
junction temperature (TJ) inside of the ADIS16505 is 76.7°C.
Barometric Pressure
TJ = θJA × VDD × IDD + 70°C
TJ = 107.1°C/W × 3.3 V × 0.044 A + 70°C
TJ = 85.6°C
1 Extended exposure to temperatures that are lower than −40°C or higher
than +105°C can adversely affect the accuracy of the factory calibration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4. Package Characteristics
1
2
Package Type θJA
ML-100-13
107.1°C/W
θJC
Device Weight
74.7°C/W
<1.75 g
1 θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
2 θJC is the junction to case thermal resistance.
3 Thermal impedance values come from direct observation of the hottest
temperature inside of the ADIS16505 when it is attached to an FR4-08 PCB
that has two metal layers and has a thickness of 0.063 inches.
ESD CAUTION
Rev. B | Page 7 of 41
ADIS16505
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16505
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K1
A10
K
A1
Figure 5. Pin Assignments, Bottom View
Figure 6. Pin Assignments, Package Level View
Table 5. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
Mnemonic
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
GND
GND
GND
GND
NC
Type
Description
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Not applicable
Not applicable
Not applicable
Not applicable
Supply
Supply
Supply
Supply
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Supply
Not applicable
Not applicable
Not applicable
Supply
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
No Connection
No Connection
No Connection
No Connection
Power Ground
Power Ground
Power Ground
Power Ground
No Connection
No Connection
No Connection
No Connection
No Connection
Power Ground
Do Not Connect
No Connection
No Connection
Power Ground
Power Supply
No Connection
No Connection
No Connection
NC
NC
NC
NC
GND
DNC
NC
NC
GND
VDD
NC
NC
NC
Supply
Not applicable
Not applicable
Not applicable
C9
C10
Rev. B | Page 8 of 41
Data Sheet
ADIS16505
Pin No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
Mnemonic
NC
NC
GND
NC
NC
VDD
NC
NC
NC
NC
Type
Description
Not applicable
Not applicable
Supply
Not applicable
Not applicable
Supply
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Supply
No Connection
No Connection
Power Ground
No Connection
No Connection
Power Supply
No Connection
No Connection
No Connection
No Connection
No Connection
Power Ground
Power Supply
No Connection
No Connection
Power Ground
Power Ground
No Connection
No Connection
No Connection
Power Ground
No Connection
Reset
NC
GND
VDD
NC
Supply
Not applicable
Not applicable
Supply
NC
GND
GND
NC
NC
NC
GND
NC
RST
NC
GND
GND
NC
GND
NC
Supply
Not applicable
Not applicable
Not applicable
Supply
Not applicable
Input
E10
F1
F2
F3
F4
F5
F6
F7
F8
F9
Not applicable
Supply
Supply
Not applicable
Supply
Not applicable
Not applicable
Supply
No Connection
Power Ground
Power Ground
No Connection
Power Ground
No Connection
No Connection
Power Supply
Power Ground
SPI, Chip Select
No Connection
No Connection
SPI, Data Input
Power Supply
No Connection
No Connection
No Connection
Power Supply
No Connection
SPI, Data Output
No Connection
No Connection
SPI, Serial Clock
No Connection
Power Ground
No Connection
No Connection
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
NC
VDD
GND
CS
Supply
Input
NC
NC
DIN
GND
NC
NC
NC
VDD
NC
DOUT
NC
NC
SCLK
NC
GND
NC
NC
Not applicable
Not applicable
Input
Supply
Not applicable
Not applicable
Not applicable
Supply
Not applicable
Output
Not applicable
Not applicable
Input
Not applicable
Supply
Not applicable
Not applicable
Rev. B | Page 9 of 41
ADIS16505
Data Sheet
Pin No.
J1
J2
J3
J4
Mnemonic
NC
Type
Description
Not applicable
Supply
Input
Supply
Supply
No Connection
Power Ground
Sync (External Clock)
Power Supply
Power Supply
Data Ready
GND
SYNC
VDD
VDD
DR
J5
J6
Output
J7
J8
J9
GND
NC
NC
NC
GND
NC
GND
NC
NC
VDD
NC
GND
NC
Supply
Power Ground
No Connection
No Connection
No Connection
Power Ground
No Connection
Power Ground
No Connection
No Connection
Power Supply
No Connection
Power Ground
No Connection
No Connection
Not applicable
Not applicable
Not applicable
Supply
Not applicable
Supply
Not applicable
Not applicable
Supply
Not applicable
Supply
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
Not applicable
Not applicable
NC
Rev. B | Page 10 of 41
Data Sheet
ADIS16505
TYPICAL PERFORMANCE CHARACTERISTICS
GYROSCOPES
100
0.5
0.4
MEAN
MEAN + 1σ
X AXIS
Y AXIS
Z AXIS
MEAN + SIGMA
MEAN
MEAN – SIGMA
0.3
0.2
0.1
10
0
–0.1
–0.2
–0.3
–0.4
–0.5
1
–10
1
10
100
1k
10k
100k
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
INTEGRATION PERIOD, TAU (Seconds)
Figure 10. Gyroscope Bias Error vs. Temperature, ADIS16505-1,
All Axes
Figure 7. Gyroscope Allan Deviation, TC = 25°C, ADIS16505-1,
Plot Taken After 10 Hours of Settling Time
1.0
100
MEAN
MEAN + 1σ
MEAN + SIGMA
X AXIS
Y AXIS
Z AXIS
MEAN
0.8
MEAN – SIGMA
0.6
0.4
0.2
0
10
–0.2
1
–0.4
–0.6
–0.8
–1.0
–10
–60
–40
–20
0
20
40
60
80
100
–10
1
10
100
1k
10k
100k
TEMPERATURE (°C)
INTEGRATION PERIOD, TAU (Seconds)
Figure 11. Gyroscope Bias Error vs. Temperature, ADIS16505-2,
All Axes
Figure 8. Gyroscope Allan Deviation, TC = 25°C, ADIS16505-2,
Plot Taken After 10 Hours of Settling Time
0.5
100
MEAN + SIGMA
MEAN
MEAN + 1σ
X AXIS
Y AXIS
Z AXIS
MEAN
0.4
MEAN – SIGMA
0.3
0.2
0.1
0
10
–0.1
–0.2
–0.3
–0.4
–0.5
1
–10
–60
–40
–20
0
20
40
60
80
100
1
10
100
1k
10k
100k
TEMPERATURE (°C)
INTEGRATION PERIOD, TAU (Seconds)
Figure 12. Gyroscope Bias Error vs. Temperature, ADIS16505-3,
All Axes
Figure 9. Gyroscope Allan Deviation, TC = 25°C, ADIS16505-3,
Plot Taken After 10 Hours of Settling Time
Rev. B | Page 11 of 41
ADIS16505
Data Sheet
0.5
0.4
0.20
0.15
0.10
0.05
0
MEAN + SIGMA
MEAN
MEAN – SIGMA
MEAN + SIGMA
MEAN
MEAN – SIGMA
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.05
–0.10
–0.15
–0.20
–60
–40
–20
0
20
40
60
80
100
0
5
10
15
20
25
30
35
TEMPERATURE (°C)
POWER-ON TIME (Minutes)
Figure 13. Gyroscope Sensitivity Error vs. Temperature, ADIS16505-1,
All Axes
Figure 16. Gyroscope Bias Error vs. Power-On Time, TC = −40°C,
All Axes
1.0
0.20
MEAN + SIGMA
MEAN
MEAN – SIGMA
MEAN + SIGMA
MEAN
0.8
0.6
0.15
0.10
0.05
0
MEAN – SIGMA
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
–60
–40
–20
0
20
40
60
80
100
0
5
10
15
20
25
30
35
TEMPERATURE (°C)
POWER-ON TIME (Minutes)
Figure 14. Gyroscope Sensitivity Error vs. Temperature, ADIS16505-2,
All Axes
Figure 17. Gyroscope Bias Error vs. Power-On Time, TC = 25°C, All Axes
0.20
0.5
MEAN + SIGMA
MEAN + SIGMA
MEAN
MEAN – SIGMA
MEAN
0.4
MEAN – SIGMA
0.15
0.3
0.2
0.10
0.05
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.05
–0.10
–0.15
–0.20
–60
–40
–20
0
20
40
60
80
100
0
5
10
15
20
25
30
35
TEMPERATURE (°C)
POWER-ON TIME (Minutes)
Figure 15. Gyroscope Sensitivity Error vs. Temperature, ADIS16505-3,
All Axes
Figure 18. Gyroscope Bias Error vs. Power-On Time, TC = 85°C,
All Axes
Rev. B | Page 12 of 41
Data Sheet
ADIS16505
0.5
0.4
0.5
0.4
MEAN + SIGMA
MEAN
MEAN – SIGMA
MEAN + SIGMA
MEAN
MEAN – SIGMA
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
–60
–40
–20
0
20
40
60
80
100
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Axis to Axis Gyroscope Misalignment Error vs. Temperature,
All Axes, ADIS16505-1
Figure 21. Axis to Axis Gyroscope Misalignment Error vs. Temperature,
All Axes, ADIS16505-3
0.5
10
MEAN + SIGMA
0.4
0.3
MEAN
MEAN – SIGMA
0
–10
–20
–30
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
BARTLETT OFF
N = 1
N = 2
N = 3
N = 4
N = 5
N = 6
–40
–50
–60
–3dB
–60
–40
–20
0
20
40
60
80
100
1
10
100
FREQUENCY (Hz)
1k
TEMPERATURE (°C)
Figure 20. Axis to Axis Gyroscope Misalignment Error vs. Temperature,
All Axes, ADIS16505-2
Figure 22. Normalized Gyroscope Noise Density, All Axes, TC = 25°C
Rev. B | Page 13 of 41
ADIS16505
Data Sheet
ACCELEROMETERS
1k
0.20
0.15
0.10
0.05
0
MEAN
MEAN + 1σ
MEAN + SIGMA
MEAN
MEAN – SIGMA
X AXIS
Y AXIS
Z AXIS
100
–0.05
–0.10
–0.15
–0.20
10
0.1
1
10
100
1k
10k
100k
–60
–40
–20
0
20
40
60
80
100
INTEGRATION PERIOD (Seconds)
TEMPERATURE (°C)
Figure 23. Accelerometer Allan Deviation, TC = 25°C
Figure 26. Accelerometer Sensitivity Error vs. Temperature,
Hot to Cold, All Axes
40
MEAN + SIGMA
MEAN
MEAN – SIGMA
0.20
30
20
MEAN + SIGMA
MEAN
MEAN – SIGMA
0.15
0.10
0.05
0
10
0
–10
–20
–30
–40
–0.05
–0.10
–0.15
–0.20
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
–60
–40
–20
0
20
40
60
80
100
Figure 24. Accelerometer Bias Error vs. Temperature,
All Axes
TEMPERATURE (°C)
Figure 27. Accelerometer Axis to Axis Misalignment Error vs. Temperature
0.20
0.15
0.10
0.05
0
10
MEAN + SIGMA
MEAN
MEAN – SIGMA
0
–10
–20
–30
BARTLETT OFF
N = 1
N = 2
N = 3
N = 4
N = 5
N = 6
–0.05
–0.10
–0.15
–0.20
–40
–50
–60
–3dB
–60
–40
–20
0
20
40
60
80
100
1
10
100
FREQUENCY (Hz)
1k
TEMPERATURE (°C)
Figure 25. Accelerometer Sensitivity Error vs. Temperature,
Cold to Hot, All Axes
Figure 28. Accelerometer Normalized Noise Density
Rev. B | Page 14 of 41
Data Sheet
ADIS16505
THEORY OF OPERATION
Scaled Sync Mode
INTRODUCTION
Setting MSC_CTRL register, Bits[3:2] = 10 selects scaled sync
mode, which supports use of an external sync clock between
1 Hz and 128 Hz that can come from video systems or global
positioning systems (GPSs). When operating in scaled sync
mode, the frequency of the sample clock is equal to the product
of the external clock scale factor, KECSF (from the UP_SCALE
register, see Table 107 and Table 108), and the frequency of
the clock signal on the SYNC pin. As in input sync mode, the
ADIS16505 performs best when fSM is between 1900 Hz and
2100 Hz.
Figure 30 provides the basic signal chain for the accelerometers
and gyroscopes of the ADIS16505. When using the factory
default configuration, the ADIS16505 initializes itself at power-
up and automatically starts a continuous process of sampling,
processing, and loading calibrated sensor data into its output
registers at a rate of 2000 SPS.
CLOCK CONTROL
The ADIS16505 provides four modes of operation with respect
to the source of the sampling and processing clock (see the
frequency sampling clock (fSM) in Figure 30): internal, direct
input sync, scaled sync, and output sync. The MSC_CTRL
register, Bits[3:2] (see Table 105 and Table 106) provide user
selection of these modes.
Changes to the UP_SCALE register value resets the clock
multiplication phase-locked loop (PLL) and restarts the locking
process. The locking process starts with an input reference
clock edge resetting the feedback clock edge, and lock is declared
when time differences between these two edges is ≤100 ꢀs.
Note that changes to the MSC_CTRL[3:2] and UP_SCALE
registers are only updated for readback after the internal clock
configuration is complete. Therefore, the user must wait until
the DR pin toggles before attempting to verify the desired
settings by reading the values of these registers. Changes to
MSC_CTRL[9:6] may take up to 200 μs after writing to indicate
to the new value during readback. The external clock must also
be present for two external clock cycles if either direct input
sync mode or scaled sync mode is programmed.
For example, when using a 1 Hz input signal, set UP_SCALE =
0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of
2000 SPS for the inertial sensors and their signal processing.
Use the following sequence on the DIN pin to configure
UP_SCALE for this scenario: 0xE2D0, then 0xE307.
Output Sync Mode
When Register MSC_CTRL, Bits[3:2] = 11, the ADIS16505
operates in output sync mode, which is the same as internal
clock mode except that the SYNC pin pulses when the internal
processor collects data from the inertial sensors. Figure 29
provides an example of this signal.
Internal Clock Mode
Setting MSC_CTRL register, Bits[3:2] = 00 selects the internal
clock mode and is the default. In this mode, the ADIS16505
uses an internally generated clock that has a nominal frequency
of 2000 Hz to drive sampling and data processing for each
sensor and associated signal chain.
GYROSCOPE AND
ACCELEROMETER
DATA ACQUISITION
ACCELEROMETER
DATA ACQUISITION
Direct Input Sync Mode
SYNC
Setting MSC_CTRL register, Bits[3:2] = 01 selects direct input
sync mode and allows fSM to come directly from an external
clock to control the sensor sampling using the SYNC pin as an
input. When operating in input sync mode, the ADIS16505
performs best when the external clock frequency (fSYNC) is
between 1900 Hz and 2100 Hz.
250µs
500µs
Figure 29. Sync Output Signal, Register MSC_CTRL, Bits[3:2] = 11
fODR
BARTLETT
WINDOW
FILTER
OUTPUT
ACCELEROMETER/
GYROSCOPE
DIGITAL
FILTER
DECIMATION
FILTER
CALIBRATION
DATA
REGISTERS
SERIAL
PERIPHERAL
INTERFACE
SYNC PIN
CLOCK
CONTROL
fSM
CONTROL
REGISTERS
(fSYNC)
Figure 30. Sensor Signal Chain
Rev. B | Page 15 of 41
ADIS16505
Data Sheet
The factory calibration of the accelerometer applies the following
correction formulas to the data of each accelerometer:
BARTLETT WINDOW FILTER
The Bartlett window filter is a finite impulse response (FIR) filter
(see Figure 31) that contains two averaging filter stages in a
cascade configuration. The FILT_CTRL register (see Table 102)
provides the configuration controls for this filter.
bX
a
m11 m12
m
a
XC
13
X
aYC m21 m22 m23
aY bY
aZC
m31 m32 m33
aZ
bZ
2
XC
FROM
USER
CALIBRATION
N
N
TO AVERAGING
DECIMATING
FILTER
1
N
1
N
0
p12
p
Σ ω(n)
Σ ω(n)
13
n = 1
n = 1
p21
0
p23 Y2C
2
Figure 31. Bartlett Window FIR Filter Signal Path
p31 p32
0
ZC
CALIBRATION
where:
The inertial sensor calibration function for the gyroscopes and the
accelerometers has two components: factory calibration and
user calibration (see Figure 32).
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
aX, aY, and aZ are the accelerometer outputs (precalibration).
bX, bY, and bZ provide bias correction.
FROM
TO
BARTLETT
WINDOW
FIR FILTER
FACTORY
USER
AVERAGING
DECIMATING
FILTER
CALIBRATION
CALIBRATION
p12, p13, p21, p23, p31 and p32 provide a point of percussion
alignment correction (see Figure 59).
Figure 32. Inertial Sensor Calibration Processing
ω2XC, ω2YC, and ω2ZC are the square of the gyroscope outputs
(post calibration).
The factory calibration of the gyroscope applies the following
correction formulas to the data of each gyroscope:
All of the correction factors in this relationship come from
direct observation of the response of each accelerometer at
multiple temperatures, over the calibration temperature range
(−40°C ≤ TC ≤ +85°C). These correction factors are stored
in the flash memory bank but are not available for observation
or configuration. MSC_CTRL, Bit 6 (see Table 106) provides
the only user configuration option for the factory calibration of
the accelerometers: an on/off control for the point of percussion,
alignment function. See Figure 57 for more details on the user
calibration options available for the accelerometers.
bX
ω
m11 m12
m
ω
XC
13
X
ωYC m21 m22 m23
ωY bY
ωZC
m31 m32 m33
ωZ
bZ
l
l12
l
a
11
13
XC
l21 l22 l23 aYC
l31 l32 l33
aZC
where:
ωXC, ωYC, and ωZC are the gyroscope outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
ωX, ωY, and ωZ are the gyroscope outputs (precalibration).
bX, bY, and bZ provide bias correction.
DECIMATION FILTER
The second digital filter averages multiple samples together to
produce each register update. The number of samples in the
average is equal to the reduction in the update rate (fODR) for the
output data registers (see Figure 33). The DEC_RATE register
(see Table 110) provides the configuration controls for this filter.
l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear acceleration
correction
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
FROM
USER
N
1
N
TO OUTPUT
REGISTERS
Σ ω(n)
All of the correction factors in this relationship come from
direct observation of the response of each gyroscope at multiple
temperatures over the calibration temperature range (−40°C ≤
TC ≤ +85°C). These correction factors are stored in the flash
memory bank, but they are not available for observation or
configuration.
n = 1
CALIBRATION
÷N
Figure 33. Decimating Filter Diagram
REGISTER STRUCTURE
All communication between the ADIS16505 and an external
processor involves either reading the contents of an output
register or writing configuration/command information to a
control register. The output data registers include the latest
sensor data, error flags, and identification information. The
control registers include sample rate, filtering, calibration, and
diagnostic options. Each user accessible register has two bytes
(upper and lower), each of which has its own unique address.
See Table 9 for a detailed list of all user registers, along with
their addresses.
Register MSC_CTRL, Bit 7 (see Table 106) provides the only
user-configurable option for the factory calibration of the
gyroscopes: an on/off control for the linear acceleration
compensation. See Figure 56 for more details on the user
calibration options available for the gyroscopes.
Rev. B | Page 16 of 41
Data Sheet
ADIS16505
SPI
DATA READY (DR)
The SPI provides access to the user registers (see Table 9).
Figure 34 shows the most common connections between the
ADIS16505 and a SPI master device, which is often an
embedded processor that has a SPI-compatible interface. In this
example, the SPI master uses an interrupt service routine to
collect data every time the data ready (DR) signal pulses.
The factory default configuration provides users with a DR
signal on the DR pin (see Table 5), which pulses when the output
data registers are updating. Connect the DR pin to an input pin
on the embedded processor and configure this pin to trigger data
collection on the second edge of the pulse on the DR pin. The
MSC_CTRL register, Bit 0 (see Table 106), controls the polarity
of this signal. In Figure 35 shows a DR signal with
Additional information on the SPI can be found in the
Applications Information section.
Register MSC_CTRL, Bit 0 = 1, meaning that data collection
must start on the rising edges of the DR pulses.
INPUT/OUTPUT LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
+3.3V
VDD
DR
INACTIVE
ACTIVE
SYSTEM
Figure 35. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)
ADIS16505
PROCESSOR
SS
SCLK
MOSI
MISO
IRQ
CS
SPI MASTER
During the start-up and reset recovery processes, the DR signal
can exhibit some transient behavior before data production
begins. Figure 36 shows an example of the DR behavior during
startup, and Figure 37 and Figure 38 provide examples of the
DR behavior during recovery from reset commands.
SCLK
DIN
DOUT
DR
TIME THAT VDD > 3V
Figure 34. Electrical Connection Diagram
VDD
Table 6 provides an example list of pin names for the SPI port
in an embedded processor.
PULSING INDICATES
DATA PRODUCTION
Table 6. Generic SPI Master Pin Names and Functions
DR
Mnemonic
Function
SS
Slave select
START-UP TIME
SCLK
MOSI
MISO
IRQ
Serial clock
Figure 36. Data Ready Response During Startup
Master output, slave input
Master input, slave output
Interrupt request
SOFTWARE RESET COMMAND
GLOB_CMD, BIT 7 = 1
DR PULSING
RESUMES
Embedded processors typically configure their serial ports for
communicating with SPI slave devices such as the ADIS16505 by
using control registers on the processor itself. Table 7 lists the
SPI protocol settings for the ADIS16505.
DR
RESET RECOVERY TIME
Figure 37. Data Ready Response During Reset Recovery
(Register GLOB_CMD, Bit 7 = 1)
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
RST PIN
RELEASED
Master
ADIS16505 operates as slave
SCLK ≤ 2 MHz1
SPI Mode 3
MSB First Mode
16-Bit Mode
Maximum serial clock rate
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence, see Figure 40 for coding
Shift register and data length
RST
DR PULSING
RESUMES
DR
1 A burst mode read requires this value to be ≤1 MHz (see Table 2 for more
information).
RESET RECOVERY TIME
RST
Figure 38. Data Ready Response During Reset (
= 0) Recovery
Rev. B | Page 17 of 41
ADIS16505
Data Sheet
requests on DIN while also transmitting data out on DOUT
within the same 16-bit SPI cycle.
READING SENSOR DATA
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 40) for a
NEXT
ADDRESS
DIN
0x0C00
0x0E00
DOUT
Z_GYRO_LOW
Z_GYRO_OUT
R
read request on the SPI has three parts: the read bit ( /W = 0),
either address of the register, [A6:A0], and eight don’t care bits,
[DC7:DC0]. Figure 39 shows an example that includes two register
reads in succession. This example starts with DIN = 0x0C00 to
request the contents of the Z_GYRO_LOW register, and follows
with 0x0E00 to request the contents of the Z_GYRO_OUT
register. The sequence in Figure 39 also shows full duplex mode
of operation, which means that the ADIS16505 can receive
Figure 39. SPI Read Example
Figure 41 provides an example of the four SPI signals when
reading the PROD_ID register (see Table 120) in a repeating
pattern. This pattern can be helpful when troubleshooting the
SPI interface setup and communications because the signals are
the same for each 16-bit sequence, except during the first cycle.
CS
SCLK
DIN
R/W A6
A5
R/W A6
A5
A4
A3
A2
A1
D9
A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
D15 D14 D13 D12 D11 D10
D15 D14 D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS INA THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 40. SPI Communication Bit Sequence
CS
SCLK
DIN
DIN = 0x7200 = 0111 0010 0000 0000
HIGH-Z
HIGH-Z
DOUT
DOUT = 0100 0000 0111 1001 = 0x4079 = 16505 (PROD_ID)
Figure 41. SPI Signal Pattern, Repeating Read of the PROD_ID Register
Rev. B | Page 18 of 41
Data Sheet
ADIS16505
In these cases, use the following formula to verify the 16-bit
checksum value, treating each byte in the formula as an
independent, unsigned, 8-bit number:
BURST READ FUNCTION
The burst read function provides a way to read a batch of output
data registers, using a continuous stream of bits, at a rate of up
to 1 MHz (SCLK). This method does not require a stall time
between each 16-bit segment (see Figure 3). As shown in Figure 42,
start this mode by setting DIN = 0x6800, and then read each of
the registers in the sequence out of DOUT while keeping
low for the entire data transfer sequence.
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
CS
The three options for burst mode include: scaled sync mode on
or off, BURST32 enabled and disabled, and BURST_SEL = 0 or
BURSET_SEL = 1. This results in eight possible burst data formats.
Scaled Sync Mode Enabled vs. Disabled
16-Bit Burst Mode with BURST_SEL = 1
The only differences in the burst data format between these two
modes are the final two bytes in a burst. In scaled sync mode,
the final two bytes are the values of the TIME_STAMP registers.
When scaled sync mode is disabled, the final two bytes are the
values in the DATA_CNTR registers. As always, Bits[15:8]
appear before Bits[7:0] in both modes.
In 16-bit burst mode with BURST_SEL = 1, a burst contains
calibrated delta angle and delta velocity data in 16-bit format.
This mode is particularly appropriate for cases where there is
no decimation nor filtering. Not only is the sample rate high
(~2 kSPS), the lower 16 bits are not used.
1
2
3
11
CS
For the rest of this section, it is assumed that scaled sync mode
is disabled.
SCLK
16-Bit Burst Mode with BURST_SEL = 0
In 16-bit burst mode with BURST_SEL = 0, a burst contains
calibrated gyroscope and accelerometer data in 16-bit format.
This mode is particularly appropriate for cases where there is
no decimation nor filtering. Not only is the sample rate high
(~2 kSPS), the lower 16 bits are not used unless the user is
averaging or filtering.
0x6800
DIN
X_DELTANG_
OUT
DIAG_STAT
CHECKSUM
DOUT
Figure 43. Burst Read Sequence with BURST_SEL = 1
The sequence of registers (and checksum value) in the burst
read includes the following registers and value: DIAG_STAT,
X_DELTANG_OUT, Y_DELTANG_OUT,
1
2
3
11
CS
Z_DELTANG_OUT, X_DELTVEL_OUT, Y_DELTVEL_OUT,
Z_DELTVEL_OUT, TEMP_OUT, DATA_ CNTR, and the
checksum value.
SCLK
0x6800
In these cases, use the following formula to verify the 16-bit
checksum value, treating each byte in the formula as an
independent, unsigned, 8-bit number:
DIN
DIAG_STAT
X_GYRO_OUT
CHECKSUM
DOUT
Figure 42. Burst Read Sequence with BURST_SEL = 0
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_DELTANG_OUT, Bits[15:8] + X_DELTANG_OUT, Bits[7:0] +
Y_DELTANG_OUT, Bits[15:8] + Y_DELTANG_OUT, Bits[7:0] +
Z_DELTANG_OUT, Bits[15:8] + Z_DELTANG_OUT, Bits[7:0] +
X_DELTVEL_OUT, Bits[15:8] + X_DELTVEL_OUT, Bits[7:0] +
Y_DELTVEL_OUT, Bits[15:8] + Y_DELTVEL_OUT, Bits[7:0] +
Z_DELTVEL_OUT, Bits[15:8] + Z_DELTVEL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
The sequence of registers (and checksum value) in the burst
read includes the following registers and value: DIAG_STAT,
X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_
OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, DATA_
CNTR, and the checksum value.
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
Rev. B | Page 19 of 41
ADIS16505
Data Sheet
32-Bit Burst Mode with BURST_SEL = 0
32-Bit Burst Mode with BURST_SEL = 1
In 32-bit burst mode with BURST_SEL = 0, a burst contains
calibrated gyroscope and accelerometer data in 32-bit format.
This mode is appropriate for cases where there is averaging
(decimation) and/or low-pass filtering of the data.
In 32-bit burst mode with BURST_SEL = 1, a burst contains
calibrated delta angle and delta velocity data in 32-bit format.
This mode is appropriate for cases where there is averaging
(decimation) and/or low-pass filtering of the data.
1
2
3
17
1
2
3
17
CS
CS
SCLK
SCLK
0x6800
0x6800
DIN
DIN
X_DELTANG_
LOW
DIAG_STAT
X_GYRO_LOW
CHECKSUM
DIAG_STAT
CHECKSUM
DOUT
DOUT
Figure 44. Burst Read Sequence with BURST_SEL = 0
Figure 45. Burst Read Sequence with BURST_SEL = 1
The sequence of registers (and checksum value) in the burst
read includes the following registers and value: DIAG_STAT,
X_GYRO_LOW, X_GYRO_OUT, Y_GYRO_LOW,
Y_GYRO_OUT, Z_GYRO_LOW, Z_GYRO_OUT,
X_ACCL_LOW, X_ACCL_OUT, Y_ACCL_LOW,
Y_ACCL_OUT, Z_ACCL_LOW, Z_ACCL_OUT, TEMP_OUT,
DATA_ CNTR, and the checksum value. In these cases, use the
following formula to verify the 16-bit checksum value, treating
each byte in the formula as an independent, unsigned, 8-bit
number:
The sequence of registers (and checksum value) in the burst
read includes the following registers and value: DIAG_STAT,
X_DELTANG_LOW, X_DELTANG_OUT,
Y_DELTANG_LOW, Y_DELTANG_OUT,
Z_DELTANG_LOW, Z_DELTANG_OUT, X_DELTVEL_LOW,
X_DELTVEL_OUT, Y_DELTVEL_LOW, Y_DELTVEL_OUT,
Z_DELTVEL_LOW, Z_DELTVEL_OUT, TEMP_OUT, DATA_
CNTR, and the checksum value. In these cases, use the following
formula to verify the 16-bit checksum value, treating each byte
in the formula as an independent, unsigned, 8-bit number:
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_LOW, Bits[15:8] + X_GYRO_LOW, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_LOW, Bits[15:8] + Y_GYRO_LOW, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_LOW, Bits[15:8] + Z_GYRO_LOW, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_LOW, Bits[15:8] + X_ACCL_LOW, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_LOW, Bits[15:8] + Y_ACCL_LOW, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_LOW, Bits[15:8] + Z_ACCL_LOW, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_DELTANG_LOW, Bits[15:8] + X_DELTANG_LOW, Bits[7:0] +
X_DELTANG_OUT, Bits[15:8] + X_DELTANG_OUT, Bits[7:0] +
Y_DELTANG_LOW, Bits[15:8] + Y_DELTANG_LOW, Bits[7:0] +
Y_DELTANG_OUT, Bits[15:8] + Y_DELTANG_OUT, Bits[7:0] +
Z_DELTANG_LOW, Bits[15:8] + Z_DELTANG_LOW, Bits[7:0] +
Z_DELTANG_OUT, Bits[15:8] + Z_DELTANG_OUT, Bits[7:0] +
X_DELTVEL_LOW, Bits[15:8] + X_DELTVEL_LOW, Bits[7:0] +
X_DELTVEL_OUT, Bits[15:8] + X_DELTVEL_OUT, Bits[7:0] +
Y_DELTVEL_LOW, Bits[15:8] + Y_DELTVEL_LOW, Bits[7:0] +
Y_DELTVEL_OUT, Bits[15:8] + Y_DELTVEL_OUT, Bits[7:0] +
Z_DELTVEL_LOW, Bits[15:8] + Z_DELTVEL_LOW, Bits[7:0] +
Z_DELTVEL_OUT, Bits[15:8] + Z_DELTVEL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
Rev. B | Page 20 of 41
Data Sheet
ADIS16505
data for that location, [DC7:DC0]. Figure 46 shows a coding
example for writing 0x0004 to the FILT_CTRL register (see
Table 102). In Figure 46, the 0xDC04 command writes 0x04 to
Address 0x5C (lower byte) and the 0xDD00 command writes
0x00 to Address 0x5D (upper byte).
LATENCY
Table 8 contains the group delay for each inertial sensor when
the ADIS16505 is operating with the factory default settings for
the FILT_CTRL (see Table 101) and DEC_RATE (see Table 109)
registers.
CS
Table 8. Group Delay with No Filtering
Inertial Sensor
Group Delay (ms)1
SCLK
Accelerometer
1.57
1.51
1.51
1.29
Gyroscope (X-Axis)
Gyroscope (Y-Axis)
Gyroscope (Z-Axis)
DIN
0xDC04
0xDD00
Figure 46. SPI Sequence for Writing 0x0004 to FILT_CTRL
1 In this context, latency represents the time between the motion (linear
acceleration and/or angular rate of rotation) and the time that the
representative data is available in the output data register.
MEMORY STRUCTURE
Figure 47 provides a functional diagram for the memory
structure of the ADIS16505. The flash memory bank contains
the operational code, unit specific calibration coefficients, and
user configuration settings. During initialization (power
application or reset recover), this information loads from the
flash memory into the static random access memory (SRAM),
which supports all normal operation including register access
through the SPI port. Writing to a configuration register using
the SPI updates the SRAM location of the register but does not
automatically update its settings in the flash memory bank. The
manual flash memory update command (Register GLOB_CMD,
Bit 3, see Table 112) provides a convenient method for saving
all of these settings to the flash memory bank at one time. A yes
in the flash backup column of Table 9 identifies the registers
that have storage support in the flash memory bank.
When the FILT_CTRL register is not equal to 0, the group
delay contribution of the Bartlett window filter (in terms of
sample cycles) is equal to N (see Table 102). When the DEC_RATE
register is not equal to 0, the group delay contribution of the
decimation filter (in terms of sample cycles) is equal D + 1,
divided by 2 (see Table 110).
Data Acquisition
The total latency is equal to the sum of the group delay and
the data acquisition time, which represents the time it takes the
system processor to read the data from the output data registers
of the ADIS16505. For example, when using the burst read
function, with an SCLK rate of 1 MHz, the data acquisition
time is equal to 176 ꢀs (11 segments × 16 SCLKs/segment ×
1 ꢀs/SCLK).
MANUAL
FLASH
BACKUP
DEVICE CONFIGURATION
Each configuration register contains 16 bits (two bytes). Bits[7:0]
contain the low byte, and Bits[15:8] contain the high byte. Each
byte has its own unique address in the user register map (see
Table 9). Updating the contents of a register requires writing to
both of its bytes in the following sequence: low byte first, high
byte second. There are three parts to coding a SPI command
(see Figure 40) that write a new byte of data to a register: the
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
SPI ACCESS
(NO SPI ACCESS)
START-UP
RESET
Figure 47. SRAM and Flash Memory Diagram
R
write bit ( /W = 1), the address of the byte, [A6:A0], and the new
Rev. B | Page 21 of 41
ADIS16505
Data Sheet
USER REGISTER MEMORY MAP
Table 9. User Register Memory Map (N/A Means Not Applicable)
Name
R/W
N/A
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
R
R
R
R
R
R
R
R
R
R
R
R
Flash Backup
N/A
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
N/A
No
No
No
No
No
No
No
No
No
No
No
No
Address
Default
Register Description
Reserved
DIAG_STAT
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x20, 0x21
0x22, 0x23
0x24, 0x25
0x26, 0x27
0x28, 0x29
0x2A, 0x2B
0x2C, 0x2D
0x2E, 0x2F
0x30, 0x31
0x32, 0x33
0x34, 0x35
0x36, 0x37
0x38, 0x39
0x3A, 0x3B
0x3C to 0x3F
0x40, 0x41
0x42, 0x43
0x44, 0x45
0x46, 0x47
0x48, 0x49
0x4A, 0x4B
0x4C, 0x4D
0x4E, 0x4F
0x50, 0x51
0x52, 0x53
0x54, 0x55
0x56, 0x57
0x58 to 0x5B
0x5C, 0x5D
0x5E, 0x5F
N/A
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
Reserved
Output, system error flags
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TEMP_OUT
Output, x-axis gyroscope, low word
Output, x-axis gyroscope, high word
Output, y-axis gyroscope, low word
Output, y-axis gyroscope, high word
Output, z-axis gyroscope, low word
Output, z-axis gyroscope, high word
Output, x-axis accelerometer, low word
Output, x-axis accelerometer, high word
Output, y-axis accelerometer, low word
Output, y-axis accelerometer, high word
Output, z-axis accelerometer, low word
Output, z-axis accelerometer, high word
Output, temperature
TIME_STAMP
Reserved
DATA_CNTR
Output, time stamp
Reserved
New data counter
X_DELTANG_LOW
X_DELTANG_OUT
Y_DELTANG_LOW
Y_DELTANG_OUT
Z_DELTANG_LOW
Z_DELTANG_OUT
X_DELTVEL_LOW
X_DELTVEL_OUT
Y_DELTVEL_LOW
Y_DELTVEL_OUT
Z_DELTVEL_LOW
Z_DELTVEL_OUT
Reserved
XG_BIAS_LOW
XG_BIAS_HIGH
YG_BIAS_LOW
YG_BIAS_HIGH
ZG_BIAS_LOW
ZG_BIAS_HIGH
XA_BIAS_LOW
XA_BIAS_HIGH
YA_BIAS_LOW
YA_BIAS_HIGH
ZA_BIAS_LOW
ZA_BIAS_HIGH
Reserved
Output, x-axis delta angle, low word
Output, x-axis delta angle, high word
Output, y-axis delta angle, low word
Output, y-axis delta angle, high word
Output, z-axis delta angle, low word
Output, z-axis delta angle, high word
Output, x-axis delta velocity, low word
Output, x-axis delta velocity, high word
Output, y-axis delta velocity, low word
Output, y-axis delta velocity, high word
Output, z-axis delta velocity, low word
Output, z-axis delta velocity, high word
Reserved
Calibration, offset, gyroscope, x-axis, low word
Calibration, offset, gyroscope, x-axis, high word
Calibration, offset, gyroscope, y-axis, low word
Calibration, offset, gyroscope, y-axis, high word
Calibration, offset, gyroscope, z-axis, low word
Calibration, offset, gyroscope, z-axis, high word
Calibration, offset, accelerometer, x-axis, low word
Calibration, offset, accelerometer, x-axis, high word
Calibration, offset, accelerometer, y-axis, low word
Calibration, offset, accelerometer, y-axis, high word
Calibration, offset, accelerometer, z-axis, low word
Calibration, offset, accelerometer, z-axis, high word
Reserved
R
No
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R/W
R
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
Yes
No
FILT_CTRL
RANG_MDL
0x0000
N/A1
Control, Bartlett window FIR filter
Measurement range (model specific) identifier
Rev. B | Page 22 of 41
Data Sheet
ADIS16505
Name
R/W
R/W
R/W
R/W
N/A
W
N/A
R
R
R
R
R
R/W
R/W
R/W
R
Flash Backup
Yes
Yes
Yes
N/A
No
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Address
Default
0x00C1
0x07D0
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
0x4079
N/A
N/A
N/A
N/A
N/A
N/A
Register Description
MSC_CTRL
UP_SCALE
DEC_RATE
Reserved
GLOB_CMD
Reserved
FIRM_REV
FIRM_DM
FIRM_Y
0x60, 0x61
0x62, 0x63
0x64, 0x65
0x66, 0x67
0x68, 0x69
0x6A to 0x6B
0x6C, 0x6D
0x6E, 0x6F
0x70, 0x71
0x72, 0x73
0x74, 0x75
0x76, 0x77
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 0x7E
Control, input/output and other miscellaneous options
Control, scale factor for input clock, scaled sync mode
Control, decimation filter (output data rate)
Reserved
Control, global commands
Reserved
Identification, firmware revision
Identification, date code, day and month
Identification, date code, year
Identification, device number (0x4079 = 16,505 decimal)
Identification, serial number
User Scratch Register 1
PROD_ID
SERIAL_NUM
USER_SCR_1
USER_SCR_2
USER_SCR_3
FLSHCNT_LOW
FLSHCNT_HIGH
User Scratch Register 2
User Scratch Register 3
Output, flash memory write cycle counter, lower word
Output, flash memory write cycle counter, upper word
R
1 See Table 103 for the model specific default value for this register.
Rev. B | Page 23 of 41
ADIS16505
Data Sheet
USER REGISTER DEFINTIONS
Bits
Description
Status/Error Flag Indicators (DIAG_STAT)
2
Flash memory update failure. A 1 indicates that the
most recent flash memory update (Register GLOB_CMD,
Bit 3, see Table 112) failed. If this error occurs, ensure that
VDD ≥ 3 V and repeat the update attempt. If this error
persists, replace the ADIS16505.
Table 10. DIAG_STAT Register Definition
Addresses
Default
Access
Flash Backup
0x02, 0x03
0x0000
R
No
1
0
Data path overrun. A 1 indicates that one of the data
paths experienced an overrun condition. If this error
occurs, initiate a reset using the RST pin (see Table 5,
Pin F3) or Register GLOB_CMD, Bit 7 (see Table 112).
Table 11. DIAG_STAT Bit Assignments
Bits Description
[15:11] Reserved.
10
Accelerometer failure. A 1 indicates failure of the
accelerometer at the conclusion of the self test
(Register GLOB_CMD, Bit 2, see Table 112). If this error
occurs, repeat the same test. If this error persists,
replace the ADIS16507. Motion during this test may
cause a false failure.
Reserved.
The DIAG_STAT register (see Table 10 and Table 11) provides
error flags for monitoring the integrity and operation of the
ADIS16505. Reading this register resets its bits to 0. The error
flags in DIAG_STAT are sticky, meaning that when they raise
to a 1, they remain there until a read request clears them. If an
error condition persists, the flag (bit) automatically returns to
an alarm value of 1.
9
8
7
Gyroscope 2 failure. A 1 indicates failure of Gyroscope 2 at
the conclusion of the self test (Register GLOB_CMD, Bit 2,
see Table 112). If this error occurs, repeat the same test.
If this error persists, replace the ADIS16507. Motion
during this test may cause a false failure.
GYROSCOPE DATA
Gyroscope 1 failure. A 1 indicates failure of Gyroscope 1 at
the conclusion of the self test (Register GLOB_CMD, Bit 2,
see Table 112). If this error occurs, repeat the same test.
If this error persists, replace the ADIS16507. Motion
during this test may cause a false failure.
The gyroscopes in the ADIS16505 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 48
shows the orientation of each gyroscope axis along with the
direction of rotation that produces a positive response in each
of their measurements.
Clock error. A 1 indicates that the internal data
sampling clock (fSM, see Figure 30) does not
Z-AXIS
synchronize with the external clock, which only applies
when using scaled sync mode (Register MSC_CTRL,
Bits[3:2] = 10, see Table 106). When this error occurs,
adjust the frequency of the clock signal on the SYNC pin
to operate within the appropriate range.
ω
Z
X-AXIS
Y-AXIS
6
5
Memory failure. A 1 indicates a failure in the flash memory
test (Register GLOB_CMD, Bit 4, see Table 112), which
involves a comparison between a cyclic redundancy
check (CRC) calculation of the present flash memory
and a CRC calculation from the same memory locations at
the time of initial programming (during the production
process). If this error occurs, repeat the same test. If this
error persists, replace the ADIS16505.
ω
X
ω
Y
K1
A10
A1
Figure 48. Gyroscope Axis and Polarity Assignments
Each gyroscope has two output data registers. Figure 49 shows
how these two registers combine to support a 32-bit, twos
complement data format for the x-axis gyroscope measurements.
This format also applies to the y- and z-axes.
Sensor failure. A 1 indicates failure of at least one
sensor, at the conclusion of the self test (Register
GLOB_CMD, Bit 2, see Table 112). If this error occurs,
repeat the same test. If this error persists, replace the
ADIS16505. Motion during this test may cause a false
failure.
X_GYRO_OUT
X_GYRO_LOW
4
3
Standby mode. A 1 indicates that the voltage across
VDD and GND is <2.8 V, which causes data processing
to stop. When VDD ≥ 2.8 V for 250 ms, the ADIS16505
reinitializes itself and starts producing data again.
BIT 15
BIT 0 BIT 15
BIT 0
X-AXIS GYROSCOPE DATA
Figure 49. Gyroscope Output Data Structure
SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer
multiple of 16. When this error occurs, repeat the
previous communication sequence. Persistence in this
error can indicate that the SPI connection between the
host and the ADIS16505 is not robust (for example,
marginal voltage levels, timing, or signal integrity).
Rev. B | Page 24 of 41
Data Sheet
ADIS16505
Gyroscope Measurement Range/Scale Factor
The X_GYRO_LOW (see Table 15 and Table 16) and X_GYRO_
OUT (see Table 17 and Table 18) registers contain the gyroscope
data for the x-axis.
Table 12 provides the range and scale factor for the angular rate
(gyroscope) measurements in each ADIS16505 model.
Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT)
Table 12. Gyroscope Measurement Range and Scale Factors
Table 19. Y_GYRO_LOW Register Definition
Range, ±±MAX
(°/sec)
Scale Factor, KG
(°/sec/LSB)
Model
Addresses
Default
Access
Flash Backup
ADIS16505-1BMLZ
ADIS16505-2BMLZ
ADIS16505-3BMLZ
125
500
2000
0.00625
0.025
0.1
0x08, 0x09
Not applicable
R
No
Table 20. Y_GYRO_LOW Bit Definitions
Bits
Description
[15:0]
Y-axis gyroscope data; additional resolution bits
Gyroscope Data Formatting
Table 21. Y_GYRO_OUT Register Definition
Table 13 and Table 14 offer various numerical examples that
demonstrate the format of the rotation rate data in both 16-bit
and 32-bit formats.
Addresses
Default
Access
Flash Backup
0x0A, 0x0B
Not applicable
R
No
Table 22. Y_GYRO_OUT Bit Definitions
Table 13. 16-Bit Gyroscope Data Format Examples
Bits
Description
Rotation Rate
+ωMAX
+2 KG
Decimal Hex
Binary
[15:0]
Y-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = KG (see Table 12 for KG)
+20,000
0x4E20
0100 1110 0010 0000
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1011 0001 1110 0000
+2
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xB1E0
+KG
+1
The Y_GYRO_LOW (see Table 19 and Table 20) and Y_GYRO_
OUT (see Table 21 and Table 22) registers contain the gyroscope
data for the y-axis.
0°/sec
−KG
0
−1
−2 KG
−2
Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT)
−ωMAX
−20,000
Table 23. Z_GYRO_LOW Register Definition
Table 14. 32-Bit Gyroscope Data Format Examples
Addresses
Default
Access
Flash Backup
Rotation Rate (°/sec)
Decimal
Hex
0x0C, 0x0D
Not applicable
R
No
+ωMAX
+KG/215
+KG/216
0
−KG /216
−KG /215
−ωMAX
+1,310,720,000 0x4E200000
+2
+1
0
−1
−2
0x00000002
0x00000001
0x0000000
0xFFFFFFFF
0xFFFFFFFE
Table 24. Z_GYRO_LOW Bit Definitions
Bits
Description
[15:0]
Z-axis gyroscope data; additional resolution bits
Table 25. Z_GYRO_OUT Register Definition
Addresses
Default
Access
Flash Backup
−1,310,720,000 0xB1E00000
0x0E, 0x0F
Not applicable
R
No
X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT)
Table 26. Z_GYRO_OUT Bit Definitions
Table 15. X_GYRO_LOW Register Definition
Bits
Description
Addresses
Default
Access
Flash Backup
[15:0]
Z-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = KG (see Table 12 for KG)
0x04, 0x05
Not applicable
R
No
The Z_GYRO_LOW (see Table 23 and Table 24) and Z_GYRO_
OUT (see Table 25 and Table 26) registers contain the gyroscope
data for the z-axis.
Table 16. X_GYRO_LOW Bit Definitions
Bits
Description
[15:0]
X-axis gyroscope data; additional resolution bits
Table 17. X_GYRO_OUT Register Definition
Addresses
Default
Access
Flash Backup
0x06, 0x07
Not applicable
R
No
Table 18. X_GYRO_OUT Bit Definitions
Bits
Description
[15:0]
X-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = KG (See Table 12 for KG)
Rev. B | Page 25 of 41
ADIS16505
Data Sheet
Acceleration Data
X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT)
The accelerometers in the ADIS16505 measure both dynamic
and static (response to gravity) acceleration along the same three
orthogonal axes that define the axes of rotation for the gyroscopes
(x, y, and z). Figure 50 shows the orientation of each accelerometer
axis along with the direction of acceleration that produces a
positive response in each of their measurements.
Table 29. X_ACCL_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x10, 0x11
Not applicable
R
No
Table 30. X_ACCL_LOW Bit Definitions
Bits Description
Z-AXIS
[15:0] X-axis accelerometer data; additional resolution bits
Table 31. X_ACCL_OUT Register Definition
Addresses
Default
Access
Flash Backup
aZ
X-AXIS
0x12, 0x13
Not applicable
R
No
Y-AXIS
aY
aX
Table 32. X_ACCL_OUT Bit Definitions
Bits Description
K1
A10
[15:0] X-axis accelerometer data, high word; twos complement,
78.3 m/sec2 range; 0 m/sec2 = 0x0000,
1 LSB = 2.45 mm/sec2
A1
Figure 50. Accelerometer Axis and Polarity Assignments
The X_ACCL_LOW (see Table 29 and Table 30) and X_ACCL_
OUT (see Table 31 and Table 32) registers contain the
accelerometer data for the x-axis.
Each accelerometer has two output data registers. Figure 51
shows how these two registers combine to support a 32-bit,
twos complement data format for the x-axis accelerometer
measurements. This format also applies to the y- and z-axes.
Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT)
X_ACCL_OUT
X_ACCL_LOW
Table 33. Y_ACCL_LOW Register Definition
BIT 15
BIT 0 BIT 15
X-AXIS ACCELEROMETER DATA
BIT 0
Addresses
Default
Access
Flash Backup
0x14, 0x15
Not applicable
R
No
Figure 51. Accelerometer Output Data Structure
Table 34. Y_ACCL_LOW Bit Definitions
Bits Description
Accelerometer Resolution
Table 27 and Table 28 offer various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
[15:0] Y-axis accelerometer data; additional resolution bits
Table 35. Y_ACCL_OUT Register Definition
Addresses Default
Access
Flash Backup
Table 27. 16-Bit Accelerometer Data Format Examples
0x16, 0x17 Not applicable
R
No
Acceleration
+78.3 m/sec2
Dec
Hex
Binary
Table 36. Y_ACCL_OUT Bit Definitions
Bits Description
+32,000 0x7D00 0111 1101 0000 0000
+2
+4.9/215 mm/sec2
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF
0xFFFE
+2.45/216 mm/sec2 +1
[15:0] Y-axis accelerometer data, high word; twos complement,
78.3 m/sec2 range; 0 m/sec2 = 0x0000,
1 LSB = 2.45 mm/sec2
0
0
−2.45/216 mm/sec2 −1
1111 1111 1111 1111
1111 1111 1111 1110
−4.9/215 mm/sec2
−78.3 m/sec2
−2
The Y_ACCL_LOW (see Table 33 and Table 34) and
Y_ACCL_ OUT (see Table 35 and Table 36) registers contain
the accelerometer data for the y-axis.
−32,000 0x8300 1000 0011 0000 0000
Table 28. 32-Bit Accelerometer Data Format Examples
Acceleration
+78.3 m/sec2
+4.9/215 mm/sec2
+2.45/216 mm/sec2
0
−2.45/216 mm/sec2
−4.9/215 mm/sec2
−78.3 m/sec2
Decimal
Hex
+2,097,152,000
+2
+1
0
−1
−2
0x7D000000
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x83000000
−2,097,152,000
Rev. B | Page 26 of 41
Data Sheet
ADIS16505
Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT)
Time Stamp (TIME_STAMP)
Table 37. Z_ACCL_LOW Register Definition
Table 44. TIME_STAMP Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x18, 0x19
Not applicable
R
No
0x1E, 0x1F
Not applicable
R
No
Table 38. Z_ACCL_LOW Bit Definitions
Bits Description
Table 45. TIME_STAMP Bit Definitions
Bits
Description
[15:0] Z-axis accelerometer data; additional resolution bits
[15:0]
Time from the last pulse on the SYNC pin; offset binary
format, 1 LSB = 49.02 μs
Table 39. Z_ACCL_OUT Register Definition
The TIME_STAMP register (see Table 44 and Table 45) works
in conjunction with scaled sync mode (Register MSC_CTRL,
Bits[3:2] = 10, see Table 106). The 16-bit number in TIME_
STAMP contains the time associated with the last sample in
each data update relative to the most recent edge of the clock
signal in the SYNC pin. For example, when the value in the
UP_SCALE register (see Table 108) represents a scale factor of
20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the
following time stamp sequence results: 0 LSB, 10 LSB, 20 LSB,
30 LSB, 40 LSB, 50 LSB, 61 LSB, 71 LSB, … , 193 LSB for the 20th
sample, which translates to 0 ꢀs, 490 ꢀs, … , 9460 ꢀs, the time
from the first SYNC edge.
Addresses
Default
Access
Flash Backup
0x1A, 0x1B
Not applicable
R
No
Table 40. Z_ACCL_OUT Bit Definitions
Bits Description
[15:0] Z-axis accelerometer data, high word; twos complement,
78.3 m/sec2 range; 0 m/sec2 = 0x0000,
1 LSB = 2.45 mm/sec2
The Z_ACCL_LOW (see Table 37 and Table 38) and Z_ACCL_
OUT (see Table 39 and Table 40) registers contain the
accelerometer data for the z-axis.
Internal Temperature (TEMP_OUT)
Data Update Counter (DATA_CNTR)
Table 41. TEMP_OUT Register Definition
Addresses
Table 46. DATA_CNTR Register Definition
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x1C, 0x1D
Not applicable
R
No
0x22, 0x23
Not applicable
R
No
Table 42. TEMP_OUT Bit Definitions
Table 47. DATA_CNTR Bit Definitions
Bits
Description
Bits
Description
[15:0]
Temperature data; twos complement, 1 LSB = 0.1°C,
0°C = 0x0000
[15:0]
Data update counter, offset binary format
When the ADIS16505 goes through its power-on sequence or
when it recovers from a reset command, DATA_CNTR (see
Table 46 and Table 47) starts with a value of 0x0000 and
increments every time new data loads into the output registers.
When the DATA_CNTR value reaches 0xFFFF, the next data
update causes it to wrap back around to 0x0000 where it
continues to increment every time new data loads into the
output registers.
The TEMP_OUT register (see Table 41 and Table 42) provides
a coarse measurement of the temperature inside of the ADIS16505.
This data is most useful for monitoring relative changes in the
thermal environment.
Table 43. TEMP_OUT Data Format Examples
Temperature (°C)
Decimal Hex
Binary
+105
+25
+0.2
+0.1
+0
+0.1
+0.2
−40
+1050
+250
+2
+1
0
−1
−2
−400
0x041A 0000 0100 0001 1010
0x00FA 0000 0000 1111 1010
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0xFE70 1111 1110 0111 0000
Rev. B | Page 27 of 41
ADIS16505
Data Sheet
Delta Angle Measurement Range
DELTA ANGLES
Table 48 shows the measurement range and scale factor for
each ADIS16505 model.
In addition to the angular rate of rotation (gyroscope)
measurements around each axis (x, y, and z), the ADIS16505 also
provides delta angle measurements that represent a calculation
of angular displacement between each sample update.
Z-AXIS
Table 48. Delta Angle Measurement Range and Scale Factor
Model
Measurement Range, ±ꢀθMAX (°)
ADIS16505-1BMLZ
ADIS16505-2BMLZ
ADIS16505-3BMLZ
360
720
2160
Δθ
Z
X-AXIS
X-Axis Delta Angle (X_DELTANG_LOW and
X_DELTANG_OUT)
Y-AXIS
Δθ
X
Δθ
Y
Table 49. X_DELTANG_LOW Register Definitions
K1
A10
Addresses
Default
Access
Flash Backup
0x24, 0x25
Not applicable
R
No
A1
Figure 52. Delta Angle Axis and Polarity Assignments
Table 50. X_DELTANG_LOW Bit Definitions
Bits
Description
The delta angle outputs represent an integration of the gyroscope
measurements and use the following formula for all three axes
(x-axis displayed):
[15:0]
X-axis delta angle data; low word
Table 51. X_DELTANG_OUT Register Definitions
Addresses
D 1
1
Default
Access
Flash Backup
x, nD
x, nD d 1
x, nD d
2 fS
d 0
0x26, 0x27
Not applicable
R
No
where:
Table 52. X_DELTANG_OUT Bit Definitions
Bits Description
[15:0] X-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 48 for ΔθMAX
D is the decimation rate (DEC_RATE + 1, see Table 110).
fS is the sample rate.
d is the incremental variable in the summation formula.
ωX is the x-axis rate of rotation (gyroscope).
n is the sample time, prior to the decimation filter.
)
The X_DELTANG_LOW (see Table 49 and Table 50) and
X_DELTANG_OUT (see Table 51 and Table 52) registers
contain the delta angle data for the x-axis.
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 109), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency, and multiply it by 2000. Each axis of
the delta angle measurements has two output data registers.
Figure 53 shows how these two registers combine to support a
32-bit, twos complement data format for the x-axis delta angle
measurements. This format also applies to the y- and z-axes.
Y-Axis Delta Angle (Y_DELTANG_LOW and
Y_DELTANG_OUT)
Table 53. Y_DELTANG_LOW Register Definitions
Addresses
Default
Access
Flash Backup
0x28, 0x29
Not applicable
R
No
Table 54. Y_DELTANG_LOW Bit Definitions
Bits
Description
[15:0]
Y-axis delta angle data; low word
X_DELTANG_OUT
X_DELTANG_LOW
BIT 0 BIT 15
BIT 15
BIT 0
Table 55. Y_DELTANG_OUT Register Definitions
Addresses
X-AXIS DELTA ANGLE DATA
Default
Access
Flash Backup
0x2A, 0x2B
Not applicable
R
No
Figure 53. Delta Angle Output Data Structure
Table 56. Y_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 48 for ΔθMAX
)
The Y_DELTANG_LOW (see Table 53 and Table 54) and
Y_DELTANG_OUT (see Table 55 and Table 56) registers
contain the delta angle data for the y-axis.
Rev. B | Page 28 of 41
Data Sheet
ADIS16505
Z-Axis Delta Angle (Z_DELTANG_LOW and
Z_DELTANG_OUT)
DELTA VELOCITY
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16505 also provides delta velocity
measurements that represent a calculation of linear velocity
change between each sample update.
Table 57. Z_DELTANG_LOW Register Definitions
Addresses
Default
Access
Flash Backup
0x2C, 0x2D
Not applicable
R
No
Z-AXIS
Table 58. Z_DELTANG_LOW Bit Definitions
Bits
Description
[15:0]
Z-axis delta angle data; low word
X-AXIS
Δ
VZ
ΔVX
Y-AXIS
Δ
VY
Table 59. Z_DELTANG_OUT Register Definitions
Addresses
Default
Access
Flash Backup
K1
0x2E, 0x2F
Not applicable
R
No
A10
Table 60. Z_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 48 for ΔθMAX
A1
Figure 54. Delta Velocity Axis and Polarity Assignments
The delta velocity outputs represent an integration of the
acceleration measurements and use the following formula for
all three axes (x-axis displayed):
)
The Z_DELTANG_LOW (see Table 57 and Table 58) and
Z_DELTANG_OUT (see Table 59 and Table 60) registers
contain the delta angle data for the z-axis.
D 1
1
Vx, nD
a
ax, nD d 1
x, nD d
2 fS
d 0
Delta Angle Resolution
where:
x is the x-axis.
Table 61 and Table 62 show various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
n is the sample time, prior to the decimation filter.
D is the decimation rate (DEC_RATE + 1, see Table 110).
fS is the sample rate.
Table 61. 16-Bit Delta Angle Data Format Examples
Delta Angle (°)
ΔθMAX × (215−1)/215 +32,767
Decimal Hex
Binary
d is the incremental variable in the summation formula.
aX is the x-axis acceleration.
0x7FFF 0111 1111 1110 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+ΔθMAX/214
+ΔθMAX/215
0
−ΔθMAX/215
−ΔθMAX/214
−ΔθMAX
+2
+1
0
−1
−2
−32,768
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 109), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency, and multiply it by 2000. Each axis of
the delta velocity measurements has two output data registers.
Figure 55 shows how these two registers combine to support
32-bit, twos complement data format for the delta velocity
measurements along the x-axis. This format also applies to the
y- and z-axes.
Table 62. 32-Bit Delta Angle Data Format Examples
Delta Angle (°)
+ΔθMAX × (231 − 1)/231
+ΔθMAX/230
+ΔθMAX/231
0
−ΔθMAX/231
−ΔθMAX/230
−ΔθMAX
Decimal
Hex
+2,147,483,647 0x7FFFFFFF
+2
+1
0
−1
−2
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
X_ DELTVEL_OUT
BIT 0 BIT 15
X_ DELTVEL_LOW
BIT 0
BIT 15
X-AXIS DELTA VELOCITY DATA
−2,147,483,648 0x80000000
Figure 55. Delta Velocity Output Data Structure
Rev. B | Page 29 of 41
ADIS16505
Data Sheet
X-Axis Delta Velocity (X_DELTVEL_LOW and
X_DELTVEL_OUT)
Z-Axis Delta Velocity (Z_DELTVEL_LOW and
Z_DELTVEL_OUT)
Table 63. X_DELTVEL_LOW Register Definition
Table 71. Z_DELTVEL_LOW Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x30, 0x31
Not applicable
R
No
0x38, 0x39
Not applicable
R
No
Table 64. X_DELTVEL_LOW Bit Definitions
Table 72. Z_DELTVEL_LOW Bit Definitions
Bits
Description
Bits
Description
[15:0]
X-axis delta velocity data; additional resolution bits
[15:0]
Z-axis delta velocity data; additional resolution bits
Table 65. X_DELTVEL_OUT Register Definition
Table 73. Z_DELTVEL_OUT Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x32, 0x33
Not applicable
R
No
0x3A, 0x3B
Not applicable
R
No
Table 66. X_DELTVEL_OUT Bit Definitions
Table 74. Z_DELTVEL_OUT Bit Definitions
Bits Description
Bits
Description
[15:0]
X-axis delta velocity data; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
[15:0] Z-axis delta velocity data; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
1 LSB = +100 m/sec ÷ 215 = ~+0.003052 m/sec
1 LSB = +100 m/sec ÷ 215 = ~+0.003052 m/sec
The X_DELTVEL_LOW (see Table 63 and Table 64) and
X_DELTVEL_OUT (see Table 65 and Table 66) registers
contain the delta velocity data for the x-axis.
The Z_DELTVEL_LOW (see Table 71 and Table 72) and
Z_DELTVEL_OUT (see Table 73 and Table 74) registers
contain the delta velocity data for the z-axis.
Y-Axis Delta Velocity (Y_DELTVEL_LOW and
Y_DELTVEL_OUT)
Delta Velocity Resolution
Table 75 and Table 76 offer various numerical examples that
demonstrate the format of the delta velocity data in both 16-bit
and 32-bit formats.
Table 67. Y_DELTVEL_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x34, 0x35
Not applicable
R
No
Table 75. 16-Bit Delta Velocity Data Format Examples
Velocity (m/sec)
+100 × (215 − 1)/215 +32,767
Decimal Hex
Binary
Table 68. Y_DELTVEL_LOW Bit Definitions
0x7FFF 0111 1111 1111 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
Bits
Description
+100/214
+100/215
0
−100/215
−100/214
−100
+2
+1
0
−1
−2
−32,768
[15:0]
Y-axis delta velocity data; additional resolution bits
Table 69. Y_DELTVEL_OUT Register Definition
Addresses
Default
Access
Flash Backup
0x36, 0x37
Not applicable
R
No
Table 70. Y_DELTVEL_OUT Bit Definitions
Bits Description
Table 76. 32-Bit Delta Velocity Data Format Examples
Velocity (m/sec)
+100 × (231 − 1)/231
+100/230
+100/231
0
−100/231
−100/230
−100
Decimal
Hex
[15:0] Y-axis delta velocity data; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
+2,147,483,647
+2
+1
0
−1
−2
0x7FFFFFFF
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x80000000
1 LSB = +100 m/sec ÷ 215 = ~+0.003052 m/sec
The Y_DELTVEL_LOW (see Table 67 and Table 68) and
Y_DELTVEL_OUT (see Table 69 and Table 70) registers
contain the delta velocity data for the y-axis.
+2,147,483,648
Rev. B | Page 30 of 41
Data Sheet
ADIS16505
Calibration, Gyroscope Bias (YG_BIAS_LOW and
YG_BIAS_HIGH)
CALIBRATION
The signal chain of each inertial sensor (accelerometers and
gyroscopes) includes the application of unique correction
formulas, which are derived from extensive characterization
of bias, sensitivity, alignment, response to linear acceleration
(gyroscopes), and point of percussion (accelerometer location)
over a temperature range of −40°C to +85°C, for each ADIS16505.
These correction formulas are not accessible, but users do have
the opportunity to adjust the bias for each sensor individually
through user accessible registers. These correction factors
follow immediately after the factory derived correction formulas
in the signal chain, which processes at a rate of 2000 Hz when
using the internal sample clock.
Table 81. YG_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x44, 0x45
0x0000
R/W
Yes
Table 82. YG_BIAS_LOW Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction; lower word
Table 83. YG_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
0x46, 0x47
0x0000
R/W
Yes
Table 84. YG_BIAS_HIGH Bit Definitions
Bits Description
Calibration, Gyroscope Bias (XG_BIAS_LOW and
XG_BIAS_HIGH)
[15:0] Y-axis gyroscope offset correction factor, upper word
The YG_BIAS_LOW (see Table 81 and Table 82) and YG_BIAS_
HIGH (see Table 83 and Table 84) registers combine to allow
users to adjust the bias of the y-axis gyroscopes. The data format
examples in Table 13 also apply to the YG_BIAS_HIGH register,
and the data format examples in Table 14 apply to the 32-bit
combination of the YG_BIAS_LOW and YG_BIAS_HIGH
registers. These registers influence the y-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 56).
Table 77. XG_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x40, 0x41
0x0000
R/W
Yes
Table 78. XG_BIAS_LOW Bit Definitions
Bits
Description
[15:0]
X-axis gyroscope offset correction; lower word
Table 79. XG_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
0x42, 0x43
0x0000
R/W
Yes
Calibration, Gyroscope Bias (ZG_BIAS_LOW and
ZG_BIAS_HIGH)
Table 80. XG_BIAS_HIGH Bit Definitions
Bits Description
Table 85. ZG_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
[15:0] X-axis gyroscope offset correction factor, upper word
0x48, 0x49
0x0000
R/W
Yes
The XG_BIAS_LOW (see Table 77 and Table 78) and XG_BIAS_
HIGH (see Table 79 and Table 80) registers combine to allow
users to adjust the bias of the x-axis gyroscopes. The data format
examples in Table 13 also apply to the XG_BIAS_HIGH register,
and the data format examples in Table 14 apply to the 32-bit
combination of the XG_BIAS_LOW and XG_BIAS_HIGH
registers. See Figure 56 for an illustration of how these two
registers combine and influence the x-axis gyroscope
measurements.
Table 86. ZG_BIAS_LOW Bit Definitions
Bits Description
[15:0] Z-axis gyroscope offset correction; lower word
Table 87. ZG_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
0x4A, 0x4B
0x0000
R/W
Yes
Table 88. ZG_BIAS_HIGH Bit Definitions
Bits Description
FACTORY
X-AXIS
GYRO
CALIBRATION
AND
[15:0] Z-axis gyroscope offset correction factor, upper word
X_GYRO_OUT X_GYRO_LOW
FILTERING
The ZG_BIAS_LOW (see Table 85 and Table 86) and ZG_BIAS_
HIGH (see Table 87 and Table 88) registers combine to allow
users to adjust the bias of the z-axis gyroscopes. The data format
examples in Table 13 also apply to the ZG_BIAS_HIGH register,
and the data format examples in Table 14 apply to the 32-bit
combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH registers.
XG_BIAS_HIGH XG_BIAS_LOW
Figure 56. User Calibration Signal Path, Gyroscopes
Rev. B | Page 31 of 41
ADIS16505
Data Sheet
These registers influence the z-axis gyroscope measurements in
the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH
registers influence the x-axis gyroscope measurements (see
Figure 56).
The YA_BIAS_LOW (see Table 93 and Table 94) and
YA_BIAS_HIGH (see Table 95 and Table 96) registers combine to
allow users to adjust the bias of the y-axis accelerometers. The data
format examples in Table 27 also apply to the YA_BIAS_HIGH
register, and the data format examples in Table 28 apply to the
32-bit combination of the YA_BIAS_LOW and YA_BIAS_HIGH
registers. These registers influence the y-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW
and XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 57).
Calibration, Accelerometer Bias (XA_BIAS_LOW and
XA_BIAS_HIGH)
Table 89. XA_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x4C, 0x4D
0x0000
R/W
Yes
Calibration, Accelerometer Bias (ZA_BIAS_LOW and
ZA_BIAS_HIGH)
Table 90. XA_BIAS_LOW Bit Definitions
Bits
Description
[15:0]
X-axis accelerometer offset correction; lower word
Table 97. ZA_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
Table 91. XA_BIAS_HIGH Register Definition
0x54, 0x55
0x0000
R/W
Yes
Addresses
Default
Access
Flash Backup
0x4E, 0x4F
0x0000
R/W
Yes
Table 98. ZA_BIAS_LOW Bit Definitions
Bits Description
Table 92. XA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction; lower word
[15:0] X-axis accelerometer offset correction, upper word
Table 99. ZA_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
The XA_BIAS_LOW (see Table 89 and Table 90) and XA_BIAS_
HIGH (see Table 91 and Table 92) registers combine to allow
users to adjust the bias of the x-axis accelerometers. The data
format examples in Table 27 also apply to the XA_BIAS_HIGH
register and the data format examples in Table 28 apply to the
32-bit combination of the XA_BIAS_LOW and XA_BIAS_HIGH
registers. See Figure 57 for an illustration of how these two registers
combine and influence the x-axis accelerometer measurements.
0x56, 0x57
0x0000
R/W
Yes
Table 100. ZA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction, upper word
The ZA_BIAS_LOW (see Table 97 and Table 98) and ZA_BIAS_
HIGH (see Table 99 and Table 100) registers combine to allow
users to adjust the bias of the z-axis accelerometers. The data
format examples in Table 27 also apply to the ZA_BIAS_HIGH
register and the data format examples in Table 28 apply to the
32-bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH
registers. These registers influence the z-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW
and XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 57).
FACTORY
X-AXIS
ACCL
CALIBRATION
AND
X_ACCL_OUT X_ACCL_LOW
FILTERING
XA_BIAS_HIGH
XA_BIAS_LOW
Figure 57. User Calibration Signal Path, Accelerometers
Calibration, Accelerometer Bias (YA_BIAS_LOW and
YA_BIAS_HIGH)
Table 93. YA_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x50, 0x51
0x0000
R/W
Yes
Table 94. YA_BIAS_LOW Bit Definitions
Bits
Description
[15:0]
Y-axis accelerometer offset correction; lower word
Table 95. YA_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
0x52, 0x53
0x0000
R/W
Yes
Table 96. YA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction, upper word
Rev. B | Page 32 of 41
Data Sheet
ADIS16505
Filter Control Register (FILT_CTRL)
Miscellaneous Control Register (MSC_CTRL)
Table 101. FILT_CTRL Register Definition
Table 105. MSC_CTRL Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x5C, 0x5D
0x0000
R/W
Yes
0x60, 0x61
0x00C1
R/W
Yes
Table 102. FILT_CTRL Bit Definitions
Bits Description
[15:3] Not used
Table 106. MSC_CTRL Bit Definitions
Bits Description
[15:10] Not used
[2:0]
Filter Size Variable B; number of taps in each stage; N = 2B,
where B = 0 to 6 (decimal). Changes to this register may
take up to 30 ꢀs after writing to indicate the new value
during readback.
9
8
7
6
BURST32. 32-bit burst enable bit. The user must wait
until a full data ready cycle until the burst array
updates with the desired data type. Changes to this bit
may take up to 200 ꢀs after writing to indicate the new
value during readback.
1 = 32-bit burst data.
0 = 16-bit burst data (default).
The FILT_CTRL register (see Table 101 and Table 102) provides
user controls for the Bartlett window FIR filter (see Figure 31),
which contains two cascaded averaging filters. For example, use
the following sequence to set Register FILT_CTRL, Bits[2:0] =
0100, which sets each stage to have 16 taps: 0xCC04 and 0xCD00.
Figure 58 provides the frequency response for several settings in
the FILT_CTRL register.
BURST_SEL. Burst read output array selection. This bit
controls what calibrated data is in a burst read.
Changes to this bit may take up to 200 ꢀs after writing
to indicate the new value during readback.
1 = burst data has delta angle and delta velocity data.
0 = burst data has gyroscope and accelerometer data
(default).
0
–20
–40
–60
–80
Linear acceleration compensation for gyroscopes.
When enabled, factory calibrated linear acceleration
compensation data is applied to the gyroscope
outputs. Changes to this bit may take up to 200 ꢀs after
writing to indicate the new value during readback.
1 = enabled.
0 = disabled (default).
Point of percussion alignment. When set, this bit allows
for relocation of the acceleration sensors to a common
point of percussion on the package corner by
considering angular rotations. Changes to this bit may
take up to 200 ꢀs after writing to indicate the new
value during readback.
–100
N = 2
–120
N = 4
N = 16
N = 64
–140
0.001
0.01
0.1
1
FREQUENCY (f/fS)
1 = enabled.
Figure 58. Bartlett Window, FIR Filter Frequency Response
(Phase Delay = N Samples)
0 = disabled (default).
Not used. Always set to 0.
5
4
Range Identifier (RANG_MDL)
SENS_BW. Internal sensor bandwidth. Changing this
bit reinitializes the sensors, and the user must wait
until the DR pin starts toggling after changing this bit.
This operation may require up to 250 ms to complete.
Table 103. RANG_MDL Register Definition
Addresses
Default
Access
Flash Backup
0x5E, 0x5F
Not applicable
R
No
0 = wide bandwidth (default), see Table 1.
1 = 370 Hz. The gyroscope group delay increases by
0.17 ms and the accelerometer group delay increases
by 0.63 ms in this mode.
Table 104. RANG_MDL Bit Definitions
Bits
Description
[3:2]
SYNC mode select (see the Clock Control section for
more information). The user must wait until the DR pin
starts toggling after changing these bits and/or the
UP_SCALE register in order to correctly read back the
new values. However, the user can write these registers
in succession before waiting for the DR pin to resume
toggling.
[15:3]
[3:2]
Not used
Gyroscope measurement range
00 = 125°/sec (ADIS16505-1BMLZ)
01 = 500°/sec (ADIS16505-2BMLZ)
10 = reserved
11 = 2000°/sec (ADIS16505-3BMLZ)
Reserved, binary value = 11
00 = internal SYNC (default). Internal 2 kHz clock used.
[1:0]
01 = direct input sync mode. The user provides an
external input clock between 1900 Hz and 2100 Hz.
10 = scaled sync mode. The user provides an external
input clock between 1 Hz and 128 Hz, which upscales
to 1900 Hz to 2100 Hz inside the ADIS16505.
Rev. B | Page 33 of 41
ADIS16505
Data Sheet
Sync Mode Select
Bits
Description
11 = output sync mode. Identical to internal sync mode,
except the SYNC pin functions as an output signal,
indicating when the internal clock samples sensors.
Refer to the Clock Control section for the functions of the sync
mode select bits.
Sync Input Frequency Multiplier (UP_SCALE)
1
SYNC polarity (input or output). Changes to this bit
may take up to 200 ꢀs after writing to indicate the new
value during readback.
1 = rising edge triggers sampling.
0 = falling edge triggers sampling (default).
Table 107. UP_SCALE Register Definition
Addresses
Default
Access
Flash Backup
0x62, 0x63
0x07D0
R/W
Yes
0
DR polarity. This bit controls the polarity of the DR pin.
Changes to this bit may take up to 200 ꢀs after writing
to indicate the new value during readback.
Table 108. UP_SCALE Bit Definitions
Bits
Description
[15:0]
KECSF; binary format. The user must wait until the DR
1 = active high when data is valid.
pin starts toggling after changing this register and/or
MSC_CTRL[3:2] to correctly read back the new values.
However, the user can write these registers in succession
before waiting for the DR pin to resume toggling.
0 = active low when data is valid (default).
Point of Percussion
Register MSC_CTRL, Bit 6 (see Table 106) offers an on/off control
for the point of percussion alignment function, which maps the
accelerometer sensors to the corner of the package that is closest
to Pin A1 (see Figure 59). The factory default setting in the
MSC_CTRL register activates this function. To turn this function
off while retaining the rest of the factory default settings in the
MSC_CTRL register, set Register MSC_CTRL, Bit 6 = 0 using
the following command sequence on the DIN pin: 0xE081, then
0xE100.
Refer to the Clock Control section for the function and
programming of the UP_SCALE register.
Decimation Filter (DEC_RATE)
Table 109. DEC_RATE Register Definition
Addresses
Default
Access
Flash Backup
0x64, 0x65
0x0000
R/W
Yes
Table 110. DEC_RATE Bit Definitions
Bits
Description
[15:11]
[10:0]
Don’t care
Decimation rate, binary format, maximum = 1999.
Changes to this register may take up to 30 ꢀs after
writing to indicate the new value during readback.
K1
The DEC_RATE register (see Table 109 and Table 110) provides
user control for the averaging decimating filter, which averages
and decimates the gyroscope and accelerometer data; it also
extends the time that the delta angle and the delta velocity track
between each update. When the ADIS16505 operates in internal
clock mode (see Register MSC_CTRL, Bits[3:2], in Table 106),
the nominal output data rate is equal to 2000/(DEC_RATE + 1).
For example, set DEC_RATE = 0x0013 to reduce the output
sample rate to 100 SPS (2000 ÷ 20) using the following DIN pin
sequence: 0xE413, then 0xE500.
A10
POINT OF
PERCUSSION
A1
Figure 59. Point of Percussion Reference Point
Linear Acceleration Effect on Gyroscope Bias
Register MSC_CTRL, Bit 7 (see Table 106) provides an on/off
control for the linear acceleration compensation in the signal
calibration routines of the gyroscope. The factory default
contents in the MSC_CTRL register enable this compensation.
To turn the compensation off, set Register MSC_CTRL,
Bit 7 = 0 using the following sequence on the DIN pin: 0xE041,
0xEF00.
Data Update Rate in External Sync Modes
When using the input sync option in scaled sync mode
(Register MSC_CTRL, Bits[3:2] = 10, see Table 106), the
output data rate is equal to
(fSYNC × KECSF)/(DEC_RATE + 1)
where:
f
K
SYNC is the frequency of the clock signal on the SYNC pin.
ESCF is the value from the UP_SCALE register (see Table 108).
When using direct sync mode, KESCF = 1.
Rev. B | Page 34 of 41
Data Sheet
ADIS16505
Flash Memory Update
Global Commands (GLOB_CMD)
Use the following DIN sequence to set Register GLOB_CMD,
Bit 3 = 1, which triggers a backup of all user configurable registers
in the flash memory: 0xE808, then 0xE900. Register DIAG_STAT,
Bit 2 (see Table 11), identifies success (0) or failure (1) in
completing this process.
Table 111. GLOB_CMD Register Definition
Addresses
Default
Access
Flash Backup
0x68, 0x69
Not applicable
W
No
Table 112. GLOB_CMD Bit Definitions
Bits
Description
Sensor Self Test
[15:8]
Not used
Use the following DIN sequence to set Register GLOB_CMD,
Bit 2 = 1, which triggers the self test routine for the inertial sensors:
0xE804, then 0xE900. The self test routine uses the following
steps to validate the integrity of each inertial sensor:
7
Software reset
Not used
[6:5]
4
Flash memory test
Flash memory update
Sensor self test
Factory calibration restore
Not used
3
1. Measure the output on each sensor.
2
2. Activate an internal stimulus on the mechanical elements of
each sensor to move them in a predicable manner and
create an observable response in the sensors.
1
0
The GLOB_CMD register (see Table 111 and Table 112) provides
trigger bits for several operations. Write a 1 to the appropriate
bit in GLOB_CMD to start a particular function. During the
execution of these commands, data production stops, pulsing stops
on the DR pin, and the SPI interface does not respond to requests.
Table 1 provides the execution time for each GLOB_CMD
command.
3. Measure the output response on each sensor.
4. Deactivate the internal stimulus on each sensor.
5. Calculate the difference between the sensor measurements
from Step 1 (stimulus is off) and from Step 4 (stimulus is on).
6. Compare the difference with internal pass and fail criteria.
7. Report the pass and fail result to Register DIAG_STAT, Bit 5
(see Table 11).
Software Reset
Motion during the execution of this test can indicate a false failure.
Use the following DIN sequence to set Register GLOB_CMD,
Bit 7 = 1, which triggers a reset: 0xE880, then 0xE900. This reset
clears all data, and then restarts data sampling and processing.
This function provides a firmware alternative to toggling the
Factory Calibration Restore
Use the following DIN sequence to set Register GLOB_CMD,
Bit 1 = 1, to restore the factory default settings for the MSC_
CTRL, DEC_RATE, and FILT_CTRL registers and to clear all
user configurable bias correction settings: 0xE802, then 0xE900.
Executing this command results in writing 0x0000 to the following
registers: XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW,
YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_ HIGH,
XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW,
RST
pin (see Table 5, Pin F3).
Flash Memory Test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 4 = 1, which tests the flash memory: 0xE810, then 0xE900.
The command performs a CRC computation on the flash memory
(excluding user register locations) and compares it to the original
CRC value, which comes from the factory configuration process.
If the current CRC value does not match the original CRC
value, Register DIAG_STAT, Bit 6 (see Table 11), rises to 1,
indicating a failing result.
YA_BIAS_HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH.
Rev. B | Page 35 of 41
ADIS16505
Data Sheet
The PROD_ID register (see Table 119 and Table 120) contains
the numerical portion of the device number (16,505). See Figure 41
for an example of how to use a looping read of this register to
validate the integrity of the communication.
Firmware Revision (FIRM_REV)
Table 113. FIRM_REV Register Definition
Addresses
Default
Access
Flash Backup
0x6C, 0x6D
Not applicable
R
Yes
Serial Number (SERIAL_NUM)
Table 114. FIRM_REV Bit Definitions
Table 121. SERIAL_NUM Register Definition
Bits
Description
Addresses
Default
Access
Flash Backup
[15:0]
Firmware revision, binary coded decimal (BCD) format
0x74, 0x75
Not applicable
R
Yes
The FIRM_REV register (see Table 113 and Table 114) provides
the firmware revision for the internal firmware. This register uses a
BCD format where each nibble represents a digit. For example,
if FIRM_REV = 0x0104, the firmware revision is 1.04.
Table 122. SERIAL_NUM Bit Definitions
Bits Description
[15:0] Lot specific serial number
Firmware Revision Day and Month (FIRM_DM)
Scratch Registers (USER_SCR_1 to USER_SCR_3)
Table 115. FIRM_DM Register Definition
Table 123. USER_SCR_1 Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x6E, 0x6F
Not applicable
R
Yes
0x76, 0x77
Not applicable
R/W
Yes
Table 116. FIRM_DM Bit Definitions
Table 124. USER_SCR_1 Bit Definitions
Bits Description
Bits
Description
[15:8]
[7:0]
Factory configuration month, BCD format
Factory configuration day, BCD format
[15:0] User defined
Table 125. USER_SCR_2 Register Definition
The FIRM_DM register (see Table 115 and Table 116)
Addresses
Default
Access
Flash Backup
contains the month and day of the factory configuration date.
Register FIRM_DM, Bits[15:8], contain digits that represent the
month of the factory configuration. For example, November is
the 11th month in a year and is represented by Register FIRM_DM,
Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0], contain the
day of factory configuration. For example, the 27th day of the
month is represented by Register FIRM_DM, Bits[7:0] = 0x27.
0x78, 0x79
Not applicable
R/W
Yes
Table 126. USER_SCR_2 Bit Definitions
Bits Description
[15:0] User defined
Table 127. USER_SCR_3 Register Definition
Firmware Revision Year (FIRM_Y)
Addresses
Default
Access
Flash Backup
0x7A, 0x7B
Not applicable
R/W
Yes
Table 117. FIRM_Y Register Definition
Addresses
Default
Access
Flash Backup
Table 128. USER_SCR_3 Bit Definitions
Bits Description
[15:0] User defined
0x70, 0x71
Not applicable
R
Yes
Table 118. FIRM_Y Bit Definitions
The USER_SCR_1 (see Table 123 and Table 124), USER_SCR_2
(see Table 125 and Table 126), and USER_SCR_3 (see Table 127
and Table 128) registers provide three locations for the user to
store information. For nonvolatile storage, use the manual flash
memory update command (Register GLOB_CMD, Bit 3, see
Table 112) after writing information to these registers.
Bits
Description
[15:0]
Factory configuration year, BCD format
The FIRM_Y register (see Table 117 and Table 118) contains
the year of the factory configuration date. For example, the
year, 2017, is represented by FIRM_Y = 0x2017.
Product Identification (PROD_ID)
Table 119. PROD_ID Register Definition
Addresses
Default
Access
Flash Backup
0x72, 0x73
0x4079
R
Yes
Table 120. PROD_ID Bit Definitions
Bits
Description
[15:0]
Product identification = 0x4079
Rev. B | Page 36 of 41
Data Sheet
ADIS16505
Flash Memory Endurance Counter (FLSHCNT_LOW and
FLSHCNT_HIGH)
The FLSHCNT_LOW (see Table 129 and Table 130) and
FLSHCNT_HIGH (see Table 131 and Table 132) registers
combine to provide a 32-bit, binary counter that tracks the
number of flash memory write cycles. In addition to the
number of write cycles, the flash memory has a finite service
lifetime, which depends on the junction temperature. Figure 60
provides guidance for estimating the retention life for the flash
memory at specific junction temperatures. The junction
temperature is approximately 7°C above the case temperature.
Table 129. FLSHCNT_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x7C, 0x7D
Not applicable
R
Yes
Table 130. FLSHCNT_LOW Bit Definitions
Bits Description
[15:0] Flash memory write counter, low word
Table 131. FLSHCNT_HIGH Register Definition
600
450
300
Addresses
Default
Access
Flash Backup
0x7E, 0x7F
Not applicable
R
Yes
Table 132. FLSHCNT_HIGH Bit Definitions
Bits Description
[15:0] Flash memory write counter, high word
150
0
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
Figure 60. Flash Memory Retention
Rev. B | Page 37 of 41
ADIS16505
Data Sheet
APPLICATIONS INFORMATION
ASSEMBLY AND HANDLING TIPS
Package Attributes
PCB Layout Suggestions
Figure 62 shows an example of the pad design and layout
for the ADIS16505 on a PCB. This example uses a solder mask
opening with a diameter of 0.73 mm, around a metal pad that
has a diameter of 0.56 mm. When using a material for the system
PCB that has similar thermal expansion properties as the
substrate material of the ADIS16505, the system PCB can also
use the solder mask to define the pads that support attachment
to the balls of the ADIS16505. The coefficient of thermal
expansion (CTE) in the substrate of the ADIS16505 is
approximately 14 ppm/°C.
The ADIS16505 is a multichip module package that has a 100-ball
BGA interface. This package has three basic attributes that
influence its handling and assembly to the PCB of the system:
the lid, the substrate, and the BGA pattern. The material of the
lid is a liquid crystal polymer (LCP), and its nominal thickness
is 0.5 mm. The substrate is a laminate that has a nominal thickness
of 1.57 mm. The solder ball material is SAC305, and each ball
has a nominal diameter of 0.75 mm ( 0.15 mm). The BGA
pattern is a 10 × 10 array.
0.73
All electrical and physical connections are through the 10 × 10
array shown in Figure 62. The bottom view in Figure 66 shows
additional features from the manufacture of the ADIS16505
that are not relevant to the mounting or use of the ADIS16505.
(MASK OPENING)
0.56
(COPPER PAD)
Assembly Tips
When attaching the ADIS16505 to a PCB, follow these guidelines:
The ADIS16505 supports solder reflow attachment processes
in accordance with J-STD-020E.
Limit device exposure to one pass through the solder
reflow process (no rework).
The hole in the top of the lid (see Figure 61) provides venting
and pressure relief during the assembly process of the
ADIS16505. This hole must be kept clear while attaching
the ADIS16505 to a PCB. Although, covering the hole in
normal operation is not typically a problem.
1.27
1.27
ALL DIMENSIONS IN MILLIMETERS
Figure 62. Recommend PCB Pattern, Solder Mask Defined Pads
Underfill
Underfill can be a useful technique in managing certain threats
to the integrity of the solder joints of the ADIS16505, including
peeling stress and extended exposure to vibration. When selecting
underfill material and developing an application and curing
process, ensure that the material fills the gap between each surface
(the ADIS16505 substrate and system PCB) and adheres to
both surfaces. The ADIS16505 does not require the use of
underfill materials in applications that do not anticipate exposure
to these types of mechanical stresses and when the CTE of the
system PCB is close to the same value as the CTE of the
substrate of the ADIS16505 (~14 ppm/°C).
OPENING IN
PACKAGE LID
K1
A10
A1
Figure 61. Pressure Relief Hole
Use no clean flux and avoid exposing the device to
cleaning solvents that can penetrate the inside of the
ADIS16505 through multiple paths.
Manage moisture exposure prior to the solder reflow
processing in accordance with J-STD-033, Moisture
Sensitivity Level 5.
Avoid exposing the ADIS16505 to mechanical shock
survivability that exceeds the maximum rating in Table 3.
In standard PCB processing, high speed handling equipment
and panel separation processes often present the most risk of
introducing harmful levels of mechanical shock survivability.
Process Validation and Control
These guidelines provide a starting point for developing a process
for attaching the ADIS16505 to a system PCB. Because each
system and situation can present unique requirements for this
attachment process, ensure that the process supports optimal
solder joint integrity, verify that the final system meets all
environmental test requirements, and establish observation
and control strategies for all key process attributes (for example,
peak temperatures, dwell times, and ramp rates).
Rev. B | Page 38 of 41
Data Sheet
ADIS16505
POWER SUPPLY CONSIDERATIONS
The electrical interface (J1) on each breakout board comes from
a dual row, 2 mm pitch, 16-pin interface, which supports standard
ribbon cabling (1 mm pitch). Table 134 provides the J1 pin
assignments, which support direct connection with an
embedded processor board using standard ribbon cables.
Although each case may present its own set of sensitivities
(such as electromagnetic interference (EMI)), these boards can
typically support reliable communication over ribbon cables up
to 20 cm in length.
The ADIS16505 contains 6 ꢀF of decoupling capacitance across
the VDD and GND pins. When the VDD voltage rises from 0 V
to 3.3 V, the charging current for this capacitor bank imposes
the following current profile (in amperes):
dVDD
dt
dVDD
dt
t
IDD
t
C
6106
where:
IDD(t) is the current demand on the VDD pin during the initial
power supply ramp, with respect to time.
Table 134. J1 Pin Assignments, Breakout Board
C is the internal capacitance across the VDD and GND pins (6 ꢀF).
VDD(t) is the voltage on the VDD pin, with respect to time.
J1 Pin Number
Signal
Function
1
RST
Reset
2
3
SCLK
CS
SPI
SPI
For example, if VDD follows a linear ramp from 0 V to 3.3 V,
in 66 ꢀs, the charging current is 300 mA for that timeframe.
The ADIS16505 also contains embedded processing functions
that present transient current demands during initialization or
reset recovery operations. During these processes, the peak
current demand reaches 250 mA and occurs at a time that is
approximately 40 ms after VDD reaches 3.0 V (or ~40 ms
after initiating a reset sequence).
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
NC
DIN
GND
GND
GND
VDD
VDD
VDD
DR
SPI
No connect
SPI
Ground
Ground
Ground
Power, 3.3 V
Power, 3.3 V
Power, 3.3 V
Data ready
Input clock
No connect
No connect
EVALUATION TOOLS
Breakout Boards
The ADIS16505 has three difference breakout boards, which
provide a simple way to connect an ADIS16505 model and an
existing embedded processor platform. Table 133 provides a list
of the model numbers for each breakout board, along with the
ADIS16505 model that is on each breakout board. Figure 63
shows the ADIS16505-2 which is identical to the ADIS16505-1
and ADIS16505-3 boards.
SYNC
NC
NC
Figure 64 provides a top view of the breakout board, including
dimensional locations for all the key mechanical features, such as
the mounting holes and the 16-pin header. Figure 65 provides an
electrical schematic for this breakout board. For additional
information, refer to the ADIS1650x-x/PCBZ Breakout Board
Wiki Guide.
PC-Based Evaluation, EVAL-ADIS2
In addition to supporting quick prototype connections between
the ADIS16505 and an embedded processing system, J1 on the
breakout boards also connects directly to J1 on the EVAL-ADIS2
evaluation system. When used in conjunction with the IMU
Evaluation Software for the EVAL-ADISX Platforms, the
EVAL-ADIS2 provides a simple, functional test platform that
allows users to configure and collect data from the ADIS16505
IMUs.
Figure 63. ADIS16505-2 Breakout Board
Table 133. Breakout Board Models
Breakout Board Model
ADIS16505-1/PCBZ
ADIS16505-2/PCBZ
ADIS16505-3/PCBZ
ADIS16505 Model
ADIS16505-1BMLZ
ADIS16505-2BMLZ
ADIS16505-3BMLZ
Rev. B | Page 39 of 41
ADIS16505
Data Sheet
6.03
ADIS1650x - x / PCB
08 - 050552 - 01 - A
5.125
Z
R2
Y
J1
X
U1
10
1
2
16.99
A1
33.25
K
15
16
16.99
5.125
ML / BEL
8 / 24 / 18
3.62
3.62
30.7
DIMENSIONS SHOWN IN MILLIMETERS
Figure 64. Top View of the ADIS16505 Breakout Board
VDD
VDD
DIN
SCLK
DOUT
DR
SYNC
G6
H6
D3
F6
F3
H3
J6
J3
C3
E3
DIN
DOUT
DIO0
DIO1
DNC
SCLK
GND
GND
RST
U1
RST
VDD
ADIS16500
CS
G3
CS
GND
GND
VDD
R2
10kΩ
J1
RST
SCLK
CS
1
2
3
DOUT
4
5
6
DIN
7
8
9
10
11
12
13
14
15
16
DR
SYNC
GND
Figure 65. ADIS16505 Breakout Board Schematic
Rev. B | Page 40 of 41
Data Sheet
ADIS16505
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
15.127
11.430
REF
15.000 SQ
14.873
1.785
BSC
1.270
BSC
A1 BALL
CORNER INDICATOR
A1 BALL
CORNER
INDICAT
OR
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
1.785
BSC
G
H
J
K
0.900
TOP VIEW
BOTTOM VIEW
Ø 0.750
0.600
3.450
3.400
3.350
SIDE VIEW
6.077
5.720
5.363
0.900
0.750
0.600
SEATING
PLANE
Figure 66. 100-Ball Ball Grid Array Module [BGA]
(ML-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
ML-100-1
ML-100-1
ADIS16505-1BMLZ
ADIS16505-2BMLZ
ADIS16505-3BMLZ
ADIS16505-1/PCBZ
ADIS16505-2/PCBZ
ADIS16505-3/PCBZ
100-Ball Ball Grid Array Module [BGA]
100-Ball Ball Grid Array Module [BGA]
100-Ball Ball Grid Array Module [BGA]
ADIS16505-1 Breakout Board
ADIS16505-2 Breakout Board
ADIS16505-3 Breakout Board
ML-100-1
1 Z = RoHS Compliant Part.
©2019–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17328-7/20(B)
Rev. B | Page 41 of 41
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